A method for manufacturing a substrate frame with a port for embedding a device and a substrate with a port

Abstract

The application discloses a kind of for embedding device's substrate mouth frame manufacturing method and substrate with mouth frame, disclose a kind of for embedding device's packaging substrate mouth frame and its manufacturing method, method includes the following steps: preparation metal layer;First surface etching first via hole, manufacturing first conducting metal column and first etching metal column in metal layer;First surface pressing first dielectric layer in metal layer;Second surface etching second via hole in metal layer;Manufacturing seed layer in the second surface of metal layer;Second surface manufacturing second conducting metal column and second etching metal column in metal layer;Second surface pressing second dielectric layer in metal layer;First dielectric layer and second dielectric layer are thinned;First etching metal column and second etching metal column are etched, and packaging substrate mouth frame is obtained.The mouth frame in the packaging substrate of the application has great improvement on production efficiency relative to mechanical or laser drilling preparation;By introducing metal layer in the packaging substrate, the mechanical strength and heat dissipation performance of the prepared packaging substrate are improved, and the coplanarity of packaging is also optimized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a substrate frame for embedded devices and a substrate with a frame. Background Technology

[0002] Existing embedded device substrates typically require the fabrication of frames within the substrate to embed components. Frame fabrication is generally performed using mechanical or laser drilling in CCL (Copper Clad Laminate) processes, or copper pillar etching in coreless processes. However, mechanical or laser-based frame fabrication in CCL processes is inefficient and results in poor heat dissipation; while coreless processes are complex, costly, have low mechanical strength, and poor heat dissipation. Therefore, existing frame fabrication processes for embedded devices are unsuitable for mass production. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a substrate frame for embedding devices and a method for manufacturing the same.

[0004] A first aspect of the present invention provides a method for fabricating a substrate frame for embedding devices, comprising the following steps:

[0005] Prepare a metal layer, the metal layer comprising a first side and a second side disposed opposite to each other;

[0006] A first through-hole is etched on the first surface of the metal layer to create a first conductive metal pillar and a first etched metal pillar;

[0007] A first dielectric layer is laminated onto the first surface of the metal layer, the first dielectric layer covering the first through-hole, the first conductive metal pillar and the first etched metal pillar; the thickness of the first dielectric layer is greater than the height of the first conductive metal pillar and the first etched metal pillar.

[0008] A second through-hole is etched on the second side of the metal layer, and the second through-hole is connected to the first through-hole;

[0009] A seed layer is formed on the second side of the metal layer, and the seed layer contacts the first dielectric layer through a second through-hole;

[0010] A second conductive metal pillar and a second etched metal pillar are formed on the second surface of the metal layer;

[0011] A second dielectric layer is laminated to the second surface of the metal layer, the second dielectric layer covering the second through hole, the second conductive metal pillar and the second etched metal pillar; the thickness of the first dielectric layer is greater than the height of the second conductive metal pillar and the second etched metal pillar.

[0012] The first dielectric layer and the second dielectric layer are thinned so that the top end faces of the first conductive metal pillar, the first etched metal pillar, the second conductive metal pillar and the second etched metal pillar are exposed from the dielectric layer.

[0013] The first and second etched metal pillars are etched to obtain the substrate frame.

[0014] Further, etching the first through-hole on the first surface of the metal layer specifically includes the following steps:

[0015] A first photoresist layer is bonded to the first and second surfaces of the metal layer;

[0016] Select a first position on the first side, expose and develop the first photoresist layer, and dissolve the first photoresist layer at the second position;

[0017] The metal layer is etched to form a first through hole with a first depth at a first location;

[0018] Remove the first photoresist layer.

[0019] Furthermore, the process of fabricating the first conductive metal pillar and the first etched metal pillar on the first surface of the metal layer specifically includes the following steps:

[0020] A second photoresist layer is bonded to the first and second surfaces of the metal layer;

[0021] Select a second position on the first side, expose and develop the second photoresist layer to dissolve the second photoresist layer at the second position;

[0022] Electroplating metal at the opening in the second position forms a first conductive metal pillar and a first etched metal pillar;

[0023] Remove the second photoresist layer.

[0024] Further, etching the second through-hole on the second surface of the metal layer specifically includes the following steps:

[0025] A third photoresist layer is bonded to the second side of the metal layer;

[0026] Based on the first position, a third position symmetrical to the first position along the metal layer is selected on the second surface, and the third photoresist layer is exposed and developed to dissolve the third photoresist layer at the third position.

[0027] The metal layer is etched to form a second through hole with a second depth at a third location; the sum of the first depth and the second depth is not less than the thickness of the metal layer, so that the first through hole and the second through hole are connected.

[0028] Remove the third photoresist layer.

[0029] Furthermore, after creating a seed layer on the second surface of the metal layer, the method further includes the following steps:

[0030] A metal plating layer is laid on the seed layer.

[0031] Further, the process of fabricating a second conductive metal pillar and a second etched metal pillar on the second surface of the metal layer specifically includes the following steps:

[0032] A fourth photoresist layer is bonded to the second side of the metal layer;

[0033] Select the fourth position on the second side, expose and develop the fourth photoresist layer, causing the fourth photoresist layer at the fourth position to dissolve;

[0034] Electroplating metal at the opening in the fourth position forms a second conductive metal pillar and a second etched metal pillar;

[0035] Remove the fourth photoresist layer and the seed layer.

[0036] Furthermore, the etching of the first and second etched metal pillars specifically includes the following steps:

[0037] A fifth photoresist layer is bonded onto the first dielectric layer and the second dielectric layer;

[0038] The top end face of the first etched metal pillar and the second etched metal pillar is selected as the fifth position. The fifth photoresist layer is exposed and developed to dissolve the fifth photoresist layer at the fifth position.

[0039] The first and second etched metal pillars are etched.

[0040] Remove the fifth photoresist layer to obtain the substrate frame.

[0041] Furthermore, the positions of the first etched metal pillar on the first surface and the positions of the second etched metal pillar on the second surface are symmetrical along the metal layer.

[0042] Furthermore, the distance between the first etched metal pillar and the first through hole on the first surface is greater than a first preset distance; the distance between the second etched metal pillar and the second through hole on the second surface is greater than a second preset distance.

[0043] A second aspect of the present invention discloses a substrate with a frame for embedding devices, comprising a dielectric layer, a metal layer and a photoresist layer; the metal layer is covered on both sides by the dielectric layer; conductive metal pillars are formed on the dielectric layer and are conductive to the metal layer; the conductive metal pillars are covered by the photoresist layer; a frame for embedding devices is formed on the dielectric layer, the frame being fabricated by a method for fabricating a substrate frame for embedding devices.

[0044] The embodiments of the present invention have the following beneficial effects: the frame in the substrate of the present invention is prepared by etching, which greatly improves the production efficiency compared with mechanical or laser drilling; at the same time, the present invention also improves the mechanical strength and heat dissipation performance of the substrate by introducing a metal layer into the substrate, and optimizes the coplanarity of the package. In addition, the design of the metal layer combined with the copper pillars in the present invention allows for flexible control of the thickness of the substrate, and has strong compatibility with various packaging designs.

[0045] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of a substrate structure with an embedded device frame, obtained by the substrate frame fabrication method for embedded devices provided in the embodiments of the present invention.

[0048] Figures 2 to 20 This is a schematic diagram of the substrate corresponding to the intermediate process of the substrate frame fabrication method for embedded devices provided in the embodiments of the present invention.

[0049] Reference numerals: Metal layer 100, Photoresist layer 200, First photoresist layer 210, Second photoresist layer 220, Third photoresist layer 230, Fourth photoresist layer 240, Fifth photoresist layer 250, Dielectric layer 300, First dielectric layer 310, Second dielectric layer 320, Seed layer 400, Metal plating layer 410, First positions 211, 212, 213, 214, First vias 111, 112, 113, 114, Second positions 221, 222. 223, 224, Conductive metal pillar 500, First conductive metal pillar 501, 502, Frame 600, First etched metal pillar 601, 602, Third position 231, 232, 233, 234, Second through hole 121, 122, 123, 124, Fourth position 241, 242, 243, 244, Second conductive metal pillar 503, 504, Second etched metal pillar 603, 604, Fifth position 251, 252, 253, 254. Detailed Implementation

[0050] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0051] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0052] In the description of this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0053] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0054] Figure 1 The packaged substrate structure shown is a top view of the substrate with a frame obtained according to an embodiment of the present invention. Figure 1 As can be seen, the frame 600 obtained in this embodiment is located inside the substrate. The substrate surface is a dielectric layer 300, and the material of the dielectric layer can be selected from organic dielectric materials, inorganic dielectric materials, or combinations thereof; such as polyimide, epoxy resin, glass fiber, etc. In this embodiment, epoxy resin is used as the dielectric layer material.

[0055] The frame in the substrate structure is used to embed active or passive devices, such as IC chips, surface mount resistors, surface mount capacitors, etc., or single packages after preliminary packaging such as ball grid array (BGA) / grid array (LGA) and combinations of these devices. In this embodiment, the frame 600 is used to embed active IC chips.

[0056] In the substrate structure, the metal layer 100 located within the dielectric layer 300 is connected to other layers of the substrate via conductive metal pillars 500. The shapes and / or sizes of the multiple conductive metal pillars can be the same or different; the top end face of the conductive metal pillars can be flush with or higher than the dielectric layer. The material of the metal layer 100 can be selected from metals with good heat dissipation performance, such as copper, silver, and aluminum. In this embodiment, the metal layer 100 is a copper metal layer.

[0057] A protective photoresist layer 200 is covered on the surface of the conductive metal pillar 500. Specific examples of photoresist layers include dry film photoresist, wet film photoresist, photosensitive ink, etc. In this embodiment, dry film photoresist is used as the photoresist layer 200.

[0058] To facilitate the explanation of the substrate frame fabrication method for embedding devices in this embodiment, Figures 2-20 The schematic diagrams of each process are shown using a cross-sectional view of the substrate.

[0059] The method for fabricating a substrate frame for embedding devices provided in this embodiment includes the following steps:

[0060] S1. Prepare a metal layer 100, which includes a first surface and a second surface disposed opposite to each other. The metal layer 100 prepared in step S1 is as follows: Figure 2 As shown. In step S1, the upper surface of the metal layer 100 is defined as the first surface, and the lower surface of the metal layer 100 is defined as the second surface.

[0061] S2. Etch first through holes 111, 112, 113, and 114 on the first surface of metal layer 100, and fabricate first conductive metal pillars 501 and 502 and first etched metal pillars 601 and 602. An illustration of step S2 includes... Figures 3 to 8 .

[0062] In step S2, the first through holes 111, 112, 113, and 114 are etched on the first surface of the metal layer 100, which is specifically achieved through the following steps:

[0063] S2-a1. A first photoresist layer 210 is bonded to the first and second surfaces of the metal layer 100.

[0064] S2-a2. Select the first positions 211, 212, 213, 214 on the first surface, expose and develop the first photoresist layer 210, and dissolve the first photoresist layer 210 at the second positions 221, 222, 223, 224.

[0065] like Figure 3As shown, a first photoresist layer 210 is mounted on the upper and lower surfaces of the metal layer 100, completely covering both surfaces. The first photoresist layer 210 on the upper surface is used for exposure and development according to design requirements; the first photoresist layer 210 on the lower surface protects the metal layer 100 from corrosion. According to the design pattern, first positions 211, 212, 213, and 214 are selected on the first photoresist layer 210 on the upper surface. The first photoresist layers 210 at positions 211, 212, 213, and 214 are then masked. The remaining first photoresist layers 210 on the upper surface are exposed, while the first photoresist layers 210 on the lower surface are exposed for the entire board. The first photoresist layers 210 at positions 211, 212, 213, and 214 are dissolved using a developer, thereby exposing the metal layer 100 beneath the first photoresist layer 210 for subsequent etching.

[0066] S2-a3. The metal layer 100 is etched to form first through holes 111, 112, 113, and 114 with a first depth at first positions 211, 212, 213, and 214. For example... Figure 4 As shown, the exposed metal layers 100 at the first positions 211, 212, 213, and 214 are etched using plasma etching, chemical wet etching, or other methods. This etches the metal layers 100 at the first positions 211, 212, 213, and 214, while protecting the remaining metal surfaces of the metal layers 100 covered by the first photoresist layer 210. The orientation and depth of the first vias 111, 112, 113, and 114 can be specifically set as needed. Preferably, the etched first vias 111, 112, 113, and 114 are perpendicular to the upper surface of the metal layer 100, and their depth is controlled to be approximately half the thickness of the metal layer 100.

[0067] S2-a4. Remove the first photoresist layer 210. (e.g.) Figure 5 As shown, an organic / inorganic stripping solution, such as sodium hydroxide, is used to perform a double-sided stripping treatment on the upper and lower surfaces of the metal layer 100 to obtain a metal layer 100 containing first through holes 111, 112, 113, and 114 on the upper surface.

[0068] In step S2, first conductive metal pillars 501 and 502 and first etched metal pillars 601 and 602 are fabricated on the first surface of the metal layer 100, which is specifically achieved through the following steps.

[0069] S2-b1. A second photoresist layer 220 is bonded to the first and second surfaces of the metal layer 100.

[0070] S2-b2. Select the second positions 221, 222, 223, and 224 on the first surface, expose and develop the second photoresist layer 220, and dissolve the second photoresist layer 220 at the second positions 221, 222, 223, and 224;

[0071] like Figure 6 As shown, a second photoresist layer 220 is mounted on the upper and lower surfaces of the metal layer 100, respectively. The second photoresist layer 220 completely covers the upper and lower surfaces of the metal layer 100, but does not necessarily need to fill the first vias 111, 112, 113, and 114. The second photoresist layer 220 on the upper surface is used for exposure and development according to design requirements; the second photoresist layer 220 on the lower surface is also used to protect the metal layer 100 on the lower surface.

[0072] According to the design pattern, second positions 221, 222, 223, and 224 are selected on the second photoresist layer 220 on the upper surface. The second photoresist layers 220 at positions 221, 222, 223, and 224 are blocked. The remaining second photoresist layers 220 on the upper surface are exposed, while the second photoresist layers 220 on the lower surface are exposed as a whole. The second photoresist layers 220 at positions 221, 222, 223, and 224 are dissolved by the developing solution, thereby exposing the metal layer 100 beneath the second photoresist layers 220. Subsequently, when electroplating metal pillars at positions 221, 222, 223, and 224, the metal pillars can be used to establish conductivity in the metal layer 100. Preferably, the distance between the second positions 221, 222, 223, 224 and the first through holes 111, 112, 113, 114 in the metal layer 100 is not less than a first preset distance, so as to avoid the electroplating affecting the first through holes 111, 112, 113, 114. The first preset distance can be set to 30 micrometers.

[0073] S2-b3. Electroplating metal at the openings of the second positions 221, 222, 223, 224 forms first conductive metal pillars 501, 502 and first etched metal pillars 601, 602. For example... Figure 7 As shown, metal pillars are electroplated at second positions 221, 222, 223, and 224 on the second photoresist layer 220 on the upper surface of the metal layer 100. The metal pillars include first conductive metal pillars 501 and 502 and first etched metal pillars 601 and 602. The first conductive metal pillars 501 and 502 are used to conduct the intermediate metal layer 100 on the substrate surface, while the first etched metal pillars 601 and 602 are used to etch and form a frame. The metal material of the first conductive metal pillars 501 and 502 and the first etched metal pillars 601 and 602 can be the same as or different from the metal material of the metal layer 100; in this embodiment, copper is used as the electroplated metal material.

[0074] S2-b4. Remove the second photoresist layer 220. (e.g.) Figure 8 As shown, a double-sided stripping process is performed on the upper and lower surfaces of the metal layer 100 to obtain a metal layer 100 containing first through holes 111, 112, 113, 114, first conductive metal pillars 501, 502 and first etched metal pillars 601, 602 on the upper surface.

[0075] Alternatively, first conductive metal pillars 501, 502 and first etched metal pillars 601, 602 can be fabricated on the upper surface of the metal layer 100 firstly, and then first through holes 111, 112, 113, 114 can be etched on the upper surface of the metal layer 100. In this way, a metal layer 100 containing first through holes 111, 112, 113, 114, first conductive metal pillars 501, 502 and first etched metal pillars 601, 602 can be obtained on the upper surface.

[0076] S3. A first dielectric layer 310 is laminated onto the first surface of the metal layer 100. The first dielectric layer 310 covers the first through holes 111, 112, 113, 114, the first conductive metal pillars 501, 502, and the first etched metal pillars 601, 602. The thickness of the first dielectric layer 310 is greater than the height of the first conductive metal pillars 501, 502 and the first etched metal pillars 601, 602. Figure 9 As shown, a first dielectric layer 310 is pressed onto the upper surface of the metal layer 100 to ensure that the first through holes 111, 112, 113, and 114 are filled with dielectric material, and the thickness of the dielectric layer is greater than the height of the first conductive metal pillars 501 and 502 and the first etched metal pillars 601 and 602. That is, the first dielectric layer 310 covers the first through holes 111, 112, 113, and 114, the first conductive metal pillars 501 and 502, and the first etched metal pillars 601 and 602, thus completing the processing of the upper surface of the metal layer 100.

[0077] S4. Etch second through holes 121, 122, 123, and 124 on the second surface of metal layer 100. The second through holes 121, 122, 123, and 124 are connected to the first through holes 111, 112, 113, and 114. Step S4, etching the second through holes 121, 122, 123, and 124 on the second surface of metal layer 100, is specifically achieved through the following steps:

[0078] S4-1. A third photoresist layer 230 is bonded to the second side of the metal layer 100;

[0079] S4-2. Based on the first positions 211, 212, 213, 214, select the third positions 231, 232, 233, 234 symmetrical to the first positions 211, 212, 213, 214 along the metal layer 100 on the second surface, expose and develop the third photoresist layer 230, and dissolve the third photoresist layer 230 at the third positions 231, 232, 233, 234;

[0080] S4-3. The metal layer 100 is etched to form second through holes 121, 122, 123, and 124 with a second depth at the third positions 231, 232, 233, and 234; the sum of the first depth and the second depth is not less than the thickness of the metal layer 100, so that the first through holes 111, 112, 113, and 114 and the second through holes 121, 122, 123, and 124 are connected;

[0081] S4-4 Remove the third photoresist layer 230.

[0082] like Figure 10 As shown, since the fabrication process of the upper surface of the metal layer 100 has been completed and it is protected by the first dielectric layer 310, the upper surface of the metal layer 100 will not be damaged in the subsequent etching process. Therefore, it is only necessary to attach the third photoresist layer 230 to the lower surface of the metal layer 100.

[0083] Since the second vias 121, 122, 123, and 124 need to communicate with the first vias 111, 112, 113, and 114, the metal layer 100 needs to be penetrated. Therefore, preferably, the positions on the lower surface symmetrical to the first positions 211, 212, 213, and 214 along the metal layer 100 are set as the third positions 231, 232, 233, and 234. Based on the same exposure and development steps as in step S2, the metal layer 100 at the third positions 231, 232, 233, and 234 is exposed. The metal layer 100 is etched, protecting the metal layer 100 under the exposed portion of the third photoresist layer 230, while the metal layer 100 at the third positions 231, 232, 233, and 234 is etched to form the second vias 121, 122, 123, and 124. The orientation and depth of the second through holes 121, 122, 123, and 124 can be specifically set as needed. Preferably, the etched second through holes 121, 122, 123, and 124 are perpendicular to the lower surface of the metal layer 100, communicate with the first through holes 111, 112, 113, and 114, and penetrate the metal layer 100. After etching, the third photoresist layer 230 is removed, and the metal layer 100 is in the following state: Figure 11 As shown.

[0084] S5. A seed layer 400 is formed on the second surface of the metal layer 100. The seed layer 400 contacts the first dielectric layer 310 through the second vias 121, 122, 123, and 124. Figure 12 As shown, a seed layer 400 is formed on the lower surface of the metal layer 100 by chemical plating or sputtering. The material used for the seed layer 400 may include titanium, copper, titanium-tungsten alloy, or combinations thereof. In this embodiment, titanium and copper are sputtered to form the seed layer 400. Preferably, a metal plating layer 410 may be flash-plated on the seed layer 400 to improve the electroplating quality of the lower surface.

[0085] S6. Fabricate second conductive metal pillars 503 and 504 and second etched metal pillars 603 and 604 on the second surface of metal layer 100. Step S6, which involves fabricating the second conductive metal pillars 503 and 504 and the second etched metal pillars 603 and 604 on the second surface of metal layer 100, specifically includes the following steps:

[0086] S6-1. A fourth photoresist layer 240 is bonded to the second side of the metal layer 100.

[0087] S6-2. Select the fourth positions 241, 242, 243, and 244 on the second side, expose and develop the fourth photoresist layer 240, and dissolve the fourth photoresist layer 240 at the fourth positions 241, 242, 243, and 244.

[0088] like Figure 13 As shown, positions 241, 242, 243, and 244 are used for electroplating to form the second conductive metal pillars 503 and 504 and the second etched metal pillars 603 and 604. The design of the second conductive metal pillars 503 and 504 is not necessarily symmetrical; however, the second etched metal pillars 603 and 604 are basically symmetrical with the first etched metal pillars 601 and 602. After the fourth photoresist layer 240 is bonded to the lower surface of the metal layer 100, positions 241, 242, 243, and 244 are selected on the fourth photoresist layer 240, and the fourth photoresist layer 240 is exposed and developed, thus exposing the seed layer 400 under the fourth positions 241, 242, 243, and 244. Preferably, the distance between the fourth positions 241, 242, 243, 244 and the second through holes 121, 122, 123, 124 in the metal layer 100 is not less than a second preset distance, so as to avoid the electroplating affecting the second through holes 121, 122, 123, 124. The second preset distance can be set to 30 micrometers.

[0089] S6-3. Electroplating metal at the openings of the fourth positions 241, 242, 243, and 244 forms the second conductive metal pillars 503 and 504 and the second etched metal pillars 603 and 604. For example... Figure 14 As shown, metal pillars are electroplated at the fourth positions 241, 242, 243, and 244 of the fourth photoresist layer 240 on the lower surface of the metal layer 100. The metal pillars include second conductive metal pillars 503 and 504 and second etched metal pillars 603 and 604. The second conductive metal pillars 503 and 504 are used to conduct the middle metal layer 100 on the substrate surface, while the first etched metal pillars 601 and 602 are used to etch and form the frame.

[0090] S6-4. Remove the fourth photoresist layer 240 and the seed layer 400. (e.g.) Figure 15As shown, after removing the fourth photoresist layer 240, the lower surface of the metal layer 100 containing the second through holes 121, 122, 123, 124, the second conductive metal pillars 503, 504, and the second etched metal pillars 603, 604 is obtained.

[0091] S7. A second dielectric layer 320 is laminated onto the second side of the metal layer 100. The second dielectric layer 320 covers the second through holes 121, 122, 123, 124, the second conductive metal pillars 503, 504, and the second etched metal pillars 603, 604. The thickness of the first dielectric layer 310 is greater than the height of the second conductive metal pillars 503, 504 and the second etched metal pillars 603, 604.

[0092] like Figure 16 As shown, in step S7, a second dielectric layer 320 is pressed onto the lower surface of the metal layer 100 to ensure that the second through holes 121, 122, 123, and 124 are filled with dielectric material. That is, the second dielectric layer 320 is connected to the first dielectric layer 310 through the first through holes 111, 112, 113, and 114 and the second through holes 121, 122, 123, and 124. The thickness of the second dielectric layer 320 also needs to be greater than the height of the second conductive metal pillars 503 and 504 and the second etched metal pillars 603 and 604 to complete the processing of the lower surface of the metal layer 100. The second dielectric layer 320 can be made of the same dielectric material as the first dielectric layer 310, or it can be made of a different dielectric material. However, the second dielectric layer 320 must be compatible with the first dielectric layer 310. The first dielectric layer 310 and the second dielectric layer 320 are fixed through the connecting surfaces of the dielectric layers in the first through holes 111, 112, 113, 114 and the second through holes 121, 122, 123, 124 to ensure that the dielectric layers do not fall off.

[0093] S8. Thinning process is performed on the first dielectric layer 310 and the second dielectric layer 320 so that the top end faces of the first conductive metal pillars 501, 502, the first etched metal pillars 601, 602, the second conductive metal pillars 503, 504 and the second etched metal pillars 603, 604 are exposed from the dielectric layer.

[0094] The thinning methods for the first and second dielectric layers 320 can include overall thinning using methods such as grinding or plasma etching; or local thinning using lasers or drilling. In the aforementioned design process, to protect the conductive metal pillars and etched metal pillars from corrosion, the first dielectric layer 310 completely covers the first conductive metal pillars 501, 502 and the first etched metal pillars 601, 602; the second dielectric layer 320 completely covers the second conductive metal pillars 503, 504 and the second etched metal pillars 603, 604. To expose the top surfaces of the first conductive metal pillars 501, 502, the first etched metal pillars 601, 602, the second conductive metal pillars 503, 504, and the second etched metal pillars 603, 604 from the dielectric layer, the first dielectric layer 310 and the second dielectric layer 320 need to be thinned. In step S8, grinding is specifically used to thin the first dielectric layer 310 and the second dielectric layer 320 overall, and the thinning effect is as follows: Figure 17 As shown.

[0095] S9. Etch the first etched metal pillars 601, 602 and the second etched metal pillars 603, 604 to obtain the substrate frame.

[0096] In step S9, the first etched metal pillars 601 and 602 and the second etched metal pillars 603 and 604 are etched, which is specifically achieved through the following steps:

[0097] S9-1. A fifth photoresist layer 250 is bonded onto the first dielectric layer 310 and the second dielectric layer 320. S9-2. The top end faces of the first etched metal pillars 601, 602 and the second etched metal pillars 603, 604 are selected as the fifth positions 251, 252, 253, 254. The fifth photoresist layer 250 is exposed and developed to dissolve the fifth photoresist layer 250 at the fifth positions 251, 252, 253, 254.

[0098] In step S9, the first etched metal pillars 601 and 602, the second etched metal pillars 603 and 604, and the metal layer 100 connected thereto need to be etched to form a frame. Therefore, the top surfaces of the first conductive metal pillars 501 and 502 and the second conductive metal pillars 503 and 504 need to be protected. Figure 18 As shown, a fifth photoresist layer 250 is bonded to the first dielectric layer 310 and the second dielectric layer 320, and the fifth photoresist layer 250 is exposed and developed, so that the top end faces of the first etched metal pillars 601, 602 and the second etched metal pillars 603, 604 are exposed.

[0099] Alternatively, an etching protection layer may be made on the top end face of the first conductive metal pillar 501, 502 and the second conductive metal pillar 503, 504 to achieve the same effect of protecting the first conductive metal pillar 501, 502 and the second conductive metal pillar 503, 504 from etching.

[0100] S9-3. Etch the first etched metal pillars 601 and 602 and the second etched metal pillars 603 and 604. For example... Figure 19 As shown, the etching of the metal layer 100 connected to the first etch metal pillars 601, 602 and the second etch metal pillars 603, 604 is completed by the first etch metal pillars 601, 602 and the second etch metal pillars 603, 604, thereby forming a frame in the substrate.

[0101] S9-4. Remove the fifth photoresist layer 250 to obtain the substrate frame. (Example:) Figure 20 As shown, after removing the fifth photoresist layer 250 and the separated dielectric layer, a finished packaging substrate with a frame is obtained, and the device embedding operation is then performed at the frame position.

[0102] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0103] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0104] The above is a detailed description of the preferred embodiments of the present invention, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A method for fabricating a substrate frame for embedding devices, characterized in that, Includes the following steps: Prepare a metal layer, the metal layer comprising a first side and a second side disposed opposite to each other; A first through-hole is etched on the first surface of the metal layer to create a first conductive metal pillar and a first etched metal pillar; A first dielectric layer is laminated onto the first surface of the metal layer, the first dielectric layer covering the first through-hole, the first conductive metal pillar and the first etched metal pillar; the thickness of the first dielectric layer is greater than the height of the first conductive metal pillar and the first etched metal pillar. A second through-hole is etched on the second side of the metal layer, and the second through-hole is connected to the first through-hole; A seed layer is formed on the second side of the metal layer, and the seed layer contacts the first dielectric layer through a second through-hole; A second conductive metal pillar and a second etched metal pillar are formed on the second surface of the metal layer; A second dielectric layer is laminated onto the second side of the metal layer, the second dielectric layer covering the second through hole, the second conductive metal pillar and the second etched metal pillar; The thickness of the first dielectric layer is greater than the height of the second conductive metal pillar and the second etched metal pillar; The first dielectric layer and the second dielectric layer are thinned so that the top end faces of the first conductive metal pillar, the first etched metal pillar, the second conductive metal pillar and the second etched metal pillar are exposed from the dielectric layer. The first and second etched metal pillars are etched to obtain the substrate frame.

2. The method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, Etching the first through-hole on the first surface of the metal layer specifically includes the following steps: A first photoresist layer is bonded to the first and second surfaces of the metal layer; Select a first position on the first side, expose and develop the first photoresist layer, and dissolve the first photoresist layer at the second position; The metal layer is etched to form a first through hole with a first depth at a first location; Remove the first photoresist layer.

3. The method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, The process of fabricating the first conductive metal pillar and the first etched metal pillar on the first surface of the metal layer specifically includes the following steps: A second photoresist layer is bonded to the first and second surfaces of the metal layer; Select a second position on the first side, expose and develop the second photoresist layer to dissolve the second photoresist layer at the second position; Electroplating metal at the opening in the second position forms a first conductive metal pillar and a first etched metal pillar; Remove the second photoresist layer.

4. The method for fabricating a substrate frame for embedding devices according to claim 2, characterized in that, Etching the second through-hole on the second side of the metal layer specifically includes the following steps: A third photoresist layer is bonded to the second side of the metal layer; Based on the first position, a third position symmetrical to the first position along the metal layer is selected on the second surface, and the third photoresist layer is exposed and developed to dissolve the third photoresist layer at the third position. The metal layer is etched to form a second through hole with a second depth at a third location; the sum of the first depth and the second depth is not less than the thickness of the metal layer, so that the first through hole and the second through hole are connected. Remove the third photoresist layer.

5. A method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, After creating a seed layer on the second side of the metal layer, the method further includes the following steps: A metal plating layer is laid on the seed layer.

6. The method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, The process of fabricating a second conductive metal pillar and a second etched metal pillar on the second surface of the metal layer specifically includes the following steps: A fourth photoresist layer is bonded to the second side of the metal layer; Select the fourth position on the second side, expose and develop the fourth photoresist layer, causing the fourth photoresist layer at the fourth position to dissolve; Electroplating metal at the opening in the fourth position forms a second conductive metal pillar and a second etched metal pillar; Remove the fourth photoresist layer and the seed layer.

7. A method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, The etching of the first and second etched metal pillars specifically includes the following steps: A fifth photoresist layer is bonded onto the first dielectric layer and the second dielectric layer; The top end face of the first etched metal pillar and the second etched metal pillar is selected as the fifth position. The fifth photoresist layer is exposed and developed to dissolve the fifth photoresist layer at the fifth position. The first and second etched metal pillars are etched. Remove the fifth photoresist layer to obtain the substrate frame.

8. A method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, The positions of the first etched metal pillar on the first surface and the positions of the second etched metal pillar on the second surface are symmetrical along the metal layer.

9. A method for fabricating a substrate frame for embedding devices according to claim 1, characterized in that, The distance between the first etched metal pillar and the first through hole on the first surface is greater than a first preset distance; the distance between the second etched metal pillar and the second through hole on the second surface is greater than a second preset distance.

10. A substrate with a frame, characterized in that, It includes a dielectric layer, a metal layer, and a photoresist layer; the metal layer is covered on both sides by the dielectric layer; a conductive metal post is formed on the dielectric layer and is connected to the metal layer; the conductive metal post is covered by the photoresist layer; a frame for embedding a device is formed on the dielectric layer, and the frame is fabricated by the substrate frame fabrication method for embedding a device according to any one of claims 1 to 9.

Images