Method for forming image sensor and image sensor
By protecting the source follower transistor channel region and reducing parasitic capacitance in CMOS image sensors, the problems of difficult photodiode readout and insufficient transistor performance are solved, thereby improving the electrical performance of high-performance image sensors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2021-05-17
- Publication Date
- 2026-07-10
Smart Images
Figure CN115360202B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of image sensors, and more particularly to a method for forming an image sensor and an image sensor itself. Background Technology
[0002] An image sensor is a semiconductor device that converts light signals into electrical signals; it contains photoelectric conversion elements. Image sensors are widely used in digital still cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. Currently, image sensors can be divided into charge-coupled device (CCD) image sensors and metal-oxide-semiconductor (CMOS) image sensors. Existing CMOS image sensor pixel units consist of a 3T or 4T structure. A 4T (4-Transistor) pixel consists of a transfer transistor, a source follower transistor, a reset transistor, and a row gate transistor; a 3T (3-Transistor) pixel consists of a transfer transistor, a source follower transistor, and a reset transistor. Figure 1 This is a side cross-sectional view of a portion of a pixel unit in a CMOS image sensor in the prior art, where TX is a transfer transistor and SF is a source follower transistor. Its working principle is briefly described as follows: Incident light is injected into the photodiode region, generating photogenerated carriers (electrons and holes); the photogenerated electrons and holes separate under the influence of the built-in electric field of the PN junction, causing the photogenerated electrons to accumulate in the N-type region of the photodiode; when the TX transistor is turned on, the photogenerated electrons accumulated in the N-type region of the photodiode are guided into the FD floating diffusion region. The SF source follower transistor senses the potential change in the FD floating diffusion region before and after the TX transistor is turned on to read out the signal in the photodiode. As the pixel size of CMOS image sensors shrinks, on the one hand, high-performance source follower transistors are needed to reduce readout noise; on the other hand, to obtain a relatively large full-well capacity of the pixel unit, the N-type doping dose and doping depth of the photodiode must be increased. However, in the prior art, the gate structure of the TX transistor is a planar structure. Therefore, photogenerated electrons deep in the N-type region of the photodiode may not be read out, leading to lag (image residue). Summary of the Invention
[0003] To achieve high-performance source follower transistors to reduce readout noise and obtain a relatively large full-well capacity while continuously improving the integration density of image sensors, and to minimize lag (image retention), optimize the performance of transfer transistors, and improve the electrical performance of image sensors, this invention provides a method for forming an image sensor, which includes at least the following:
[0004] A semiconductor substrate is etched to form a first trench; wherein a portion of the semiconductor substrate region between two adjacent first trenches is used to form the channel region of the source follower transistor of the image sensor pixel unit;
[0005] By filling the first dielectric layer into the first trench, the surface of the source follower transistor channel region is prevented from being damaged in the process steps prior to the formation of the gate of the source follower transistor.
[0006] Before the gate of the source follower transistor is formed, the first dielectric layer is removed to form the gate structure of the source follower transistor.
[0007] In some embodiments, the forming method further includes: forming a floating diffusion region with a raised structure, such that the surface of the semiconductor substrate corresponding to the floating diffusion region is higher than the surface of the semiconductor substrate corresponding to the photodiode, so as to reduce the capacitance of the floating diffusion region.
[0008] In some embodiments, the forming method further includes: forming a vertical transfer gate structure of a transfer transistor; wherein at least a portion of the vertical transfer gate structure is dielectrically isolated from the floating diffusion region, thereby reducing the parasitic capacitance between the vertical transfer gate structure and the floating diffusion region.
[0009] In some embodiments, the bottom portion of the gate structure of the source follower transistor is covered on the semiconductor substrate, and the remaining portion is covered on a fourth dielectric layer to reduce the parasitic capacitance between the gate structure of the source follower transistor and the semiconductor substrate.
[0010] In some embodiments, the forming method further includes forming at least a partial dielectric isolation between the gate structure of the source follower transistor and the source / drain of the source follower transistor to reduce the parasitic capacitance between the gate structure of the source follower transistor and the source / drain of the source follower transistor.
[0011] In some embodiments, before forming the gate structure of the source follower transistor, a hard mask layer is present on the upper surfaces of the source and drain of the source follower transistor, so that the hard mask layer serves as an etch stop layer for the gate structure of the source follower transistor.
[0012] In some embodiments, the first dielectric layer is a dielectric that can be removed by wet etching; and the first dielectric layer includes at least one dielectric with a wet etching selectivity higher than that of silicon oxide.
[0013] In some embodiments, the first dielectric layer comprises one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
[0014] In some embodiments, the formation method further includes: forming a hard mask layer on the semiconductor substrate; the etching of the semiconductor substrate to form a first trench includes: etching the hard mask layer and the semiconductor substrate to form the first trench; the step of preventing damage to the surface of the source follower transistor channel region in the process steps prior to the formation of the gate of the source follower transistor by filling the first dielectric layer into the first trench includes: forming a first oxide layer on the surface of the first trench; filling the first trench with a second dielectric layer; the second dielectric layer includes silicon nitride or silicon oxynitride; the first dielectric layer includes the first oxide layer and the second dielectric layer.
[0015] In some embodiments, forming the floating diffusion region with a raised structure includes: etching the second dielectric layer, the hard mask layer, and the semiconductor substrate to form a second trench, thereby forming the floating diffusion region with a raised structure.
[0016] In some embodiments, the forming method further includes: etching the sidewalls of the second trench to remove a portion of the semiconductor substrate below the first trench; depositing a second oxide layer on the semiconductor substrate and etching back the second oxide layer so that the height of the second oxide layer exceeds the first trench; depositing a third dielectric layer on the semiconductor substrate; the third dielectric layer comprising silicon nitride or silicon oxynitride; etching the third dielectric layer, the second oxide layer, and the semiconductor substrate to form a third trench for forming a vertical transfer gate structure of a transfer transistor; the first dielectric layer comprising the first oxide layer, the second dielectric layer, and the third dielectric layer.
[0017] In some embodiments, the formation method further includes: removing the second dielectric layer, the third dielectric layer, and the first oxide layer; forming the gate dielectric layer of the source follower transistor and the gate dielectric layer of the transfer transistor; depositing polysilicon on the semiconductor substrate; and etching the polysilicon to form the gate structure of the source follower transistor and the vertical transfer gate structure of the transfer transistor.
[0018] In some embodiments, the thickness of the first oxide layer is 2 to 50 nanometers; the thickness of the hard mask layer is 10 to 200 nanometers.
[0019] This invention also provides an image sensor formed by the above-described forming method.
[0020] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:
[0021] In this embodiment of the invention, the surface of the channel region of the source follower transistor is protected by a dielectric before the gate of the source follower transistor is formed, which can prevent the surface of the channel region of the source follower transistor from being damaged in the process steps before the gate of the source follower transistor is formed.
[0022] In this embodiment of the invention, the bottom portion of the gate structure of the source follower transistor is covered on the semiconductor substrate, and the remaining portion is covered on the dielectric layer, thereby reducing the parasitic capacitance between the gate structure of the source follower transistor and the semiconductor substrate.
[0023] In this embodiment of the invention, a floating diffusion region with a raised structure is formed, so that the surface height of the floating diffusion region exceeds the surface of the photodiode, which can reduce the capacitance of the floating diffusion region and thereby improve the conversion gain.
[0024] The transfer transistor in this embodiment of the invention employs a vertical transfer gate structure, and there is at least partial dielectric isolation between the vertical transfer gate structure and the floating diffusion region, thereby reducing the parasitic capacitance between the vertical transfer gate structure and the floating diffusion region.
[0025] In this embodiment of the invention, at least partial dielectric isolation is formed between the gate structure of the source follower transistor and the source / drain of the source follower transistor, which can reduce the parasitic capacitance between the gate structure of the source follower transistor and the source / drain of the source follower transistor. Attached Figure Description
[0026] The present invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals denote the same structures, wherein:
[0027] Figure 1 This is a side cross-sectional view of a portion of a pixel unit in a CMOS image sensor in the prior art.
[0028] Figures 2 to 16 This is a schematic diagram of the structure of a portion of the image sensor in each step of an exemplary method for forming an image sensor according to an embodiment of the present invention.
[0029] Figure 17 For the corresponding Figure 15 A top view of the gate structure of the source follower transistor;
[0030] Figure 18 For the corresponding Figure 16 A top view of the gate structure of the source follower transistor;
[0031] Figure 19 This is a flowchart illustrating a method for forming an image sensor according to an embodiment of the present invention. Detailed Implementation
[0032] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.
[0033] This invention provides a method for forming an image sensor, comprising: etching a semiconductor substrate to form a first trench; wherein a channel region of a source follower transistor (SPT) for an image sensor pixel unit is formed in a portion of the semiconductor substrate region between two adjacent first trenches; filling the first trench with a first dielectric layer to prevent damage to the surface of the SPT channel region during process steps prior to the formation of the SPT gate; and removing the first dielectric layer prior to the formation of the SPT gate to form the gate structure of the SPT. The first dielectric layer may include one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. In some embodiments, the first dielectric layer is a dielectric that can be removed by wet etching. In some embodiments, the first dielectric layer includes at least one dielectric with a wet etching selectivity higher than that of silicon oxide.
[0034] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings. (See also...) Figures 2 to 16 , Figures 2 to 16 This is a schematic diagram illustrating the steps of an exemplary image sensor formation method according to an embodiment of the present invention.
[0035] like Figure 2 A semiconductor substrate 10 is provided, which serves as a carrier for forming an image sensor. The semiconductor substrate 10 can be a silicon wafer, and a photodiode (PD) is pre-formed in the semiconductor substrate 10. A hard mask layer 101 is formed on the semiconductor substrate 10, and the hard mask layer 101 can include materials such as silicon oxide, silicon nitride, or silicon oxynitride. The thickness of the hard mask layer 101 is 10 to 200 nanometers.
[0036] like Figure 3 As shown, the semiconductor substrate 10 is etched to form a first trench 102; wherein, a portion of the semiconductor substrate region between two adjacent first trenches 102 is used to form the channel region 10A of the source follower transistor of the image sensor pixel unit; by etching the semiconductor substrate 10 through a preset mask pattern, a plurality of first trenches 102 can be formed, and a hard mask layer 101 covering the channel region, source and drain of the source follower transistor is retained.
[0037] like Figure 4 and Figure 5 As shown, a first oxide layer 103 is formed on the surface of the first trench 102; the first trench 102 is filled by a second dielectric layer 104. The second dielectric layer 104 includes materials such as silicon nitride or silicon oxynitride; the first dielectric layer includes the first oxide layer 103 and the second dielectric layer 104. The thickness of the first oxide layer is 2 to 50 nanometers.
[0038] like Figure 6 As shown, the second dielectric layer 104, the hard mask layer 101, and the semiconductor substrate 10 are etched to form a second trench 105, thereby forming a floating diffusion region 10B with a raised structure. The surface of the semiconductor substrate corresponding to the floating diffusion region is higher than the surface of the semiconductor substrate corresponding to the photodiode PD, thus reducing the capacitance of the floating diffusion region 10B. Compared to the conventional planar structure of image sensors, the reduced capacitance of the floating diffusion region 10B improves the conversion gain.
[0039] like Figure 7 As shown, the sidewalls of the second trench 105 are etched to remove a portion of the semiconductor substrate 10C below the first trench 102.
[0040] like Figure 8 and Figure 9 As shown, a second oxide layer 107 is deposited on a semiconductor substrate 10, and the second oxide layer 107 is etched back so that the height of the second oxide layer 107 exceeds the first trench 102.
[0041] like Figure 10 As shown, a third dielectric layer 108 is deposited on a semiconductor substrate 10; the third dielectric layer 108 may include materials such as silicon nitride or silicon oxynitride.
[0042] like Figure 11 As shown, the third dielectric layer 108, the second oxide layer 107, and the semiconductor substrate 10 are etched to form a third trench 109 for forming the vertical transfer gate structure of the transfer transistor. The first dielectric layer includes a first oxide layer 103, a second dielectric layer 104, and a third dielectric layer 108.
[0043] like Figure 12 As shown, the second dielectric layer 104, the third dielectric layer 108, and the first oxide layer 103 are removed. Specifically, the second dielectric layer 104, the third dielectric layer 108, and the first oxide layer 103 can be removed by wet etching.
[0044] like Figure 13 As shown, a gate dielectric layer 110 for a source follower transistor and a gate dielectric layer 111 for a transfer transistor are formed.
[0045] like Figure 14 As shown, polysilicon 111 is deposited on semiconductor substrate 10.
[0046] like Figure 15 As shown, polysilicon 111 is etched to form the gate structure 111a of the source follower transistor and the vertical transfer gate structure 111b of the transfer transistor.
[0047] like Figure 16 As shown, a fourth dielectric layer 112 is deposited on a semiconductor substrate 10.
[0048] Figure 17 For the corresponding Figure 15 The top view of the source follower transistor shows that, before forming the gate structure 111a of the source follower transistor, a hard mask layer 101 is present on the upper surface of the source 21 and drain 22 of the source follower transistor. When etching the polysilicon 111, the hard mask layer 101 can serve as an etching stop layer for the gate structure 111a of the source follower transistor.
[0049] Figure 18 For the corresponding Figure 16 A top view of the source follower transistor. By depositing a fourth dielectric layer 112 on the semiconductor substrate 10, at least partial dielectric isolation (i.e., the fourth dielectric layer 112) can be formed between the gate structure 111a of the source follower transistor and the source 21 / drain 22 of the source follower transistor, thereby reducing the parasitic capacitance between the gate structure 111a of the source follower transistor and the source 21 / drain 22 of the source follower transistor.
[0050] There is at least partial dielectric isolation (i.e., fourth dielectric layer 112) between the vertical transfer gate structure 111b of the transfer transistor and the floating diffusion region 10B with a raised structure, thereby reducing the parasitic capacitance between the vertical transfer gate structure 111b and the floating diffusion region 10B.
[0051] Figure 19 This is a flowchart of a method 400 for forming an image sensor according to an embodiment of the present invention.
[0052] Formation method 400 includes:
[0053] Step S1: Etch a semiconductor substrate to form a first trench; wherein, a portion of the semiconductor substrate region between two adjacent first trenches forms the channel region of the source follower transistor of the image sensor pixel unit;
[0054] Step S2: By filling the first dielectric layer into the first trench, the surface of the source follower transistor channel region is prevented from being damaged in the process steps before the gate of the source follower transistor is formed;
[0055] Step S3: Before the gate of the source follower transistor is formed, the first dielectric layer is removed to form the gate structure of the source follower transistor.
[0056] The method for forming an image sensor 400 also includes:
[0057] A floating diffusion region with a raised structure is formed, such that the surface of the semiconductor substrate corresponding to the floating diffusion region is higher than the surface of the semiconductor substrate corresponding to the photodiode, so as to reduce the capacitance of the floating diffusion region.
[0058] The image sensor formation method 400 further includes: forming a vertical transfer gate structure of a transfer transistor; the vertical transfer gate structure and the floating diffusion region are at least partially dielectrically isolated, thereby reducing the parasitic capacitance between the vertical transfer gate structure and the floating diffusion region.
[0059] The image sensor forming method 400 further includes: forming at least a partial dielectric isolation between the gate structure of the source follower transistor and the source / drain of the source follower transistor to reduce the parasitic capacitance between the gate structure of the source follower transistor and the source / drain of the source follower transistor.
[0060] In some embodiments, the bottom portion of the gate structure of the source follower transistor is covered on the semiconductor substrate, and the remaining portion is covered on a fourth dielectric layer to reduce the parasitic capacitance between the gate structure of the source follower transistor and the semiconductor substrate.
[0061] In some embodiments, before forming the gate structure of the source follower transistor, a hard mask layer is present on the upper surfaces of the source and drain of the source follower transistor, so that the hard mask layer serves as an etch stop layer for the gate structure of the source follower transistor.
[0062] In some embodiments, the first dielectric layer is a dielectric that can be removed by wet etching; and the first dielectric layer includes at least one dielectric with a wet etching selectivity higher than that of silicon oxide.
[0063] In some embodiments, the first dielectric layer comprises one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
[0064] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for forming an image sensor, characterized in that, At least including: A semiconductor substrate is etched to form a first trench; wherein a portion of the semiconductor substrate region between two adjacent first trenches is used to form the channel region of the source follower transistor of the image sensor pixel unit; By filling the first dielectric layer into the first trench, the surface of the source follower transistor channel region is prevented from being damaged in the process steps prior to the formation of the gate of the source follower transistor. Before the gate of the source follower transistor is formed, the first dielectric layer is removed to form the gate structure of the source follower transistor; The bottom portion of the gate structure of the source follower transistor covers the semiconductor substrate, and the remaining portion covers the fifth dielectric layer to reduce the parasitic capacitance between the gate structure of the source follower transistor and the semiconductor substrate.
2. The method for forming an image sensor as described in claim 1, characterized in that, Also includes: A floating diffusion region with a raised structure is formed, such that the surface of the semiconductor substrate corresponding to the floating diffusion region is higher than the surface of the semiconductor substrate corresponding to the photodiode, so as to reduce the capacitance of the floating diffusion region.
3. The method for forming an image sensor as described in claim 2, characterized in that, Also includes: A vertical transfer gate structure is formed to create the transfer transistor; There is at least partial dielectric isolation between the vertical transfer gate structure and the floating diffusion region, thereby reducing the parasitic capacitance between the vertical transfer gate structure and the floating diffusion region.
4. The method for forming an image sensor as described in claim 1, characterized in that, Also includes: At least partial dielectric isolation is formed between the gate structure of the source follower transistor and the source / drain of the source follower transistor to reduce the parasitic capacitance between the gate structure of the source follower transistor and the source / drain of the source follower transistor.
5. The method for forming an image sensor as described in claim 1, characterized in that, Before forming the gate structure of the source follower transistor, a hard mask layer is present on the upper surface of the source and drain of the source follower transistor, so that the hard mask layer serves as the etch stop layer of the gate structure of the source follower transistor.
6. The method for forming an image sensor as described in claim 1, characterized in that, The first dielectric layer is a dielectric that can be removed by wet etching; and the first dielectric layer includes at least one dielectric with a wet etching selectivity higher than that of silicon oxide.
7. The method for forming an image sensor as described in claim 6, characterized in that, The first dielectric layer comprises one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.
8. The method for forming an image sensor as described in claim 7, characterized in that, Also includes: A hard mask layer is formed on the semiconductor substrate; The etching of the semiconductor substrate to form the first trench includes: The hard mask layer and the semiconductor substrate are etched to form the first trench; The step of preventing damage to the surface of the source follower transistor channel region during the process steps prior to the formation of the gate of the source follower transistor by filling the first dielectric layer into the first trench includes: A first oxide layer is formed on the surface of the first trench; The first trench is filled by a second dielectric layer; the second dielectric layer comprises silicon nitride or silicon oxynitride. The first dielectric layer includes the first oxide layer and the second dielectric layer.
9. The method for forming an image sensor as described in claim 8, characterized in that, Also includes: The second dielectric layer, the hard mask layer, and the semiconductor substrate are etched to form a second trench, thereby forming a floating diffusion region with a raised structure.
10. The method for forming an image sensor as described in claim 9, wherein the fifth dielectric layer is a second oxide layer, characterized in that, Also includes: The sidewalls of the second trench are etched to remove a portion of the semiconductor substrate beneath the first trench; The second oxide layer is deposited on the semiconductor substrate, and the second oxide layer is etched back so that the height of the second oxide layer exceeds the first trench; A third dielectric layer is deposited on the semiconductor substrate; the third dielectric layer comprises silicon nitride or silicon oxynitride; The third dielectric layer, the second oxide layer, and the semiconductor substrate are etched to form a third trench for forming a vertical transfer gate structure of the transfer transistor; The first dielectric layer includes the first oxide layer, the second dielectric layer, and the third dielectric layer.
11. The method for forming an image sensor as described in claim 10, characterized in that, Also includes: Remove the second dielectric layer, the third dielectric layer, and the first oxide layer; The gate dielectric layer of the source follower transistor and the gate dielectric layer of the transfer transistor are formed. Polycrystalline silicon is deposited on the semiconductor substrate; The polysilicon is etched to form the gate structure of the source follower transistor and the vertical transfer gate structure of the transfer transistor.
12. The method for forming an image sensor as described in claim 11, characterized in that, The thickness of the first oxide layer is 2 to 50 nanometers; the thickness of the hard mask layer is 10 to 200 nanometers.
13. An image sensor, characterized in that, Prepared by the method described in any one of claims 1 to 12.