Electrostatic protection element and semiconductor device
By employing MOS transistor structures with high and low concentrations of source and drain regions in semiconductor devices, the problems of voltage drop and area increase caused by the Kirk effect in ESD protection are solved, thus achieving effective electrostatic protection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LAPIS SEMICON CO LTD
- Filing Date
- 2021-09-17
- Publication Date
- 2026-07-03
Smart Images
Figure CN114335136B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to an electrostatic discharge (ESD) protection element and a semiconductor device comprising the ESD protection element. Background Technology
[0002] In a semiconductor IC chip, which is a semiconductor device, there is an ESD protection circuit that prevents large currents associated with electrostatic discharge (hereinafter referred to as ESD) generated outside the chip from flowing into the internal circuit through the power supply terminals.
[0003] This ESD protection circuit includes an ESD protection transistor that connects the power line and the ground line when the voltage value of the power line becomes a high voltage exceeding a predetermined voltage value. In the ESD protection circuit, when a high voltage associated with ESD is applied to the power line via an external terminal, the ESD protection transistor operates, the current associated with the high voltage flows through the ESD protection transistor, the voltage applied to the transistor decreases, and the internal circuit is protected by a cyclic voltage that is maintained at a certain voltage (called the holding voltage) (for example, see Patent Document 1).
[0004] Existing technical documents
[0005] Patent documents
[0006] Patent document 1: Japanese Patent Application Publication No. 2016-162844. Summary of the Invention
[0007] The problem that the invention aims to solve
[0008] However, when the current flowing into the ESD protection transistor is too large, the Kirk effect sometimes occurs. When the Kirk effect occurs, a depletion layer forms, and the current density in the current path increases. When a high voltage is continuously applied in this state, compared to the case where the Kirk effect does not occur, a large current flows between the collector and emitter, and the aforementioned holding voltage becomes lower. At this time, when a power supply voltage higher than this holding voltage is applied to the power line, the ESD protection transistor continues to operate after the ESD event has ended. Therefore, the current based on this power supply voltage continues to flow into the ESD protection transistor, potentially leading to insufficient power supply to the internal circuitry or damage to the ESD protection transistor itself.
[0009] Therefore, to eliminate such adverse conditions, the electrostatic discharge (ESD) protection circuit described in Patent Document 1 employs a structure in which two ESD protection transistors are cascaded between the power supply line and the ground line. In this ESD protection circuit, the sum of the holding voltages generated by the two cascaded ESD protection transistors becomes the holding voltage of the circuit. Therefore, compared to the power supply voltage, the holding voltage of the circuit can be made higher, thus suppressing the current flowing to the ESD protection transistors even when the power supply voltage is applied after ESD termination.
[0010] However, in the structure disclosed in Patent Document 1, two ESD protection transistors are required in order to prevent damage to the device along with the internal circuitry, which results in a larger footprint within the semiconductor device.
[0011] Therefore, the object of the present invention is to provide an electrostatic protection element and a semiconductor device that can prevent electrostatic damage to itself along with the internal circuit without causing an increase in the occupied area or insufficient power supply to the internal circuit.
[0012] Solution for solving the problem
[0013] This invention provides an electrostatic discharge (ESD) protection element, characterized by comprising: a semiconductor substrate of a first conductivity type; a high-concentration source region of a second conductivity type, formed along the surface of the semiconductor substrate and connected to one of a power line for transmitting power supply voltage and a ground line; a low-concentration source region of the second conductivity type, having an exposed surface exposed from the surface of the semiconductor substrate, connected to the high-concentration source region, and having a lower impurity concentration than the high-concentration source region; and a high-concentration drain region of the second conductivity type, formed separately from the high-concentration source region and the low-concentration source region along the surface of the semiconductor substrate, and connected to the other of the power line and the ground line; and a second... A conductive, low-concentration drain region is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, has a lower impurity concentration than the high-concentration drain region, and extends to a region deeper from the surface of the semiconductor substrate than the low-concentration source region; a gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and in the region between the exposed surfaces on the surface of the semiconductor substrate; and a gate electrode is formed on the gate insulating film and connected to one of the power line and the ground line.
[0014] Furthermore, the present invention provides an electrostatic discharge protection element, characterized in that it comprises: a semiconductor substrate of a first conductivity type; a high-concentration source region of a second conductivity type, formed along the surface of the semiconductor substrate, connected to one of a power line for transmitting power supply voltage and a ground line; a low-concentration source region of the second conductivity type, having an exposed surface exposed from the surface of the semiconductor substrate, connected to the high-concentration source region, and having a lower impurity concentration than the high-concentration source region; a high-concentration drain region of the second conductivity type, formed separately from the high-concentration source region and the low-concentration source region, along the surface of the semiconductor substrate, connected to the other of the power line and the ground line; and a low-concentration drain region of the second conductivity type. A high-concentration drain region, formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region; a gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate; a gate electrode is formed on the gate insulating film and is connected to one of the power line and the ground line; and a second conductivity type well region is formed on the bottom surface of the low-concentration drain region, and has a lower impurity concentration than the high-concentration drain region.
[0015] This invention provides a semiconductor device, characterized in that it comprises: a power line and a ground line for transmitting a power supply voltage; a semiconductor substrate of a first conductivity type; an internal circuit formed on the semiconductor substrate, which operates using the power supply voltage transmitted via the power line and the ground line; and an electrostatic discharge (ESD) protection element formed on the semiconductor substrate, the ESD protection element having: a high-concentration source region of a second conductivity type formed along the surface of the semiconductor substrate and connected to one of the power line and the ground line; a low-concentration source region of the second conductivity type having an exposed surface exposed from the surface of the semiconductor substrate, connected to the high-concentration source region, and having a lower impurity concentration than the high-concentration source region; and a high-concentration drain region of the second conductivity type connected to the high-concentration source region and the ground line. A low-concentration source region is formed separately along the surface of the semiconductor substrate and connected to the other of the power line and the ground line; a low-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, has a lower impurity concentration than the high-concentration drain region, and extends to a region deeper from the surface of the semiconductor substrate than the low-concentration source region; a gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region respectively, and on the region between the exposed surfaces on the surface of the semiconductor substrate; and a gate electrode is formed on the gate insulating film and connected to one of the power line and the ground line.
[0016] Furthermore, the present invention provides a semiconductor device, characterized in that it comprises: a power line and a ground line for transmitting a power supply voltage; a semiconductor substrate of a first conductivity type; an internal circuit formed on the semiconductor substrate, which operates using the power supply voltage transmitted via the power line and the ground line; and an electrostatic discharge (ESD) protection element formed on the semiconductor substrate, the ESD protection element having: a high-concentration source region of a second conductivity type, formed along the surface of the semiconductor substrate and connected to one of the power line and the ground line; a low-concentration source region of a second conductivity type, having an exposed surface exposed from the surface of the semiconductor substrate, connected to the high-concentration source region, and having a lower impurity concentration than the high-concentration source region; and a high-concentration drain region of a second conductivity type, connected to both the high-concentration source region and the low-concentration source region. A region is formed separately along the surface of the semiconductor substrate and connected to one of the power line and the ground line; a low-concentration drain region of a second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region; a gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate; a gate electrode is formed on the gate insulating film and connected to one of the power line and the ground line; and a well region of a second conductivity type is formed on the bottom surface of the low-concentration drain region and has a lower impurity concentration than the high-concentration drain region.
[0017] Invention Effects
[0018] In this invention, when a high voltage caused by ESD is applied, the parasitic bipolar transistor that exists between the source and drain regions of the MOS transistor, which serves as an electrostatic protection element, breaks down. As a result, the current associated with ESD flows into this parasitic transistor instead of into the internal circuitry, thereby preventing electrostatic damage to the internal circuitry.
[0019] Furthermore, in this invention, the current path implemented by the parasitic transistor that causes current flow associated with ESD is extended in the depth direction of the semiconductor substrate. As a result, the current density of the current path implemented by the parasitic transistor formed in the region directly beneath the gate oxide film of the MOS transistor becomes lower, and the threshold current causing the Kirk effect during the breakdown of the parasitic transistor becomes correspondingly higher. That is, the Kirk effect is difficult to generate, and as a result, the decrease in the holding voltage between the collector and emitter of the parasitic transistor associated with the Kirk effect is suppressed. Therefore, even if a power supply voltage is applied after ESD termination, a large current will not flow into the parasitic transistor.
[0020] Therefore, according to the present invention, by using a single MOS transistor as an electrostatic protection element, it is possible to prevent not only damage to the internal circuit caused by EDS, but also damage to the transistor itself after ESD termination, without increasing the occupied area or causing insufficient power supply to the internal circuit. Attached Figure Description
[0021] Figure 1 This is a circuit diagram that schematically shows the circuit formed in the semiconductor IC chip 100, which is the semiconductor device of the present invention.
[0022] Figure 2A This is a top view of the transistor 10 as seen from above the semiconductor IC chip 100.
[0023] Figure 2B It means Figure 2A A cross-sectional view of the transistor 10 with the W-W line.
[0024] Figure 3 It is a diagram that symbolizes the parasitic transistor in transistor 10 and represents it in a cross-sectional view of transistor 10.
[0025] Figure 4 It means Figure 2A Cross-sectional views of other sections of transistor 10 along the W-W line. Detailed Implementation
[0026] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
[0027] Figure 1 This is a circuit diagram that schematically shows the circuit formed in the semiconductor IC chip 100, which is the semiconductor device of the present invention.
[0028] The semiconductor IC chip 100 includes an internal circuit UC that performs the main functions and an n-channel MOS (Metal-Oxide-Semiconductor) transistor 10 that serves as an electrostatic discharge (ESD) protection element of the present invention. Furthermore, the semiconductor IC chip 100 includes pads Pd1 and Pd2 that receive power supply voltage from an external source, and a power line VL and a ground line GL that transmit the power supply voltage received by the pads Pd1 and Pd2. The internal circuit UC operates using the power supply voltage transmitted via the power line VL and the ground line GL.
[0029] In addition, such as Figure 1 As shown, the drain of transistor 10 is connected to the power supply line VL, and the gate and source are both connected to the ground line GL.
[0030] The structure of transistor 10 will be described below.
[0031] Figure 2A This is a top view of the transistor 10 as seen from above the semiconductor IC chip 100. Figure 2B It is along Figure 2A A cross-sectional view of the W-W line in the diagram.
[0032] like Figure 2B As shown, transistor 10 is formed on semiconductor substrate 11 made of P-type Si (silicon).
[0033] Near the surface of the semiconductor substrate 11, there are N-type high-concentration source regions 12s that serve as source regions of transistor 10 and N-type low-concentration source regions 13s with lower impurity concentrations than the high-concentration source regions 12s.
[0034] The upper surface of the high-concentration source region 12s is exposed from the surface of the semiconductor substrate 11, and a grounding wire GL is connected to the contact Ct disposed on its upper surface.
[0035] The low-concentration source region 13s has an exposed surface that is exposed from the surface of the semiconductor substrate 11, and is connected to the high-concentration source region 12s in such a way that it covers the side and bottom surfaces of the high-concentration source region 12s within the region of the semiconductor substrate 11.
[0036] In addition, an N-type high-concentration drain region 12d serving as the drain region of the transistor 10 and an N-type low-concentration drain region 13d with a lower impurity concentration than the high-concentration drain region 12d are formed near the surface of the semiconductor substrate 11.
[0037] The upper surface of the high-concentration drain region 12d is exposed from the surface of the semiconductor substrate 11, and a power line VL is connected to the contact Ct located on its upper surface.
[0038] The low-concentration drain region 13d has an exposed surface that is exposed from the surface of the semiconductor substrate 11, and is connected to the high-concentration drain region 12d in such a way that it covers the side and bottom surfaces of the high-concentration drain region 12d within the area of the semiconductor substrate 11.
[0039] In addition, such as Figure 2B As shown, a gate insulating film 14 is formed on the exposed surfaces of the low-concentration source region 13s and the low-concentration drain region 13d, and in the region between the exposed surfaces on the surface of the semiconductor substrate 11. A gate electrode 15 is formed on the gate oxide film 14. A ground line GL is connected to the gate electrode 15.
[0040] In addition, an element separation insulating film 20 with an STI (shallow trench isolation) structure is formed by forming the regions with the above-mentioned high-concentration source region 12s, high-concentration drain region 12d, low-concentration source region 13s and low-concentration drain region 13d in a ring shape.
[0041] Additionally, a P-type high-concentration diffusion layer 21 is formed on a portion of the outer periphery of the annular element separation insulating film 20 near the surface of the semiconductor substrate 11. A ground line GL is connected to the high-concentration diffusion layer 21, and a ground potential is applied to the back gate of the transistor 10 via the ground line GL and the high-concentration diffusion layer 21.
[0042] Furthermore, such as Figure 2B As shown, an N-type n-well 30 with a lower impurity concentration than the high-concentration drain region 12d is formed on the bottom surface of the low-concentration drain region 13d within the region of the semiconductor substrate 11.
[0043] Here, n-well 30 is as follows Figure 2B As shown, the side S1 of itself extends towards the source region (12s, 13s) compared to the side S2 opposite to the high-concentration source region 12s of the high-concentration drain region 12d.
[0044] The following uses Figure 3 To Figure 1 , Figure 2A as well as Figure 2B The electrostatic discharge protection action performed by the transistor 10 shown will be explained.
[0045] Figure 3 It is a diagram that symbolizes and represents the bipolar parasitic transistor that is parasitic between the drain and source of transistor 10 in a cross-sectional view of transistor 10.
[0046] First, such as Figure 1 As shown, when a high voltage is applied between pads Pd1 and Pd2 using ESD generated near the semiconductor IC chip 100, the parasitic bipolar transistor parasitic between the drain and source of the MOS transistor 10 is broken down.
[0047] Next, as Figure 3 As shown, in transistor 10, a bipolar parasitic transistor is formed between the low-concentration source region 13s and the low-concentration drain region 13d, and a bipolar parasitic transistor is also formed between the low-concentration source region 13s and the low-concentration drain region 13d via n-well 30.
[0048] When the aforementioned parasitic transistor breaks down, the discharge current associated with ESD flows from the power line VL through a current path consisting of the high-concentration drain region 12d, the low-concentration drain region 13d, the region near the surface of the semiconductor substrate 11, the low-concentration source region 13s, and the high-concentration source region 12s to the ground line GL. Furthermore, this discharge current flows to the ground line GL through a current path consisting of the high-concentration drain region 12d, the low-concentration drain region 13d, the n-well 30, the region of the semiconductor substrate 11 that exits from the surface, the low-concentration source region 13s, and the high-concentration source region 12s.
[0049] Therefore, the current associated with ESD does not flow into the internal circuit UC, but instead flows into... Figure 3 The current path implemented by the bipolar parasitic transistor shown prevents electrostatic damage to the internal circuit UC.
[0050] Here, in transistor 10, the current path during parasitic transistor breakdown extends into the depth direction of semiconductor substrate 11 by utilizing the n-well 30 formed on the bottom surface of the low-concentration drain region 13d. Consequently, the current density of the current path realized by the parasitic transistor formed in the region directly below the gate oxide film 14 is lower. As a result, the threshold of the current causing the Kirk effect is higher compared to the current flowing through this parasitic transistor between the high-concentration drain region 12d and the high-concentration source region 12s. Therefore, compared to the case where the n-well 30 is not formed on the bottom surface of the low-concentration drain region 13d, the Kirk effect is less likely to occur, and as a result, the decrease in the collector-emitter holding voltage of the parasitic transistor associated with the Kirk effect is suppressed.
[0051] Therefore, after ESD termination, even though the normal power supply voltage is applied to transistor 10 via power line VL and ground line GL, the inflow of large current to the parasitic transistor is prevented. Thus, after ESD termination, the current based on the power supply voltage does not flow into the parasitic transistor but is supplied to the internal circuit UC. Therefore, the insufficient power supply to the internal circuit UC is resolved, and damage to transistor 10, which is an electrostatic protection element, is prevented.
[0052] In this way, by using a single transistor 10 as an electrostatic protection element, it is possible to prevent damage to the internal circuit UC caused by ESD and damage to the electrostatic protection element (transistor 10) itself after ESD termination without increasing the occupied area or causing insufficient power supply to the internal circuit.
[0053] Furthermore, in transistor 10, such as Figure 2BAs shown, along the direction of the surface of the semiconductor substrate 11, the shortest distance L1 from the boundary of the region of the semiconductor substrate 11 and the low-concentration drain region 13d to the high-concentration drain region 12d is made larger than the shortest distance L2 from the boundary of the region of the semiconductor substrate 11 and the low-concentration source region 13s to the high-concentration source region 12s.
[0054] At this point, the larger the distance L1, the better. Figure 3 As the resistance in the current path of the parasitic transistor increases, the threshold voltage for the Kirk effect also increases, thus suppressing the decrease in the holding voltage between the collector and emitter of the parasitic transistor associated with the Kirk effect. Therefore, it is possible to more reliably prevent insufficient power supply to the internal circuit UC after ESD termination and damage to the electrostatic protection element (10).
[0055] In addition, Figure 2B In one example shown, an n-well 30 is provided to extend the current path during breakdown into the depth direction of the semiconductor substrate 11. However, it is also possible not to form an n-well 30 separately, but to extend the low-concentration drain region itself into the depth direction of the semiconductor substrate 11.
[0056] Figure 4 It shows the path taken along that point. Figure 2A A cross-sectional view of the structure of transistor 10 with W-W lines.
[0057] In addition, Figure 4 The structure shown is identical to the previous one except for the use of a low-concentration drain region 23d instead of a low-concentration drain region 13d and an n-well 30. Figure 2B The structures shown are the same. Therefore, the following... Figure 4 The structure of the low-concentration drain region 23d shown is explained.
[0058] Like the low-concentration drain region 13d, the low-concentration drain region 23d has an exposed surface that protrudes from the surface of the semiconductor substrate 11, and is connected to the high-concentration drain region 12d in such a way that it covers the side and bottom surfaces of the high-concentration drain region 12d within the area of the semiconductor substrate 11.
[0059] However, as Figure 4 As shown, the depth h1 of the low-concentration drain region 23d from the surface to the bottom of the semiconductor substrate 11 is deeper than the depth h2 of the low-concentration source region 13s from the surface to the bottom of the semiconductor substrate 11. That is, the low-concentration drain region 23d extends within the semiconductor substrate 11 to a region where the depth from the surface of the semiconductor substrate 11 is deeper than that of the low-concentration source region 13s.
[0060] Therefore, compared to the case where the depth of the low-concentration drain region is equal to the depth h2 of the low-concentration source region 13s, the current path during breakdown of the parasitic bipolar transistor in the MOS transistor 10 extends towards the depth of the semiconductor substrate 11. Consequently, the current density of the current path realized by the parasitic transistor formed near the gate oxide film 14 decreases, and the threshold of the current causing the Kirk effect increases accordingly.
[0061] Therefore, compared to the case where the depth of the low-concentration drain region is equal to the depth of the low-concentration source region 13s, it is difficult for the Kirk effect to occur. As a result, the decrease in the holding voltage between the collector and emitter of the parasitic transistor associated with the Kirk effect is suppressed.
[0062] Therefore, after ESD termination, even if the normal power supply voltage is applied to transistor 10 via power line VL and ground line GL, the inflow of large current to the parasitic transistor is prevented.
[0063] Therefore, after adopting Figure 4 In the case of the structure shown, it is also similar to the one that uses Figure 2B Similarly, in the case of the structure shown, by using a single transistor 10 as an electrostatic protection element, it is possible not only to prevent damage to the internal circuit UC associated with electrostatic discharge without increasing the occupied area or causing insufficient power supply to the internal circuit, but also to prevent damage to itself after ESD termination.
[0064] Furthermore, in the above embodiment, a structure is shown in which the MOS-type transistor 10 is formed on a P-type conductive semiconductor substrate 11, but it can also be formed on an N-type conductive semiconductor substrate in the same way. Alternatively, the transistor 10 can be formed in an N-type well region formed on a P-type semiconductor substrate or in a P-type well region formed on an N-type semiconductor substrate.
[0065] In summary, the transistor 10, which serves as an electrostatic protection element, can be any transistor having a first conductivity type semiconductor substrate, a high-concentration source region and a low-concentration source region of a second conductivity type, a high-concentration drain region and a low-concentration drain region of a second conductivity type, a gate insulating film, and a gate electrode.
[0066] That is, a high-concentration source region (12s) is formed along the surface of the semiconductor substrate (11) and is connected to one of a power line (VL) for transmitting power supply voltage and a ground line (GL). A low-concentration source region (13s) is a region with a lower impurity concentration than the high-concentration source region, has an exposed surface that protrudes from the surface of the semiconductor substrate, and is connected to the high-concentration source region. A high-concentration drain region (12d) is formed separately from these high-concentration and low-concentration source regions along the surface of the semiconductor substrate and is connected to the other of a power line for transmitting power supply voltage and a ground line. A low-concentration drain region (23d) is a region that is formed separately from the high-concentration and low-concentration source regions, has an exposed surface that protrudes from the surface of the semiconductor substrate, is connected to the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region. A gate insulating film (14) is formed on the surface of the semiconductor substrate and on the exposed surfaces of the low-concentration source region and the low-concentration drain region, respectively. A gate electrode (15) is formed on a gate insulating film and is connected to either a power line or a ground line. Furthermore, the depth (h1) of the low-concentration drain region (23d) from the surface of the semiconductor substrate is deeper than the depth (h2) of the low-concentration source region (13s) from the surface of the semiconductor substrate. That is, the low-concentration drain region extends into a region of the semiconductor substrate deeper than the low-concentration source region from the surface of the semiconductor substrate.
[0067] Alternatively, the transistor 10, which serves as an electrostatic discharge protection element, may also be a transistor having a first conductivity type semiconductor substrate, a high-concentration source region and a low-concentration source region of a second conductivity type, a high-concentration drain region and a low-concentration drain region of a second conductivity type, a well region of a second conductivity type, a gate insulating film, and a gate electrode.
[0068] That is, a high-concentration source region (12s) is formed along the surface of the semiconductor substrate (11) and is connected to one of a power line (VL) for transmitting power supply voltage and a ground line (GL). A low-concentration source region (13s) is a region with a lower impurity concentration than the high-concentration source region, has an exposed surface that protrudes from the surface of the semiconductor substrate, and is connected to the high-concentration source region. A high-concentration drain region (12d) is formed separately from these high-concentration and low-concentration source regions along the surface of the semiconductor substrate and is connected to the other of a power line for transmitting power supply voltage and a ground line. A low-concentration drain region (23d) is a region that is formed separately from the high-concentration and low-concentration source regions, has an exposed surface that protrudes from the surface of the semiconductor substrate, is connected to the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region. A well region (30) is formed on the bottom surface of the low-concentration drain region (13d) and has a lower impurity concentration than the high-concentration drain region.
[0069] Symbol Explanation
[0070] 10 transistors
[0071] 12d high-concentration drain region
[0072] 12s high-concentration source region
[0073] 13d low-concentration drain region
[0074] 13s low-concentration source region
[0075] 30 n-well.
Claims
1. An electrostatic discharge protection element, characterized in that, have: First conductivity type semiconductor substrate; A high-concentration source region of the second conductivity type is formed along the surface of the semiconductor substrate and is connected to one of a power line that transmits power supply voltage and a ground line. The low-concentration source region of the second conductivity type has an exposed surface that is exposed from the surface of the semiconductor substrate, is in contact with the high-concentration source region, and has a lower impurity concentration than the high-concentration source region. The first element is a separation insulating film, which is disposed next to the high-concentration source region and the low-concentration source region and is grounded to their respective surfaces; The high-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region along the surface of the semiconductor substrate and is connected to the other of the power line and the ground line. The low-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, has a lower impurity concentration than the high-concentration drain region, and extends to a region at a depth from the surface of the semiconductor substrate that is deeper than the low-concentration source region. The second element is a separation insulating film, which is disposed next to the high-concentration drain region and the low-concentration drain region and is grounded to their respective surfaces; A gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate. as well as A gate electrode, formed on the gate insulating film, is connected to one of the power supply line and the ground line. The first element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration source region. The low-concentration drain region is directly connected to the semiconductor substrate at a depth greater than that of the insulating film separating the second element.
2. The electrostatic protection element according to claim 1, characterized in that, The distance from the boundary between the low-concentration drain region and the region of the semiconductor substrate to the high-concentration drain region along the surface of the semiconductor substrate is greater than the distance from the boundary between the low-concentration source region and the region of the semiconductor substrate to the high-concentration source region along the surface of the semiconductor substrate.
3. An electrostatic discharge protection element, characterized in that, have: First conductivity type semiconductor substrate; A high-concentration source region of the second conductivity type is formed along the surface of the semiconductor substrate and is connected to one of a power line that transmits power supply voltage and a ground line. The low-concentration source region of the second conductivity type has an exposed surface that is exposed from the surface of the semiconductor substrate, is in contact with the high-concentration source region, and has a lower impurity concentration than the high-concentration source region. The first element is a separation insulating film, which is disposed next to the high-concentration source region and the low-concentration source region and is grounded to their respective surfaces; The high-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region along the surface of the semiconductor substrate and is connected to the other of the power line and the ground line. The low-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region. A gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate. A gate electrode is formed on the gate insulating film and is connected to one of the power line and the ground line; A second conductivity type well region is formed on the bottom surface of the low concentration drain region, and the impurity concentration is lower than that of the high concentration drain region. as well as The second element, a separating insulating film, is disposed adjacent to the high-concentration drain region, the low-concentration drain region, and the well region, and is grounded to their respective surfaces. The first element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration source region. The second element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration drain region. The well region is in direct contact with the semiconductor substrate at a depth greater than that of the second element separation insulating film within the semiconductor substrate, and the distance from the boundary between the low-concentration drain region and the region of the semiconductor substrate to the high-concentration drain region along the surface of the semiconductor substrate is greater than the distance from the boundary between the low-concentration source region and the region of the semiconductor substrate to the high-concentration source region along the surface of the semiconductor substrate.
4. The electrostatic protection element according to claim 3, characterized in that, One of the sides of the trap region extends toward the high-concentration source region, relative to the side of the high-concentration drain region that is opposite to the high-concentration source region.
5. The electrostatic protection element according to claim 3 or 4, characterized in that, The distance from the boundary between the low-concentration drain region and the region of the semiconductor substrate to the high-concentration drain region along the surface of the semiconductor substrate is greater than the distance from the boundary between the low-concentration source region and the region of the semiconductor substrate to the high-concentration source region along the surface of the semiconductor substrate.
6. The electrostatic protection element according to claim 4, characterized in that, The side of the low-concentration drain region protrudes toward the high-concentration source region compared to one side of the trap region.
7. A semiconductor device, characterized in that, Include: Power lines that transmit power voltage and grounding wires; First conductivity type semiconductor substrate; The internal circuitry is formed on the semiconductor substrate and operates using the power supply voltage transmitted via the power supply line and the ground line. as well as An electrostatic discharge (ESD) protection element is formed on the semiconductor substrate. The electrostatic protection element has the following characteristics: A high-concentration source region of the second conductivity type is formed along the surface of the semiconductor substrate and is connected to one of a power line that transmits power supply voltage and a ground line. The low-concentration source region of the second conductivity type has an exposed surface that is exposed from the surface of the semiconductor substrate, is in contact with the high-concentration source region, and has a lower impurity concentration than the high-concentration source region. The first element is a separation insulating film, which is disposed next to the high-concentration source region and the low-concentration source region and is grounded to their respective surfaces; The high-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region along the surface of the semiconductor substrate and is connected to the other of the power line and the ground line. The low-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, has a lower impurity concentration than the high-concentration drain region, and extends to a region at a depth from the surface of the semiconductor substrate that is deeper than the low-concentration source region. A gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate. A gate electrode is formed on the gate insulating film and is connected to one of the power line and the ground line; as well as The second element, a separating insulating film, is disposed adjacent to the high-concentration drain region and the low-concentration drain region and is grounded to their respective surfaces. The first element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration source region. The low-concentration drain region is directly connected to the semiconductor substrate at a depth greater than that of the insulating film separating the second element.
8. A semiconductor device, characterized in that, Include: Power lines that transmit power voltage and grounding wires; First conductivity type semiconductor substrate; The internal circuitry is formed on the semiconductor substrate and operates using the power supply voltage transmitted via the power supply line and the ground line. as well as An electrostatic discharge (ESD) protection element is formed on the semiconductor substrate. The electrostatic protection element has the following characteristics: A high-concentration source region of the second conductivity type is formed along the surface of the semiconductor substrate and is connected to one of a power line that transmits power supply voltage and a ground line. The low-concentration source region of the second conductivity type has an exposed surface that is exposed from the surface of the semiconductor substrate, is in contact with the high-concentration source region, and has a lower impurity concentration than the high-concentration source region. The first element is a separation insulating film, which is disposed next to the high-concentration source region and the low-concentration source region and is grounded to their respective surfaces; The high-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region along the surface of the semiconductor substrate and is connected to the other of the power line and the ground line. The low-concentration drain region of the second conductivity type is formed separately from the high-concentration source region and the low-concentration source region, has an exposed surface exposed from the surface of the semiconductor substrate, is in contact with the high-concentration drain region, and has a lower impurity concentration than the high-concentration drain region. A gate insulating film is formed on the exposed surfaces of the low-concentration source region and the low-concentration drain region, and on the region between the exposed surfaces on the surface of the semiconductor substrate. A gate electrode is formed on the gate insulating film and is connected to one of the power line and the ground line; A second conductivity type well region is formed on the bottom surface of the low concentration drain region, and the impurity concentration is lower than that of the high concentration drain region. as well as The second element, a separating insulating film, is disposed adjacent to the high-concentration drain region, the low-concentration drain region, and the well region, and is grounded to their respective surfaces. The first element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration source region. The second element separation insulating film extends from the surface of the semiconductor substrate to a region deeper than the low-concentration drain region. The well region is in direct contact with the semiconductor substrate at a depth greater than that of the insulating film separating the second element.