Post driver with voltage protection

Abstract

Embodiments of the present application disclose a post driver with voltage protection, which includes an input pair circuit, a protection circuit, a common mode sensing circuit and an amplifier. The input pair circuit outputs a first signal from a first node and a second signal from a second node according to a first input signal and a second input signal. The protection circuit provides voltage protection for the input pair circuit according to a plurality of first bias voltages and a second bias voltage, and transmits the first signal to a first load to generate a first output signal and transmits the second signal to a second load to generate a second output signal. The common mode sensing circuit senses a level of the first node and a level of the second node to generate a feedback signal. The amplifier generates the second bias voltage according to a reference voltage and the feedback signal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of post driver, and particularly relates to a post driver with voltage protection. BACKGROUND

[0002] Post drivers are commonly used in transmitters, which can be used to output differential signals with large swing. In actual applications, due to the limited types of transistors that can be provided by the process, transistors with low voltage resistance may need to be used to implement the post driver. However, these transistors may be damaged due to large voltage difference, so that the operation of the post driver appears to be wrong. SUMMARY

[0003] The embodiments of the present application provide a post driver with voltage protection.

[0004] In some embodiments, the post driver includes an input pair circuit, a protection circuit, a common mode sensing circuit, and an amplifier. The input pair circuit outputs a first signal from a first node and a second signal from a second node according to a first input signal and a second input signal. The protection circuit provides voltage protection for the input pair circuit according to a plurality of first bias voltages and a second bias voltage, and transmits the first signal to a first load to generate a first output signal and transmits the second signal to a second load to generate a second output signal. The common mode sensing circuit senses the level of the first node and the level of the second node to generate a feedback signal. The amplifier generates the second bias voltage according to a reference voltage and the feedback signal.

[0005] In some embodiments, the post driver includes a plurality of drive circuits, a common mode sensing circuit, and an amplifier. The plurality of drive circuits generates a first output signal via a first load and a second output signal via a second load according to a plurality of sets of input signals, wherein each of the plurality of drive circuits includes an input pair circuit and a protection circuit. The input pair circuit outputs a first signal via a first node and a second signal via a second node according to a first input signal and a second input signal of a corresponding one of the plurality of sets of input signals. The protection circuit is turned on to provide a voltage protection for the input pair circuit according to a plurality of first bias voltages and a second bias voltage, and transmits the first signal to the first load and transmits the second signal to the second load. The common mode sensing circuit generates a feedback signal according to the level of the first node of a corresponding one of the plurality of drive circuits and the level of the second node of the corresponding one of the plurality of drive circuits. The amplifier generates the second bias voltage according to a reference voltage and the feedback signal.

[0006] The post driver in some embodiments of the present application can utilize a feedback control method to generate a proper bias to ensure that the transistors in the post driver will not be damaged. In this way, the post driver can be implemented using transistors of a low voltage process.

[0007] The features, implementations, and effects of the present application will be described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort based on these drawings.

[0009] Figure 1 A schematic diagram of a post driver according to some embodiments of the present application;

[0010] Figure 2 A schematic diagram of a post driver according to some embodiments of the present application; and

[0011] Figure 3 A schematic diagram of a post driver according to some embodiments of the present application. DETAILED DESCRIPTION

[0012] All the terms used herein have their usual meanings. The definitions of the above terms in the commonly used dictionaries are included in the content of the present application, and the use examples of any of the terms discussed herein are only examples and should not limit the scope and meaning of the present application. Similarly, the present application is not limited to the various embodiments shown in the specification.

[0013] As for the "coupling" or "connection" used herein, it can mean that two or more components are in direct physical or electrical contact with each other, or are indirectly in physical or electrical contact with each other, or can mean that two or more components operate or act on each other. As used herein, the term "circuit" can be a device that processes signals by connecting at least one transistor and / or at least one active or passive component in a certain manner.

[0014] Figure 1 A schematic diagram of a post driver 100 according to some embodiments of the present application. In some embodiments, the post driver 100 can be applied to (but not limited to) a transmitter.

[0015] The post driver 100 includes an input pair circuit 110, a protection circuit 120, a common mode sensing circuit 130, and an amplifier 140. The input pair circuit 110 is biased by a current source circuit 105 and outputs a signal S1 from a node N1 and a signal S2 from a node N2 according to an input signal VIP and an input signal VIN. In some embodiments, the input pair circuit 110 can include a transistor Ml and a transistor M2. A first end (e.g., a source) of the transistor Ml is coupled to the node N1 and outputs the signal S1, a second end (e.g., a drain) of the transistor Ml is coupled to ground via the current source circuit 105, and a control end (e.g., a gate) of the transistor Ml receives the input signal VIP. A first end of the transistor M2 is coupled to the node N2 and outputs the signal S2, a second end of the transistor M2 is coupled to the second end of the transistor Ml, and a control end of the transistor M2 receives the input signal VIN. In some embodiments, the input signal VIP and the input signal VIN can be, but are not limited to, a set of signals output from a pre-driver in a transmitter. In some embodiments, the set of signals can be, but are not limited to, differential signals.

[0016] The protection circuit 120 is coupled to the input pair circuit 110 and operates according to a plurality of bias voltages VB1P, VB1N, and VB to provide voltage protection for the input pair circuit 110. The protection circuit 120 further transmits the signal S1 to a load RL1 to generate an output signal VOP and transmits the signal S2 to a load RL2 to generate an output signal VON. In some embodiments, the bias voltage VB1P and the bias voltage VB1N can be voltages having the same level.

[0017] In some embodiments, the protection circuit 120 includes a plurality of transistors M3-M6. A first end of the transistor M3 is coupled to the load RL1 to generate the output signal VOP, a second end of the transistor M3 is coupled to a first end of the transistor M5, and a control end of the transistor M3 receives the bias voltage VB1P. The transistor M3 can be biased by the bias voltage VB1P and generate the output signal VOP. A second end of the transistor M5 is coupled to a first end of the transistor Ml to receive the signal S1, and a control end of the transistor M5 receives the bias voltage VB. The transistor M5 can be biased by the bias voltage VB and receive the signal S1 from the input pair circuit 110. A first end of the transistor M4 is coupled to the load RL2 to generate the output signal VON, a second end of the transistor M4 is coupled to a first end of the transistor M6, and a control end of the transistor M4 receives the bias voltage VB1N. The transistor M4 can be biased by the bias voltage VB1N and generate the output signal VON. A second end of the transistor M6 is coupled to a first end of the transistor M2 to receive the signal S2, and a control end of the transistor M6 receives the bias voltage VB. The transistor M6 can be biased by the bias voltage VB and receive the signal S2 from the input pair circuit 110.

[0018] like Figure 1 As shown, input pair circuit 110 receives the supply voltage VDD via protection circuit 120, load RL1, and load RL2. Input pair circuit 110 and protection circuit 120 can be powered by the supply voltage VDD. With the above arrangement, in some embodiments, the voltage rating of the transistors (e.g., the aforementioned plurality of transistors M1 to M6) included in each of the input pair circuit 110 and protection circuit 120 is lower than the supply voltage VDD. For example, the supply voltage VDD is approximately 3.3 volts, each of the plurality of transistors M3 to M6 can be an input / output (I / O) transistor with a voltage rating of 1.8 volts, while the plurality of transistors M1 and M2 can be core transistors with a voltage rating of 1.8 volts. Generally, the voltage rating of an I / O transistor with a voltage rating of 1.8 volts is approximately lower than 1.8 volts (or lower than 1.98 volts), and the voltage rating of the core transistor is lower than the voltage rating of the I / O transistor. Therefore, to avoid damage to transistors M1 and M2, a stacked structure formed by multiple transistors M3 to M6 can be used to withstand the supply voltage VDD.

[0019] Common-mode sensing circuit 130 senses the level of node N1 (hereinafter referred to as voltage VN1) and the level of node N2 (hereinafter referred to as voltage VN2) to generate a feedback signal VFB. In some embodiments, common-mode sensing circuit 130 is used to extract the common-mode level between voltage VN1 and voltage VN2. For example, the feedback signal VFB may be half the sum of voltage VN1 and voltage VN2. In some embodiments, common-mode sensing circuit 130 may include resistive component 131 and resistive component 132, which can divide voltage VN2 to generate feedback signal VFB. A first terminal of resistive component 131 is coupled to node N2 to receive voltage VN2. A first terminal of resistive component 132 is coupled to a second terminal of resistive component 131 and generates feedback signal VFB. A second terminal of resistive component 132 is coupled to node N1 to receive voltage VN1. In some embodiments, each of resistive component 131 and resistive component 132 may be implemented by a passive component. For example, the passive component may be (but is not limited to) a polysilicon resistor. In some embodiments, each of resistive component 131 and resistive component 132 may be implemented by an active component. For example, the active component may be (but is not limited to) a transistor.

[0020] In some optional embodiments, the common-mode sensing circuit 130 further includes a capacitive component C (drawn in dashed lines to indicate that it is optional) coupled between a first terminal of the resistive component 132 and ground. The capacitive component C can operate as a filter capacitor to make the feedback signal VFB more stable.

[0021] The negative input of the amplifier 140 is coupled to the common-mode sensing circuit 130 to receive a feedback signal VFB. The positive input of the amplifier 140 receives a reference voltage VREF. The amplifier 140 generates a bias voltage VB according to the reference voltage VREF and the feedback signal VFB. Ideally, the reference voltage VREF is identical to the feedback voltage VFB (e.g., VREF = VFB = (VN1 + VN2) / 2). If the voltage VN1 and / or the voltage VN2 changes, the feedback signal VFB also changes. The amplifier 140 can adjust the bias voltage VB in response to the change of the feedback signal VFB to restore the voltage VN1 and / or the voltage VN2 to a preset level. In this way, the voltage VN1 and / or the voltage VN2 can be prevented from being too high to damage the transistors M1 and M2.

[0022] In some embodiments, the reference voltage VREF is set to be slightly higher than or identical to half of the voltage withstand value of the core transistors (i.e., the transistors M1 and / or the transistors M2). In an extreme case, if the transistor M1 is turned on according to the input signal VIP and the transistor M2 is turned off according to the input signal VIN, the voltage VN1 is pulled to a low level by the current source circuit 105, and the voltage VN2 has a highest level. By setting the protection circuit 120, the common-mode sensing circuit 130, and the amplifier 140, the level of the voltage VN2 can be clamped to a certain level, which can be determined by the reference voltage VREF and the voltage VN1. For example, the certain level can be represented as 2xVREF-VN1. Because the current source circuit 105 usually operates in the saturation region, the voltage VN1 can be higher than 0 volt under various variations (e.g., process variation, voltage variation, temperature variation, etc.). In this way, the certain level will be lower than the voltage withstand value to ensure that the transistor M2 is not damaged.

[0023] In some related arts, a current mirror circuit with a similar setting as the post driver is used to generate multiple bias voltages in an attempt to properly bias the post driver under various variations. However, in these related arts, the connection relationship of the transistors in the current mirror circuit is not exactly the same as the connection relationship of the transistors in the post driver, so the generated bias voltages and the variations affecting the post driver cannot achieve a completely linear change. Furthermore, there are transistors connected in a diode-connected manner and resistors in the current mirror circuit, which are coupled between the node providing the supply voltage and the ground, so a certain current is fixedly generated to cause additional power consumption. If the power consumption is to be reduced, the resistance value of the resistors needs to be increased. In this way, the circuit area will be significantly increased.

[0024] In some embodiments of the present application, the voltage level (e.g., the voltage VN1 and the voltage VN2) at the internal nodes of the input circuit 110 is used to perform feedback control to ensure that the post driver 100 can be biased more accurately under the influence of various variations and to ensure that the voltage across each of the transistors M1-M6 does not exceed its voltage rating. In addition, the fixed current (if any) generated by the common-mode sensing circuit 130 and the amplifier 140 can be lower than the fixed current generated by the current mirror circuit used in the above techniques, and thus can have lower power consumption.

[0025] Figure 2 A schematic diagram of a post driver 200 according to some embodiments of the present application is shown. Compared to the post driver 100 shown in FIG. 1, the post driver 200 further includes a switching circuit 250. Figure 1 In this example, the post driver 200 further includes a switching circuit 250. The switching circuit 250 selectively outputs the bias voltage VB or a fixed voltage (e.g., the bias voltage VB2P and the bias voltage VB2N) to the protection circuit 120.

[0026] In detail, the switching circuit 250 includes a plurality of switches SW1-SW4. The switch SW1 is coupled between the amplifier 140 and the control terminal of the transistor M5, and is selectively turned on according to the control signal S[l] to transmit the bias voltage VB to the transistor M5. The switch SW2 is coupled between the amplifier 140 and the control terminal of the transistor M6, and is selectively turned on according to the control signal S[l] to transmit the bias voltage VB to the transistor M6. The first terminal of the switch SW3 receives the bias voltage VB2P, and the second terminal of the switch SW3 is coupled to the control terminal of the transistor M5. The switch SW3 is selectively turned on according to the control signal S[2] to transmit the bias voltage VB2P to the transistor M5. The first terminal of the switch SW4 receives the bias voltage VB2N, and the second terminal of the switch SW4 is coupled to the control terminal of the transistor M6. The switch SW4 is selectively turned on according to the control signal S[2] to transmit the bias voltage VB2N to the transistor M6. In some embodiments, the bias voltage VB2N and the bias voltage VB2P can be voltages having the same voltage level. In some embodiments, the bias voltages VB1N, VB1P, VB2N, and VB2P can be generated by dividing the supply voltage VDD.

[0027] In some embodiments, the control signal S[l] and the control signal S[2] have opposite logic values, such that the plurality of switches SWl-SW2 and the plurality of switches SW3-SW4 have opposite conducting states. For example, when the plurality of switches SWl-SW2 are conducting, the plurality of switches SW3-SW4 are not conducting, and vice versa. By using the switching circuit 250, the adjustability of the post driver 200 can be increased. For example, when testing or adjusting, different bias voltages can be input to the protection circuit 120 by using the switching circuit 250. In some embodiments, when the post driver 200 enters the power saving mode, the current source circuit 105 is turned off to save power consumption. As a result, the voltage VNl and the voltage VN2 are increased. Under this condition, the switching circuit 250 can output a fixed voltage (e.g., the bias voltage VB2P and the bias voltage VB2N) to the protection circuit 120 to ensure that the transistor Ml and the transistor M2 are not damaged. That is, in the operation mode, the switching circuit 250 turns on the switches SWl-SW2 and turns off the switches SW3-SW4 to provide the bias voltage VB to the protection circuit 120, while in the power saving mode or the test mode, the switching circuit 250 turns on the switches SW3-SW4 and turns off the switches SWl-SW2 to output the fixed voltage to the protection circuit 120.

[0028] Figure 3 A schematic diagram of a post driver 300 according to some embodiments of the present application is shown. Compared to the example of the post driver 200 of Figure 1 or Figure 2 the post driver 300 can perform pre-emphasis or de-emphasis functions to meet the requirements of high speed data transmission applications.

[0029] The post driver 300 includes multi-stage drive circuits 310, 320 and 330. In some embodiments, the multi-stage drive circuits 310, 320 and 330 correspond to a plurality of taps, respectively, wherein the drive circuit 310 corresponds to a main tap among the taps. The multi-sets of input signals received by the drive circuits 310, 320 and 330 are input signal VIP[l] and input signal VIN[l], input signal VIP[2] and input signal VIN[2], and input signal VIP[3] and input signal VIN[3], in sequence. In some embodiments, there is a predetermined time difference between two of the input signal VIP[l], the input signal VIP[2] and the input signal VIP[3]. For example, the input signal VIP[l] can be denoted as VIP[t] (i.e., the input signal VIP at time t), the input signal VIP[2] can be denoted as VIP[t-l] (i.e., the input signal VIP at time t-l), and the input signal VIP[3] can be denoted as VIP[t+l] (i.e., the input signal VIP at time t+l). Alternatively, in another example, the input signal VIP[l] can be denoted as VIP[t], the input signal VIP[2] can be denoted as VIP[t-l], and the input signal VIP[3] can be denoted as VIP[t-2] (i.e., the input signal VIP at time t-2). The relationship between the input signal VIN[l], the input signal VIN[2] and the input signal VIN[3] can be referred to the relationship between the input signal VIP[l], the input signal VIP[2] and the input signal VIP[3], and thus will not be repeated here.

[0030] The drive circuits 310, 320 and 330 generate an output signal VOP via the load RLl and an output signal VON via the load RL2 according to the above-mentioned multi-sets of input signals. The circuit structure of each of the drive circuits 310, 320 and 330 can be referred to the post driver 100 of Figure 1 and thus will not be repeated here. The transistor sizes and / or the current of the current source circuits of each of the drive circuits 310, 320 and 330 are not the same. For example, since the drive circuit 310 corresponds to the main tap, the transistors Ml-M6 in the drive circuit 310 have the largest sizes (or the largest number of parallel connections) and the current source circuit 105 in the drive circuit 310 has the highest current, as compared to the other drive circuits 320 or 330.

[0031] In this example, the common mode sensing circuit 130 generates a feedback signal VFB according to the level of node Nl and the level of node N2 in the driving circuit 310 corresponding to the main tap to provide the feedback signal VFB to the amplifier 140 to generate the bias voltage VB. In other words, in this example, the plurality of driving circuits 310, 320 and 330 corresponding to the plurality of taps can share the common mode sensing circuit 130 and the amplifier 140. In addition, the output of the driving circuit 310 corresponding to the main tap is opposite to the outputs of the plurality of driving circuits 320 and 330 corresponding to the other taps. For example, as shown in FIG. 3, the positive output of the driving circuit 310 (corresponding to the first terminal of transistor M3) is coupled to the negative outputs of the plurality of driving circuits 320 and 330 to generate the output signal VOP via the load RLl, and the negative output of the driving circuit 310 (corresponding to the first terminal of transistor M4) is coupled to the positive outputs of the plurality of driving circuits 320 and 330 to generate the output signal VON via the load RL2. In other words, the positions of nodes Nl and N2 in the plurality of driving circuits 320 and 330 are opposite to the positions of nodes Nl and N2 in the driving circuit 310. Figure 3

[0032] The above description of the number of driving circuits is for example only, and the present application is not limited thereto. Depending on the actual application requirements, the number of taps required is different, and thus the number of driving circuits in the post driver 300 can be adjusted accordingly. In other embodiments, each of the plurality of driving circuits 310, 320 and 330 can further include the switching circuit 250 in FIG. 2 to increase the adjustability of the post driver 300. Figure 2

[0033] In summary, the post driver in some embodiments of the present application can use the feedback control method to generate a suitable bias voltage to ensure that the transistors in the post driver are not damaged. In this way, the post driver can be implemented using low-voltage process transistors. In addition, if the actual application requires pre-emphasis or de-emphasis functions, the post driver in some embodiments of the present application can use multiple stages of circuits to implement the multiple taps in the equalizer to achieve the above functions, and these stages of circuits can share some circuits to save circuit area.

[0034] Although the embodiments of the present application are described as above, these embodiments are not intended to limit the present application, and those skilled in the art can make changes to the technical features of the present application according to the explicit or implicit content of the present application, and any such changes can fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the scope of the patent application defined in the specification.

[0035] Symbol explanation:

[0036] ​​100, 200, 300: follower driver;

[0037] 105: current source circuit;

[0038] 110: input pair circuit;

[0039] 120: protection circuit;

[0040] 130: common-mode sensing circuit;

[0041] 131, 132: resistive component;

[0042] 140: amplifier;

[0043] 250: switching circuit;

[0044] 310, 320, 330: driver circuit;

[0045] C: capacitive component;

[0046] M1 ~ M6: transistor;

[0047] N1, N2: node;

[0048] RL1, RL2: load;

[0049] S[1], S[2]: control signal;

[0050] S1, S2: signal;

[0051] SW1 ~ SW4: switch;

[0052] VB, VB1N, VB1P, VB2N, VB2P: bias voltage;

[0053] VDD: supply voltage;

[0054] VFB: feedback signal;

[0055] VIN, VIP: input signal;

[0056] VN1, VN2: voltage;

[0057] VON, VOP: output signal;

[0058] VREF: reference voltage.

Claims

1. A back driver, characterized by, comprises: an input pair circuit, outputting a first signal from a first node and a second signal from a second node according to a first input signal and a second input signal; a protection circuit, providing voltage protection to the input pair circuit according to a plurality of first bias voltages and a second bias voltage, and transmitting the first signal to a first load to generate a first output signal and transmitting the second signal to a second load to generate a second output signal; a common mode sensing circuit, sensing a level of the first node and a level of the second node to generate a feedback signal; and an amplifier, generating the second bias voltage according to a reference voltage and the feedback signal; a switching circuit, selectively outputting the second bias voltage or a fixed voltage to the protection circuit; the switching circuit outputs the fixed voltage to the protection circuit in a power saving mode and outputs the second bias voltage to the protection circuit in an operation mode. the common mode sensing circuit comprises:

2. The post driver of claim 1, wherein, a first resistive component, wherein a first end of the first resistive component is coupled to the second node; and a second resistive component, wherein a first end of the second resistive component is coupled to a second end of the first resistive component and generates the feedback signal, and a second end of the second resistive component is coupled to the first node. the input pair circuit receives a supply voltage via the protection circuit, the first load and the second load, and a withstand voltage of transistors included in each of the protection circuit and the input pair circuit is lower than the supply voltage.

3. The post driver of claim 1, wherein, the input pair circuit comprises:

4. The post driver of claim 1, wherein, a first transistor, wherein a first end of the first transistor is coupled to the first node and outputs the first signal, a second end of the first transistor is coupled to ground via a current source circuit, and a control end of the first transistor receives the first input signal; and a second transistor, wherein a first end of the second transistor is coupled to the second node and outputs the second signal, a second end of the second transistor is coupled to the second end of the first transistor, and a control end of the second transistor receives the second input signal. when the second transistor is turned off in response to the second input signal, the level of the second node is clamped to a certain level via the protection circuit, the common mode sensing circuit and the amplifier, and the certain level is determined via the reference voltage and the level of the first node.

5. The post driver of claim 4, wherein, the protection circuit comprises:

6. The post driver of claim 1, wherein, a first transistor, biased via a first one of the plurality of first bias voltages and generating the first output signal; a second transistor, biased via the second bias voltage and receiving the first signal from the input pair circuit; a third transistor, biased via a second one of the plurality of first bias voltages and generating the second output signal; and a fourth transistor, biased via the second bias voltage and receiving the second signal from the input pair circuit. comprises:

7. A post driver, characterized by ​ A plurality of driver circuits generates a first output signal via a first load and a second output signal via a second load according to a plurality of sets of input signals, wherein each of the plurality of driver circuits comprises: an input pair circuit outputs a first signal via a first node and a second signal via a second node according to a first input signal and a second input signal of a corresponding one of the plurality of sets of input signals; and a protection circuit conducts according to a plurality of first bias voltages and a second bias voltage to provide a voltage protection for the input pair circuit and to transmit the first signal to the first load and the second signal to the second load; a common mode sensing circuit generates a feedback signal according to a level of the first node of a corresponding one of the plurality of driver circuits and a level of the second node of the corresponding one of the plurality of driver circuits; and an amplifier generates the second bias voltage according to a reference voltage and the feedback signal; a switching circuit to selectively output the second bias voltage or a fixed voltage to the protection circuit; the switching circuit outputs the fixed voltage to the protection circuit in a power saving mode and outputs the second bias voltage to the protection circuit in an operating mode.

8. The post driver of claim 7, wherein, the plurality of driver circuits correspond to a plurality of taps, the corresponding driver circuit being a circuit of the plurality of driver circuits corresponding to a primary tap of the plurality of taps.

9. The set driver of claim 7, wherein, each of the plurality of driver circuits comprises a plurality of transistors, the plurality of transistors included in the corresponding driver circuit having a size greater than a size of transistors included in other ones of the plurality of driver circuits. the plurality of driver circuits correspond to a plurality of taps, the corresponding driver circuit being a circuit of the plurality of driver circuits corresponding to a primary tap of the plurality of taps. each of the plurality of driver circuits comprises a plurality of transistors, the plurality of transistors included in the corresponding driver circuit having a size greater than a size of transistors included in other ones of the plurality of driver circuits.

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