Compliant organic substrate assembly for rigid probes

Abstract

A wafer testing device and method for assembling the same include a first laminate structure and a second laminate structure arranged to interface with a microcircuit on a wafer. The wafer testing device includes a compliant layer between the first and second laminate structures. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement.

Description

Technical Field

[0001] The present invention relates to wafer testing and, more particularly, to a compliant organic substrate assembly for rigid probes. Background Art

[0002] A wafer is a semiconductor layer used in the manufacture of integrated circuits. The wafer serves as the substrate for the microcircuits of the microelectronic devices, which are built in and on the wafer and constitute the integrated circuits. During manufacturing, wafer testing is performed to identify any functional defects in the microelectronic devices. A probe device, which may be referred to as a wafer probe, is used to perform automated testing. In order to perform electrical testing, a set of contacts or probes of the probe device is held in electrical contact with the contact points or solder bumps of the microelectronic device of each microcircuit in sequence. Once testing is complete, individual integrated circuits are obtained through a process called dicing. Dicing separates each microcircuit into dies ("dies"), which are then packaged as integrated circuits.

[0003] For example, existing probe devices include those with vertical probes (such as, bent beam needles). The probe device may be referred to as a probe card, which includes a large number of these needles with pointed or flat tips. When a load is applied to bring the probe card into contact with the microcircuit of the wafer, the amount by which each of the needles bends is independent of the movement of the other needles. Each needle of the probe card contacts a corresponding solder bump of the microcircuit and deforms it. The probe card provides an electrical path between the test system and a given microcircuit of the wafer. The wafer can be moved relative to the probe device to test each microcircuit in turn.

[0004] Another existing type of probe device is rigid. A rigid probe array is mounted on a rigid substrate. The probes are typically copper and can be electroplated (e.g., nickel or gold). Unlike compliant (i.e., individually flexed) vertical probes, rigid probes are not limited in the power they can deliver to the microelectronic devices of each microcircuit of a wafer. In addition, for example, the cost of manufacturing a rigid probe device is relatively less than the cost of manufacturing a vertical probe card. This is because, unlike vertical probes, rigid probes can be manufactured using photolithography. Although rigid probes are more convenient for transmitting more power than flexible vertical probes, the lack of deformation in any aspect of the probe device may cause problems in coupling to uneven solder balls. The shape of the solder ball is typically characterized by height, diameter, and volume (e.g., tin). The tin height of the solder ball typically decreases (e.g., from 55 microns to 17 microns), and approximately 20,000 to 30,000 contact points of the solder ball can be presented on a given microcircuit. Therefore, any increased tolerance due to the shape of the solder balls may make it challenging to achieve electrical contact with the complete set of solder balls of the microcircuit. Summary of the Invention

[0005] Embodiments of the present invention relate to a wafer testing apparatus. The wafer testing apparatus includes a first laminate structure and a second laminate structure, the second laminate structure being arranged to interface with a microcircuit on a wafer. A compliant layer between the first and second laminate structures includes an elastomer that exhibits compliance within a limited range of movement.

[0006] Embodiments of the present invention also relate to a method for assembling a wafer testing device. The method includes forming a first laminate structure and arranging a second laminate structure, the second laminate structure being arranged to interface with a microcircuit on a wafer. A compliant layer is arranged between the first and second laminate structures. The compliant layer includes an elastomer that exhibits compliance within a limited range of movement. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The examples described throughout this document will be better understood with reference to the following drawings and descriptions. The components in the figures are not necessarily to scale. In addition, in the drawings, the same reference numerals represent corresponding parts in different views.

[0008] Figure 1 A wafer and a corresponding wafer prober according to one or more embodiments of the present invention are shown;

[0009] Figure 2 is a cross-sectional view of aspects of testing an interconnect according to one or more embodiments of the present invention;

[0010] Figure 3A 、 Figure 3B and Figure 3C The need for a compliant organic substrate assembly for a rigid probe according to one or more embodiments is shown, wherein:

[0011] Figure 3A A solder bump having a height of 55 microns is shown;

[0012] Figure 3B A solder bump having a height of 40 microns is shown;

[0013] Figure 3C A solder bump with a height of 17 microns is shown;

[0014] Figure 4 shows a concave solder bump array profile required for a compliant organic substrate assembly for a rigid probe in accordance with one or more embodiments; and

[0015] Figure 5 is a block diagram of aspects of a test apparatus for use with a compliant organic substrate assembly for a rigid probe, according to one or more embodiments. DETAILED DESCRIPTION

[0016] As previously mentioned, the rigid probe of the rigid probe device can transmit more power to the contact points of the microelectronic device of the wafer under test compared to the flexible probe of the vertical probe device. Typically, the rigid probe device includes two laminated structures with a copper ball layer soldered between them to increase the rigidity of the laminated support structure. The rigid probe is formed on the laminated support structure by photolithography, more specifically, on the surface of one of the laminated structures, which is opposite to the surface soldered to the copper balls. As previously mentioned, correctly contacting each contact point of each microcircuit of the wafer under test can be challenging for the correct probe device. Typically, the solder balls of lower height and the uneven height of the solder balls of the microelectronic device across the microcircuit may cause insufficient contact between multiple rigid probes and the corresponding solder balls. Sufficient contact requires the solder balls to deform by about 10 to 15 microns. The solder balls of a given microcircuit can generally have a concave shape because the solder balls on the periphery of each microcircuit are relatively higher (e.g., 8 microns higher) than those closer to the center of the microcircuit. However, the rigid laminated structure supporting the rigid probes causes all rigid probes to be at the same uniform level above the microcircuit. Thus, while this level may be sufficient to contact and deform many solder balls (e.g., those on the periphery of the microcircuit), it may not be sufficient to contact all solder balls (e.g., those closer to the center of the microcircuit). Failure to establish proper contact between the rigid probes and their corresponding solder balls may result in inadequate wafer testing and inaccurate results.

[0017] Embodiments of the present invention relate to a compliant organic substrate assembly for a rigid probe. Although the power and performance capabilities of the rigid probe are maintained, the support structure is made more compliant in a particular manner. The laminate structure on which the rigid probe is formed can deflect relative to another laminate structure. As described in detail, this independent deflection of the two laminate structures is due to the use of a compliant layer to replace the solder copper balls between the two laminate structures. That is, the ability of the compliant layer between the laminate structures to deform or compress can result in different degrees of deflection of the two laminate structures. The laminate structure on which the rigid probe is formed can be made to deflect so as to match the profile (e.g., concave) of the solder bump array of the chip, while the other laminate structure of the support structure can remain unchanged or deform to different degrees. The load applied to the probe device to achieve increased contact between the rigid probe and the solder bump does not change compared to the load required for a fully rigid probe device.

[0018] Figure 1A wafer 100 and a corresponding wafer test assembly 130 according to one or more embodiments of the present invention are shown. The wafer 100 may include a plurality of microcircuits 110 that are tested sequentially. The microcircuits 110 may be, for example, on the order of one square inch and are shown to include a plurality of solder bumps 120 that serve as contact points for testing the microcircuits 110. The wafer 100 may be supported by a wafer prober (not shown) and moved into position for testing. The wafer test assembly 130 includes a test interconnect 200 that serves as an electrical and mechanical interface between the microcircuit 110 under test and a test device 140 that controls the test. That is, the test device 140 determines and controls the test mode applied to the microcircuit 110 under test via the test interconnect 200. The test interconnect 200 includes a thin, flexible laminate structure 220 and a thicker, rigid laminate structure 240 connected by a compliant layer 230. Rigid probes 210 extend from the laminate structure 220 to couple to the solder bumps 120 of the microcircuit 110 under test. As shown, floating pins 145 (eg, pogo pins or spring-loaded pins) extend from the laminate structure 240 and are coupled to the printed circuit board (PCB) 135. The test equipment 140 is coupled to the PCB 135.

[0019] In existing fully rigid wafer prober test interconnects (i.e., rigid probe devices), the laminate structure may be connected by a layer of copper balls that are soldered to the laminate structure on the opposite side and filled with epoxy to further strengthen the test interconnect. Figure 2 As discussed, according to one or more embodiments of the present invention, compliant layer 230 facilitates independent bending capabilities for each of laminate structures 220, 240. Compliant layer 230 is designed or tuned for a particular wafer 100. In this way, the desired compliance of compliant layer 230 is achieved to facilitate deformation of solder bumps 120 within a given tolerance.

[0020] The test equipment 140 refers to a processor, memory, and other components that control the test patterns implemented on each microcircuit under test 110. For example, the test equipment 140 may include an automatic test pattern generator (ATPG) that applies a signal sequence to the microcircuit under test 110 via the test interconnect 200. The test equipment 140 distinguishes between correct circuit behavior caused by the signal sequence and faulty circuit behavior that indicates a defect in the microcircuit under test 110. As previously described, the test equipment 140 may be connected to the PCB 135, which is coupled to the test interconnect 200. The test equipment 140 may control the signals provided to the microcircuit under test 110 through the test interconnect 200, and more specifically, through each rigid probe 210.

[0021] The laminate structure 220 is approximately sized to fit each microcircuit 110 on the wafer 100. The laminate structure 240 can have a larger area than the microcircuit 110 and facilitates scaling so that a PCB 135 that is larger than the microcircuit 110 can be coupled to the microcircuit 110 via the test interconnect 200. Floating pins 145 extending from the surface of the laminate structure 240 of the test interconnect 200 facilitate coupling between the test interconnect 200 and the PCB 135. Rigid probes 210 extending from the laminate structure 220 of the test interconnect 200 facilitate coupling between the test interconnect 200 and the microcircuit 110 under test. Each solder bump 120 of the microcircuit 110 is contacted and deformed by the rigid probe 210.

[0022] Typically, to perform a wafer test, the wafer 100 is moved to establish contact between the solder bumps 120 of the microcircuit 110 and the rigid probes 210 of the test interconnect 200. In order to accurately perform the test, electrical contact must be established between each solder bump 120 of the microcircuit 110 and each corresponding rigid probe 210 of the test interconnect 200. Specifically, each rigid probe 210 must contact and deform the corresponding solder bump 120. As the spacing (i.e., the distance between the centers of adjacent solder bumps 120) and size of the solder bumps 120 decrease in technology, establishing sufficient electrical contact becomes more challenging. According to one or more embodiments of the present invention, the compliant layer 230 is manufactured so that the rigid probes 210, or areas of the rigid probes 210 supported by the compliant layer 230, can move independently of each other, rather than as a single rigid layer. Thus, during the process of contacting the wafer 100 with the wafer test element 130, the wafer 100 can be moved toward the wafer test element 130 until the smallest or furthest solder bumps 120 contact their corresponding rigid probes 210. The compliance in the compliant layer 230 allows the rigid probes 210 that have contacted larger or closer solder bumps 120 to deflect (i.e., move backward) along with the laminate structure 220 based on the compression of the compliant layer 230 in the area of these rigid probes 210.

[0023] Figure 2 is a cross-sectional view of aspects of a test interconnect 200 according to one or more embodiments of the present invention. Figure 2An exemplary compliant layer 230 of test interconnect 200 is shown in detail. Springs 250 are connected to laminate structures 220 and 240 on opposite sides using solder 260. According to an exemplary embodiment of the present invention, springs 250 may be constructed of copper. Pads 265 (e.g., gold-plated pads) on laminate structures 220 and 240 promote electrical conductivity and solderability. Elastomer 270 serves as a filler between and within springs 250. Thus, instead of the inflexible copper balls and epoxy fillers used in existing rigid wafer probe technology, the exemplary embodiment of compliant layer 230 includes springs 250 and elastomer 270 as fillers. Elastomer 270 has greater elasticity than epoxy, but does not permanently deform. As a result, elastomer 270 promotes compliance beyond which it exhibits rigidity, and the degree of compliance is adjustable. That is, elastomer 270 is compliant within a limited range of motion, which is adjustable, and rigid outside of this range. In other words, the load required for compliance (ie, compression) of the elastomer 270 increases exponentially outside a certain range of motion, and the material of the elastomer may be selected to accommodate the exponential increase in load that occurs outside of that range.

[0024] As previously mentioned, the compliance layer 230 is designed or adjusted for a specific wafer 100. The shape and tolerance (e.g., concave shape) of the solder bumps 120 of each microcircuit 110 are two parameters associated with the wafer 100 that affect the required compliance. This will be further discussed with reference to Figures 3 and 4. The required compliance refers to the flexibility required in the test interconnect 200 to ensure that all solder bumps 120 of each microcircuit 110 of the wafer 100 will be sufficiently deformed by the corresponding rigid probe 210 to establish electrical contact. Exemplary parameters adjusted in the compliance layer 230 include the size of the spring 250 and the thickness and hardness of the elastomer 270. For example, the spring 250 can be a copper spring with a diameter on the order of 0.1 millimeters (mm). The exemplary elastomer 270 can have a thickness of 0.508 mm and a hardness of 90 on the Shore A scale.

[0025] Figure 3A 、 3B 3C illustrates one of the factors that may lead to the need for a compliant organic substrate assembly for the rigid probe 210 according to one or more embodiments. Each of the figures in the accompanying drawings illustrates a solder bump 120 and a corresponding rigid probe 210. As shown, each rigid probe 210 includes three blades 310. When the microcircuit 110 is moved into contact with the wafer test element 130, the blade 310 of each rigid probe 210 contacts and deforms the corresponding solder bump 120 to establish electrical contact. Figure 3A 、 3B The solder bumps 120 shown in FIG. 3C exhibit different shapes (ie, heights / diameters) and may be arranged at different pitches. Figure 3AAn exemplary solder bump 120 is shown having a 150 micron pitch. The height of the solder bump 120 is 55 microns. Figure 3B An exemplary solder bump 120 is shown having a height of 40 microns. Figure 3C An exemplary solder bump 120 is shown having a 50 micron pitch. The height of the solder bump 120 is 17 microns.

[0026] and Figure 3A Compared to the exemplary solder bump 120 shown, it is more difficult to create Figure 3C The electrical contacts of the exemplary solder bumps 120 are shown. For example, Figure 3A The blade 310 of the rigid probe 210 shown can deform the solder bump 120 by up to 20 microns to ensure adequate contact. Figure 3C The solder bump 120 shown in FIG. 1 starts out as only 17 microns high. Therefore, the solder bump 120 used to create the solder bump with a height of Figure 3C The margin of contact for solder bumps 120 of the order of height shown is much narrower. That is, if all rigid probes 210 were maintained at the same level, small variations in solder bump 120 height within a range of 17 microns could result in gaps between some shorter solder bumps 120 and their corresponding rigid probes 210. For example, the heights of solder bumps 120 of microcircuits 110 may vary by an order of magnitude of approximately 8 microns. Thus, the compliant layer 230 according to one or more embodiments of the present invention promotes independent deflection within regions of the compliant layer 230, and therefore among corresponding rigid probes 210, based on varying degrees of compression, thereby increasing the likelihood of contact being established despite this narrow margin.

[0027] Figure 4 Another factor leading to the need for a compliant organic substrate assembly for a rigid probe 210 according to one or more embodiments is shown. For illustration purposes, three exemplary solder bumps 120 of a microcircuit 110 are shown. As shown discontinuously, Figure 4 The solder bumps 120 shown are not necessarily adjacent. The two solder bumps 120 on the end represent solder bumps 120 at the periphery of the microcircuit 110, and the middle solder bump 120 represents solder bumps 120 in the central area of the microcircuit 110. Figure 4 As shown, the solder bumps 120 of the microcircuit 110 generally have a concave shape. This is because the electroplating process used to form the solder bumps 120 generally results in the solder bumps 120 being taller near the perimeter of the microcircuit 110. The result is a concave shape among the solder bumps 120 of a given microcircuit 110. The exemplary solder bumps 120 are each shown in contact with a corresponding rigid probe 210.

[0028] exist Figure 4, a cross-sectional view of an exemplary compliant layer 230 of a test interconnect 200 is shown having laminate structures 220, 240 that are not rigid (i.e., cannot be compressed). As previously described, based on compression of one or more regions of the compliant layer 230 between the laminate structures 220, 240, the laminate structures 220, 240 may deflect differently in those different regions. However, deflection alone, without compression facilitated by the compliant layer 230 in accordance with one or more embodiments of the present invention, may not achieve the coupling between the rigid probes 210 and the solder bumps 120 facilitated by one or more embodiments of the present invention. The distance between each rigid probe 210 and the compliant layer 230 above is the same to indicate that the space will be filled with a laminate structure 220, the thickness of which will not change (i.e., the laminate structure 220 is not compressed), regardless of any compression in the compliant layer 230 itself. Additionally, the laminate structure 240 is not compressed, but may also deflect. In Figure 4 In FIG. 1 , the compliance of the portion of the compliant layer 230 corresponding to each rigid probe 210 is of interest and is therefore shown separately. Specifically, the compression of the portion of the compliant layer 230 corresponding to each rigid probe 210 is shown after contact is established between the rigid probe 210 and the solder bump 120. Figure 4 As shown, the compliant layer 230 deforms (i.e., compresses) more at the periphery over the rigid probes 210 than at the center over the rigid probes 210. This uneven deformation of the compliant layer 230 promotes contact between all of the rigid probes 210 and their corresponding solder bumps 120, regardless of the concave shape of the solder bumps 120 on the surface of the microcircuit 110.

[0029] Figure 5 2 is a block diagram of various aspects of a test apparatus 140. As previously described, the test apparatus 140 generates test patterns for testing the microcircuit 110, to which the test apparatus 140 is coupled via a test interconnect 200. The test apparatus 140 includes one or more central processing units (processors) 21a, 21b, 21c, etc. (collectively, or collectively, processor(s) 21 and / or processing devices). According to one or more embodiments of the present invention, each processor 21 may comprise a reduced instruction set computer (RISC) microprocessor. The processors 21 are coupled to system memory (e.g., random access memory (RAM) 24) and various other components via a system bus 33, to which a read-only memory (ROM) 22 is coupled, and may include a basic input / output system (BIOS) that controls certain basic functions of the test apparatus 140.

[0030] Further shown are an input / output (I / O) adapter 27 and a communications adapter 26 coupled to the system bus 33. The I / O adapter 27 may be a Small Computer System Interface (SCSI) adapter that communicates with the hard disk 23 and / or the tape storage drive 25, or any other similar component. The I / O adapter 27, the hard disk 23, and the tape storage device 25 are collectively referred to herein as mass storage 34. The operating system 40 executing on the processing system 110 may be stored in the mass storage 34. The RAM 22, ROM 24, and the mass storage 34 are examples of the memory 19 of the processing system 110. The network adapter 26 interconnects the system bus 33 with an external network 36, enabling the test device 140 to communicate with other such systems.

[0031] A display (e.g., a display monitor) 35 is connected to the system bus 33 via a display adapter 32, which may include a graphics adapter and a video controller for improving the performance of graphics-intensive applications. According to one or more embodiments of the present invention, adapters 26, 27, and / or 32 may be connected to one or more I / O buses that are connected to the system bus 33 via an intermediate bus bridge (not shown). Suitable I / O buses for connecting peripheral devices such as hard disk controllers, network adapters, and graphics adapters typically include a common protocol, such as the Peripheral Component Interconnect (PCI). Additional input / output devices are shown as being connected to the system bus 33 via a user interface adapter 28 and a display adapter 32. A keyboard 29, a mouse 30, and a speaker 31 may be interconnected to the system bus 33 via the user interface adapter 28, which may include, for example, a super I / O chip that integrates multiple device adapters into a single integrated circuit.

[0032] According to one or more embodiments of the present invention, the test device 140 includes a graphics processing unit 37. The graphics processing unit 37 is a specialized electronic circuit designed to manipulate and modify memory to accelerate the creation of images in a frame buffer intended for output to a display. Generally, the graphics processing unit 37 is very efficient at manipulating computer graphics and image processing and has a highly parallel structure, which makes it more efficient than a general-purpose CPU for algorithms in which processing of large blocks of data is performed in parallel.

[0033] Thus, as configured herein, the test device 140 includes processing capability in the form of a processor 21, storage capability including system memory (e.g., RAM 24) and mass storage 34, input components such as a keyboard 29 and a mouse 30, and output capability including a speaker 31 and a display 35. According to one or more embodiments of the present invention, portions of the system memory (e.g., RAM 24) and the mass storage 34 together store computer programs such as those from IBM Corporation. An operating system is provided to coordinate the functions of the various components shown in the test device 140 .

[0034] Various embodiments of the present invention are described herein with reference to relevant drawings. Without departing from the scope of the present invention, alternative embodiments of the present invention can be designed. In the following description and accompanying drawings, various connections and positional relationships (e.g., above, below, adjacent, etc.) are set forth between elements. Unless otherwise indicated, these connections and / or positional relationships can be direct or indirect, and the present invention is not intended to be limited in this respect. Therefore, the coupling of entity can refer to direct or indirect coupling, and the positional relationship between the entity can be a direct or indirect positional relationship. In addition, various tasks and process steps described herein can be incorporated into a more comprehensive program or process with additional steps or functionality not described in detail herein.

[0035] One or more methods described herein may be implemented using any of the following technologies or combinations thereof known in the art: (a plurality of) discrete logic circuits having logic gates for implementing logic functions according to data signals, application specific integrated circuits (ASICs) having appropriate combinational logic gates, (a plurality of) programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0036] For the sake of brevity, conventional techniques related to making and using aspects of the present invention may or may not be described in detail herein. In particular, various aspects of computing systems and specific computer programs for implementing the various technical features described herein are known. Therefore, for the sake of brevity, many conventional implementation details are only briefly mentioned herein or omitted entirely, without providing well-known system and / or process details.

[0037] In some embodiments, various functions or actions can occur at a given location and / or in conjunction with the operation of one or more devices or systems. In some embodiments, part of a given function or action can be performed at a first device or location, and the remainder of the function or action can be performed at one or more additional devices or locations.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] The corresponding structures, materials, actions and equivalents of all parts or step-plus-function elements in the following claims are intended to include any structure, material or action for performing a function in combination with other claimed elements as specifically claimed. The present invention has been presented for the purpose of illustration and description, but is not intended to be exhaustive or limited to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The selected and described embodiments are in order to best explain the principles and practical applications of the present invention, and to enable other persons of ordinary skill in the art to understand the various embodiments of the present invention with various modifications that are suitable for the specific purposes under consideration.

[0040] The figures described herein are illustrative. Without departing from the scope of the present invention, many changes may be made to the figures or steps (or operations) described therein. For example, actions may be performed in different orders, or actions may be added, deleted, or modified. In addition, the term "coupling" describes a signal path between two elements and does not imply a direct connection between the elements without an intermediate element / connection therebetween. All of these changes are considered to be parts of the present invention.

[0041] The following definitions and abbreviations are used to interpret the claims and specification. As used herein, the terms "comprises," "includes," "has," "contains," or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0042] Additionally, the term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" are understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect and direct "connections."

[0043] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time this application is filed. For example, "about" may include a range of ±8%, 5%, or 2% of a given value.

[0044] The present invention may be a system, method and / or computer program product at any possible level of technical detail integration. The computer program product may include (a plurality of) computer-readable storage media having computer-readable program instructions thereon, the computer-readable program instructions being used to cause a processor to perform various aspects of the present invention.

[0045] Computer readable storage medium can be a tangible device that can retain and store the instructions used by the instruction execution device.Computer readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer readable storage medium includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card or a raised structure in a groove on which instructions are recorded, and any suitable combination of the foregoing. As used herein, computer readable storage medium is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (e.g., a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0046] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0047] The computer-readable program instructions for performing the operation of the present invention can be assembly instructions, instruction set architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, configuration data of an integrated circuit, or source code or object code written in any combination of one or more programming languages (including object-oriented programming languages, such as Smalltalk, C++, etc.) and procedural programming languages (such as "C" programming language or similar programming languages). The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, executed as an independent software package, partially on the user's computer and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, using an Internet service provider through the Internet). In some embodiments, in order to perform various aspects of the present invention, an electronic circuit comprising, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) can execute the computer-readable program instructions to personalize the electronic circuit by utilizing the state information of the computer-readable program instructions.

[0048] Various aspects of the present invention are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It will be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0049] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device create components for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, which can direct the computer, programmable data processing device, and / or other device to operate in a specific manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture, which includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0050] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other apparatus to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other apparatus to produce a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other apparatus implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0051] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present invention.In this regard, each frame in the flow chart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for realizing the logical function of (multiple) specifications. In some alternative embodiments, the function noted in the frame can not occur in the order noted in the figure. For example, the two frames shown in succession can actually be performed substantially simultaneously, or these frames can sometimes be performed in reverse order, depending on the function involved. It will also be noted that the combination of the frames in each frame of the block diagram and / or flow chart illustration and the block diagram and / or flow chart illustration can be realized by a dedicated hardware-based system that performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0052] The description of various embodiments of the present invention has been provided for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, practical applications, or improvements over existing technologies in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.

Claims

1. A wafer testing device, comprising: a first laminate structure comprising a first pad; a second laminate structure arranged to interface with the microcircuit of the wafer, the second laminate structure comprising second pads; and a compliant layer between the first laminate structure and the second laminate structure, the compliant layer comprising an elastomer exhibiting compliance within a limited range of movement, and a coil spring secured to the first laminate structure and the second laminate structure, wherein the coil spring is welded to the first welding pad of the first laminate structure on a first side of the coil spring, and the coil spring is welded to the second welding pad of the second laminate structure on a second side of the coil spring opposite the first side; wherein the compliant layer compresses to provide independent deflection of the second laminate structure relative to the first laminate structure.

2. The device of claim 1 , wherein the first pad of the first laminate structure and the second pad of the second laminate structure are gold-plated pads, so that the spring is soldered to the gold-plated pad of the first laminate structure on the first side and to the gold-plated pad of the second laminate structure on the second side. 3 . The apparatus of claim 1 , further comprising a test device coupled to the first laminate structure, the test device configured to generate a test pattern to be applied to the microcircuit. 4 . The apparatus of claim 3 , further comprising a floating pin configured to couple the test equipment to the first laminate structure.

5. The apparatus of claim 1, further comprising a rigid probe configured to couple the microcircuit to the second laminate structure.

6. The apparatus of claim 5, wherein the rigid probes are spaced apart such that each rigid probe couples with a solder bump of the microcircuit.

7. The device of claim 1, wherein the elastic body of the compliant layer exhibits compliance within a specific range of movement and exhibits rigidity outside the range of movement.

8. The device of claim 7, wherein the material of the elastomer determines the specific range of movement.

9. A method of assembling a wafer testing device, the method comprising: forming a first laminate structure including a first pad; arranging a second laminate structure, the second laminate structure being arranged to interface with the microcircuit of the wafer, the second laminate structure comprising second pads; and disposing a compliant layer between the first laminate structure and the second laminate structure, the compliant layer comprising an elastomer and a coil spring exhibiting compliance within a limited range of movement; as well as welding the spring to the first pad of the first laminate structure on a first side of the spring, and welding the spring to the second pad of the second laminate structure on a second side of the spring opposite the first side to secure the coil spring to the first and second laminate structures; The compliant layer is compressed to provide independent deflection of the second laminate structure relative to the first laminate structure.

10. The method according to claim 9, wherein the first pad and the second pad are gold-plated pads, and the welding comprises: The spring is soldered to the gold-plated pad of the first laminate structure on the first side, and the spring is soldered to the gold-plated pad of the second laminate structure on the second side.

11. The method according to claim 9, further comprising: The first laminate structure is coupled to a test device configured to generate a test pattern that is applied to the microcircuit.

12. The method of claim 11, wherein coupling the first laminate structure to the test equipment is performed using floating pins.

13. The method according to claim 9, further comprising: A rigid probe is attached to the second laminate structure to couple the microcircuit to the second laminate structure.

14. The method of claim 13, wherein the rigid probes are spaced apart such that each rigid probe couples with a solder bump of the microcircuit.

15. The method according to claim 9, further comprising: The elastomer of the compliant layer is designed to be compliant within a specific range of motion and rigid outside of the range of motion.

16. The method according to claim 15, wherein Designing the elastic body includes selecting a material for the elastic body to control the specific range of movement.

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