Method for manufacturing image display device and image display device

Abstract

The present invention provides a method for manufacturing an image display device and an image display device. The method for manufacturing an image display device of an embodiment comprises: preparing a first substrate including a circuit having a circuit element formed on a light-transmitting substrate and a first insulating film covering the circuit; forming a conductive layer including a portion of a single crystal metal on the first insulating film; forming a semiconductor layer including a light-emitting layer on the portion; etching the semiconductor layer to form a light-emitting element; forming a second insulating film covering the conductive layer, the light-emitting element and the first insulating film; forming a through hole penetrating the first insulating film and the second insulating film; and electrically connecting the light-emitting element to the circuit element via the through hole at the light-emitting surface of the light-emitting element opposite to the first insulating film side.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method for manufacturing an image display device and an image display device. Background Art

[0002] It is desired to realize a thin image display device with high brightness, wide viewing angle, high contrast, and low power consumption. In order to meet the above market demand, a display device using a self-luminous element is being developed.

[0003] As a self-luminous element, a display device using a fine light-emitting element, namely a micro-LED, is expected to appear. As a manufacturing method of a display device using a micro-LED, a method of sequentially transferring a single formed micro-LED to a drive circuit has been introduced. However, as the number of micro-LED elements increases with high image quality such as full HD, 4K, and 8K, the transfer process requires a lot of time in the process of forming a large number of micro-LEDs individually and sequentially transferring them to a substrate forming a drive circuit, etc. In addition, there may be problems with the connection between the micro-LED and the drive circuit, etc., resulting in a problem of reduced yield.

[0004] A technique is known in which a semiconductor layer including a light-emitting layer is grown on a Si substrate, electrodes are formed on the semiconductor layer, and then the semiconductor layer is bonded to a circuit board having a driving circuit formed thereon (for example, Patent Document 1).

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: (Japanese) Patent Publication No. 2002-141492

[0008] Non-patent literature

[0009] Non-patent literature 1: H. Kim, J. Ohta, K. Ueno, A. Kobayashi, M. Morita, Y. Tokumoto & H. Fujioka, “Manufacturing method of full-color GaN-based light-emitting diodes on nearly lattice-matched flexible metal foils,” Scientific Reports, 7: 2112, May 18, 2017

[0010] Non-patent document 2: J. W. Shon, J. Ohta, K. Ueno, A. Kobayashi & H. Fujioka, "Manufacturing method of full-color InGaN-based light-emitting diodes on amorphous substrates by pulsed sputtering", Scientific Reports, 4: 5325, June 23, 2014 Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] One embodiment of the present invention provides a method for manufacturing an image display device that shortens the transfer process of a light-emitting element and improves the yield.

[0013] Technical solutions for solving technical problems

[0014] A method for manufacturing an image display device according to one embodiment of the present invention comprises: a process of preparing a first substrate including a circuit having a circuit element formed on a light-transmitting substrate and a first insulating film covering the circuit; a process of forming a conductive layer including a portion of a single crystal metal on the first insulating film; a process of forming a semiconductor layer including a light-emitting layer on the portion; a process of etching the semiconductor layer to form a light-emitting element; a process of forming a second insulating film covering the conductive layer, the light-emitting element and the first insulating film; a process of forming a through hole penetrating the first insulating film and the second insulating film; and a process of electrically connecting the light-emitting element to the circuit element via the through hole at the light-emitting surface of the light-emitting element opposite to the side of the first insulating film.

[0015] An image display device according to one embodiment of the present invention comprises: a light-transmitting substrate having a first surface, a circuit element arranged on the first surface, a first wiring layer arranged on the circuit element and electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer on the first surface, a conductive layer arranged on the first insulating film and including a portion of a single crystal metal, a first light-emitting element arranged on the portion and electrically connected to the portion, a second insulating film covering at least a portion of the first light-emitting element, the first insulating film, and the conductive layer, a second wiring layer arranged on the second insulating film and electrically connected to a light-emitting surface of the first light-emitting element opposite to a side of the first insulating film, and a through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer.

[0016] An image display device according to one embodiment of the present invention comprises: a substrate having a first surface and being flexible, a circuit element arranged on the first surface, a first wiring layer arranged on the circuit element and electrically connected to the circuit element, a first insulating film covering the circuit element and the first wiring layer on the first surface, a conductive layer arranged on the first insulating film and including a portion of a single crystal metal, a first light-emitting element arranged on the portion and electrically connected to the portion, a second insulating film covering at least a portion of the first light-emitting element, the first insulating film, and the conductive layer, a second wiring layer arranged on the second insulating film and electrically connected to a light-emitting surface of the first light-emitting element opposite to a side of the first insulating film, and a through hole penetrating the first insulating film and the second insulating film and electrically connecting the first wiring layer and the second wiring layer.

[0017] An image display device according to one embodiment of the present invention comprises: a light-transmitting substrate having a first surface, a plurality of transistors arranged on the first surface, a first wiring layer arranged on the plurality of transistors and electrically connected to the plurality of transistors, a first insulating film covering the plurality of transistors and the first wiring layer on the first surface, a conductive layer arranged on the first insulating film and including a portion of a single crystal metal, a first semiconductor layer of a first conductivity type arranged on the portion and electrically connected to the portion, a light-emitting layer arranged on the first semiconductor layer, a second semiconductor layer of a second conductivity type different from the first conductivity type arranged on the light-emitting layer, a second insulating film covering the conductive layer, the first insulating film, the light-emitting layer and the first semiconductor layer and covering at least a portion of the second semiconductor layer, a second wiring layer exposed from the second insulating film respectively corresponding to the plurality of transistors and connected to light-transmitting electrodes arranged on the plurality of light-emitting surfaces of the second semiconductor layer, and a plurality of through holes penetrating the first insulating film and the second insulating film and electrically connecting wiring of the first wiring layer and wiring of the second wiring layer respectively.

[0018] Effects of the Invention

[0019] According to one embodiment of the present invention, it is possible to realize a method for manufacturing an image display device in which the transfer process of a light emitting element is shortened and the yield is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a schematic cross-sectional view illustrating a part of the image display device according to the first embodiment.

[0021] Figure 2A This is a schematic cross-sectional view illustrating a part of a modification of the image display device according to the first embodiment.

[0022] Figure 2B This is a schematic cross-sectional view illustrating a part of a modification of the image display device according to the first embodiment.

[0023] Figure 3 is a schematic block diagram illustrating an image display device according to the first embodiment.

[0024] Figure 4 It is a schematic plan view illustrating a part of the image display device according to the first embodiment.

[0025] Figure 5A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0026] Figure 5B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0027] Fig. 6A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0028] Figure 6B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0029] Fig. 7A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0030] Figure 7B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0031] Fig. 8A It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0032] Figure 8B It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0033] Fig.9A It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0034] Fig. 9B It is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device according to the first embodiment.

[0035] Fig.10 It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0036] Fig.11A It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0037] Fig. 11B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0038] Fig. 11C It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0039] Fig.11D It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to the first embodiment.

[0040] Fig.12 is a schematic cross-sectional view illustrating a part of the image display device according to the second embodiment.

[0041] Fig.13 is a schematic block diagram illustrating an image display device according to the second embodiment.

[0042] Fig.14A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0043] Fig. 14B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0044] Fig. 14C It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0045] Fig.15A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0046] Fig. 15B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the second embodiment.

[0047] Fig.16 is a schematic cross-sectional view illustrating a part of an image display device according to a third embodiment.

[0048] Fig.17A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0049] Fig. 17B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the third embodiment.

[0050] Fig.18 is a schematic cross-sectional view illustrating a portion of an image display device according to a fourth embodiment.

[0051] Fig.19A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0052] Fig.19B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0053] Fig.19C It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0054] Fig. 20A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0055] Fig. 20B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0056] Fig.21A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0057] Fig.21B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0058] Fig.22A It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0059] Fig. 22B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the fourth embodiment.

[0060] Fig.23 This is a schematic cross-sectional view of a part of an image display device illustrating a modification example of the fourth embodiment.

[0061] Fig.24A It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fourth embodiment.

[0062] Fig. 24B It is a schematic cross-sectional view illustrating a method for manufacturing an image display device according to a modification example of the fourth embodiment.

[0063] Fig.25 is a graph illustrating the characteristics of a pixel LED element.

[0064] Fig.26 This is a block diagram illustrating an image display device according to the fifth embodiment.

[0065] Fig. 27 This is a block diagram illustrating an image display device according to a modification of the fifth embodiment.

[0066] Fig.28 It is a perspective view schematically illustrating the image display device according to the first to fourth embodiments and the above-mentioned modification example. DETAILED DESCRIPTION

[0067] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0068] It should be noted that the accompanying drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as the actual situation. In addition, even when representing the same part, sometimes the mutual size and ratio are represented differently due to the accompanying drawings.

[0069] It should be noted that, in the present specification and each drawing, the same reference numerals are used for main components that are the same as those described in relation to the drawings that have already been shown, and detailed descriptions thereof are appropriately omitted.

[0070] (First Embodiment)

[0071] Figure 1 is a schematic cross-sectional view illustrating a portion of an image display device according to an embodiment.

[0072] Figure 1 The structure of the sub-pixel 20-1 of the image display device of this embodiment is schematically shown. The pixels constituting the image displayed in the image display device are composed of the pixels described below. Figure 3 The plurality of sub-pixels 20 shown in FIG. Figure 1 , in addition to the sub-pixel 20 - 1 , a part of the sub-pixel 20 - 2 is also shown.

[0073] In the following, the three-dimensional coordinate system of XYZ is sometimes used for explanation. The sub-pixels 20-1 and 20-2 are arranged on a two-dimensional plane. The two-dimensional plane on which the sub-pixels 20-1 and 20-2 are arranged is called an XY plane. The sub-pixels 20-1 and 20-2 are arranged along the X-axis and the Y-axis. Figure 1 Indicates the following description Figure 4 The sagittal section of the A-A' line is a cross-sectional view that connects the sections of multiple planes perpendicular to the XY plane into one. Figure 1 As shown, in the cross-sectional views of multiple planes perpendicular to the XY plane, the X axis and the Y axis are not shown, and the Z axis perpendicular to the XY plane is shown. That is, in the above figure, the plane perpendicular to the Z axis is the XY plane.

[0074] The sub-pixels 20-1 and 20-2 have light-emitting surfaces 153S1 and 153S2 that are substantially parallel to the XY plane, respectively. The light-emitting surfaces 153S1 and 153S2 emit light mainly in the positive direction of the Z axis that is perpendicular to the XY plane.

[0075] like Figure 1 As shown, the sub-pixel 20-1 of the image display device of this embodiment includes: a substrate 102, a transistor (circuit element) 103, a first wiring layer (first wiring layer) 110, a first interlayer insulating film (first insulating film) 112, a light-emitting element (first light-emitting element) 150-1, a second interlayer insulating film (second insulating film) 156, a conductive layer 130, a plurality of through holes 161d, 161k, and a second wiring layer (second wiring layer) 160.

[0076] In this embodiment, the image display device has a sub-pixel 20-2. For example, the sub-pixel 20-2 is arranged adjacent to the sub-pixel 20-1. The sub-pixel 20-2 includes: a substrate 102, a first wiring layer 110, a first interlayer insulating film 112, a second interlayer insulating film 156, a conductive layer 130, and a second wiring layer 160, and the above-mentioned parts are shared with the sub-pixel 20-1. The light-emitting element (second light-emitting element) 150-2 is arranged on the conductive layer 130 together with the light-emitting element 150-1. Figure 1 , the transistor for the sub-pixel 20-2 is not shown, but a transistor for driving the light-emitting element 150-2 is separately provided.

[0077] In this embodiment, the substrate 102 on which the circuit element including the transistor 103 is formed is a light-transmitting substrate, such as a glass substrate. The substrate 102 has a first surface 102a, on which a thin film transistor (TFT) is formed as the transistor 103. The first surface 102a is a surface substantially parallel to the XY plane. The light-emitting elements 150-1 and 150-2 are driven by the TFT formed on the glass substrate. The process of forming the circuit element including the TFT on a large glass substrate is established for the manufacture of liquid crystal panels, organic EL panels, etc., and has the advantage of being able to utilize existing equipment.

[0078] The sub-pixel 20 further includes a color filter 180. The color filter (wavelength conversion member) 180 is provided on the surface resin layer 170 via a transparent thin film adhesive layer 188. The surface resin layer 170 is provided on the interlayer insulating film 156 and the wiring layer 160.

[0079] The transistor 103 is formed on a TFT lower film 106 formed on the first surface 102a of the substrate 102. The TFT lower film 106 is provided for the purpose of ensuring flatness when forming the transistor 103 and protecting the TFT channel 104 of the transistor 103 from contamination during heat treatment. The TFT lower film 106 is, for example, SiO2.

[0080] In the substrate 102, except for the driving transistor 103 of the light emitting element 150-1, Figure 1 Although not shown in the figure, a driving transistor for the light emitting element 150-2, other transistors, capacitors and other circuit elements are formed, and the circuit 101 is composed of wiring and the like. For example, the transistor 103 corresponds to the transistor described later. Figure 3 The driving transistor 26 is shown.

[0081] In the following, it is assumed that the circuit 101 includes: TFT channel 104, insulating layer 105, insulating film 108, through holes 111s, 111d, and wiring layer 110. The main components including substrate 102, TFT lower film 106, circuit 101 and interlayer insulating film 112 are sometimes referred to as circuit substrate 100.

[0082] The transistor 103 is a p-channel TFT in this example. The transistor 103 includes a TFT channel 104 and a gate 107. The TFT is preferably formed by a low temperature polysilicon (LTPS) process. The TFT channel 104 is a region of polycrystalline Si formed on the substrate 102, and the region formed as amorphous Si is annealed by laser irradiation, thereby being polycrystallized and activated. The TFT formed by the LTPS process has a sufficiently high mobility.

[0083] The TFT channel 104 includes regions 104s, 104i, and 104d. The regions 104s, 104i, and 104d are all disposed on the TFT lower film 106. The region 104i is disposed between the regions 104s and 104d. The regions 104s and 104d are doped with p-type impurities such as boron (B) and are ohmically connected to the through holes 111s and 111d.

[0084] The gate electrode 107 is provided on the TFT channel 104 via the insulating layer 105. The insulating layer 105 is provided to insulate the TFT channel 104 from the gate electrode 107 and from other adjacent circuit elements. When a potential lower than that of the region 104s is applied to the gate electrode 107, a channel is formed in the region 104i, and the current flowing between the regions 104s and 104d can be controlled.

[0085] The insulating layer 105 is, for example, SiO 2. The insulating layer 105 may be a multilayer insulating layer containing SiO 2, Si 3 N 4, etc., depending on the area to be covered.

[0086] The gate 107 is, for example, polycrystalline Si. The polycrystalline Si film of the gate 107 can be manufactured by a common CVD process.

[0087] In this example, the gate 107 and the insulating layer 105 are covered with an insulating film 108. The insulating film 108 is, for example, SiO2, Si3N4, etc. The insulating film 108 is used as a planarization film for forming the wiring layer 110. The insulating film 108 is, for example, a multilayer insulating film containing SiO2, Si3N4, etc.

[0088] The through holes 111s and 111d are provided to penetrate the insulating film 108. A first wiring layer (first wiring layer) 110 is formed on the insulating film 108. The first wiring layer 110 includes a plurality of wirings having different potentials, including wirings 110s and 110d. Figure 1 In the wiring layer of the subsequent cross-sectional views, for the purpose of marking the mark, the mark of one wiring included in the wiring layer is shown at a position next to the wiring.

[0089] The through hole 111s is provided between the wiring 110s and the region 104s to electrically connect them. The through hole 111d is provided between the wiring 110d and the region 104d to electrically connect them.

[0090] In this example, the wiring 110s connects the source region of the transistor 103, that is, the region 104s, to the Figure 3 The wiring 110d is electrically connected to the p-type semiconductor layer 153-1 on the light emitting surface 153S1 side of the light emitting element 150-1 via the through hole 161d and the wiring 160a-1 as described later.

[0091] The wiring layer 110 and the through holes 111s and 111d are formed of, for example, Al, an Al alloy, a laminated film of Al and Ti, etc. For example, in a laminated film of Al and Ti, Al is laminated on a thin film of Ti, and Ti is laminated on Al.

[0092] A first interlayer insulating film 112 is provided on the insulating film 108 and the wiring layer 110. The interlayer insulating film (first insulating film) 112 is, for example, an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass). The interlayer insulating film 112 insulates the circuit elements of the circuit 101 formed on the circuit substrate 100 and provides a flat surface for forming the conductive layer 130. The interlayer insulating film 112 also serves as a protective film for protecting the surface of the circuit substrate 100.

[0093] The conductive layer 130 is provided on the interlayer insulating film 112. The conductive layer 130 includes a light reflecting plate 130a. In this example, one light reflecting plate 130a is provided for every two sub-pixels. Different light reflecting plates 130a may be connected to each other in the conductive layer 130, or may not be connected. In this example, different light reflecting plates 130a are connected to each other via through holes 161k and wirings 160k provided in each light reflecting plate 130a, for example, as described later. Figure 3 The ground wire 4 is connected.

[0094] At least a portion of the conductive layer 130 is formed of a single crystal metal. Preferably, the conductive layer 130 is entirely a single crystal metal layer. At least a portion of the light reflecting plate 130a is formed of a single crystal metal. At least the portion of the light reflecting plate 130a where the light emitting elements 150-1 and 150-2 are provided is formed of a single crystal metal, for example, formed as a single crystal metal layer. In the following, including other embodiments, the conductive layer 130 and the light reflecting plate (portion) 130a are entirely formed of a single crystal metal layer.

[0095] The metal material forming the conductive layer 130 and the light reflecting plate 130a is, for example, Cu, Hf, etc. The metal material used for the conductive layer 130 is not limited to Cu and Hf as long as it can be a metal material that can be single-crystallized by the integrated low-temperature annealing process in the LTPS process. Since the light reflecting plate 130a is formed of a metal material, etc., it can be electrically connected to the light emitting elements 150-1 and 150-2 with low resistance. Since the light emitting elements 150-1 and 150-2 are arranged on the same light reflecting plate 130a, the light emitting elements 150-1 and 150-2 can be electrically connected to each other with low resistance.

[0096] The periphery of the light reflecting plate 130a includes the entire periphery of the light emitting elements 150-1 and 150-2 when the light emitting elements 150-1 and 150-2 are projected onto the light reflecting plate 130a in an XY plan view. By appropriately selecting the material of the light reflecting plate 130a, it is possible to reflect the scattered light downward from the light emitting elements 150-1 and 150-2 toward the light emitting surfaces 153S1 and 153S2, thereby improving the light emitting efficiency.

[0097] Since the light reflecting plate 130a reflects the scattered light of the light emitting element 150-1 downward toward the light emitting surface 153S1 side, the light can be prevented from reaching the transistor 103. Since the light reflecting plate 130a also reflects the scattered light of the light emitting element 150-2 downward toward the light emitting surface 153S2 side, the light can be prevented from reaching the transistor driving the light emitting element 150-2. By shielding the scattered light of the light emitting elements 150-1 and 150-2 downward, the light can be suppressed from reaching the circuit elements including the transistor 103, and the circuit elements can be prevented from malfunctioning.

[0098] The light emitting element 150-1 includes an n-type semiconductor layer (first semiconductor layer) 151-1, a light emitting layer 152-1, and a p-type semiconductor layer (second semiconductor layer) 153-1. The n-type semiconductor layer 151-1, the light emitting layer 152-1, and the p-type semiconductor layer 153-1 are sequentially laminated from the interlayer insulating film 112 side to the light emitting surface 153S1 side.

[0099] The light emitting element 150-2 includes an n-type semiconductor layer (third semiconductor layer) 151-2, a light emitting layer 152-2, and a p-type semiconductor layer (fourth semiconductor layer) 153-2. The n-type semiconductor layer 151-2, the light emitting layer 152-2, and the p-type semiconductor layer 153-2 are sequentially laminated from the interlayer insulating film 112 side to the light emitting surface 153S2 side.

[0100] The XY plan view area of ​​the light emitting element is set according to the luminous colors of the red, green and blue sub-pixels. The XY plan view area of ​​the light emitting elements 150-1 and 150-2 is appropriately set according to the visual sensitivity, the conversion efficiency of the color conversion unit 182 of the color filter 180, etc. In this example, the XY plan view areas of the two light emitting elements 150-1 and 150-2 are different. Because the light emitting elements 150-1 and 150-2 are placed on the light reflecting plate 130a having a surface substantially parallel to the XY plane, the XY plan view area refers to the area of ​​the region surrounded by the periphery of the light emitting elements 150-1 and 150-2 projected on the XY plane. Hereinafter, the XY plan view area is simply referred to as the area. In this example, the area of ​​the light emitting element 150-1 is smaller than the area of ​​the light emitting element 150-2.

[0101] The light emitting elements 150-1 and 150-2 have a substantially square or rectangular shape in XY plan view, for example, but the corners may be rounded. The light emitting element 150 may also have an elliptical or circular shape in XY plan view, for example. By appropriately selecting the shape and arrangement of the light emitting element in plan view, the degree of freedom in design is increased.

[0102] For example, the light emitting elements 150 - 1 and 150 - 2 are preferably made of In X Al Y Ga 1-X-Y N (0≦X, 0≦Y, X+Y<1) and other gallium nitride compound semiconductors of the light-emitting layer. Hereinafter, the above-mentioned gallium nitride compound semiconductors are sometimes simply referred to as gallium nitride (GaN). The light-emitting elements 150-1 and 150-2 of one embodiment of the present invention are so-called light-emitting diodes, and the wavelength of light emitted by the light-emitting elements 150-1 and 150-2 is, for example, about 467nm±20nm. The wavelength of light emitted by the light-emitting elements 150-1 and 150-2 may also be blue-violet light of about 410nm±20nm. The wavelength of light emitted by the light-emitting elements 150-1 and 150-2 is not limited to the above-mentioned values ​​and may be appropriate values.

[0103] The second interlayer insulating film 156 covers the first interlayer insulating film 112, the conductive layer 130, and the light emitting elements 150-1 and 150-2. The interlayer insulating film 156 is formed of, for example, an organic insulating material. The interlayer insulating film 156 protects the light emitting elements 150-1, 150-2, the conductive layer 130, etc. from the surrounding environment such as dust and humidity by covering the light emitting elements 150-1, 150-2, the conductive layer 130, etc. The interlayer insulating film 156 has the function of insulating the light emitting elements, the conductive layer, etc. from other conductive objects by covering the light emitting elements 150, the conductive layer 130, etc. The surface of the interlayer insulating film 156 only needs to be flat enough to form the wiring layer 160 on the interlayer insulating film 156.

[0104] The organic insulating material used for the interlayer insulating film 156 is preferably white resin. The interlayer insulating film 156 of white resin reflects the lateral emission light of the light emitting elements 150-1 and 150-2 and the return light generated by the interface of the color filter 180, etc., and can actually improve the light emission efficiency of the light emitting elements 150-1 and 150-2.

[0105] The white resin is formed by dispersing scattering particles having a Mie scattering effect in a transparent resin such as a silicon-based resin such as SOG (Spin On Glass), a novolac-type phenolic-based resin, or the like. The particles are colorless or white, and have a diameter of about 1 / 10 to several times the wavelength of the light emitted by the light-emitting elements 150-1 and 150-2. Particles having a diameter of about 1 / 2 the wavelength of the light are suitable for use as scattering particles. For example, TiO2, Al2SO3, and ZnO can be cited as the above-mentioned scattering particles. Alternatively, the white resin can also be formed by utilizing a large number of fine pores dispersed in the transparent resin. In the interlayer insulating film 156, SOG, etc. can also be replaced, for example, by using a SiO2 film formed by ALD (Atomic-layer-deposition) or CVD to make it white.

[0106] The second interlayer insulating film 256 may also be made of black resin. By making the interlayer insulating film 256 of black resin, it is possible to suppress light scattering in the sub-pixels 20-1, 20-1, and more effectively suppress stray light. An image display device with suppressed stray light can display clearer images.

[0107] The through hole 161k is provided to penetrate the second interlayer insulating film 156. One end of the through hole 161k is connected to the light reflecting plate 130a.

[0108] The through hole 161d is provided to penetrate the first interlayer insulating film 112 and the second interlayer insulating film 156. One end of the through hole 161d is connected to the wiring 110d.

[0109] The wiring layer 160 is provided on the interlayer insulating film 156. The wiring layer 160 includes wirings 160a-1 and 160k. The wiring 160a-1 is connected to the other end of the through hole 161d.

[0110] The light-transmitting electrode 159a1 is provided over the wiring 160a-1. The light-transmitting electrode 159a1 is provided over the light-emitting surface 153S1 of the light-emitting element 150-1. The light-transmitting electrode 159a1 is provided between the wiring 160a-1 and the light-emitting surface 153S1, and electrically connects the wiring 160a-1 and the p-type semiconductor layer 153-1. Therefore, the anode electrode of the light-emitting element 150-1, that is, the p-type semiconductor layer 153-1, is electrically connected to the drain electrode of the transistor 103, that is, the channel region 104d, via the light-transmitting electrode 159a1, the wiring 160a-1, the through hole 161d, and the wiring 110d.

[0111] The light-transmitting electrode 159a2 is provided over the light-emitting surface 153S2 of the light-emitting element 150-2. As in the case of the light-emitting element 150-1, the light-emitting surface 153S2 is electrically connected to the transistor driving the light-emitting element 150-2 via the light-transmitting electrode 159a2, the wiring included in the wiring layer 160, and the through hole penetrating the interlayer insulating films 112 and 156.

[0112] The wiring 160k is connected to the other end of the through hole 161k. The light-transmitting electrode 159k is provided over the wiring 160k. The wiring 160k and the light-transmitting electrode 159k are connected to the wiring 160k described later. Figure 3 Therefore, the n-type semiconductor layers 151-1 and 151-2 are connected to the ground line 4 via the light reflecting plate 130a, the through hole 161k, the wiring 160k and the light-transmitting electrode 159k.

[0113] The source electrode of the transistor 103, that is, the region 104s of the TFT channel 104, is connected to the transistor 103 via the wiring 110s. Figure 3 The power supply line 3 is shown to be electrically connected.

[0114] The surface resin layer 170 covers the second interlayer insulating film 156, the second wiring layer 160, and the light-transmitting electrodes 159a1, 159a2, and 159k. The surface resin layer 170 is a transparent resin, protects the interlayer insulating film 156, the wiring layer 160, and the light-transmitting electrodes 159a1, 159a2, and 159k, and provides a flat surface for bonding the color filter 180.

[0115] The color filter 180 includes a light shielding portion 181 and a color conversion portion 182. The color conversion portion 182 is provided just above the light emitting surfaces 153S1 and 153S2 of the light emitting elements 150-1 and 150-2 according to the shapes of the light emitting surfaces 153S1 and 153S2. In the color filter 180, the portion other than the color conversion portion 182 is the light shielding portion 181. The light shielding portion 181 is a so-called black matrix, and reduces blurring caused by color mixing of light emitted from adjacent color conversion portions 182, and can display a clear image.

[0116] The color conversion unit 182 has one layer or two layers. Figure 1 The color conversion unit 182 is a two-layered portion. Whether the color conversion unit 182 is a single layer or a double layer depends on the color, that is, the wavelength, of the light emitted by the sub-pixels 20-1 and 20-2. When the light emission color of the sub-pixels 20-1 and 20-2 is red or green, the color conversion unit 182 is preferably a two-layered color conversion layer 183 and a filter layer 184 described later. When the light emission color of the sub-pixels 20-1 and 20-2 is blue, it is preferably a single layer.

[0117] In the case where the color conversion unit 182 has two layers, the first layer closer to the light emitting element 150 is the color conversion layer 183 , and the second layer is the filter layer 184 . That is, the filter layer 184 is laminated on the color conversion layer 183 .

[0118] The color conversion layer 183 is a layer that converts the wavelength of light emitted by the light emitting elements 150-1 and 150-2 into a desired wavelength. For example, when the sub-pixel emits red light, the color conversion layer 183 converts the light of the light emitting element 150-1, i.e., the wavelength of 467nm±20nm, into light of about 630nm±20nm, for example. When the sub-pixel emits green light, the color conversion layer 183 converts the light of the light emitting element, i.e., the wavelength of 467nm±20nm, into light of about 532nm±20nm, for example.

[0119] The filter layer 184 blocks the wavelength component of the blue light that remains without being color-converted by the color conversion layer 183 .

[0120] When the color of the light emitted by the sub-pixel is blue, the light-emitting element of the sub-pixel may output light via the color conversion layer 183, or may directly output light without passing through the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element is about 467nm±20nm, the light-emitting element of the sub-pixel may also output light without passing through the color conversion layer 183. When the wavelength of the light emitted by the light-emitting element is 410nm±20nm, in order to convert the wavelength of the output light to about 467nm±20nm, a color conversion layer 183 is preferably provided.

[0121] Even in the case of a blue sub-pixel, the sub-pixel may include a filter layer 184. By providing the filter layer 184 in the blue sub-pixel, minute reflection of external light generated on the surface of the light-emitting element of the sub-pixel can be suppressed.

[0122] (Variation Example)

[0123] Modifications of the sub-pixel structure will be described.

[0124] Figure 2A and Figure 2B Each of the schematic cross-sectional views illustrates a part of a modified example of the image display device according to the present embodiment.

[0125] exist Figure 2A In, for Figure 1 The light emitting element 150-1 is shown as one of the two light emitting elements 150-1 and 150-2 provided on the light reflecting plate 130a. The structure related to the two light emitting elements 150-1 and 150-2 is the same. Regarding this variation, the following is a description of matters related to the structure including the light emitting element 150-1. Figure 2B In the embodiment, the light emitting element 150a-1 and the light emitting element 150a-1 described below Fig.9A The structure of the light emitting element 150 a - 2 shown is also the same, and matters related to the structure of the light emitting element 150 a - 1 will be described.

[0126] exist Figure 2A In the subsequent cross-sectional views of the sub-pixels, the surface resin layer 170 and the color filter 180 are not shown in order to avoid complication. In the subsequent drawings, unless otherwise specified, the surface resin layer 170 and the color filter 180 are provided on the second interlayer insulating film 156, 256 and the second wiring layer 160. The same is true for other embodiments and their modified examples described later.

[0127] exist Figure 2A In the sub-pixel 20a-1, the connection method between the light emitting element 150-1 and the wiring 160a1-1 is different from that in the first embodiment. The same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0128] like Figure 2A As shown, the sub-pixel 20a-1 includes a wiring 160a1-1. In this modification, the wiring 160a1-1 is different from the wiring 160a-1 in the case of the first embodiment.

[0129] Wiring 160a1-1 extends to light emitting surface 153S1 of light emitting element 150-1, and one end of wiring 160a1-1 is electrically connected to the surface of p-type semiconductor layer 153-1 including light emitting surface 153S1. Light emitting surface 153S1 and the surface including light emitting surface 153S1 are on the same plane.

[0130] The light emitting surface 153S1 is preferably roughened as in the above-mentioned embodiment. When the light emitting surface 153S1 of the light emitting element 150-1 is roughened, the light extraction efficiency can be improved.

[0131] exist Figure 2B In the sub-pixel 20b-1, the difference from the first embodiment is that the light-emitting element 150a-1 includes a p-type semiconductor layer 153a-1 that is not roughened. In the sub-pixel 20b-1, the connection method between the light-emitting element 150a-1 and the wiring 160a2-1 is different from that in the first embodiment.

[0132] like Figure 2B As shown, in the sub-pixel 20b-1, the second interlayer insulating film (second insulating film) 256 is a resin with light transmittance, preferably a transparent resin. As a transparent resin material, a silicon-based resin such as SOG, a phenolic varnish-type phenolic-based resin, etc. can be used. The light-emitting element 150a-1 emits light from the light-emitting surface 153S1 via the transparent interlayer insulating film 256. The light-emitting surface 153S1 is connected to the wiring 160a2-1 of the second wiring layer 160 via a contact hole.

[0133] In the sub-pixel 20b-1 of this variation, the light-emitting element 150a-1 emits light from the light-emitting surface 153S1 via the interlayer insulating film 256. Therefore, the steps of forming an opening in the interlayer insulating film 256 and roughening the light-emitting surface 153S1 can be omitted.

[0134] In this embodiment, any of the structures of the sub-pixels 20 - 1 , 20 a - 1 , and 20 b - 1 described above may be included.

[0135] Figure 3 : is a schematic block diagram illustrating an image display device according to this embodiment.

[0136] like Figure 3 As shown, the image display device 1 of this embodiment has a display area 2. Sub-pixels 20 are arranged in the display area 2. The sub-pixels 20 are arranged in a grid pattern, for example. For example, n sub-pixels 20 are arranged along the X axis, and m sub-pixels 20 are arranged along the Y axis.

[0137] The pixel 10 includes a plurality of sub-pixels 20 that emit light of different colors. The sub-pixel 20R emits red light. The sub-pixel 20G emits green light. The sub-pixel 20B emits blue light. By emitting light at a desired brightness, the color and brightness of light emitted by one pixel 10 can be determined.

[0138] A pixel 10 includes three sub-pixels 20R, 20G, and 20B. The sub-pixels 20R, 20G, and 20B are as follows. Figure 3 In the example shown, the sub-pixels are arranged in a straight line on the X axis. In each pixel 10, sub-pixels of the same color may be arranged in the same column, or, as shown in this example, sub-pixels of different colors may be arranged in each column.

[0139] The image display device 1 further includes a power line 3 and a ground line 4. The power line 3 and the ground line 4 are arranged in a grid shape along the arrangement of the sub-pixels 20. The power line 3 and the ground line 4 are electrically connected to each sub-pixel 20, and power is supplied to each sub-pixel 20 from a DC power supply connected between a power terminal 3a and a GND terminal 4a. The power terminal 3a and the GND terminal 4a are respectively provided at the ends of the power line 3 and the ground line 4, and are connected to a DC power supply circuit provided outside the display area 2. The power terminal 3a supplies a positive voltage with reference to the GND terminal 4a.

[0140] The image display device 1 further includes a scanning line 6 and a signal line 8. The scanning line 6 is wired in a direction parallel to the X axis. That is, the scanning line 6 is wired along the arrangement of the sub-pixels 20 in the row direction. The signal line 8 is wired in a direction parallel to the Y axis. That is, the signal line 8 is wired along the arrangement of the sub-pixels 20 in the column direction.

[0141] The image display device 1 further includes a row selection circuit 5 and a signal voltage output circuit 7. The row selection circuit 5 and the signal voltage output circuit 7 are provided along the outer edge of the display area 2. The row selection circuit 5 is provided along the Y-axis direction of the outer edge of the display area 2. The row selection circuit 5 is electrically connected to the sub-pixels 20 of each column via the scanning lines 6, and supplies a selection signal to each sub-pixel 20.

[0142] The signal voltage output circuit 7 is provided along the X-axis direction of the outer edge of the display region 2. The signal voltage output circuit 7 is electrically connected to the sub-pixels 20 of each row via the signal lines 8, and supplies a signal voltage to each sub-pixel 20.

[0143] The sub-pixel 20 includes a light emitting element 22, a selection transistor 24, a driving transistor 26, and a capacitor 28. Figure 3 In the diagram, the selection transistor 24 is sometimes represented by T1, the drive transistor 26 is sometimes represented by T2, and the capacitor 28 is sometimes represented by Cm.

[0144] The light emitting element 22 is connected in series with the driving transistor 26. In the present embodiment, the driving transistor 26 is a p-channel TFT, and the main electrode, i.e., the drain electrode, of the driving transistor 26 is connected to an anode electrode connected to the p-type semiconductor layer of the light emitting element 22. The series circuit of the light emitting element 22 and the driving transistor 26 is connected between the power supply line 3 and the ground line 4. The driving transistor 26 corresponds to, for example, Figure 1 The transistor 103, the light emitting element 22 corresponds to Figure 1 The light emitting element 150. The current flowing to the light emitting element 22 is determined by the voltage applied between the gate and the source of the driving transistor 26, and the light emitting element 22 emits light with a brightness corresponding to the flowing current.

[0145] The selection transistor 24 is connected between the gate electrode of the drive transistor 26 and the signal line 8 via a main electrode. The gate electrode of the selection transistor 24 is connected to the scanning line 6. The capacitor 28 is connected between the gate electrode of the drive transistor 26 and the power supply line 3.

[0146] The row selection circuit 5 selects a row from the arrangement of the m rows of sub-pixels 20, and supplies a selection signal to the scanning line 6. The signal voltage output circuit 7 supplies a signal voltage having a required analog voltage value to each sub-pixel 20 of the selected row. The signal voltage is applied between the gate and the source of the driving transistor 26 of the sub-pixel 20 of the selected row. The signal voltage is held by the capacitor 28. The driving transistor 26 flows a current corresponding to the signal voltage to the light-emitting element 22. The light-emitting element 22 emits light at a brightness corresponding to the current flowing in the light-emitting element 22.

[0147] The row selection circuit 5 sequentially switches the selected row and supplies the selection signal. That is, the row selection circuit 5 scans the row where the sub-pixels 20 are arranged. A current corresponding to the signal voltage flows to the light-emitting element 22 of the sequentially scanned sub-pixel 20, and the light is emitted. Each pixel 10 emits light with the color and brightness determined by the color and brightness of the light emitted by the sub-pixel 20 of each RGB color, and an image is displayed in the display area 2.

[0148] Figure 4 This is a schematic plan view illustrating a part of the image display device according to this embodiment.

[0149] In this embodiment, if Figure 1 In the description, the light emitting element 150-1 (in Figure 3 The light emitting element 22) and the driving transistor 103 (in Figure 3The anode electrode of the light emitting element 150-1 is electrically connected to the drain electrode of the driving transistor 103 through the through hole 161d. In addition, the cathode electrode of the light emitting element 150-1 is connected to the light reflecting plate 130a, and the light reflecting plate 130a is connected to the through hole 161k. Figure 3 The light emitting element 150-2 is electrically connected to the ground line 4. Similarly, the anode electrode and the cathode electrode of the light emitting element 150-2 are electrically connected to a predetermined circuit via a through hole. Figure 4 The above-mentioned three-dimensional structure is decomposed into two top views and schematically represented.

[0150] Figure 4 The upper part schematically shows a top view of layer I, and the lower part schematically shows a top view of layer II. Figure 4 In the embodiment, the first layer is denoted as "I" and the second layer is denoted as "II". The first layer is a layer where the light emitting elements 150-1 and 150-2 are formed. Figure 1 denoted in FIG. 1 , the main components closer to the positive side of the Z axis than the first interlayer insulating film 112. The main components are the layers from the light reflection plate 130a to the second wiring layer 160. Figure 4 In the figure, the second interlayer insulating film 156 is not shown.

[0151] Level II Figure 1 1 shows the main components closer to the positive side of the Z axis than the TFT lower film 106, and the main components are the layers from the transistor 103 to the first interlayer insulating film 112. Figure 4 In the figure, the substrate 102, the insulating layer 105, the insulating film 108 and the first interlayer insulating film 112 are not shown.

[0152] Figure 1 The cross-sectional view is in Figure 4 The sagittal cross-section of the layer I and the layer II of the AA' line is represented by a dashed line.

[0153] In this embodiment, the case where the wiring 160k of the first layer and the wiring 110s of the second layer extend substantially parallel to the Y axis on substantially the same X coordinate is exemplified. Figure 4 The end of the A side is on the AA' line of the wiring 160k and the wiring 110s. The wirings 160k and 110s extend along the Y axis on the same X coordinate and are arranged parallel to each other. Therefore, in the cross-sectional view of the AA' line, the cross section of the end of the A side of the wiring 160k actually exists above the wiring 110s. However, when the cross section of the wiring 160k at the end of the A side is shown, the illustration becomes complicated, so Figure 1In the cross-sectional views of the drawings, for the end of the A side, the cross-section of the wiring 110s is shown, and for the B region including the wiring 160k and the translucent electrode 159k, it is not shown. In addition, for the A' side, the cross-section of the wiring 160k and the translucent electrode 159k is shown, and for the C region including the wiring 110s, it is not shown. The same is also true in the other embodiments described below. In the B region, although the wiring 160k and the translucent electrode 159k of the first layer exist in the cutting line AA' line, it is an unmarked area in the cross-sectional view. In the C region, although the wiring 110s of the second layer exists in the cutting line AA' line, it is an unmarked area in the cross-sectional view.

[0154] like Figure 4 As shown in FIG. 1 , the light emitting elements 150 - 1 and 150 - 2 are disposed on the light reflecting plate 130 a. Figure 1 The through hole 161k is shown connected. Figure 1 The through hole 161k shown is connected to the wiring 160k at the contact hole 162k1.

[0155] The light emitting element 150-1 has an opening 158-1 of the interlayer insulating film. The light emitting element 150-1 has a through hole 161d adjacent thereto. The through hole 161d is formed at Figure 4 In the diagram, the through hole 161d is schematically indicated by a two-dot chain line. In the first layer, the through hole 161d is connected to the wiring 160a-1 through the contact hole 162d1. The light-transmitting electrode 159a1 is provided over the light-emitting element 150-1 and the wiring 160a-1 exposed from the opening 158-1, and the light-emitting element 150-1 is electrically connected to the through hole 161d. In the second layer, the through hole 161d is connected to the wiring 110d through the contact hole 162d2.

[0156] The wiring 110d is connected to the insulating film 108 through a contact hole 111c1 opened in the insulating film 108. Figure 1 The through hole 111 d shown is connected to a drain electrode provided in the TFT channel 104 of the transistor 103 .

[0157] In this way, the light emitting element 150-1 formed on the first layer can be electrically connected to the wiring 110d formed on the second layer different from the first layer through the through hole 161d penetrating the two interlayer insulating films 112 and 156, and the light emitting element 150-1 can be electrically connected to the transistor 103. Similarly, the interlayer connection between the light emitting element 150-2 and the transistor driving the light emitting element 150-2 is also performed through the through hole provided through the two interlayer insulating films.

[0158] use Figure 4 , the configuration of the light reflecting plate 130a and the light emitting elements 150-1 and 150-2 will be described.

[0159] The light reflecting plate 130a is a square having a length L1 in the X-axis direction and a length W1 in the Y-axis direction in the XY plan view. On the other hand, the light emitting element 150-1 has a square bottom surface having a length L21 in the X-axis direction and a length W2 in the Y-axis direction in the XY plan view. The light emitting element 150-2 has a square bottom surface having a length L22 in the X-axis direction and a length W2 in the Y-axis direction in the XY plan view.

[0160] The lengths of each part are set so that L1>L21, L1>L22, and W1>W2. That is, the area of ​​the light reflecting plate 130a is set larger than the sum of the areas of the light emitting elements 150-1 and 150-2. The light reflecting plate 130a is disposed directly below the light emitting elements 150-1 and 150-2, and the periphery of the light reflecting plate 130a includes the entire periphery of the light emitting elements 150-1 and 150-2. As long as the periphery of the light reflecting plate 130a includes the entire periphery of the light emitting elements 150-1 and 150-2. The shape of the light reflecting plate 130a can be any appropriate shape according to the design on the circuit substrate 100, etc., and is not limited to the square shape.

[0161] The light emitting element 150 emits light upward. On the other hand, there is radiated (emitted) light emitted downward from the light emitting element 150, and there is scattered light and the like in the reflected light at the interface between the interlayer insulating film 112 and the surface resin layer 170. Since the conductive layer 130 includes a light reflecting plate 130a having light reflectivity, the scattered light downward from the light emitting elements 150-1 and 150-2 is reflected upward by the light reflecting plate 130a. Therefore, the proportion of light emitted from the light emitting elements 150-1 and 150-2 distributed toward the light emitting surfaces 153S1 and 153S2 increases. Therefore, the actual light emitting efficiency of the light emitting element 150 is improved. In addition, by setting the light reflecting plate 130a in this way, light is suppressed from reaching the bottom of the light emitting elements 150-1 and 150-2, so even when the circuit elements are arranged near directly below the light emitting elements 150-1 and 150-2, the influence of light on the circuit elements can be reduced.

[0162] The conductive layer 130 is not limited to being connected to the ground line 4 via the light reflecting plate 130a, and may be connected to another potential such as the potential of the power line 3 according to the circuit structure and circuit design.

[0163] A method for manufacturing the image display device 1 according to the present embodiment will be described.

[0164] Figure 5A to Figure 7B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0165] like Figure 5AAs shown in FIG. 1 , in the method for manufacturing the image display device 1 of the present embodiment, a circuit substrate 1100 is prepared. The circuit substrate (first substrate) 1100 includes Figure 1 The circuit 101 described in, etc. In the circuit substrate 1100 , a first interlayer insulating film (first insulating film) 112 is provided so as to cover the wiring layer 110 .

[0166] like Figure 5B As shown, a conductive layer 1130 is formed on the interlayer insulating film 112. The conductive layer 1130 is formed by forming a layer of a metal material forming the conductive layer 1130 by sputtering or the like on the entire surface of the interlayer insulating film 112, and then patterning is performed to leave a position for forming a light-emitting element. Alternatively, a mask having a pattern that opens a position for forming a light-emitting element may be provided on the interlayer insulating film 112, and then a patterned conductive layer is formed. A metal material such as Cu or Hf is used for the conductive layer 1130. For forming the conductive layer 1130 at a low temperature, sputtering or the like is preferably used.

[0167] The patterned conductive layer 1130 is crystallized by annealing. Preferably, the annealing is performed to crystallize the entire patterned conductive layer 1130. The crystallization of the conductive layer 1130 is suitably performed by annealing by laser irradiation, for example. In pulse laser annealing, the conductive layer 1130 can be crystallized while suppressing the influence of the temperature on the lower layer relative to the conductive layer at a low temperature of about 400° C. to about 500° C., so it is suitable for processing the circuit substrate 1100 formed by the LTPS process.

[0168] like Fig. 6A As shown, the semiconductor layer 1150 is formed over the single-crystallized conductive layer 1130a. The semiconductor layer 1150 is formed in the order of the n-type semiconductor layer 1151, the light-emitting layer 1152, and the p-type semiconductor layer 1153 from one side of the conductive layer 1130a to the positive direction of the Z axis. In the early stage of the growth of the semiconductor layer 1150, crystal defects are easily generated due to lattice mismatch, and the crystal with GaN as the main component usually exhibits n-type semiconductor characteristics. Therefore, by growing from the n-type semiconductor layer 1151 on the conductive layer 1130a, the yield can be improved.

[0169] The formation of the semiconductor layer 1150 can utilize physical vapor phase growth methods such as evaporation, ion beam deposition, molecular beam epitaxy (MBE), sputtering, and preferably utilize low-temperature sputtering. It should be noted that in the low-temperature sputtering method, when light or plasma is assisted during film formation, a lower temperature can be achieved, and therefore it is preferred. In epitaxial growth by MOCVD, it sometimes exceeds 1000°C. In contrast, it is known that in the low-temperature sputtering method, at a low temperature of about 400°C to about 700°C, a GaN crystal including a light-emitting layer can be epitaxially grown on a single crystal metal layer (refer to non-patent documents 1, 2, etc.). The above-mentioned low-temperature sputtering method is consistent with forming the semiconductor layer 1150 on a circuit substrate having a TFT, etc. formed by the LTPS process. By using an appropriate film forming technique, a GaN semiconductor layer 1150 is grown on the entire surface of the single-crystallized conductive layer 1130a, thereby forming a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 on the conductive layer 1130a. The conductive layer 1130a is patterned so that there are locations where the conductive layer 1130a does not exist and locations in the conductive layer that are not single-crystallized, such as Fig. 6A As shown by the dotted line, a deposit 1160 including GaN but not subjected to single crystallization is formed.

[0170] In this embodiment, the conductive layer 1130a of a single crystal metal is used as a seed crystal to promote the crystal formation of GaN. In the case where the semiconductor layer 1150 is formed on the single crystal conductive layer 1130a, a conductive buffer layer may be provided on the conductive layer 1130a, and a semiconductor layer may be grown on the buffer layer by the above-mentioned low temperature sputtering method or the like. The buffer layer may be made of a material that promotes the crystal formation of GaN, regardless of its type. The graphene sheet in the case of other embodiments described later may also be used.

[0171] like Figure 6B As shown, the conductive layer is shaped into a conductive layer 130 having a desired shape and pattern by etching or the like. The conductive layer 130 includes a light reflecting plate (portion) 130a. The semiconductor layer 1150 is shaped into a desired shape by etching or the like to form light emitting elements 150-1 and 150-2. In this example, the area of ​​the light emitting element 150-1 in the XY plan view is formed to be smaller than the area of ​​the light emitting element 150-2 in the XY plan view. Thereafter, a second interlayer insulating film (second insulating film) 156 is formed to cover the first interlayer insulating film 112, the conductive layer 130, and the light emitting elements 150-1 and 150-2.

[0172] like Fig. 7AAs shown, the via hole 162k is formed to penetrate the second interlayer insulating film 156. The via hole 162d is formed to penetrate the interlayer insulating films 112 and 156. When the via holes 162k and 162d are formed, openings 158-1 and 158-2 are formed in the interlayer insulating film 156 to expose the light emitting surfaces 153S1 and 153S2. The openings 158-1 and 158-2 may be formed before or after the via holes 162k and 162d are formed. The exposed light emitting surfaces 153S1 and 153S2 are roughened.

[0173] like Figure 7B As shown, Fig. 7A The via holes 162d and 162k shown are filled with a conductive material. Afterwards, or while the via holes are filled, the second wiring layer 160 is formed. A light-transmitting electrode 159a1 is formed over the light-emitting surface 153S1 and the wiring 160a-1, electrically connecting the p-type semiconductor layer 153-1 and the wiring 160a-1. At the same time, a light-transmitting electrode 159a2 is formed over the light-emitting surface 153S2, and the light-transmitting electrode 159a2 is electrically connected to an electrode for a driving transistor other than the transistor 103. A light-transmitting electrode 159k is also formed on the wiring 160k at the same time.

[0174] It should be noted that, as described above, the interlayer insulating film 156 can be covered for the purpose of insulating the light emitting elements 150-1, 150-2, etc. The flatness of the interlayer insulating film 156 can be such that the second wiring layer 160 can be formed on the interlayer insulating film 156, and planarization may not be performed when the interlayer insulating film 156 is formed. In the case where the interlayer insulating film 156 is not planarized, in addition to being able to reduce the number of steps for planarization, there is also an advantage that the thickness of the interlayer insulating film 156 can be thinned at locations other than the locations where the light emitting elements 150-1, 150-2 are formed. The depth of the via holes 162k, 162d can be reduced at locations where the thickness of the interlayer insulating film 156 is thinner. By forming the via hole shallower, a sufficient opening diameter can be ensured throughout the depth of the via hole, so that it is easy to ensure electrical connection by the through hole. Therefore, it is possible to suppress the reduction in yield due to problems with electrical characteristics.

[0175] Fig. 8A and Figure 8B This is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device of the present embodiment.

[0176] Fig. 8A and Figure 8B Indicates the use to form Figure 2AIn this modification, before the openings 158-1 and 158-2 are formed, the same steps as those in the other embodiments are performed. Fig. 7A Later, execute Fig. 8A and Figure 8B The situation of the process is explained below.

[0177] like Fig. 8A As shown, after the openings 158-1 and 158-2 are formed to expose the light emitting surfaces 153S1 and 153S2 of the p-type semiconductor layers 153-1 and 153-2, the light emitting surfaces 153S1 and 153S2 are roughened. Figure 7B Similar to the embodiment shown, a conductive material is filled into via hole 162k penetrating interlayer insulating film 156 to form through hole 161k. Similarly, a conductive material is filled into via hole 162d penetrating interlayer insulating films 112 and 156 to form through hole 161d.

[0178] like Figure 8B As shown, a wiring layer 160 including wirings 160a1-1, 160a1-2, and 160k is formed on the interlayer insulating film 156. The wiring 160a1-1 is connected to the surface including the exposed light emitting surface 153S1. The wiring 160a1-2 is connected to the surface including the exposed light emitting surface 153S2.

[0179] In this way, sub-pixels 20 a - 1 and 20 a - 2 according to the modification are formed.

[0180] Fig.9A and Fig. 9B This is a schematic cross-sectional view illustrating a method for manufacturing a modified example of the image display device of the present embodiment.

[0181] Fig.9A and Fig. 9B Indicates the use to form Figure 2B In this variant, before forming the light emitting element, the same steps as those in the other embodiments are performed. Fig. 6A Later, execute Fig.9A and Fig. 9B In the case of other embodiments, the interlayer insulating film 156 is formed of an insulating material having opacity such as white resin, whereas in this modification, the interlayer insulating film 256 is formed of an insulating material having translucency as described above.

[0182] like Fig.9A As shown, Fig. 6AThe conductive layer 1130a shown is formed into the conductive layer 130 having a desired shape and pattern by etching or the like. The conductive layer 130 includes a light reflecting plate 130a. Fig. 6A The semiconductor layer 1150 shown is shaped into a desired shape by etching or the like to form light emitting elements 150a-1 and 150a-2. Then, a second interlayer insulating film 256 is formed to cover the first interlayer insulating film 112, the conductive layer 130, and the light emitting elements 150a-1 and 150a-2. The interlayer insulating film 256 is an insulating resin having light transmittance, preferably a transparent resin.

[0183] Contact holes 162a-1 and 162a-2 are formed in the second interlayer insulating film 256. A via hole 162k is formed to pass through the interlayer insulating film 256. A via hole 162d is formed to pass through the interlayer insulating films 112 and 156. The contact holes and the via holes are formed by, for example, RIE or the like.

[0184] like Fig. 9B As shown, the contact holes 162a-1, 162a-2 and the via holes 162d, 162k are filled with a conductive material. Thereafter, the second wiring layer 160 is formed, and wirings 160a2-1, 160a2-2, 160k are formed. The wiring 160a2-1 is connected to the p-type semiconductor layer 153a-1 at one end, and is connected to the wiring 110d at the other end via the through hole 161d. The wiring 160a2-2 is connected to the p-type semiconductor layer 153a-2 at one end, and is connected to wirings for other driving transistors at the other end via the through hole. The second wiring layer 160 may also be formed while the via holes 162d, 162k are filled with a conductive material.

[0185] In this way, sub-pixels 20b-1 and 20b-2 according to the modification are formed.

[0186] Part of the circuit other than the sub-pixels 20 - 1 and 20 - 2 is formed in the circuit substrate 1100 . Figure 3 The row selection circuit 5 shown is formed together with the driving transistor, the selection transistor, etc. in the circuit substrate 1100. That is, the row selection circuit 5 is sometimes assembled at the same time through the above-mentioned manufacturing process. On the other hand, the signal voltage output circuit 7 is preferably assembled in a semiconductor device manufactured by a manufacturing process that can be highly integrated through fine processing. The signal voltage output circuit 7 is mounted on another substrate together with the CPU and other main circuit components, for example, before assembling the color filter described later, or after assembling the color filter, and is connected to the wiring of the circuit substrate 1100.

[0187] For example, the circuit substrate 1100 includes a light-transmitting substrate 102 formed of a glass substrate having a circuit 101. The substrate 102 is substantially square. The circuit 101 for one or more image display devices is formed on the circuit substrate 1100. In the case of a larger screen size, the circuit 101 for constituting one image display device may be divided into a plurality of circuit substrates 1100, and all the divided circuits may be combined to constitute one image display device.

[0188] The circuit substrate 1100 includes a substrate 102, and a plurality of circuits 101 are arranged in a grid pattern on the substrate 102. The circuit 101 includes all sub-pixels 20 required for one image display device 1. A gap of the width of a scribe line is provided between adjacently arranged circuits 101. No circuit elements are arranged at or near the ends of the circuit 101.

[0189] Fig.10 This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0190] exist Fig.10 In order to avoid complication, the structure of the circuit substrate 100 is not shown. Figure 1 The interlayer insulating film 112, through holes 161d, 161k, and wiring layer 160 shown in FIG. Fig.10 1 shows a portion of the color conversion components such as the color filter 180. Fig.10 In the figure, the structure including the conductive layer 130, the light emitting element 150, the interlayer insulating film 156, the surface resin layer 170, and the through hole (not shown) is referred to as the light emitting circuit portion 172. In addition, the structure provided with the light emitting circuit portion 172 on the circuit substrate 100 is referred to as the structure 1192.

[0191] like Fig.10 As shown, the color filter (wavelength conversion component) 180 is bonded to the structure 1192 on one side. The other side of the color filter 180 is bonded to the glass substrate 186. A transparent film adhesive layer 188 is provided on one side of the color filter 180, and is bonded to the surface of the light emitting circuit portion 172 of the structure 1192 via the transparent film adhesive layer 188.

[0192] In this example, the color filter 180 has color conversion sections arranged in the order of red, green, and blue in the positive direction of the X axis. For red, a red color conversion layer 183R is provided in the first layer, and for green, a green color conversion layer 183G is provided in the first layer. For blue, a blue color conversion layer 183B is provided in the first layer. In either case, a filter layer 184 is provided in the second layer, but the frequency characteristics of the filter layer 184 can be changed for each color of the color conversion section. For blue, a single-layer color conversion layer 183B can also be provided. A light shielding section 181 is provided between each color conversion section.

[0193] The positions of the color conversion layers 183R, 183G, and 183B of the respective colors are aligned with the position of the light emitting element 150 , and the color filter 180 is attached to the structure 1192 .

[0194] FIG. 11A to FIG. 11D This is a schematic cross-sectional view showing a modified example of the method for manufacturing the image display device according to the present embodiment.

[0195] FIG. 11A to FIG. 11D A method of forming a color filter by inkjet is shown.

[0196] like Fig.11A As shown in FIG. 1 , a structure 1192 in which the light emitting circuit portion 172 is attached to the circuit substrate 1100 is prepared.

[0197] like Fig. 11B As shown in FIG. 1 , a light shielding portion 181 is formed on the structure 1192. The light shielding portion 181 is formed by, for example, screen printing, photolithography technology, or the like.

[0198] like Fig. 11C As shown, the phosphor corresponding to the luminous color is ejected from the inkjet nozzle to form a color conversion layer 183. The phosphor is colored in the area where the shading portion 181 is not formed. The phosphor can use a fluorescent paint, which uses, for example, a common fluorescent material, a perovskite fluorescent material, or a quantum dot fluorescent material. When a perovskite fluorescent material or a quantum dot fluorescent material is used, various luminous colors can be achieved, and the monochromaticity is increased, which can improve the color reproducibility, and is therefore preferred. After being drawn by the inkjet nozzle, a drying process is performed at an appropriate temperature and time. When coloring, the thickness of the coating is set to be thinner than the thickness of the shading portion 181.

[0199] As described above, for the sub-pixel emitting blue light, when the color conversion unit is not formed, the phosphor is not ejected. In addition, for the sub-pixel emitting blue light, when a blue color conversion layer is formed, when the color conversion unit can be a single layer, it is preferred that the coating thickness of the blue phosphor is about the same as the thickness of the light shielding unit 181a.

[0200] like Fig.11D As shown, the paint for the filter layer 184 is ejected from an inkjet nozzle. The paint is applied so as to overlap with the coating film of the fluorescent body 183a. The total thickness of the coating film of the fluorescent body and the paint is about the same as the thickness of the light shielding portion 181.

[0201] Effects of the image display device 1 of the present embodiment will be described.

[0202] In the manufacturing method of the image display device 1 of the present embodiment, circuit elements such as the transistor 103 driving the light-emitting elements 150-1 and 150-2 are formed in advance on the circuit substrate 1100, and the conductive layer 1130 is formed on the interlayer insulating film 112 of the circuit substrate 1100. The conductive layer 1130 is crystallized by annealing the entire surface. The semiconductor layer 1150 can be formed on the crystallized conductive layer 1130a. By molding the formed semiconductor layer 1150 into a desired shape, the light-emitting elements 150-1 and 150-2 connected to the conductive layer 130 can be formed. Therefore, compared with the case where the monolithic light-emitting elements are individually transferred on the circuit substrate 1100a, the process of transferring the light-emitting elements 150-1 and 150-2 can be shortened.

[0203] For example, in a 4K image display device, the number of sub-pixels exceeds 24 million, and in an 8K image display device, the number of sub-pixels exceeds 99 million. It takes a lot of time to mount such a large number of light-emitting elements individually on a circuit substrate, and it is difficult to realize an image display device formed by micro-LEDs at a realistic cost. In addition, mounting a large number of light-emitting elements individually will reduce the yield rate due to connection problems during installation, which will inevitably increase costs.

[0204] In contrast, in the method for manufacturing the image display device 1 of the present embodiment, the light emitting elements 150 - 1 and 150 - 2 are formed after the semiconductor layer 1150 is entirely formed on the conductive layer 1130 formed on the circuit substrate 1100 . This reduces the number of transfer steps for the light emitting elements.

[0205] The semiconductor layer 1150 having a uniform crystal structure is grown on the conductive layer 1130a of the single crystal metal, so by appropriately patterning the conductive layer 1130a, the light emitting element can be arranged in a self-aligned manner. Therefore, it is not necessary to align the light emitting element on the circuit substrate 1100, and it is easy to miniaturize the light emitting elements 150-1 and 150-2, which is suitable for high-definition displays.

[0206] After the light emitting element is directly formed on the circuit substrate by etching or the like, the light emitting element is electrically connected to the circuit element in the circuit substrate 1100 by forming a through hole, so that a uniform connection structure can be achieved and a reduction in yield can be suppressed.

[0207] In this embodiment, for example, a TFT formed on a glass substrate can be used as the circuit substrate 1100 , so that existing flat panel manufacturing processes and equipment can be used.

[0208] In the image display device 1 of this embodiment, there is a conductive layer 130 including a light reflecting plate 130a, and a light emitting element is formed on the light reflecting plate 130a. The light emitting surfaces 153S1 and 153S2 of the light emitting elements 150 and 150a are arranged on the side opposite to the interlayer insulating film 112 provided with the light reflecting plate 130a. Therefore, the light scattered downward from the light emitting elements 150-1 and 150-2 is reflected by the light reflecting plate 130a and distributed to the light emitting surfaces 153S1 and 153S2. Therefore, the light emitting efficiency of the light emitting elements 150-1 and 150-2 is actually improved.

[0209] Since the light reflecting plate 130a blocks the scattered light from the light emitting elements 150-1 and 150-2, it is possible to suppress the light from irradiating the circuit elements located below and near the light emitting elements 150-1 and 150-2, thereby preventing the circuit elements from malfunctioning.

[0210] The light reflection plate 130a has conductivity and is ohmically connected to the n-type semiconductor layers 151-1 and 151-2, so that it can be used for electrical connection with the light emitting elements 150-1 and 150-2, and the number of wirings on the light emitting surfaces 153S1 and 153S2 can be reduced.

[0211] (Second Embodiment)

[0212] Fig.12 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0213] Fig.12 It means the equivalent of Figure 4 The sagittal section of the position of the AA' line.

[0214] In this embodiment, the difference from other embodiments is that the sub-pixels 220-1 and 220-2 include the graphene layer 140, and the graphene layer 140 includes the graphene sheets 140-1 and 140-2. In addition, in this embodiment, the difference from other embodiments is the structure of the light-emitting elements 250-1 and 250-2 and the structure of the transistor 203 driving the light-emitting elements. For the main components of the same structure as other embodiments, the same reference numerals are used, and detailed descriptions are appropriately omitted.

[0215] like Fig.12As shown, the sub-pixels 220-1 and 220-2 of the image display device of this embodiment include a graphene layer 140. The graphene layer 140 includes graphene sheets 140-1 and 140-2, and the graphene sheets 140-1 and 140-2 are provided on the light reflection plate 130a. The light-emitting element 250-1 is provided on the graphene sheet 140-1. The light-emitting element 250-2 is provided on the graphene sheet 140-2. In this example, although the graphene sheets 140-1 and 140-2 are provided separately for each light-emitting element 250-1 and 250-2, since the graphene sheet has conductivity, a plurality of light-emitting elements may be provided on one graphene sheet.

[0216] The two light emitting elements 250 - 1 and 250 - 2 are electrically connected via the graphene sheets 140 - 1 and 140 - 2 and the light reflecting plate 130 a .

[0217] In this embodiment, the light emitting element 250-1 is laminated in the order of the p-type semiconductor layer 253-1, the light emitting layer 252-1, and the n-type semiconductor layer 251-1 from the first interlayer insulating film 112 side to the light emitting surface 251S1 side. The light emitting element 250-2 is laminated in the order of the p-type semiconductor layer 253-2, the light emitting layer 252-2, and the n-type semiconductor layer 251-2 from the first interlayer insulating film 112 side to the light emitting surface 251S2 side. In this embodiment, the n-type semiconductor layers 251-1 and 251-2 are the light emitting surfaces 251S1 and 251S2.

[0218] The light emitting surfaces 251S1 and 251S2 are surfaces of the n-type semiconductor layers 251-1 and 251-2 that are opposite to the surfaces that are in contact with the light emitting layers 252-1 and 252-2. Both the light emitting surfaces 251S1 and 251S2 are roughened.

[0219] The light emitting elements 250-1 and 250-2 may be made of the same materials as those in the other embodiments described above. The light emitting element 350 emits, for example, blue light of about 467nm±20nm or violet light of a wavelength of 410nm±20nm.

[0220] The second interlayer insulating film (second insulating film) 156 covers the first interlayer insulating film 112, the conductive layer 130, the graphene sheets 140-1, 140-2, and the light emitting elements 250-1, 250-2. The second interlayer insulating film 156 has openings 258-1, 258-2. The openings 258-1, 258-2 are formed on the light emitting elements 250-1, 250-2, respectively, and the interlayer insulating film 156 is not provided on the light emitting surfaces 251S1, 251S2.

[0221] In this example, the transistor 203 is an n-channel TFT. The transistor 203 includes a TFT channel 204 and a gate 107. The TFT channel 204 is a region of polycrystalline Si formed on the first surface 102a of the substrate 102, and the region formed as amorphous Si is annealed by laser irradiation, thereby performing polycrystallization and activation. The TFT channel 204 includes regions 204s, 204i, and 204d. The regions 204s, 204i, and 204d are all arranged on the TFT lower film 106. The region 204i is arranged between the regions 204s and 204d. The regions 204s and 204d are doped with n-type impurities such as P and are ohmically connected to the through holes 111s and 111d.

[0222] The gate electrode 107 is provided on the TFT channel 204 via the insulating layer 105. When a higher potential than that of the region 204s is applied to the gate electrode 107, a channel is formed in the region 204i, thereby controlling the current flowing between the regions 204s and 204d.

[0223] The upper structure of the transistor 203 and the structure of the wiring layer 110 are the same as those in the above-mentioned other embodiments.

[0224] The through hole 161a is provided to penetrate the interlayer insulating film 156. One end of the through hole 161a is connected to the light reflecting plate 130a. The other end of the through hole 161a is connected to the wiring 260a. A light-transmitting electrode 259a is provided over the wiring 260a. The wiring 260a and the light-transmitting electrode 259a are, for example, the same as those described later. Fig.13 Therefore, the p-type semiconductor layers 253-1 and 253-2 of the light emitting elements 250-1 and 250-2 are electrically connected to the power line 3 via the graphene sheets 140-1 and 140-2, the light reflecting plate 130a, the through hole 161a, the wiring 260a and the light-transmitting electrode 259a.

[0225] The through hole 161d is provided to penetrate the interlayer insulating films 112 and 156. One end of the through hole 161d is connected to the wiring 110d. The wiring 110d is connected to the drain electrode of the transistor 203, that is, the region 204d, via the through hole 111d. The other end of the through hole 161d is connected to the wiring 260k1. A light-transmitting electrode 259k1 is provided over the wiring 260k1. The light-transmitting electrode 259k1 is provided over the light-emitting surface 251S1. The light-transmitting electrode 259k1 is provided between the wiring 260k1 and the light-emitting surface 251S1, and electrically connects the wiring 260k1 and the light-emitting surface 251S1.

[0226] Therefore, the n-type semiconductor layer 251 - 1 of the light emitting element 250 - 1 is electrically connected to the transistor 203 via the light-transmitting electrode 259 k 1 , the wiring 260 k 1 , the through hole 161 d , and the wiring 110 d .

[0227] The source electrode of the transistor 203, that is, the region 204s, is connected to the wiring 110s via the through hole 111s. The wiring 110s is connected to, for example, Fig.13 The ground wire 4 is connected.

[0228] The n-type semiconductor layer 251 - 2 of the light emitting element 250 - 2 is also electrically connected to the driving transistor of the light emitting element 250 - 2 via the light-transmitting electrode 259 k 2 , similarly to the case of the light emitting element 250 - 1 .

[0229] Fig.13 : is a schematic block diagram illustrating an image display device according to this embodiment.

[0230] like Fig.13 As shown, the image display device 201 of this embodiment includes a display region 2, a row selection circuit 205, and a signal voltage output circuit 207. As in the other embodiments described above, sub-pixels 220 are arranged in a grid pattern on the display region 2, for example, on the XY plane.

[0231] The pixel 10 is the same as the other embodiments described above, and includes a plurality of sub-pixels 220 that emit light of different colors. The sub-pixel 220R emits red light. The sub-pixel 220G emits green light. The sub-pixel 220B emits blue light. The three sub-pixels 220R, 220G, and 220B emit light at a desired brightness, thereby determining the luminous color and brightness of one pixel 10.

[0232] One pixel 10 is formed by three sub-pixels 220R, 220G, and 220B, and the sub-pixels 220R, 220G, and 220B are arranged in a straight line on the X axis, for example, as in this example. Each pixel 10 may arrange sub-pixels of the same color in the same column, or may arrange sub-pixels of different colors in each column, as in this example.

[0233] The sub-pixel 220 includes a light emitting element 222, a selection transistor 224, a driving transistor 226, and a capacitor 228. Fig.13 In the diagram, the selection transistor 224 is sometimes represented as T1, the driving transistor 226 is sometimes represented as T2, and the capacitor 228 is sometimes represented as Cm.

[0234] In this embodiment, the light emitting element 222 is provided on the power supply line 3 side, and the driving transistor 226 connected in series with the light emitting element 222 is provided on the ground line 4 side. That is, the driving transistor 226 is connected to the lower potential side than the light emitting element 222. The driving transistor 226 is an n-channel transistor.

[0235] The selection transistor 224 is connected between the gate electrode of the driving transistor 226 and the signal line 208. The capacitor 228 is connected between the gate electrode of the driving transistor 226 and the ground line 4.

[0236] The row selection circuit 205 and the signal voltage output circuit 207 supply a signal voltage having a different polarity from that in the other embodiments described above to the signal line 208 in order to drive the driving transistor 226 which is an n-channel transistor.

[0237] In this embodiment, since the polarity of the driving transistor 226 is an n-channel, the polarity of the signal voltage is different from that of the other embodiments described above. That is, the row selection circuit 205 supplies a selection signal to the scanning line 206 to sequentially select a row from the arrangement of the sub-pixels 220 in the m rows. The signal voltage output circuit 207 supplies a signal voltage having a required analog voltage value to each sub-pixel 220 in the selected row. The driving transistor 226 of the sub-pixel 220 in the selected row flows a current corresponding to the signal voltage to the light-emitting element 222. The light-emitting element 222 emits light at a brightness corresponding to the flowing current.

[0238] A method for manufacturing the image display device of this embodiment will be described.

[0239] Figures 14A to 15B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0240] In this embodiment, before the conductive layer 1130 is formed on the circuit substrate 1100 and the annealing process is performed, the process is the same as in the other embodiments described above. Figure 5B The steps after the shown processing will be described.

[0241] like Fig.14A As shown, the graphene layer 1140 is formed over the conductive layer 1130a that has been crystallized by patterning and annealing. The graphene layer 1140 is formed by a low temperature process such as pulse sputtering.

[0242] like Fig. 14B As shown, the semiconductor layer 1150 is formed over the graphene layer 1140. In this embodiment, the semiconductor layer 1150 is formed in the order of a p-type semiconductor layer 1153, a light emitting layer 1152, and an n-type semiconductor layer 1151 from the conductive layer 1130a side toward the positive direction of the Z axis.

[0243] The formation of the semiconductor layer 1150 is the same as in other embodiments, and can be achieved by physical vapor phase growth methods such as evaporation, ion beam deposition, MBE, sputtering, etc., preferably low-temperature sputtering. By growing the GaN semiconductor layer 1150 on the graphene layer 1140, a single-crystallized semiconductor layer 1150 including a light-emitting layer 1152 is formed over the graphene layer 1140 (see non-patent documents 1, 2, etc.).

[0244] It is known that when pulse sputtering is used, the crystal growth of GaN is promoted on the graphene layer. In this embodiment, the semiconductor layer 1150 is formed through the graphene layer 1140 grown on the conductive layer 1130a formed by the single crystal metal layer, so that the semiconductor layer 1150 with more stable and high-quality GaN crystals can be formed.

[0245] In addition, in this embodiment, since the conductive layer 130 and the light reflecting plate 130a are formed of a single crystal metal layer, they can be electrically connected to the semiconductor layer 1150 with low resistance.

[0246] like Fig. 14C As shown, the semiconductor layer 1150 is formed into a desired shape by RIE or the like to form light emitting elements 250-1 and 250-2. Fig. 14B The graphene layer 1140 shown is over-etched and formed into graphene sheets 140-1 and 140-2 having an outer peripheral shape corresponding to the outer peripheral shape of the light-emitting elements 250-1 and 250-2. The conductive layer 130 is also formed and forms a desired light reflecting plate 130a. After that, the second interlayer insulating film 156 is formed to cover the first interlayer insulating film 112, the conductive layer 130 and the light-emitting elements 250-1 and 250-2.

[0247] Then, if Fig.15A As shown, the via hole 162a is formed by penetrating the second interlayer insulating film 156. The via hole 162d is formed by penetrating the interlayer insulating films 112 and 256. When the via holes 162a and 162d are formed, openings 258-1 and 258-2 are formed in the interlayer insulating film 156 to expose the light emitting surfaces 251S1 and 251S2. The exposed light emitting surfaces 251S1 and 251S2 are roughened. The openings 258-1 and 258-2 may be formed before or after the via holes 162a and 162d are formed.

[0248] like Fig. 15B As shown, Fig.15AThe via holes 162a and 162d shown are filled with a conductive material to form through holes 161a and 161d. After that, the second wiring layer 160 is formed while the via holes are filled. Alternatively, the second wiring layer 160 is formed while the through holes 161a and 161d are formed. A light-transmitting electrode 259k1 is formed over the light-emitting surface 251S1 and the wiring 260k1 to electrically connect the n-type semiconductor layer 251-1 and the wiring 260k1. At the same time, a light-transmitting electrode 259k2 is formed over the light-emitting surface 251S2, and the light-transmitting electrode 259k2 is electrically connected to electrodes of other driving transistors that are not used for the transistor 203. It should be noted that the light-transmitting electrode 259a is also formed on the wiring 260a at the same time.

[0249] Thereafter, color filters are formed in the same manner as in the other embodiments.

[0250] In this way, the image display device of this embodiment can be manufactured.

[0251] The effects of the image display device of this embodiment will be described.

[0252] In addition to the effects of the above-mentioned other embodiments, this embodiment has the following effects. That is, in this embodiment, since the light-emitting elements 250-1 and 250-2 are formed on the single-crystal metal conductive layer 130 via the graphene sheets 140-1 and 140-2, the light-emitting elements 250-1 and 250-2 having a higher-quality crystal structure can be obtained. Therefore, the yield rate of the image display device can be improved.

[0253] (Third Embodiment)

[0254] In the image display device of this embodiment, circuit elements such as transistors are formed on a flexible substrate instead of a glass substrate. Other aspects are the same as those of the other embodiments described above, and the same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0255] Fig.16 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0256] Fig.16 It means the equivalent of Figure 4 The sagittal section showing the position of line AA' is shown.

[0257] like Fig.16As shown, the image display device of this embodiment has sub-pixels 320-1 and 320-2. The sub-pixels 320-1 and 320-2 include a common substrate 402. The substrate 402 includes a first surface 402a. Circuit elements such as the transistor 103 are provided on the first surface 402a. In the sub-pixels 320-1 and 320-2, the upper structure including the circuit elements is formed on the first surface 402a.

[0258] The substrate 402 is flexible. The substrate 402 is, for example, a polyimide resin. The interlayer insulating films 112, 156 and the wiring layers 110, 160 are preferably formed of a material having a certain degree of elasticity according to the flexibility of the substrate 402. It should be noted that the wiring layer 110 having the longest wiring length has the highest risk of being damaged when bent. Therefore, it is desirable to adjust the thickness, material, and film quality of various films so that the neutral surface, including the plurality of protective films added on the front and back surfaces, is located at the position of the wiring layer 110 as required.

[0259] In this example, the transistor 103 and the light emitting elements 150-1 and 150-2 formed on the substrate 402 are the same as those in the first embodiment, and for example, Figure 3 The circuit structure of the present invention can also be easily applied to structures including circuit structures of other embodiments.

[0260] A method for manufacturing the image display device of this embodiment will be described.

[0261] Figures 17A to 17B This is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to this embodiment.

[0262] like Fig.17A As shown, in this embodiment, a circuit substrate 3100 different from that in the above-mentioned other embodiments is prepared. The circuit substrate 3100 includes two-layer substrates 102 and 402. The substrate 402 is provided on the first surface 102a of the substrate 102, for example, by coating a polyimide material and firing it. An inorganic film such as SiNx may also be interposed between the two-layer substrates 102 and 402. The TFT lower layer film 106, the circuit 101, and the interlayer insulating film 112 are provided on the first surface 402a of the substrate 402. The first surface 402a of the substrate 402 is a surface opposite to the surface on which the substrate 102 is provided.

[0263] The circuit substrate 3100 is provided by applying Figures 5A to 11D The upper structure of the sub-pixels 320-1 and 320-2 is formed through the steps described in the above.

[0264] like Fig. 17BAs shown, the substrate 102 is removed from the structure including the upper structure such as the color filter to form a new circuit substrate 3100a. The removal of the substrate 102 can be performed by laser stripping, for example. The removal of the substrate 102 is not limited to the above-mentioned time point, and can also be performed at other appropriate time points. For example, the substrate 102 can also be removed after the wafer is bonded or before the color filter is formed. By removing the substrate 102 at an earlier time point, problems such as cracks and gaps in the manufacturing process can be reduced.

[0265] The effects of the image display device of this embodiment will be described.

[0266] Since the substrate 402 is flexible, it can be bent as an image display device, and can be attached to a curved surface or used in a wearable terminal without any discomfort.

[0267] (Fourth Embodiment)

[0268] In this embodiment, a plurality of light-emitting surfaces equivalent to a plurality of light-emitting elements are formed on a single semiconductor layer including a light-emitting layer, thereby realizing an image display device with higher light-emitting efficiency. In the following description, the same reference numerals are used for the main components of the same structure as in the other embodiments described above, and detailed description is appropriately omitted.

[0269] Fig.18 This is a schematic cross-sectional view illustrating a part of the image display device according to this embodiment.

[0270] like Fig.18 As shown, the image display device has a sub-pixel group 420. The sub-pixel group 420 includes transistors (multiple transistors) 103-1, 103-2, a first wiring layer (first wiring layer) 410, an interlayer insulating film (first insulating film) 112, a plug 416k, a conductive layer 430, a semiconductor layer 450, an interlayer insulating film (second insulating film) 456, and through holes (multiple through holes) 461d1, 461d2.

[0271] In this embodiment, by turning on the p-channel transistors 103-1 and 103-2, holes are injected into the semiconductor layer 450 through the wiring layer 460, and electrons are injected into the semiconductor layer 450 through the plug 416k, so that the light-emitting layer 452 emits light. Figure 3 The circuit structure shown in the figure. The above other embodiments can also be used to interchange the n-type semiconductor layer and the p-type semiconductor layer of the semiconductor layer, so as to form a structure in which the semiconductor layer is driven by an n-channel transistor. In this case, the driving circuit is suitable for example Fig.13 Circuit structure.

[0272] The semiconductor layer 450 includes two light emitting surfaces 453S1 and 453S2, and the sub-pixel group 420 actually includes two sub-pixels. In this embodiment, as in the case of the other embodiments described above, the sub-pixel group 420 including two sub-pixels is actually arranged in a grid to form a display area.

[0273] The transistors 103-1 and 103-2 are formed in TFT channels 104-1 and 104-2, respectively. In this example, the TFT channels 104-1 and 104-2 include regions doped to a p-type and include a channel region between the regions.

[0274] An insulating layer 105 is formed on the TFT channels 104-1 and 104-2, and gate electrodes 107-1 and 107-2 are formed via the insulating layer 105. The gate electrodes 107-1 and 107-2 are gate electrodes of the transistors 103-1 and 103-2. In this example, the transistors 103-1 and 103-2 are p-channel TFTs.

[0275] The two transistors 103 - 1 and 103 - 2 are covered with an insulating film 108 . On the insulating film 108 , a wiring layer 410 is formed.

[0276] Through holes 111s1 and 111d1 are provided between the p-type doped region of the transistor 103-1 and the wiring layer 410. Through holes 111s2 and 111d2 are provided between the p-type doped region of the transistor 103-2 and the wiring layer 410.

[0277] The wiring layer 410 includes wirings 410k, 410s1, 410s2, 410d1, and 410d2. The wiring 410k is connected to a plug 416k via a connection portion 415k. Figure 3 The ground wire 4 is shown connected.

[0278] The wiring 410s1 is electrically connected to a region corresponding to the source electrode of the transistor 103-1 via the through hole 111s1. The wiring 410s2 is electrically connected to a region corresponding to the source electrode of the transistor 103-2 via the through hole 111s2. Figure 3 The power cord 3 is shown connected.

[0279] The wiring 410d1 is connected to a region corresponding to the drain electrode of the transistor 103-1 through the through hole 111d1, and the wiring 410d2 is connected to a region corresponding to the drain electrode of the transistor 103-2 through the through hole 111d2.

[0280] The interlayer insulating film 112 covers the transistors 103-1 and 103-2 and the wiring layer 410. A plug 416k is formed on the interlayer insulating film 112.

[0281] The planarization film 414 is formed on the interlayer insulating film 112. The planarization film 414 is also provided on the side of the plug 416k. The plug 416k is buried in the planarization film 414, and the planarization film 414 and the plug 416k have surfaces in the same plane in an XY plan view. The above-mentioned surface is the surface on the side opposite to the surface on the interlayer insulating film 112 side.

[0282] A conductive layer 430 is provided on the planarization film 414 and the plug 416k. The conductive layer 430 includes a light reflecting plate 430a. The conductive layer 430 and the light reflecting plate 430a are configured in the same manner as in the other embodiments described above. That is, at least a portion of the conductive layer 430 is formed of a single crystal metal. Preferably, the entire conductive layer 430 is a single crystal metal layer. At least a portion of the light reflecting plate 430a is formed of a single crystal metal. At least the portion of the light reflecting plate 430a where the semiconductor layer 450 is provided is formed of a single crystal metal, for example, a single crystal metal layer. The conductive layer 430 and the light reflecting plate (portion) 430a are formed of a single crystal metal layer as a whole.

[0283] The semiconductor layer 450 is provided on the light reflecting plate 430a. The single crystal metal is, for example, Cu, Hf, or the like.

[0284] The semiconductor layer 450 includes an n-type semiconductor layer (first semiconductor layer) 451, a light-emitting layer 452, and a p-type semiconductor layer (second semiconductor layer) 453. The semiconductor layer 450 is laminated in the order of the n-type semiconductor layer 451, the light-emitting layer 452, and the p-type semiconductor layer 453 from the interlayer insulating film 112 side to the light-emitting surfaces 453S1 and 453S2 side. The n-type semiconductor layer 451 is provided on the light reflecting plate 430a and is electrically connected to the light reflecting plate 430a.

[0285] The interlayer insulating film 456 covers the planarizing film 414 and the conductive layer 430. The interlayer insulating film 456 covers a portion of the semiconductor layer 450. It is preferred that the interlayer insulating film 456 covers the surface of the p-type semiconductor layer 453 except for the light emitting surfaces (exposed surfaces) 453S1 and 453S2 of the semiconductor layer 450. The interlayer insulating film 456 covers the side surfaces of the semiconductor layer 450. The interlayer insulating film 456 is, for example, a white resin or a black resin.

[0286] The openings 458-1 and 458-2 are formed in the portion of the semiconductor layer 450 that is not covered by the interlayer insulating film 456. The openings 458-1 and 458-2 are formed at positions corresponding to the light emitting surfaces 453S1 and 453S2. The light emitting surfaces 453S1 and 453S2 are formed at intervals on the p-type semiconductor layer 453. The light emitting surface 453S1 is provided at a position closer to the transistor 103-1 on the p-type semiconductor layer 453. The light emitting surface 453S2 is provided at a position closer to the transistor 103-2 on the p-type semiconductor layer 453.

[0287] The openings 458-1 and 458-2 are, for example, square or rectangular in the XY plan view. The shape is not limited to a square, and may be a polygon such as a circle, an ellipse or a hexagon. The light-emitting surfaces 453S1 and 453S2 are also square, rectangular, other polygons, or a circle in the XY plan view. The shapes of the light-emitting surfaces 453S1 and 453S2 may be similar to the shapes of the openings 458-1 and 458-2, or may be different shapes.

[0288] The wiring layer 460 is provided on the interlayer insulating film 456. The wiring layer 460 includes wirings 460a1 and 460a2.

[0289] The through holes 461d1 and 461d2 are provided to penetrate the interlayer insulating films 112 and 456. The through hole 461d1 is provided between the wiring 410d1 and the wiring 460a1. One end of the through hole 461d1 is connected to the wiring 410d1, and the other end of the through hole 461d1 is connected to the wiring 460a1. The through hole 461d2 is provided between the wiring 410d2 and the wiring 460a2. One end of the through hole 461d2 is connected to the wiring 410d2, and the other end of the through hole 461d2 is connected to the wiring 460a2.

[0290] A light-transmitting electrode 459a1 is provided on the wiring 460a1, and the wiring 460a1 is electrically connected to the light-transmitting electrode 459a1. The light-transmitting electrode 459a1 extends in the opening 458-1. The light-transmitting electrode 459a1 is provided over the entire surface of the light-emitting surface 453S1 exposed from the opening 458-1, and is electrically connected to the p-type semiconductor layer 453 via the light-emitting surface 453S1.

[0291] A light-transmitting electrode 459a2 is provided on the wiring 460a2, and the wiring 460a2 is electrically connected to the light-transmitting electrode 459a2. The light-transmitting electrode 459a2 extends in the opening 458-2. The light-transmitting electrode 459a2 is provided over the entire surface of the light-emitting surface 453S2 exposed from the opening 458-2, and is electrically connected to the p-type semiconductor layer 453 via the light-emitting surface 453S2.

[0292] As described above, the light-emitting surfaces 453S1 and 453S2 exposed from the openings 458-1 and 458-2 are connected to the light-transmitting electrodes 459a1 and 459a2, respectively. When the transistor 103-1 is turned on, holes are injected into the light-transmitting electrode 459a1 via the wiring 460a1, the through hole 461d1, and the wiring 410d1. When the transistor 103-2 is turned on, holes are injected into the light-transmitting electrode 459a2 via the wiring 460a2, the through hole 461d2, and the wiring 410d2. On the other hand, electrons are injected into the n-type semiconductor layer 451 via the wiring 410k connected to the ground line 4, the connecting portion 415k, the plug 416k, and the light reflecting plate 430a.

[0293] Transistors 103-1 and 103-2 are driving transistors of adjacent sub-pixels and are driven in sequence. Therefore, holes injected from either of the two transistors 103-1 and 103-2 are injected into the light-emitting layer 452, and electrons injected from the light reflecting plate 430a are injected into the light-emitting layer 452, so that the light-emitting layer 452 emits light. When the transistor 103-1 is turned on, the light-emitting surface 453S1 emits light, and when the transistor 103-2 is turned on, the light-emitting surface 453S2 emits light. In this way, since the resistance of the p-type semiconductor layer 453 suppresses the drift current flowing in the direction parallel to the XY plane in the semiconductor layer 450, the light emission of the light-emitting layer 452 is localized.

[0294] A method for manufacturing the image display device of this embodiment will be described.

[0295] Figures 19A to 22B It is a schematic cross-sectional view illustrating a method for manufacturing the image display device according to the embodiment.

[0296] exist Figures 19A to 20B , a process of forming the plug 416k on the circuit board 4100 is shown.

[0297] exist Figures 21A to 22B , a process of forming a semiconductor layer 450 and the like on a circuit substrate 4100 on which a plug 416 k is formed, and forming a sub-pixel group 420 is shown.

[0298] like Fig.19A As shown in FIG. 4 , a circuit substrate 4100 is prepared. The circuit substrate 4100 includes Figure 1 The circuit 101 is the same as described in the above. The circuit 101 includes transistors 103-1, 103-2, etc., and is formed on the TFT lower layer film 106 formed on the substrate 102. The circuit 101 is covered by the first interlayer insulating film 112. The contact hole h is formed in the interlayer insulating film 112. The position where the contact hole h is formed is the position where the wiring 410k is provided. The contact hole h is formed to a depth where the surface of the wiring 410k is exposed.

[0299] like Fig.19B As shown in FIG. 1 , a metal layer 4416 is formed over the entire surface of the interlayer insulating film 112. The contact hole h is filled with the same conductive material as the metal layer 4416 while the metal layer 4416 is formed. A connection portion 415k is formed in the contact hole h filled with the material of the metal layer 4416. Therefore, the connection portion 415k electrically connects the wiring 410k and the metal layer 4416.

[0300] like Fig.19C As shown, a plug 416k is formed on the connection portion 415k by photolithography and dry etching.

[0301] Instead of forming the connection portion 415k, a plug may be directly formed on the wiring 410k.

[0302] like Fig. 20A As shown, a planarization film 4414 is applied to cover the interlayer insulating film 112 and the plug 416k, and then fired. The planarization film 4414 is formed thicker than the plug 416k. Thereafter, the surface of the planarization film 4414 is polished. The polishing of the planarization film 4414 can be performed by, for example, CMP (Chemical Mechanical Polishing).

[0303] like Fig. 20B As shown, the surface of the plug 416k is exposed by polishing, and a planarization film 414 is formed. In this way, the plug 416k and the connection portion 415k are formed.

[0304] In addition, if Fig.21A As shown, a conductive layer 4430 is formed on the plug 416k and the planarization film 414 of the circuit board 4100. After the conductive layer 4430 is patterned, an annealing process is performed to make the entire surface of the conductive layer 4430 single-crystallized. The annealing process is preferably laser annealing.

[0305] like Fig.21B As shown, a semiconductor layer 4450 is formed on the conductive layer 4430a which is crystallized over the entire surface. The semiconductor layer 4450 is preferably formed by pulse sputtering. The semiconductor layer 4450 grows from the n-type semiconductor layer 4451, and then grows in the order of the light emitting layer 4452 and the p-type semiconductor layer 4453. The semiconductor layer 4450 is formed on the conductive layer 4430a, and in the case where there is a position where the conductive layer 4430a does not exist or a position in the conductive layer that is not crystallized, a deposit 4160 that is not crystallized is formed.

[0306] like Fig.22A As shown, Fig.21B The conductive layer 4430a shown is formed into a conductive layer 430 including a light reflecting plate 430a having a desired shape and pattern by etching or the like. Fig.21B The semiconductor layer 4450 shown is formed into a desired shape by etching or the like, thereby forming the semiconductor layer 450 .

[0307] like Fig. 22B As shown, a second interlayer insulating film 456 is formed on the first interlayer insulating film 112, the conductive layer 430 and the semiconductor layer 450. Through holes 461d1 and 461d2 are formed penetrating the interlayer insulating films 112, 456 and the planarizing film 414. In addition, a wiring layer 460 is formed, and wirings 460a1 and 460a2 are formed.

[0308] Thereafter, openings 458-1 and 458-2 are formed between the wirings 460a1 and 460a2. The light emitting surfaces 453S1 and 453S2 of the p-type semiconductor layer exposed through the openings 458-1 and 458-2 are roughened, respectively. Thereafter, light-transmitting electrodes 459a1 and 459a2 are formed.

[0309] In this way, a sub-pixel group 420 including a semiconductor layer 450 sharing two light emitting surfaces 453S1 and 453S2 is formed.

[0310] In this embodiment, although two light emitting surfaces 453S1 and 453S2 are provided in one semiconductor layer 450, the number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 450. As an example, one or two columns of sub-pixels may be formed by a single semiconductor layer 550. Thus, as described later, the composite current that does not contribute to light emission of each light emitting surface can be reduced, and the effect of realizing a finer light emitting element can be increased.

[0311] (Variation Example)

[0312] Fig.23 This is a schematic cross-sectional view illustrating a portion of an image display device according to a modification of the present embodiment.

[0313] This modification is different from the fourth embodiment in that two p-type semiconductor layers 4453a1 and 4453a2 are provided on the light emitting layer 452. Other aspects are the same as those of the fourth embodiment, and the same reference numerals are used for the same structural main components, and detailed descriptions are appropriately omitted.

[0314] like Fig.23As shown, the image display device of this variation has a sub-pixel group 420a. The sub-pixel group 420a includes a semiconductor layer 450a. The semiconductor layer 450a includes: an n-type semiconductor layer 451, a light-emitting layer 452, and p-type semiconductor layers 4453a1 and 4453a2. The semiconductor layer 450a is provided with an n-type semiconductor layer 451 on the plug 416k. The light-emitting layer 452 is laminated on the n-type semiconductor layer 451. Two different p-type semiconductor layers 4453a1 and 4453a2 are provided on the light-emitting layer 452.

[0315] The p-type semiconductor layers 4453a1 and 4453a2 are arranged at intervals along the X-axis direction on the light emitting layer 452. An interlayer insulating film 456 is provided between the p-type semiconductor layers 4453a1 and 4453a2, and the p-type semiconductor layers 4453a1 and 4453a2 are separated by the interlayer insulating film 456.

[0316] The p-type semiconductor layers 4453a1 and 4453a2 have substantially the same shape in XY plan view, and the shape is substantially square or rectangular, but may be other polygonal shapes, circular, or the like.

[0317] The p-type semiconductor layers 4453a1 and 4453a2 have light emitting surfaces 4453S1 and 4453S2, respectively. The light emitting surfaces 4453S1 and 4453S2 are surfaces of the p-type semiconductor layers 4453a1 and 4453a2 exposed through the openings 458-1 and 458-2, respectively.

[0318] The shape of the light-emitting surfaces 4453S1 and 4453S2 in the XY plan view is the same as the shape of the light-emitting surface in the fourth embodiment, and has substantially the same shape, such as a substantially square shape. The shape of the light-emitting surfaces 4453S1 and 4453S2 is not limited to the square shape described in this embodiment, and may also be a polygon such as a circle, an ellipse, or a hexagon. The shape of the light-emitting surfaces 4453S1 and 4453S2 may be similar to the shape of the openings 458-1 and 458-2, or may be a different shape.

[0319] Translucent electrodes 459a1 and 459a2 are provided on the light-emitting surfaces 4453S1 and 4453S2, respectively. Translucent electrodes 459a1 and 459a2 are also provided on wirings 460a1 and 460a2, respectively. Translucent electrode 459a1 is provided between wiring 460a1 and light-emitting surface 4453S1, and electrically connects wiring 460a1 and light-emitting surface 4453S1. Translucent electrode 459a2 is provided between wiring 460a2 and light-emitting surface 4453S2, and electrically connects wiring 460a2 and light-emitting surface 4453S2.

[0320] The manufacturing method of this modification example will be described.

[0321] Fig.24A and Fig. 24B It is a schematic cross-sectional view illustrating the method for manufacturing the image display device according to this modification.

[0322] In this modification, before forming a conductive layer of a single crystal metal on the circuit substrate 4100 on which the plug 416k is formed and forming a semiconductor layer 4450 on the conductive layer, the same method as in the fourth embodiment is applied. Figures 20A to 22B The same process as described in the process. Next, for the manufacturing method of this variant, Fig.21B The steps after the steps shown will be described.

[0323] like Fig.24A As shown, in this modification, Fig. 22B In the embodiment, the conductive layer 4430a is etched or the like to form a conductive layer 430 including a light reflecting plate 430a. Fig. 22B The semiconductor layer 4450 shown is etched to form a semiconductor layer 450a. In the process of forming the semiconductor layer 450a, after the n-type semiconductor layer 451 and the light emitting layer 452 are formed, further etching is performed to form two p-type semiconductor layers 4453a1 and 4453a2.

[0324] The p-type semiconductor layers 4453a1 and 4453a2 may also be formed by deep etching. For example, the etching for forming the p-type semiconductor layers 4453a1 and 4453a2 may be performed to a depth reaching the inside of the light emitting layer 452 or the inside of the n-type semiconductor layer 451. Thus, when the p-type semiconductor layer is deeply etched, the etching position of the p-type semiconductor layer 4453 is preferably separated from the periphery of the light emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer by more than 1 μm. By separating the etching position from the periphery of the light emitting surfaces 4453S1 and 4453S2, the recombination current can be suppressed.

[0325] like Fig. 24B As shown, an interlayer insulating film 456 is formed to cover the planarizing film 414 and the semiconductor layer 450a, and then through holes 461d1 and 461d2 are formed. In addition, a wiring layer 460 is formed, and wirings 460a1 and 460a2 are formed.

[0326] Openings 458-1 and 458-2 are formed in the interlayer insulating film 456. Light emitting surfaces 4453S1 and 4453S2 of the p-type semiconductor layer exposed through the openings 458-1 and 458-2 are roughened. Then, light-transmitting electrodes 459a1 and 459a2 are formed.

[0327] In this way, a sub-pixel group 420a having two light-emitting surfaces 4453S1 and 4453S2 is formed.

[0328] The case of this variation is the same as that of the fourth embodiment. The number of light emitting surfaces is not limited to two, and three or more light emitting surfaces may be provided in one semiconductor layer 450a.

[0329] The effects of the image display device of this embodiment will be described.

[0330] Fig.25 is a graph illustrating the characteristics of a pixel LED element.

[0331] Fig.25 The vertical axis represents the luminous efficiency [%], and the horizontal axis represents the current density of the current flowing in the pixel LED element as a relative value.

[0332] like Fig.25 As shown in FIG. 1 , in the region where the relative value of the current density is less than 1.0, the luminous efficiency of the pixel LED element is approximately constant or monotonically increasing. In the region where the relative value of the current density is greater than 1.0, the luminous efficiency decreases monotonically. That is, for the pixel LED element, there is an appropriate current density that maximizes the luminous efficiency.

[0333] It is expected that a highly efficient image display device can be realized by suppressing the current density to a level that can obtain sufficient brightness from the light-emitting element. Fig.25 It means that at low current density, the luminous efficiency tends to decrease as the current density decreases.

[0334] For example, as described in the first embodiment, the light emitting elements 150-1 and 150-2 are formed by individually separating the entire semiconductor layer 1150 including the light emitting layers 152-1 and 152-2 by etching or the like. At this time, the junction surfaces between the light emitting layers 152-1 and 152-2 and the p-type semiconductor layers 153-1 and 153-2 are exposed at the end. Similarly, the junction surfaces between the light emitting layers 152-1 and 152-2 and the n-type semiconductor layers 151-1 and 151-2 are exposed at the end.

[0335] In the case where the above-mentioned end exists, electrons and holes recombine at the end. On the other hand, the above-mentioned recombination does not contribute to luminescence. The generation of recombination at the end has almost no relationship with the current flowing in the light-emitting element. It can be considered that the recombination is generated according to the length of the junction surface at the end that contributes to luminescence.

[0336] When two light emitting elements of the same size and in a cubic shape are caused to emit light, since the ends are formed on four sides of each light emitting element, recombination can be generated at a total of eight ends.

[0337] In contrast, in this embodiment, the semiconductor layer 450, 450a having two light-emitting surfaces has four ends. In the region between the openings 458-1 and 458-2, the injection of electrons and holes is reduced and hardly contributes to light emission, so the number of ends that contribute to light emission can be considered to be six. Thus, in this embodiment, the number of ends of the semiconductor layer is actually reduced, thereby reducing the recombination current that does not contribute to light emission, and by reducing the recombination current, the drive current can be reduced.

[0338] In the case where the distance between sub-pixels is shortened for high definition or the like, or when the current density is relatively high, in the sub-pixel group 420 of the fourth embodiment, the distance between the light-emitting surfaces 453S1 and 453S2 is shortened. In this case, when the p-type semiconductor layer 453 is shared, part of the electrons injected into the adjacent light-emitting surface is diverted, and the light-emitting surface on the undriven side may emit faint light. In the modified example, since the p-type semiconductor layers 4453a1 and 4453a2 are separated on each light-emitting surface 4453S1 and 4453S2, the light-emitting surface on the undriven side can be reduced.

[0339] In this embodiment, the semiconductor layer including the light-emitting layer is laminated in the order of the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer from the first interlayer insulating film 112 side, and the exposed surface of the p-type semiconductor layer is roughened, which is preferred from the perspective of improving the light-emitting efficiency. It is also possible to replace the lamination order of the n-type semiconductor layer and the p-type semiconductor layer, and laminate in the order of the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer, as in the case of the other embodiments described above.

[0340] In all the above-mentioned embodiments and variations, the order of laminating the light-emitting elements can be changed according to the above-mentioned appropriate manufacturing process for application. For example, for the light-emitting element of the first embodiment, the p-type semiconductor layer, the light-emitting layer, and the n-type semiconductor layer can be laminated in the order of laminating from the first interlayer insulating film 112 side to the light-emitting surface side. Similarly, for the light-emitting element of the second embodiment, the n-type semiconductor layer, the light-emitting layer, and the p-type semiconductor layer can be laminated in the order of laminating from the first interlayer insulating film 112 side to the light-emitting surface side.

[0341] (Fifth Embodiment)

[0342] The image display device may be an image display module having an appropriate number of pixels, and may be, for example, a computer monitor, a television, a portable terminal such as a smartphone, or a car navigation system.

[0343] Fig.26 This is a block diagram illustrating an image display device according to this embodiment.

[0344] Fig.26The main parts of the structure of a computer display are shown.

[0345] like Fig.26 As shown, the image display device 501 has an image display module 502. The image display module 502 is, for example, an image display device having the structure in the case of the first embodiment described above. The image display module 502 includes: a display area 2 in which sub-pixels 20 are arranged, a row selection circuit 5, and a signal voltage output circuit 7. The image display device 501 may also have the structure in any of the second to fourth embodiments and the modified examples.

[0346] The image display device 501 further includes a controller 570. The controller 570 receives a control signal separated and generated by an interface circuit (not shown) and controls the driving of each sub-pixel and the driving order of the row selection circuit 5 and the signal voltage output circuit 7.

[0347] (Variation Example)

[0348] Fig. 27 This is a block diagram illustrating an image display device according to this modification.

[0349] Fig. 27 The structure of a high-definition flat-screen TV is shown.

[0350] like Fig. 27 As shown, the image display device 601 has an image display module 602. The image display module 602 is, for example, the image display device 1 having the structure in the case of the first embodiment described above. The image display device 601 has a controller 670 and a frame memory 680. The controller 670 controls the driving order of each sub-pixel of the display area 2 based on the control signal supplied by the bus 640. The frame memory 680 stores display data of one frame for processing such as smooth motion image reproduction.

[0351] The image display device 601 has an I / O circuit 610. The I / O circuit 610 provides an interface circuit for connecting to an external terminal, device, etc. The I / O circuit 610 includes, for example, a USB interface for connecting to an external hard disk device, an audio interface, and the like.

[0352] The image display device 601 includes a receiving unit 620 and a signal processing unit 630. The receiving unit 620 is connected to an antenna 622, and separates and generates a required signal from the radio wave received by the antenna 622. The signal processing unit 630 includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), etc. The signal separated and generated by the receiving unit 620 is separated and generated into image data, audio data, etc. by the signal processing unit 630.

[0353] By making the receiving unit 620 and the signal processing unit 630 a high-frequency communication module such as a GPS receiver for sending / receiving, WiFi, etc. of a mobile phone, it can also be formed into other image display devices. For example, the image display device with an image display module with appropriate screen size and resolution can be a portable information terminal such as a smart phone or a car navigation system.

[0354] The image display module in this embodiment is not limited to the structure of the image display device in the first embodiment, and may be a modified example thereof or the structure of other embodiments.

[0355] Fig.28 It is a perspective view schematically illustrating the image display device according to the first to fourth embodiments and the above-mentioned modification example.

[0356] like Fig.28 As shown, the image display devices of the first to fourth embodiments are as described above, and a light emitting circuit portion 172 having a large number of sub-pixels is provided on the circuit substrate 100. A color filter 180 is provided on the light emitting circuit portion 172. It should be noted that in the fifth embodiment, the structure including the circuit substrate 100, the light emitting circuit portion 172 and the color filter 180 is an image display module 502, 602, which is assembled into the image display device 501, 601.

[0357] According to the above-described embodiments, it is possible to realize a method for manufacturing an image display device and an image display device that shortens the transfer process of the light emitting element and improves the yield.

[0358] Several embodiments of the present invention are described above, but the above embodiments are mentioned as examples and are not intended to limit the scope of the invention. The above new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The above embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the scope of the technical solution and its equivalent. In addition, the above embodiments can be implemented in combination with each other.

[0359] Description of Reference Numerals

[0360] 1, 201, 501, 601 image display device; 2 display area; 3 power supply line; 4 ground line; 5, 205 row selection circuit; 6, 206 scanning line; 7, 207 signal voltage output circuit; 8, 208 signal line; 10 pixel; 20-1, 20-2, 20a-1, 20b-1 sub-pixel; 22, 222 light emitting element; 24, 224 selection transistor; 26, 226 driving transistor; 28, 228 capacitor; 100 circuit substrate; 101 circuit; 102, 402 substrate; 103-1, 103-2, 203 transistor; 104, 204, 204-1, 204-2 TFT channel; 105 insulating layer; 107, 107-1, 107-2 gate; 108 insulating film; 110 first wiring layer; 112 first interlayer insulating film; 114, 414 planarization film; 130, 430 conductive layer; 130a, 430a light reflection plate; 140 graphene layer; 140-1, 140-2 graphene sheet; 150-1, 150-2, 150a-1, 250-1, 250-2 light emitting element; 156, 256, 456 second interlayer insulating film; 159a1, 159a2, 159k, 259 k1, 259a, 259k2, 459k translucent electrode; 161a, 161d, 161k through hole; 180 color filter; 460 wiring layer; 420, 420a sub-pixel group; 450, 450a semiconductor layer; 1100, 3100, 3100a, 4100 circuit substrate; 1130, 1130a conductive layer; 1150 semiconductor layer; 1192 structure.

Claims

1. A method for manufacturing an image display device, characterized in that: have: A step of preparing a first substrate, the first substrate comprising: a circuit including a circuit element formed on a light-transmitting substrate, and a first insulating film covering the circuit; forming a conductive layer including a portion of a single crystal metal on the first insulating film; forming a semiconductor layer including a light emitting layer on the portion; A step of etching the semiconductor layer to form a light-emitting element; forming a second insulating film covering the conductive layer, the light emitting element and the first insulating film; forming a through hole penetrating the first insulating film and the second insulating film; A step of electrically connecting the light emitting element to the circuit element via the through hole at a light emitting surface of the light emitting element that faces the first insulating film.

2. The method for manufacturing an image display device according to claim 1, wherein: The process of forming the conductive layer includes: forming a metal layer on the first insulating film; A step of annealing the metal layer to form the portion.

3. The method for manufacturing an image display device according to claim 2, wherein: The step of forming the conductive layer includes a step of patterning the metal layer before annealing the metal layer.

4. The method for manufacturing an image display device according to claim 2, wherein: The step of forming a metal layer on the first insulating film includes patterning the metal layer into a predetermined shape in advance.

5. The method for manufacturing an image display device according to claim 1, wherein: In the step of forming the semiconductor layer, the semiconductor layer is formed by a sputtering method.

6. The method for manufacturing an image display device according to claim 1, wherein: The first substrate includes a second substrate disposed between the light-transmitting substrate and the circuit element and having flexibility. The method further comprises the step of removing the light-transmitting substrate after the step of growing the semiconductor layer.

7. The method for manufacturing an image display device according to claim 1, wherein: The light-transmitting substrate includes a glass substrate.

8. The method for manufacturing an image display device according to claim 1, wherein: The method further includes forming a layer containing graphene on the conductive layer before forming the semiconductor layer.

9. The method for manufacturing an image display device according to claim 1, wherein: Also features: A step of exposing the light emitting surface; The step of forming a light-transmitting electrode on the exposed light-emitting surface.

10. The method for manufacturing an image display device according to claim 1, wherein: The semiconductor layer includes a gallium nitride-based compound semiconductor.

11. The method for manufacturing an image display device according to claim 1, wherein: The method further includes forming a wavelength conversion member on the light emitting element.

12. An image display device, characterized in that: have: A light-transmitting substrate having a first surface; A circuit element disposed on the first surface; A first wiring layer, which is disposed on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit element and the first wiring layer on the first surface; a conductive layer disposed on the first insulating film and including a portion of a single crystal metal; a first light emitting element disposed on the portion and electrically connected to the portion; a second insulating film covering at least a portion of the first light emitting element, the first insulating film, and the conductive layer; a second wiring layer provided on the second insulating film and electrically connected to a light emitting surface of the first light emitting element that is opposite to a surface on one side of the first insulating film; The through hole penetrates the first insulating film and the second insulating film to electrically connect the first wiring layer and the second wiring layer.

13. The image display device according to claim 12, wherein: The light-transmitting substrate includes a glass substrate.

14. An image display device, characterized in that: have: A substrate having a first surface and being flexible; A circuit element disposed on the first surface; A first wiring layer, which is disposed on the circuit element and electrically connected to the circuit element; a first insulating film covering the circuit element and the first wiring layer on the first surface; a conductive layer disposed on the first insulating film and including a portion of a single crystal metal; a first light emitting element disposed on the portion and electrically connected to the portion; a second insulating film covering at least a portion of the first light emitting element, the first insulating film, and the conductive layer; a second wiring layer provided on the second insulating film and electrically connected to a light emitting surface of the first light emitting element that is opposite to a surface on one side of the first insulating film; The through hole penetrates the first insulating film and the second insulating film to electrically connect the first wiring layer and the second wiring layer.

15. The image display device according to claim 12, wherein: The outer periphery of the portion includes the outer periphery of the first light emitting element projected on the portion in a plan view.

16. The image display device according to claim 15, wherein: The first light-emitting element includes: a first semiconductor layer of a first conductivity type, a first light-emitting layer provided on the first semiconductor layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type and provided on the first light-emitting layer, wherein the first semiconductor layer, the first light-emitting layer, and the second semiconductor layer are laminated in this order from the first insulating film side to the light-emitting surface side. The first semiconductor layer is disposed on the portion and electrically connected to the portion.

17. The image display device according to claim 16, wherein: The first conductivity type is n-type, and the second conductivity type is p-type.

18. The image display device according to claim 16, wherein: The device further comprises a second light-emitting element, the second light-emitting element comprising: a third semiconductor layer of the first conductivity type, a second light-emitting layer provided on the third semiconductor layer, and a fourth semiconductor layer of the second conductivity type provided on the second light-emitting layer, wherein the third semiconductor layer, the second light-emitting layer and the fourth semiconductor layer are laminated in this order from the first insulating film side to the light-emitting surface side. The third semiconductor layer is disposed on the portion and is electrically connected to the portion, The outer periphery of the portion includes the outer periphery of the first light emitting element and the outer periphery of the second light emitting element projected on the portion in a plan view.

19. The image display device according to claim 12, wherein: It also has a layer containing graphene provided between the portion and the first light-emitting element.

20. The image display device according to claim 12, wherein: The second insulating film has an opening for exposing the light emitting surface. It also has a light-transmitting electrode disposed on the light-emitting surface.

21. The image display device according to claim 20, wherein: The light emitting surface exposed from the opening includes a rough surface.

22. The image display device according to claim 12, wherein: The first light emitting element includes a gallium nitride-based compound semiconductor.

23. The image display device according to claim 12, wherein: A wavelength conversion component is also provided on the first light emitting element.

24. An image display device, characterized in that: have: A light-transmitting substrate having a first surface; A plurality of transistors disposed on the first surface; a first wiring layer, which is disposed on the plurality of transistors and is electrically connected to the plurality of transistors; a first insulating film covering the plurality of transistors and the first wiring layer on the first surface; a conductive layer disposed on the first insulating film and including a portion of a single crystal metal; A first semiconductor layer of a first conductivity type, disposed on the portion and electrically connected to the portion; a light emitting layer, disposed on the first semiconductor layer; A second semiconductor layer of a second conductivity type, which is disposed on the light emitting layer, wherein the second conductivity type is different from the first conductivity type; a second insulating film covering the conductive layer, the first insulating film, the light emitting layer, and the first semiconductor layer, and covering at least a portion of the second semiconductor layer; a second wiring layer connected to light-transmitting electrodes respectively exposed from the second insulating film corresponding to the plurality of transistors and arranged on the plurality of light-emitting surfaces of the second semiconductor layer; A plurality of through holes penetrate the first insulating film and the second insulating film to electrically connect the wiring of the first wiring layer and the wiring of the second wiring layer, respectively.

25. The image display device according to claim 24, wherein: The second semiconductor layer is separated by the second insulating film.

Images