Systems and methods for implementing a 16-bit floating-point matrix dot product instruction

Abstract

The present application discloses systems and methods for implementing a 16-bit floating-point matrix dot product instruction. The disclosed embodiments relate to computing the dot product of half bytes in tile operands. In one example, a processor includes: a decoding circuit for decoding a tile dot product instruction having a field for an opcode, a destination identifier for identifying an M×N destination matrix, a first source identifier for identifying an M×K first source matrix, and a second source identifier for identifying a K×N second source matrix, each matrix containing doubleword elements; and an execution circuit for executing the decoded instruction to perform a K-fold process on each element (m, n) of the specified destination matrix, thereby generating eight products by multiplying each half byte of the doubleword elements (M, K) of the specified first source matrix by the corresponding half byte of the doubleword elements (K, N) of the specified second source matrix, and accumulating and saturating the eight products with the previous contents of the doubleword elements.

Description

[0001] This application is a divisional application of the invention patent application with the priority date of November 9, 2018, application number 201910953678.4, and titled "System and Method for Implementing 16-bit Floating-point Matrix Dot Product Instructions", which was filed on October 9, 2019. Technical Field

[0002] The field of the present invention generally relates to computer processor architectures, and more particularly, to systems and methods for implementing 16-bit floating-point matrix dot product instructions. Background Art

[0003] Matrices are becoming increasingly important in many computational tasks such as machine learning and other bulk data processing. Deep learning is a class of machine learning algorithms. Deep learning architectures (such as deep neural networks) have been applied to fields including computer vision, speech recognition, natural language processing, audio recognition, social network filtering, machine translation, bioinformatics, and drug design.

[0004] Inference and training are two tools used in deep learning, and they tend to use low-precision arithmetic. Maximizing the throughput of deep learning algorithms and computations can help meet the requirements of deep learning processors, such as those implementing deep learning in data centers.

[0005] Matrix-matrix multiplication (also known as GEMM or general matrix multiplication) is a computationally intensive operation common on modern processors. Special hardware for matrix multiplication (e.g., GEMM) is a good option for improving peak computing (and energy efficiency) in certain applications such as deep learning.

[0006] As long as the output elements have enough bits (i.e., more than the input), some of these applications (including deep learning) can operate on input data elements with relatively few bits without loss of precision. Brief Description of the Drawings

[0007] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements and in which:

[0008] Figure 1A An embodiment of a configured tile is illustrated;

[0009] Figure 1B An embodiment of a configured tile is illustrated;

[0010] Figure 2 Several examples of matrix storage are illustrated;

[0011] Figure 3 An embodiment of a system utilizing a matrix (tile) operation accelerator is illustrated;

[0012] Figure 4 and 5 illustrate different embodiments of using a matrix operation accelerator shared memory;

[0013] Figure 6 illustrate an embodiment of a matrix multiply-accumulate operation ("TMMA") using tiles;

[0014] Figure 7 illustrate an embodiment of a subset of the iterative execution of chained fused multiply-accumulate instructions;

[0015] Figure 8 illustrate an embodiment of a subset of the iterative execution of chained fused multiply-accumulate instructions;

[0016] Figure 9 illustrate an embodiment of a subset of the iterative execution of chained fused multiply-accumulate instructions;

[0017] Figure 10 illustrate an embodiment of a subset of the iterative execution of chained fused multiply-accumulate instructions;

[0018] Figure 11 illustrate a SIMD implementation of a power-of-two size according to an embodiment, where the accumulator uses an input size greater than the input to the multiplier;

[0019] Figure 12 illustrate an embodiment of a system utilizing matrix operation circuitry;

[0020] Figure 13 illustrate an embodiment of a processor core pipeline that supports matrix operations using tiles;

[0021] Figure 14 illustrate an embodiment of a processor core pipeline that supports matrix operations using tiles;

[0022] Figure 15 illustrate examples of matrices expressed in row-major format and column-major format;

[0023] Figure 16 illustrate an example of the use of matrices (tiles);

[0024] Figure 17 illustrate an embodiment of a method of using matrices (tiles);

[0025] Figure 18 illustrate support for a configuration of tile usage according to an embodiment;

[0026] Figure 19 illustrate an embodiment of a description of a matrix (tile) to be supported;

[0027] Figures 20(A)-(D) illustrate examples of (one or more) registers;

[0028] Figure 21 is a block diagram illustrating matrix multiplication acceleration using the TILE16BDP instruction according to some embodiments;

[0029] Figure 22A is pseudocode illustrating the execution of the TILE16BDP instruction according to some embodiments;

[0030] Figure 22B is pseudocode illustrating the execution of the TILE16BDP instruction according to some embodiments;

[0031] Figure 22C is a pseudocode illustrating an auxiliary function used for the pseudocode of Figure 22A and 22B according to some embodiments;

[0032] Figure 23 illustrates an embodiment of a processor execution flow for processing the TILE16BDP instruction;

[0033] Figure 24 is a block diagram illustrating the format of the TILE16BDP instruction according to some embodiments;

[0034] Figure 25A-25B is a block diagram illustrating a general vector friendly instruction format and its instruction templates according to an embodiment;

[0035] Figure 25A is a block diagram illustrating a general vector friendly instruction format and its class A instruction templates according to an embodiment;

[0036] Figure 25B is a block diagram illustrating a general vector friendly instruction format and its class B instruction templates according to an embodiment;

[0037] Figure 26A is a block diagram illustrating an exemplary specific vector friendly instruction format according to an embodiment;

[0038] Figure 26B is a block diagram illustrating the fields of a specific vector friendly instruction format that constitutes a complete opcode field according to an embodiment;

[0039] Figure 26C is a block diagram illustrating the fields of a specific vector friendly instruction format that constitutes a register index field according to an embodiment;

[0040] Figure 26D is a block diagram illustrating the fields of a specific vector friendly instruction format that constitutes an extended operation field according to an embodiment;

[0041] Figure 27 is a block diagram of a register architecture according to one embodiment;

[0042] Figure 28A is a block diagram illustrating both an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline according to an embodiment;

[0043] Figure 28B is a block diagram illustrating both an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core according to an embodiment;

[0044] Figure 29A - Block diagram B illustrates a more specific exemplary in-order core architecture, which would be one of several logic blocks (including other cores of the same type and / or different types) on a chip;

[0045] Figure 29A is a block diagram of a single processor core according to an embodiment, and its connections to an on-die interconnect network and its connection to a local subset of a level 2 (L2) cache;

[0046] Figure 29B is according to an embodiment of Figure 29A an expanded view of a portion of the processor core in

[0047] Figure 30 is a block diagram of a processor according to an embodiment that can have more than one core, can have an integrated memory controller, and can have integrated graphics;

[0048] Figure 31-34 is a block diagram of an exemplary computer architecture;

[0049] Figure 31 shows a block diagram of a system according to an embodiment of the present invention;

[0050] Figure 32 is a block diagram of a first more specific exemplary system according to an embodiment of the present invention;

[0051] Figure 33 is a block diagram of a second more specific exemplary system according to an embodiment of the present invention;

[0052] Figure 34 is a block diagram of a system-on-chip (SoC) according to an embodiment of the present invention; and

[0053] Figure 35It is a block diagram of using a software instruction converter to convert binary instructions in a source instruction set into binary instructions in a target instruction set for comparison according to an embodiment. Detailed implementation

[0054] Numerous specific details are set forth in the following description. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0055] References in the specification to "one embodiment," "an embodiment," "example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes that particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments (whether or not explicitly described).

[0056] In many mainstream processors, processing matrices is a difficult and / or instruction-intensive task. For example, the rows of a matrix can be placed into multiple packed data (e.g., SIMD or vector) registers and then operated on individually. For example, depending on the data size, adding two 8×2 matrices may require loading or gathering into four packed data registers. Then, a first addition of the packed data registers corresponding to the first row from each matrix is performed, and a second addition of the packed data registers corresponding to the second row from each matrix is performed. Then, the resulting packed data registers are scattered back to memory. While this scenario may be acceptable for small matrices, it is generally unacceptable for larger matrices.

[0057] Discussion

[0058] Described herein are mechanisms that support matrix operations in computer hardware such as a central processing unit (CPU), a graphics processing unit (GPU), and an accelerator. Matrix operations utilize two-dimensional (2-D) data structures that represent one or more packed regions of memory (such as registers). Throughout this specification, these 2-D data structures are referred to as tiles. Note that a matrix can be smaller than a tile (using less than all of the tile) or utilize multiple tiles (the matrix is larger than the size of any one tile). Throughout the specification, matrix (tile) language is used to indicate operations performed using the tiles that affect the matrix; whether the matrix is larger than any one tile is generally not relevant.

[0059] Each tile can operate through different operations (such as those detailed herein), and includes but is not limited to: matrix (tile) multiplication, tile addition, tile subtraction, tile diagonal, tile zeroing, tile transformation, tile dot product, tile broadcast, tile row broadcast, tile column broadcast, tile multiplication, tile multiply-accumulate, tile shift, etc. Additionally, support for operators such as those using scale and / or bias can be used in conjunction with these operations or support future non-numeric applications, e.g., OpenCL "local memory", data compression / decompression, etc. Instructions for implementing a matrix (tile) 16-bit tile dot product (TILE16BDP) instruction are also described herein.

[0060] Portions of the storage device (such as memories (non-volatile and volatile), registers, caches, etc.) are arranged into tiles having different horizontal and vertical dimensions. For example, the horizontal dimension of a tile can be 4 (e.g., four rows of a matrix), and the vertical dimension of a tile can be 8 (e.g., 8 columns of a matrix). Generally, the horizontal dimension is related to the element size (e.g., 2-, 4-, 8-, 16-, 32-, 64-, 128-bit, etc.). Multiple data types (single-precision floating point, double-precision floating point, integer, etc.) can be supported.

[0061] Exemplary use of configured tiles

[0062] In some embodiments, tile parameters can be configured. For example, a given tile can be configured to provide tile options. Exemplary tile options include but are not limited to: the number of rows of a tile, the number of columns of a tile, whether the tile is valid, and whether the tile is composed of a pair of tiles of equal size.

[0063] Figure 1AIllustrates an embodiment of configured tiles. As shown, 4 kB of the application memory 102 has 4 1 kB headers stored thereon - tile t0 104, tile t1 106, tile t2 108, and tile t3 110. In this example, the 4 tiles are not composed of pairs, and each tile has elements arranged in rows and columns. Tiles t0 104 and t1 106 have 4-byte elements (e.g., single-precision data) with K rows and N columns, where K equals 8 and N = 32. Tiles t2 108 and t3 110 have 8-byte elements (e.g., double-precision data) with K rows and N / 2 columns. Since the double-precision operand is twice the width of the single-precision, this configuration is consistent with a palette and is used to provide tile options, thus providing at least 4 names for a total storage of at least 4 kB. In operation, tiles can be loaded from and stored to the memory using load and store operations. Depending on the instruction encoding scheme used, the amount of available application memory and the size, number, and configuration of the available tiles will vary.

[0064] Figure 1B Illustrates an embodiment of configured tiles. As shown, 4 kB of the application memory 122 has 2 pairs of 1 kB headers stored thereon, the first pair being tile t4L 124 and tile t4R 126, and the second pair being tile t5L 128 and tile t5R 130. As shown, the tile pairs are divided into left tiles and right tiles. In other embodiments, the tile pairs are divided into even tiles and odd tiles. In this example, all 4 tiles have elements arranged in rows and columns. Tiles t4L 124 and t4R 126 have 4-byte elements (e.g., single-precision floating-point data) with K rows and N columns, where K equals 8 and N equals 32. Tiles t5L 128 and t5R 130 have 8-byte elements (e.g., double-precision floating-point data) with K rows and N / 2 columns. Since the double-precision operand is twice the width of the single-precision, this configuration is consistent with a palette and is used to provide tile options, thus providing at least 2 names for a total storage of at least 4 kB. Figure 1A The four tiles of use 4 names, each name naming a 1 kB tile, while Figure 1B the 2 pairs of tiles in can use 2 names to specify paired tiles. In some embodiments, tile instructions accept the names of paired tiles as operands. In operation, tiles can be loaded from and stored to the memory using load and store operations. Depending on the instruction encoding scheme used, the amount of available application memory and the size, number, and configuration of the available tiles will vary.

[0065] In some embodiments, the tile parameters are definable. For example, a "palette" is used to provide tile options. Exemplary options include, but are not limited to: the number of tile names, the number of bytes in a stored row, the number of rows and columns in a tile, etc. For example, the maximum "height" (number of rows) of a tile can be defined as:

[0066] Maximum tile rows = architected storage / (number of palette names * bytes per row).

[0067] Accordingly, an application can be written such that the fixed use of names will be able to utilize different storage sizes across implementations.

[0068] Use the matrix (tile) configuration ("TILECONFIG") instruction to complete the configuration of the tile, where the specific tile usage is defined in a selected palette. The declaration includes: the number of tile names to be used, the number of rows and columns requested for each name (tile), and in some embodiments, the data type requested for each tile. In some embodiments, a consistency check is performed during the execution of the TILECONFIG instruction to determine its compliance with the palette entry limits.

[0069] Exemplary tile storage types

[0070] Figure 2 Illustrates several examples of matrix storage. In (A), the tile is stored in memory. As shown, each "row" consists of four packed data elements. To reach the next "row", a stride value is used. Note that the rows can be stored continuously in memory. When the tile storage does not map to the underlying memory array row width, strided memory access allows accessing one row to the next.

[0071] Loading a tile from memory and storing a tile to memory are typically strided accesses from the application memory to the packed data rows. In some embodiments, the exemplary TILELOAD and TILESTORE instructions or other references to the application memory (as tile operands in the load operation instructions) are restartable to handle (up to) 2 * page faulting rows, unmasked floating point exceptions, and / or interrupts per instruction.

[0072] In (B), the matrix is stored in a tile consisting of multiple registers, such as packed data registers (single instruction, multiple data (SIMD) or vector registers). In this example, the tile spans three physical registers. Typically, consecutive registers are used; however, this is not necessarily the case.

[0073] In (C), the matrix is stored in tiles in non-register storage, which can be used by the fused multiply-accumulate (FMA) circuits used in tile operations. This storage can be internal to the FMA or adjacent to it. Additionally, in some embodiments discussed below, the storage can be for data elements rather than entire rows or tiles.

[0074] Support parameters for the TMMA architecture are reported via the CPUID. In some embodiments, the information list includes the maximum height and the maximum SIMD size. Configuring the TMMA architecture requires specifying the size of each tile, the element size per tile, and the palette identifier. This configuration is done by executing the TILECONFIG instruction.

[0075] Successful execution of the TILECONFIG instruction enables subsequent TILE operators.

[0076] The TILERELEASEALL instruction clears the tile configuration and disables TILE operations (until the next TILECONFIG instruction is executed). In some embodiments, XSAVE, XSTORE, etc. are used for context switching using tiles. In some embodiments, 2 XCR0 bits are used in XSAVE, one for the TILECONFIG metadata and one bit for the actual tile payload data.

[0077] TILECONFIG not only configures tile usage but also sets a status variable that indicates that the program is in a code region with configured tiles. Implementations can enumerate restrictions on other instructions that can be used with the tile region, such as not using the existing register set, etc.

[0078] Exiting the tile region is typically done using the TILERELEASEALL instruction. It takes no arguments and can quickly invalidate all tiles (indicating that the data no longer requires any save or restore) and clears the internal state corresponding to being in the tile region.

[0079] In some embodiments, tile operations will zero out any rows and any columns that exceed the dimensions specified by the tile configuration. For example, when writing each row, the tile operation will zero out the data beyond the configured number of columns (taking into account the size of the elements). For example, in the case of a 64-byte row and a tile configured with 10 rows and 12 columns, the operation of writing FP32 elements will write each of the first 10 rows with 12 * 4 bytes of output / result data and zero out the remaining 4 * 4 bytes in each row. The tile operation will also completely zero out any rows after the first 10 configured rows. When using a 1K tile with 64-byte rows, there will be 16 rows, so in this example, the last 6 rows will also be zeroed out.

[0080] In some embodiments, the context restore instruction (e.g., XRSTOR) enforces when loading data that data beyond the rows configured for the tile will be maintained as zeros. If there is no valid configuration, all rows are zeroed. An XRSTOR for tile data may load garbage in columns beyond the configured columns. There should be no possibility for the XRSTOR to clear beyond the configured number of columns, since there is no element width associated with the tile configuration.

[0081] A context save (e.g., XSAVE) exposes the entire TILE memory area as it is written to memory. If XRSTOR loads garbage data into the rightmost portion of a tile, that data will be saved by XSAVE. XSAVE will write zeros for rows beyond the number specified for each tile.

[0082] In some embodiments, tile instructions are restartable. Operations accessing memory allow restarting after a page fault. Compute instructions that process floating point operations also allow unmasked floating point exceptions, where exceptions controlled by control and / or status registers are masked.

[0083] To support restarting the instruction after these events, the instruction stores information in the start registers detailed below.

[0084] Matrix (Tile) Operating System

[0085] Exemplary Hardware Support

[0086] Figure 3 An embodiment of a system utilizing a matrix (tile) operation accelerator is illustrated. In the illustration, a main processor / processing system 301 transmits a command 311 (e.g., a matrix manipulation operation such as an arithmetic or matrix manipulation operation, or a load and store operation) to a matrix operation accelerator 307. However, this is shown in this manner for discussion purposes only. As described in detail later, the accelerator 307 may be part of a processing core. Typically, a command 311 as a tile manipulation operator instruction will refer to a tile as a register-register ("reg-reg") or register-memory ("reg-mem") format. Other commands (such as TILESTORE, TILELOAD, TILECONFIG, etc.) do not perform data operations on tiles. The command may be a decoded instruction (e.g., a micro-operation) or a macro-instruction for processing by the accelerator 307.

[0087] In this example, a consistent memory interface 303 is coupled to the main processor / processing system 301 and the matrix operation accelerator 307 so that they can share memory. Figure 4 and 5Illustrates different embodiments of how to use a matrix operation accelerator to share memory. As Figure 4 shown, the main processor 401 and the matrix operation accelerator circuit 405 share the same memory 403. Figure 5 Illustrates an embodiment in which the main processor 501 and the matrix operation accelerator 505 do not share memory but can access each other's memory. For example, the processor 501 can access the tile memory 507 and utilize its main memory 503 as normal. Similarly, the matrix operation accelerator 505 can access the main memory 503, but more typically uses its own memory 507. Note that these memories can be of different types.

[0088] In some embodiments, overlays on physical registers are used to support tiles. For example, depending on the implementation, a tile can utilize 16 1,024-bit registers, 32 512-bit registers, etc. In some embodiments, matrix operations utilize 2-dimensional (2-D) data structures that represent one or more packed regions of memory (such as registers). Throughout this specification, these 2-D data structures are referred to as tiles or tile registers.

[0089] In some embodiments, the matrix operation accelerator 307 includes a plurality of FMAs 309 coupled to data buffers 305 (in some implementations, one or more of these buffers 305 are stored in the FMAs of the grid, as shown). The data buffers 305 buffer the tiles loaded from memory and / or the tiles to be stored to memory (e.g., using tile load or tile store instructions). For example, the data buffers can be a plurality of registers. Typically, these FMAs are arranged as a grid 309 of chained FMAs that are capable of reading and writing tiles. In this example, the matrix operation accelerator 307 is to perform a matrix multiplication operation using tiles T0, T1, and T2. At least one tile is accommodated in the FMA grid 309. In some embodiments, all tiles in the operation are stored in the FMA grid 309. In other embodiments, only a subset is stored in the FMA grid 309. As shown, T1 is accommodated while T0 and T2 are not. Note that A, B, and C refer to the matrices of these tiles, which may or may not occupy the entire space of the tile.

[0090] Figure 6 Illustrates an embodiment of a matrix multiply-accumulate operation using tiles ("TMMA").

[0091] The number of rows in the matrix (tile A 601) matches the number of serial (chained) FMAs including the latency of the calculation. One implementation can freely recycle on a grid with a smaller height while the calculation remains the same.

[0092] The source / destination vectors come from a tile with N rows (tile C 605), and the mesh 611 of the FMA performs N vector matrix operations, resulting in a complete instruction for performing matrix multiplication of the tile. Tile B 603 is another vector source and provides "broadcast" terms to the FMA at each stage.

[0093] In operation, in some embodiments, the elements of matrix B (stored in tile B 603) are spread across the rectangular mesh of the FMA. Matrix B (stored in tile A 601) has its row elements, which are transformed to match the columnar dimensions of the rectangular mesh of the FMA. At each FMA in the mesh, the elements of A and B are multiplied and added to the incoming addend (from above in the figure), and the outgoing sum is passed to the next row of the FMA (or the final output).

[0094] The latency of a single step is proportional to K (the row height of matrix B), and the dependent TMMA typically has sufficient source-destination rows (in a single tile or across tiles) to hide this latency. One implementation can also split the SIMD (packed data elements) size M (the row height of matrix A) across time steps, but this only changes the constant by which K is multiplied. When the K specified by the program is less than the maximum value enumerated by TMACC, one implementation freely achieves this using "masking" or "early outs".

[0095] The latency of the entire TMMA is proportional to N*K. The repetition rate is proportional to N. The number of MACs per TMMA instruction is N*K*M.

[0096] Figure 7 Embodiments are illustrated that show a subset of the iterative execution of chained fused multiply-accumulate instructions. In particular, this illustrates the execution circuitry for the iteration of one packed data element orientation of the destination. In this embodiment, the chained fused multiply-accumulate operates on signed sources, where the accumulator is twice the size of the input data.

[0097] The first signed source (source 1 701) and the second signed source (source 2 703) each have four packed data elements. Each of these packed data elements stores signed data such as floating-point data. The third signed source (source 3 709) has two packed data elements, each storing signed data. The sizes of the first and second signed sources 701 and 703 are half the size of the third signed source (initial value or previous result) 709. For example, the first signed source 701 and the second signed source 703 can have 32-bit packed data elements (e.g., single-precision floating-point numbers), while the third signed source 709 can have 64-bit packed data elements (e.g., double-precision floating-point numbers).

[0098] In this illustration, only the two most significant packed data element orientations of the first signed source 701 and the second signed source 703 and the most significant packed data element orientation of the third signed source 709 are shown. Of course, other packed data element orientations will also be processed.

[0099] As shown in the illustration, the packed data elements are processed in pairs. For example, the data of the most significant packed data element orientations of the first signed source 701 and the second signed source 703 are multiplied using the multiplier circuit 705, and the data of the second most significant packed data element orientations from the first signed source 701 and the second signed source 703 are multiplied using the multiplier circuit 707. In some embodiments, these multiplier circuits 705 and 707 are reused for other packed data element orientations. In other embodiments, additional multiplier circuits are used to enable parallel processing of the packed data elements. In some contexts, a channel having the size of the signed third source 709 is used to complete the parallel execution. The adder circuit 711 is used to add up the results of each multiplication.

[0100] The addition result of the multiplication results is added to the data of the most significant packed data element orientation from the signed source 3 709 (using a different adder 713 or the same adder 711).

[0101] Finally, the result of the second addition is stored in the signed destination 715 in the packed data element orientation corresponding to the packed data element orientation used from the signed third source 709, or passed to the next iteration if there is a next iteration. In some embodiments, a write mask is applied to this storage such that the storage occurs if the corresponding write mask (bit) is set and does not occur if it is not set.

[0102] Figure 8 An embodiment of an iterative execution subset of a chained fused multiply-accumulate instruction is illustrated. In particular, this illustrates the execution circuit for an iteration of one packed data element orientation of the destination. In this embodiment, the chained fused multiply-accumulate operates on signed sources, where the accumulator is twice the size of the input data.

[0103] Both the first signed source (Source 1 801) and the second signed source (Source 2 803) have four packed data elements. Each of these packed data elements stores signed data such as integer data. The third signed source (Source 3 809) has two packed data elements, each storing signed data. The sizes of the first signed source 801 and the second signed source 803 are half the size of the third signed source 809. For example, the first signed source 801 and the second signed source 803 may have 32-bit packed data elements (e.g., single-precision floating-point numbers), and the third signed source 809 may have 64-bit packed data elements (e.g., double-precision floating-point numbers).

[0104] In this illustration, only the two most significant packed data element orientations of the first signed source 801 and the second signed source 803 and the most significant packed data element orientation of the third signed source 809 are shown. Of course, other packed data element orientations will also be processed.

[0105] As shown in the illustration, the packed data elements are processed in pairs. For example, the data in the most significant packed data element orientation of the first signed source 801 and the second signed source 803 are multiplied using multiplier circuit 805, and the data in the second most significant packed data element orientation from the first signed source 801 and the second signed source 803 are multiplied using multiplier circuit 807. In some embodiments, multiplier circuits 805 and 807 perform multiplication with infinite precision without saturation, and adder / saturation circuit 813 is used to saturate the accumulated result to positive or negative infinity in the case of overflow and to zero in the case of any underflow. In other embodiments, multiplier circuits 805 and 807 perform saturation themselves. In some embodiments, these multiplier circuits 805 and 807 are reused for other packed data element orientations. In other embodiments, additional multiplier circuits are used to enable parallel processing of the packed data elements. In some contexts, a channel with the size of the signed third source (initial value or previous iteration result) 809 is used to complete the parallel execution. The result of each multiplication is added to the signed third source 809 using adder / saturation circuit 813.

[0106] When addition results in an overly large value, the adder / saturation (accumulator) circuit 813 preserves the sign of the operands. In particular, the saturation evaluation occurs on the infinite precision result between the multiple additions and the write destination or the next iteration. When accumulator 813 is floating-point and the input terms are integers, the sum of products and the floating-point accumulator input values are made into infinite precision values (a fixed-point number of hundreds of bits), the addition of the multiplication result and the third input is performed, and a single rounding to the actual accumulator type is performed.

[0107] Unsigned saturation means that the output value is limited to the maximum unsigned quantity (all 1s) for the width of the element. Signed saturation means that a value is limited to a range between the minimum negative number and the maximum positive number for the width of the element (e.g., for a byte, the range is from -128 (= -2^7) to 127 (= 2^7 - 1)).

[0108] The result of the addition and saturation check is stored in the signed result 815 in the packed data element location corresponding to the packed data element location used from the signed third source 809 or passed to the next iteration if there is a next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set and does not occur if it is not set.

[0109] Figure 9 Embodiments are illustrated that iterate a subset of chained fused multiply-add instructions. In particular, this illustrates the execution circuitry for iterating over one packed data element location of a destination. In this embodiment, the chained fused multiply-add operates on signed and unsigned sources, where the accumulator is four times the size of the input data.

[0110] The first signed source (source 1 901) and the second unsigned source (source 2 903) each have four packed data elements. Each of these packed data elements has data such as floating-point or integer data. The third signed source (initial value or result 915) has a packed data element storing signed data. The sizes of the first source 901 and the second source 903 are one quarter of the third signed source 915. For example, the first source 901 and the second source 903 may have 16-bit packed data elements (e.g., words), and the third signed source 915 may have 64-bit packed data elements (e.g., double-precision floating-point or 64-bit integer).

[0111] In this illustration, the four most significant packed data element locations of the first source 901 and the second source 903 and the most significant packed data element location of the third signed source 915 are shown. Of course, if there are any other packed data element locations, they will also be processed.

[0112] As shown, the packed data elements are processed in quadruples. For example, the most significant packed data element-aligned data from the first source 901 and the second source 903 are multiplied using multiplier circuit 905, the second most significant packed data element-aligned data from the first source 901 and the second source 903 are multiplied using multiplier circuit 907, the third most significant packed data element-aligned data from the first source 901 and the second source 903 are multiplied using multiplier circuit 909, and the least significant packed data element-aligned data from the first source 901 and the second source 903 are multiplied using multiplier circuit 911. In some embodiments, the signed packed data elements of the first source 901 are sign-extended, and the unsigned packed data elements of the second source 903 are zero extended before multiplication.

[0113] In some embodiments, these multiplier circuits 905-911 are reused for other packed data element alignments. In other embodiments, additional multiplier circuits are used such that the packed data elements are processed in parallel. In some contexts, a lane having the size of the signed third source 915 is used to accomplish the parallel execution. An adder circuit 913 is used to add up the results of each multiplication.

[0114] The addition result of the multiplication results is added to the most significant packed data element-aligned data from the signed source 3 915 (using a different adder 917 or the same adder 913).

[0115] Finally, the result 919 of the second addition is either stored into the signed destination in the packed data element alignment corresponding to the used packed data element alignment from the signed third source 915, or passed to the next iteration. In some embodiments, a write mask is applied to the storage such that the storage occurs if the corresponding write mask (bit) is set and does not occur if it is not set.

[0116] Figure 10 An embodiment illustrating a subset of the iterative execution of a chained fused multiply-accumulate instruction is shown. In particular, this shows the execution circuit for an iteration of one packed data element alignment of the destination. In this embodiment, the chained fused multiply-accumulate operates on signed and unsigned sources, where the accumulator is 4 times the input data size.

[0117] The first signed source 1001 and the second unsigned source 1003 each have four packed data elements. Each of these packed data elements stores data such as floating-point or integer data. The third signed source 1015 (initial or previous result) has packed data elements storing signed data. The sizes of the first and second sources are one quarter of the third signed source 1015 (initial or previous result). For example, the first and second sources may have 16-bit packed data elements (e.g., words), and the third signed source 1015 (initial or previous result) may have 64-bit packed data elements (e.g., double-precision floating-point numbers or 64-bit integers).

[0118] In this illustration, the four most significant packed data element orientations of the first signed source 1001 and the second unsigned source 1003 and the most significant packed data element orientation of the third signed source 1015 are shown. Of course, if there are any other packed data element orientations, they will also be processed.

[0119] As illustrated, the packed data elements are processed in quadruples. For example, the data of the most significant packed data element orientation of the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1005, the data of the second most significant packed data element orientation from the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1007, the data of the third most significant packed data element orientation from the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1009, and the data of the least significant packed data element orientation from the first signed source 1001 and the second unsigned source 1003 are multiplied using multiplier circuit 1011. In some embodiments, the signed packed data elements of the first signed source 1001 are sign-extended, and the unsigned packed data elements of the second unsigned source 1003 are zero-extended before multiplication.

[0120] In some embodiments, these multiplier circuits 1005 - 1011 are reused for other packed data element orientations. In other embodiments, additional multiplier circuits are used so that the packed data elements are processed in parallel. In some contexts, parallel execution is accomplished using channels of the size of the third signed source 1015 (initial or previous result). The adder / saturate 1013 circuit adds the addition result of the multiplication results to the data of the most significant packed data element orientation from the third signed source 1015 (initial or previous result).

[0121] When addition results in a value that is too large or too small for signed saturation, the add / saturate (accumulator) circuit 1013 preserves the sign of the operand. In particular, saturation evaluation occurs on the infinite-precision result between the multiple add and the write destination. When the accumulator 1013 is floating-point and the input terms are integer, the sum of products and the floating-point accumulator input values are made into infinite-precision values (a fixed-point number of hundreds of bits), the addition of the multiplication result and the third input is performed, and a single rounding to the actual accumulator type is performed.

[0122] The result 1019 of the addition and saturation check is stored into a signed destination in the packed data element orientation corresponding to the packed data element orientation of the third signed source 1015 (initial or previous result) that was used or passed to the next iteration. In some embodiments, a write mask is applied to this storage such that if the corresponding write mask (bit) is set, the storage occurs, and if not, the storage does not occur.

[0123] Figure 11 Illustrated is a power-of-two sized SIMD implementation according to an embodiment, where the accumulator uses an input size larger than the input to the multiplier. Note that the source (for the multiplier) and accumulator values can be signed or unsigned values. For an accumulator with 2x the input size (in other words, the size of the accumulator input value is twice the size of the packed data element of the source), Table 1101 illustrates different configurations. For a byte-sized source, the accumulator uses a 16-bit sized word or half-precision floating-point (HPFP) value. For a word-sized source, the accumulator uses a 32-bit integer or a 32-bit sized single-precision floating-point (SPFP) value. For a SPFP or 32-bit integer sized source, the accumulator uses a 64-bit integer or a 64-bit sized double-precision floating-point (DPFP) value.

[0124] For an accumulator with 4x the input size (in other words, the size of the accumulator input value is four times the size of the packed data element of the source), Table 1103 illustrates different configurations. For a byte-sized source, the accumulator uses a 32-bit integer or a 32-bit sized single-precision floating-point (SPFP) value. For a word-sized source, in some embodiments, the accumulator uses a 64-bit integer or a 64-bit sized double-precision floating-point (DPFP) value.

[0125] For an accumulator with 8x the input size (in other words, the size of the accumulator input value is eight times the size of the packed data element of the source), Table 1105 illustrates one configuration. For a byte-sized source, the accumulator uses a 64-bit integer.

[0126] As previously implied, the matrix operation circuit can be included in the core or as an external accelerator. Figure 12An embodiment of a system utilizing a matrix operation circuit is illustrated. In this illustration, multiple entities are coupled to a ring interconnect 1245.

[0127] Multiple cores - core 0 1201, core 1 1203, core 2 1205, and core N 1207 - provide tile - less instruction support. In some embodiments, the matrix operation circuit 1251 is provided in core 1203, and in other embodiments, the matrix operation circuits 1211 and 1213 are accessible on the ring interconnect 1245.

[0128] Additionally, one or more memory controllers 1223 - 1225 are provided to communicate with memories 1233 and 1231 on behalf of the cores and / or the matrix operation circuits.

[0129] Figure 13 An embodiment of a processor core pipeline supporting tile - based matrix operations is illustrated. The branch prediction and decoding circuit 1303 performs branch prediction of instructions, decoding of instructions, and / or both according to the instructions stored in the instruction store 1301. For example, the instructions detailed herein can be stored in the instruction store. In some implementations, separate circuits are used for branch prediction, and in some embodiments, microcode 1305 is used to decode at least some instructions into one or more micro - operations, microcode entry points, micro - instructions, other instructions, or other control signals. Various different mechanisms can be used to implement the branch prediction and decoding circuit 1303. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read - only memories (ROMs), etc.

[0130] The branch prediction and decoding circuit 1303 is coupled to an allocate / rename 1307 circuit, which in some embodiments is coupled to a scheduler circuit 1309. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functions by performing one or more of the following: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) assigning status bits and tags to the decoded instructions, and 3) scheduling the decoded instructions from the instruction pool for execution on the execution circuit (e.g., using reservation stations in some embodiments).

[0131] The scheduler circuitry 1309 represents any number of different schedulers, including reservation stations, a central instruction window, and the like. The scheduler circuitry 1309 is coupled to or includes one or more physical register files 1315. Each of the one or more physical register files 1315 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, and the like. In one embodiment, the one or more physical register files 1315 include a vector register circuit, a write mask register circuit, and a scalar register circuit. These register hardware can provide architectural vector registers, vector mask registers, and general-purpose registers. The one or more physical register files 1315 are overlapped by the retirement circuitry 1317 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using one or more reorder buffers and one or more retirement register files; using one or more future heaps, one or more history buffers, and one or more retirement register files; using register maps and register pools, etc.). The retirement circuitry 1317 and the one or more physical register files 1315 are coupled to the execution circuitry 1311.

[0132] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache outside the core and / or the processor. Alternatively, all caches may be outside the core and / or the processor.

[0133] The execution circuitry 1311 is a set of one or more execution circuits, including a scalar circuit 1321, a vector / SIMD circuit 1323, and a matrix operation circuit 1327, as well as a memory access circuit 1325 for accessing the cache 1313. The execution circuits perform various operations (such as shifts, additions, subtractions, multiplications) on various types of data (such as scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers). While some embodiments may include many execution units dedicated to specific functions or function sets, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The scalar circuit 1321 performs scalar operations, the vector / SIMD circuit 1323 performs vector / SIMD operations, and the matrix operation circuit 1327 performs matrix (tile) operations detailed herein.

[0134] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuitry performs the fetch and length decoding stages; 2) The branch and decode circuit 1303 performs the decode stage; 3) The allocation / rename 1307 circuit performs the allocation stage and the rename stage; 4) The scheduler circuit 1309 performs the scheduling stage; 5) The (one or more) physical register files (coupled to or included in the scheduler circuit 1309 and the allocation / rename 1307 circuit) and the memory unit perform the register read / memory read stage; The execution circuitry 1311 performs the execution stage; 6) The memory unit and the (one or more) physical register files (one or more) units perform the write-back / memory write stage; 7) Each unit may be involved in the exception handling stage; and 8) The retirement unit and the (one or more) physical register files (one or more) units perform the commit stage.

[0135] The core may support one or more instruction sets (such as the x86 instruction set (with some extensions that have been added to the updated versions); the MIPS instruction set of MIPS Technologies in Sunnyvale, California; the ARM instruction set of ARM Holdings in Sunnyvale, California (with optional additional extensions such as NEON), including the (one or more) instructions described herein. In one embodiment, the core 1390 includes logic to support packed data instruction set extensions (such as AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0136] It should be understood that the core can support multithreading (two or more parallel sets of executing operations or threads), and can do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (wherein a single physical core provides a logical core for each of the threads, the physical core being simultaneously multithreaded), or a combination thereof (e.g., time-sliced fetching and decoding, and subsequent simultaneous multithreading such as in hyperthreading technology).

[0137] Figure 14 An embodiment of a processor core pipeline that supports matrix operations using tiles is illustrated. The branch prediction and decoding circuit 1403 performs branch prediction of instructions, decoding of instructions, and / or both according to the instructions stored in the instruction store 1401. For example, the instructions detailed herein can be stored in the instruction store. In some implementations, separate circuits are used for branch prediction, and in some embodiments, microcode 1405 is used to decode at least some instructions into one or more micro-operations, microcode entry points, micro-instructions, other instructions, or other control signals. The branch prediction and decoding circuit 1403 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc.

[0138] The branch prediction and decoding circuit 1403 is coupled to the allocation / renaming 1407 circuit, which in some embodiments is coupled to the scheduler circuit 1409. In some embodiments, these circuits provide register renaming, register allocation, and / or scheduling functions by performing one or more of the following: 1) renaming logical operand values to physical operand values (e.g., a register alias table in some embodiments), 2) assigning status bits and tags to the decoded instructions, and 3) scheduling the decoded instructions from the instruction pool for execution on the execution circuit (e.g., using reservation stations in some embodiments).

[0139] Scheduler circuitry 1409 represents any number of different schedulers, including reservation stations, a central instruction window, etc. The (one or more) scheduler units of scheduler circuitry 1409 are coupled to or include the (one or more) physical register files 1415. Each of the (one or more) physical register files 1415 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), tiles, etc. In one embodiment, the (one or more) physical register files 1415 include vector register circuitry, write mask register circuitry, and scalar register circuitry. These register hardware can provide architectural vector registers, vector mask registers, and general-purpose registers. The (one or more) physical register files 1415 are overlapped by retirement circuitry 1417 to illustrate various ways in which register renaming and out-of-order execution can be implemented (e.g., using the (one or more) reorder buffers and the (one or more) retirement register files; using the (one or more) future heaps, the (one or more) history buffers, and the (one or more) retirement register files; using register maps and register pools, etc.). Retirement circuitry 1417 and the (one or more) physical register files 1415 are coupled to execution circuitry 1411.

[0140] Although register renaming is described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor may also include separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache, or a multi-level internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache outside the core and / or the processor. Alternatively, all caches may be outside the core and / or the processor.

[0141] Execution circuitry 1411 includes a set of one or more execution circuits 1427 and a set of one or more memory access circuits to access cache 1413. Execution circuits 1427 perform the matrix (tile) operations detailed herein.

[0142] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement a pipeline as follows: 1) The instruction fetch circuit implements the fetch and length decoding stages; 2) The branch and decode circuit 1403 implements the decoding stage; 3) The allocate / rename 1407 circuit implements the allocation stage and the renaming stage; 4) The scheduler circuit 1409 implements the scheduling stage; 5) The (one or more) physical register files (coupled to or included in the scheduler circuit 1409 and the allocate / rename 1407 circuit) and the memory unit implement the register read / memory read stage; The execution circuit 1411 implements the execution stage; 6) The memory unit and the (one or more) physical register files (one or more) units implement the write-back / memory write stage; 7) Each unit may be involved in the exception handling stage; and 8) The retirement unit and the (one or more) physical register files (one or more) units implement the commit stage.

[0143] The core may support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with updated versions); the MIPS instruction set of MIPS Technologies in Sunnyvale, California; the ARM instruction set of ARM Holdings in Sunnyvale, California (with optional additional extensions such as NEON), including the (one or more) instructions described herein. In one embodiment, the core 1490 includes logic to support a packed data instruction set extension (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0144] It should be understood that the core may support multithreading (two or more parallel sets of operations or threads), and may do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (wherein the physical core is simultaneous multithreading in the case where it provides a logical core for each of the threads), or a combination thereof (e.g., time-sliced fetching and decoding, and thereafter simultaneous multithreading such as in hyper-threading technology).

[0145] Layout

[0146] Throughout this specification, row-major data layout is used to represent data. Column-major users should transform the items according to their orientation. Figure 15 An example of a matrix represented in row-major format and column-major format is illustrated. As shown, matrix A is a 2×3 matrix. When the matrix is stored in row-major format, the data elements of the rows are contiguous. When this matrix is stored in column-major format, the data elements of the columns are contiguous. A well-known property of matrices is A T *B T =(BA) T, where the superscript T means transformation. Reading column-major data as row-major data causes the matrix to look like a transformation matrix.

[0147] In some embodiments, row-major semantics are utilized in hardware, and the column-major data has its operands' order swapped, which results in a transformed matrix, but for subsequent column-major reads from memory, it is the correct non-transformed matrix.

[0148] For example, if there are two column-major matrices to multiply:

[0149]

[0150] The input matrices will be stored in linear memory (column-major), such as:

[0151] acebdf

[0152] And

[0153] ghijk|.

[0154] Reading these matrices as row-major with dimensions 2×3 and 3×2, they will appear as:

[0155]

[0156] Swap the order and multiply the matrices:

[0157]

[0158] The transformed matrix comes out, and then it can be stored in row-major order:

[0159] ag+bh cg+dh eg+fh ai+bj ci+dj ei+fj ak+bl ck+dl ek+fl

[0160] And used in subsequent column-major calculations, which is the correct non-transformed matrix:

[0161]

[0162] Example Usage

[0163] Figure 16An example of the use of matrices (tiles) is illustrated. In this example, matrix C 1601 includes two tiles, matrix A 1603 includes one tile, and matrix B 1605 includes two tiles. This figure shows an example of the inner loop of an algorithm for calculating matrix multiplication. In this example, two result tiles tmm0 and tmm1 from matrix C 1601 are used to accumulate intermediate results. One tile from matrix A 1603 (tmm2) is reused twice because it is multiplied by two tiles from matrix B 1605. Pointers are to load new A matrices (tiles) and two new B matrices (tiles) in the direction indicated by the arrows. The outer loop, not shown, adjusts the pointers for C tiles.

[0164] The exemplary code shown includes the use of tile configuration instructions and is executed to configure tile usage, load tiles, loops for processing tiles, store tiles in memory, and release tile usage.

[0165] Figure 17 An embodiment of the use of matrices (tiles) is illustrated. At 1701, tile usage is configured. For example, the TILECONFIG instruction is executed to configure tile usage, including setting the number of rows and columns of each tile. Typically, at 1703, at least one matrix (tile) is loaded from memory. At least one matrix (tile) operation is performed using the matrix (tile) at 1705. At 1707, at least one matrix (tile) is stored out to memory, and a context switch may occur at 1709.

[0166] Exemplary Configuration

[0167] Tile Configuration Hardware Support

[0168] As discussed above, it is generally necessary to configure tile usage before use. For example, it may not be necessary to fully use all rows and columns. In some embodiments, not only does configuring these rows and columns save power, but this configuration can be used to determine whether an operation will generate an error. For example, matrix multiplication of the form (N×M)*(L×N) generally does not work if M and L are not the same.

[0169] In some embodiments, before using a matrix that utilizes tiles, tile support is to be configured. For example, the number of rows and columns of each tile, the tiles to be used, etc. are configured. The TILECONFIG instruction is an improvement to the computer itself because it provides support for configuring the computer to use a matrix accelerator (either as part of a processor core or as an external device). In particular, the execution of the TILECONFIG instruction causes a configuration to be retrieved from memory and applied to the matrix (tile) settings within the matrix accelerator.

[0170] Tile Usage Configuration

[0171] Figure 18 Illustrated is support for a configuration used for tiles according to an embodiment. Memory 1801 includes tile description 1803 of a matrix (tile) to be supported.

[0172] Instruction execution resources 1811 of processor / core 1805 store aspects of tile description 1803 into tile configuration 1817. Tile configuration 1817 includes a palette table 1813 to detail what tiles are configured for a palette (number of rows and columns in each tile) and a flag for matrix support in use. In particular, instruction execution resources 1811 are configured to use tiles as specified by tile configuration 1817. Instruction execution resources 1811 may also include machine-specific registers or configuration registers to indicate tile usage. Additional values are also set, such as values in use and initial values. Tile configuration 1817 utilizes register(s) 1819 to store tile usage and configuration information.

[0173] Figure 19 Illustrated is an embodiment of a description of a matrix (tile) to be supported. This is the description to be stored when executing the STTILECFG instruction. In this example, each field is one byte. In byte [0], palette ID 1901 is stored. The palette ID is used to index palette table 1813, which stores the number of bytes in a tile and the number of bytes per row of the tile associated with that ID as defined by the configuration.

[0174] Byte 1 stores the value to be stored in the "startRow" register 1903, and byte 2 stores the value to be stored in register startP 1905. To support restarting an instruction after these events, the instruction stores the information of these registers. To support restarting an instruction after an interrupt event such as detailed above, the instruction stores the information in these registers. The startRow value indicates the row that should be used for restart. The startP value indicates the orientation within the row for a store operation when using pairs, and in some embodiments, indicates the lower half of the row (in the lower tile of a pair) or the upper half of the row (in the upper tile of a pair). Generally, the orientation within a row (column) is not required.

[0175] In addition to TILECONFIG and STTILECFG, successful execution of a matrix (tile) instruction sets both startRow and startP to zero.

[0176] At any time when the matrix (tile) instruction is not restarted interrupted, it is the responsibility of the software to set the startRow and startP values to zero. For example, an unmasked floating-point exception handler may decide to complete the operation in software and change the program counter value to another instruction, typically the next instruction. In this case, the software exception handler must set the startRow and startP values in the exception presented to it by the operating system to zero before resuming the program. Subsequently, the operating system will use the resume instruction to reload these values.

[0177] Byte 3 stores an indication of the pair for tile 1907 (1b for each tile).

[0178] Bytes 16 - 17 store the row number 1913 and column number 1915 for tile 0, bytes 18 - 19 store the row and column numbers for tile 1, and so on. In other words, each 2-byte group specifies the row and column numbers for a tile. If the 2-byte groups are not used to specify tile parameters, their values should be zero. Specifying tile parameters for more tiles than implementation limits or palette limits will result in a failure. Unconfigured tiles are set to an initial state with 0 rows and 0 columns.

[0179] Finally, the configuration in memory usually ends with an end-of-drawing, such as several consecutive bytes all being zero.

[0180] Exemplary Tile and Tile Configuration Storage

[0181] Figures 20(A) - (D) illustrate examples of one or more registers 1819. Figure 20(A) illustrates multiple registers 1819. As shown, each tile (TMM0 2001... TMMN 2003) has a separate register, where each register stores the row and column sizes of that particular tile. StartP 2011 and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set (e.g., TILES_CONFIGURED = 1) to indicate that the tiles are configured for use.

[0182] Figure 20(B) illustrates multiple registers 1819. As shown, each tile has separate registers for rows and columns. For example, TMM0 row configuration 2021, TMM0 column configuration 2023, StartP 2011, and StartRow 2013 are stored in separate registers. One or more status registers 2015 are set (e.g., TILES_CONFIGURED = 1) to indicate that the tiles are configured for use.

[0183] Figure 20(C) illustrates a single register 1819. As shown, the register stores the tile configuration (rows and columns per tile) 2031, and StartP 2011 and StartRow 2013 are stored in a single register as packed data register. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that the tiles are configured for use.

[0184] Figure 20(D) illustrates multiple registers 1819. As shown, a single register stores the tile configuration (rows and columns per tile) 2031. StartP and StartRow are stored in separate registers 2011 and 2013. One or more status registers 2015 (e.g., TILES_CONFIGURED = 1) are set to indicate that the tiles are configured for use.

[0185] Other combinations can be considered, such as combining the initial registers into a single register where they are shown separately, and so on.

[0186] TILE16BDP

[0187] As mentioned above, special hardware for general matrix multiplication (also known as GEMM) is a good option for improving the peak computational performance (and energy efficiency) of certain applications such as deep learning. As long as the output elements have enough bits (i.e., more than the input), some of these applications (including deep learning) can operate on input data elements with relatively few bits without loss of precision.

[0188] Accordingly, the disclosed method and system implement a 16-bit floating-point matrix dot product operation (TILE16BDP) that takes a source matrix (tile) with 16-bit floating-point elements, performs dot product multiplication, and accumulates the resulting product with a 32-bit single-precision destination.

[0189] The disclosed TILE16BDP instruction is to be executed by a processor that includes fetch circuitry to fetch an instruction having a field that specifies an opcode and the locations of an M×N destination matrix (tile) with single-precision elements, an M×K first source matrix (tile), and a K×N second source matrix (tile), where the elements of the specified first and second source matrices include a pair of even and odd 16-bit floating-point values, and where the opcode is to direct execution circuitry to, for each element (M,N) of the specified destination matrix (tile), convert K pairs of elements from row M of the specified first source matrix (tile) and the corresponding K pairs of elements from column N of the specified second source matrix (tile) to single-precision values, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the specified source matrices (tiles) separately, and then sum those products separately with the previous contents of element (M,N) into a sum of even products and a sum of odd products. The processor will also include other support hardware, such as decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.

[0190] Figure 21 is a block diagram illustrating the use of the TILE16BDP instruction to accelerate matrix multiplication according to some embodiments. As shown, instruction 2101 includes a field that specifies an opcode 2102 (e.g., TILE16BDP) and the locations of an M×N destination matrix (tile) 2104 with single-precision elements, an M×K first source matrix (tile) 2106, and a K×N second source matrix (tile) 2108, where the specified source matrices have elements that include a pair of 16-bit floating-point values. According to some embodiments, the format of the TILE16BDP instruction is further illustrated and described with at least reference to Figure 24 、 25A -B and 26A-D.

[0191] Here, the specified first source matrix (tile) 2112A has dimensions of M = 4 by K = 3. The specified second source matrix (tile) 2112B has dimensions of K = 3 by N = 5. For illustrative purposes, K, M, and N are shown as having different values, but in other embodiments they may be equal.

[0192] In operation, the processor 2100 is to respond to the opcode 2102 (TILE16BDP) by, for each element (M, N) of the specified destination matrix (tile) 2122, converting, using conversion circuit 2116A, K pairs of elements of row M from the specified first source matrix (tile) 2112A, and, using conversion circuit 2116B, K pairs of elements of column N from the specified second source matrix (tile) 2112B to single precision, e.g., binary 32 single precision floating point, as specified by IEEE 794. The processor 2100 is then to multiply together the K converted even values using multiplication circuit 2118, and multiply together the K converted odd values, and accumulate the K products with the previous contents of element (M, N) using accumulation circuit 2120.

[0193] The performance of the TILE16BDP instruction is illustrated here for setting the destination element at matrix (tile) location (1, 0). Thus, the processor 2100 is to use conversion circuits 2116A and 2116B to convert K (= 3) pairs of elements of row M (= 1) from the specified first source matrix (tile) 2112A and K (= 3) pairs of elements of column N (= 0) from the specified second source matrix (tile) 2112B to single precision. The processor 2100 is then to multiply the converted even elements from the two specified source matrices (tiles) using multiplication circuit 2118, and multiply the converted odd elements from the specified source matrices (tiles) separately, and then use accumulation circuit 2120 to accumulate these products with the previous contents of element (M, N) separately into a sum of even products and a sum of odd products, where element (M, N) here is element C(1, 0).

[0194] As shown, three arrows proceed from each of the specified first and second source matrices (tiles) to indicate that the conversion and multiplication occur in parallel. In some embodiments, the processor responds to the decoded instruction by generating the results in parallel and storing the results to each element of the specified destination matrix (tile). In some embodiments, the new values are generated and stored into the destination one row or one column at a time.

[0195] The disclosed embodiments improve replacement methods by allowing software to implement the TILE16BDP instruction with a reduced source element size, which allows for less memory space and less memory bandwidth to be used, and improves the peak computational performance (and energy efficiency) for certain applications. In some applications (such as deep learning), as long as the output elements have enough bits (i.e., more than the input), input data elements with relatively few bits can be operated on without loss of precision.

[0196] At least with reference toFigure 22A -C, 23, and 28A - B are used to further illustrate and describe the system and method for executing the TILE16BDP instruction.

[0197] Exemplary Execution

[0198] Figure 22A is pseudocode that illustrates an exemplary execution of the TILE16BDP instruction according to some embodiments. As shown, instruction 2201 includes an opcode 2202 (e.g., TILE16BDP) and the locations of an M×N destination matrix 2204 with single - precision elements, an M×K first source matrix 2206, and a K×N second source matrix 2208, where the specified source matrices have elements that include a pair of 16 - bit floating - point values. The opcode 2202 (TILE16BDP) indicates that the processor is to, for each element (M, N) of the specified destination matrix (tile), convert K pairs of elements from row M of the specified first source matrix (tile) and K pairs of elements from column N of the specified second source matrix (tile) to single - precision, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then add these products to the previous contents of element (M, N) separately to form a sum of even products and a sum of odd products. In other embodiments not shown, the multiplication occurs before the conversion.

[0199] In operation, M, K, and N are to be specified in one or more of several ways: as operands to the TILE16BDP instruction (as here), as a suffix or prefix to the specified opcode (the asterisk is used herein as an abbreviation to refer to those optional suffixes and prefixes), as part of an immediate value provided with the instruction (e.g., K, M, and N are each to be specified as different 8 - bit portions of a 32 - bit immediate), as part of a control register programmed by software (e.g., XTILECONFIG is a register loaded by any matrix configuration instruction such as a TILECFG or XRSTORE* instruction and stored by a matrix save instruction such as XSAVE*), or even as architecture defaults.

[0200] Instruction 2201 further specifies the destination matrix (tile) location 2204, the first source matrix (tile) location 2206, and the second source matrix (tile) location 2208. Each specified matrix (tile) location can point to any one of a memory location, a set of vector registers, and a set of tile registers.

[0201] Figure 22Bis pseudocode that illustrates an exemplary execution of a TILE16BDP instruction according to some embodiments. As shown, instruction 2211 includes an opcode 2212 (e.g., TILE16BDP) and the locations of an M×N destination matrix 2214 with single-precision elements, an M×K first source matrix 2216, and a K×N second source matrix 2218, where the specified source matrices have elements that include a pair of 16-bit floating-point values. The pseudocode 2210 is similar to pseudocode 2200( Figure 22A ), except that the products of the odd source elements are accumulated with the destination elements before the products of the even source elements.

[0202] Refer to Figure 21 , 22B , 23, 28A-B, and 29A-B for further illustration and description of the execution of the TILE16BDP instruction. Refer to Figure 24-2 6 for further illustration and description of the format of the TILE16BDP instruction.

[0203] Figure 22C is pseudocode for an exemplary helper function for use with the TILE16BDP instruction. As shown, the pseudocode 2220 defines the make_fp32() function, the write_row_and_zero() function, the zero_upper_rows() function, and the zero_tileconfig_start() function, all of which are used by the Figure 22A TILE16BDP pseudocode.

[0204] Refer to Figure 21 , 22B , 23, 28A-B, and 29A-B for further illustration and description of the execution of the TILE16BDP instruction. Refer to Figure 24-2 6 for further illustration and description of the format of the TILE16BDP instruction.

[0205] Exemplary (One or More) Execution Methods

[0206] Figure 23 is a block flow diagram of a processor in response to a TILE16BDP instruction. As shown in flowchart 2300, at 2301, the processor is to use an acquisition circuit to acquire an instruction with fields that specify an opcode and the locations of an M×N destination matrix with single-precision elements, an M×K first source matrix, and a K×N second source matrix, where the specified source matrices have elements that include a pair of 16-bit floating-point values.

[0207] In embodiments that use the physical register file of a processor to store matrices (tiles), since the destination elements are twice the width of the source elements, having a pair of 16-bit floating-point formats in the source allows for efficient use when the matrix (tile) is a collection of vector registers, with vector registers of the same type, which are 128-bit xmm registers, 256-bit ymm registers, or 512-bit zmm registers. Such efficient use can also be achieved when the matrix is stored in tile registers. In other embodiments not shown, a single source vector with 16-bit floating-point elements is converted to 32-bit elements stored in a destination vector that is half the width of the source vector.

[0208] The specified opcode is to direct the execution circuitry to, for each element (M, N) of the specified destination matrix, convert k pairs of elements from row M of the specified first source matrix and k pairs of elements from column N of the specified second source matrix to single precision, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then add those products to the previous contents of element (m, n) separately to form a sum of the even products and a sum of the odd products.

[0209] At 2303, the processor is to use a decoding circuit to decode the fetched instruction. For example, the fetched TILE16BDP instruction is decoded by a decoding circuit such as the decoding circuit detailed herein. In the context of the illustrated system, the decoding circuit is similar to the decoding circuit illustrated and described at least with reference to Figure 13 , 14 and 28A - B.

[0210] At 2305, the execution of the decoded instruction is scheduled (as needed), which is optional in the sense that it can occur at different times or not at all (as indicated by its dashed boundary). At 2307, the processor is to use an execution circuit to respond to the decoded instruction as specified by the opcode.

[0211] In some embodiments, the instruction is committed or retired at 2309, which is optional in the sense that it can occur at different times or not at all (as indicated by its dashed boundary).

[0212] Reference Figure 3-14 further illustrates and describes the execution circuit. In some embodiments, the execution circuit is a matrix operation accelerator, such as the accelerator illustrated and described as accelerator 307 ( Figure 3 ). In some embodiments, the execution circuit is a matrix operation circuit, such as matrix operation circuit 405 ( Figure 4 ), 505 ( Figure 5 ) or 1213 (Figure 12 ) and 1327( Figure 13 ).

[0213] Exemplary (One or More) Instruction Formats

[0214] Figure 24 is a block diagram illustrating the format of a TILE16BDP instruction according to some embodiments. As shown, the TILE16BDP instruction 2400 includes fields for specifying an opcode 2402 (TILE16BDP*) that indicates that the processor is to convert K pairs of elements from row M of a specified first source matrix and K pairs of elements from column N of a specified second source matrix to single precision for each element (M, N) of a specified destination matrix, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then add these products to the previous contents of the elements (m, n) separately to form a sum of even products and a sum of odd products.

[0215] The instruction 2400 further includes a destination matrix (tile) location 2404, a first source matrix (tile) location 2406, and a second source matrix (tile) location 2408. Each of the specified source matrix locations and the destination matrix location can be in any of a memory location, a set of vector registers, and a set of tile registers.

[0216] The TILE16BDP instruction 2400 further includes a number of optional parameters to control the behavior of the processor, including a source element format 2410, K 2412, M 2414, and N 2416. In some embodiments, both N and M are any of 4, 8, 16, and 32 (however, the present invention does not set an upper limit on M or N, and M or N can be 32, 64, or larger). In some embodiments, both N and M are integers greater than or equal to 4.

[0217] The opcode 2402 is shown as including an asterisk, which is to convey that additional prefixes and / or suffixes can be added to specify instruction behavior. Prefixes or suffixes to the opcode 2402 can be used to specify one or more of the instruction modifiers 2410, 2412, 2414, and 2416.

[0218] In some embodiments, one or more of the optional instruction modifiers 2410, 2412, 2414, and 2416 are encoded in an immediate field (not shown) optionally included in the instruction 2400. In some embodiments, one or more of the optional instruction modifiers 2410, 2412, 2414, and 2416 are specified via a configuration / status register (e.g., XTILECONFIG).

[0219] When the instruction does not specify any one or more of the optional modifiers 2410, 2412, 2414, and 2416, they sometimes use default values or implicit parameters inherited from other parts of the tile architecture.

[0220] Detailed Exemplary System, Processor, and Emulation

[0221] Examples of the hardware, software, etc. for executing the above instructions are detailed herein. For example, the following description details various aspects of instruction execution, including various pipeline stages such as fetch, decode, schedule, execute, retire, etc.

[0222] Instruction Set

[0223] An instruction set may include one or more instruction formats. A given instruction format may define various fields (e.g., number of bits, position of bits) to specify, among other things, the operation to be performed (e.g., opcode) and the operand(s) and / or other data field(s) (e.g., mask) on which the operation is to be performed. Some instruction formats are further decomposed by the definition of instruction templates (or sub-formats). For example, an instruction template with a given instruction format may be defined as having a different subset of the fields of the instruction format (the included fields are typically in the same order, but at least some have different bit positions since fewer fields are included) and / or may be defined as having a given field that is interpreted differently. Thus, each instruction of the ISA is expressed using a given instruction format (and, if defined, a given instruction template having that instruction format) and includes fields for specifying the operation and operands. For example, an exemplary ADD instruction has a specific opcode and an instruction format that includes an opcode field for specifying the opcode and operand fields for selecting the operands (source 1 / destination and source 2); and the occurrence of the ADD instruction in the instruction stream will have specific contents in the operand fields for selecting the specific operands. A set of SIMD extensions known as Advanced Vector Extensions (AVX) (AVX1 and AVX2) and using the Vector Extension (VEX) encoding scheme have been published and / or announced (e.g., see 64 and IA-32 Architectures Software Developer's Manual, September 2014; and see Advanced Vector Extensions Programming Reference, October 2014).

[0224] Exemplary Instruction Format

[0225] Embodiments of the (one or more) instructions described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the (one or more) instructions may be executed on such systems, architectures, and pipelines, but the embodiments are not limited to those detailed.

[0226] General vector-friendly instruction format

[0227] A vector-friendly instruction format is an instruction format suitable for vector instructions (e.g., there are certain fields specific to vector operations). Although embodiments are described in which both vector and scalar operations are supported via a vector-friendly instruction format, alternative embodiments use only vector operations with a vector-friendly instruction format.

[0228] Figure 25A-25B is a block diagram illustrating a general vector-friendly instruction format and its instruction templates according to an embodiment. Figure 25A is a block diagram illustrating a general vector-friendly instruction format and its Class A instruction templates according to an embodiment; and Figure 25B is a block diagram illustrating a general vector-friendly instruction format and its Class B instruction templates according to an embodiment. Specifically, the general vector-friendly instruction format 2500 defines Class A and Class B instruction templates for which neither includes a memory access 2505 instruction template and a memory access 2520 instruction template. In the context of a vector-friendly instruction format, the term general refers to an instruction format that is not bound to any particular instruction set.

[0229] Although embodiments will be described in which a vector-friendly instruction format supports the following: a 64-byte vector operand length (or size) with 32-bit (4-byte) or 64-bit (8-byte) data element widths (or sizes) (and thus, a 64-byte vector is composed of 16 double-word-sized elements or alternatively 8 quad-word-sized elements); a 64-byte vector operand length (or size) with 16-bit (2-byte) or 8-bit (1-byte) data element widths (or sizes); a 32-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); and a 16-byte vector operand length (or size) with 32-bit (4-byte), 64-bit (8-byte), 16-bit (2-byte), or 8-bit (1-byte) data element widths (or sizes); alternative embodiments may support more, fewer, and / or different vector operand sizes (e.g., a 256-byte vector operand) with more, fewer, or different data element widths (e.g., a 128-bit (16-byte) data element width).

[0230] Figure 25AThe class A instruction templates in include: 1) within the no memory access 2505 instruction template, showing the no memory access, full rounding control type operation 2510 instruction template and the no memory access, data transformation type operation 2515 instruction template; and 2) within the memory access 2520 instruction template, showing the memory access, temporary 2525 instruction template and the memory access, non-temporary 2530 instruction template. Figure 25B The class B instruction templates in include: 1) within the no memory access 2505 instruction template, showing the no memory access, write mask control, partial rounding control type operation 2512 instruction template and the no memory access, write mask control, vsize type operation 2517 instruction template; and 2) within the memory access 2520 instruction template, showing the memory access, write mask control 2527 instruction template.

[0231] The general vector-friendly instruction format 2500 in Figure 25A-25B the order illustrated in includes the following fields listed below.

[0232] Format field 2540 - The specific value (instruction format identifier value) in this field uniquely identifies the vector-friendly instruction format and thus uniquely identifies the occurrence of an instruction in the instruction stream that employs the vector-friendly instruction format. Accordingly, this field is optional in the sense that it is not required for an instruction set that only has the general vector-friendly instruction format.

[0233] Basic operation field 2542 - Its content differentiates different basic operations.

[0234] Register index field 2544 - Its content directly or through address generation specifies the locations of source and destination operands, whether they are in registers or in memory. These include a sufficient number of bits to select N registers from a PxQ (e.g., 32x512, 16x128, 32x1024, 64x1024) register file. While one embodiment supports up to three sources and one destination register, alternative embodiments may support more or fewer sources and destination registers (e.g., may support up to two sources, where one of these sources also acts as the destination; may support up to three sources, where one of these sources also acts as the destination; may support up to two sources and one destination).

[0235] Modifier field 2546 -- the content of which differentiates the occurrence of an instruction in a general vector instruction format that specifies a memory access from the occurrence of an instruction in a general vector instruction format that does not specify a memory access; that is, it differentiates between the no-memory-access 2505 instruction template and the memory-access 2520 instruction template. A memory access operation reads and / or writes to the memory hierarchy (in some cases, using values in registers to specify source and / or destination addresses), while a non-memory access operation does not (e.g., the source and destination are registers). Although in one embodiment, this field also selects between three different ways to perform memory address calculation, alternative embodiments may support more, fewer, or different ways to perform memory address calculation.

[0236] Extended operation field 2550 -- in addition to the basic operation, the content of which also differentiates which one of a variety of different operations is to be performed. This field is context-specific. In one embodiment, this field is divided into a category field 2568, an alpha field 2552, and a beta field 2554. The extended operation field 2550 allows a common group of operations to be performed in a single instruction rather than in 2, 3, or 4 instructions.

[0237] Scale field 2560 -- the content of which allows the content of the index field used for memory address generation (e.g., for address generation using 2 scale * index + base address) to be scaled.

[0238] Displacement field 2562A -- the content of which is used as part of memory address generation (e.g., for address generation using 2 scale * index + base address + displacement).

[0239] Displacement factor field 2562B (note that the juxtaposition of the displacement field 2562A directly above the displacement factor field 2562B indicates that one or the other is used) -- the content of which is used as part of address generation; it specifies a displacement factor to be scaled by the size of the memory access (N) -- where N is the number of bytes in the memory access (e.g., for using 2 scale*(Index + Base + Scaled Displacement Address Generation). Redundant low-order bits are ignored, and thus the contents of the displacement factor field are multiplied by the total size of the memory operand (N) to generate the final displacement to be used in calculating the effective address. The value of N is determined by the processor hardware at run time based on the full opcode field 2574 (described later herein) and the data manipulation field 2554C. The displacement field 2562A and the displacement factor field 2562B are optional in the sense that they are not used for the no-memory-access 2505 instruction template and / or different embodiments may implement only one of the two or neither.

[0240] Data Element Width Field 2564 - whose contents distinguish which of the multiple data element widths is to be used (in some embodiments for all instructions; in other embodiments only for some instructions). This field is optional in the sense that it is not needed if only one data element width is supported and / or some aspect of the opcode is used to support the data element width.

[0241] Write Mask Field 2570 - whose contents control, on a per-data-element basis, whether that data element in the destination vector operand reflects the results of the base operation and the extended operation. Category A instruction templates support merge-write masking, while category B instruction templates support both merge-write masking and zero-write masking. When merged, the vector mask allows any set of elements in the destination to be protected from update during the execution of any operation (specified by the base operation and the extended operation); in another embodiment, the old value of each element of the destination where the corresponding mask bit has 0 is retained. In contrast, when zeroing, the vector mask allows any set of elements in the destination to be set to zero during the execution of any operation (specified by the base operation and the extended operation); in one embodiment, the elements of the destination are set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (i.e., the span of elements, from first to last, is modified); however, it is not necessary for the modified elements to be contiguous. Thus, the write mask field 257 allows partial vector operations, including loads, stores, arithmetic, logic, etc. Although embodiments have been described in which the contents of the write mask field 2570 select one of a plurality of write mask registers that contains the write mask to be used (and thus the contents of the write mask field 2570 indirectly identify the mask to be implemented), alternative embodiments instead or additionally allow the contents of the mask write field 2570 to directly specify the mask to be implemented.

[0242] Immediate digit field 2572 - the content of which permits the specification of an immediate number. This field is optional in the sense that it is absent in implementations with a general vector-friendly format that do not support immediate numbers, and it is absent in instructions that do not use immediate numbers.

[0243] Category field 2568 - the content of which differentiates between different categories of instructions. Refer to Figure 25A -B, the content of this field selects between category A and category B instructions. In Figure 25A -B, rounded rectangles are used to indicate the presence of specific values in a field (e.g., category A 2568A and category B 2568B for category field 2568 in Figure 25A -B, respectively).

[0244] Instruction Template for Category A

[0245] In the case of the non-memory access 2505 instruction template of category A, the alpha field 2552 is interpreted as the RS field 2552A, the content of which differentiates which of different extended operation types is to be performed (e.g., specifying rounding 2552A.1 and data transformation 2552A.2 for non-memory access, rounding type operation 2510 and non-memory access, data transformation type operation 2515 instruction templates respectively), and the beta field 2554 differentiates which of the specified type of operations is to be performed. In the non-memory access 2505 instruction template, the scale field 2560, the displacement field 2562A, and the displacement scale field 2562B are absent.

[0246] Non-memory access instruction template - full rounding control type operation

[0247] In the non-memory access full rounding control type operation 2510 instruction template, the beta field 2554 is interpreted as the rounding control field 2554A, the content of which (one or more) provides static rounding. Although in the described embodiments, the rounding control field 2554A includes: the suppress all floating-point exceptions (SAE) field 2556 and the rounding operation control field 2558, alternative embodiments may support encoding these concepts into the same field, or having only one or the other of these concepts / fields (e.g., may have only the rounding operation control field 2558).

[0248] SAE field 2556 - the content of which differentiates whether to disable the reporting of exception events; when the content of the SAE field 2556 indicates that suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not trigger any floating-point exception handler.

[0249] Rounding operation control field 2558 - The content thereof differentiates which one of the rounding operation groups to perform (e.g., rounding up, rounding down, rounding to zero, and rounding to the nearest). Thus, the rounding operation control field 2558 allows the rounding mode to be changed instruction by instruction. In an embodiment where the processor includes a control register for specifying the rounding mode, the content of the rounding operation control field 2550 overrides the register value.

[0250] Instruction Template without Memory Access - Data Transformation Type Operations

[0251] In the no-memory-access data transformation type operation 2515 instruction template, the beta field 2554 is interpreted as the data transformation field 2554B, and the content thereof differentiates which one of the multiple data transformations to perform (e.g., no data transformation, swizzle, broadcast).

[0252] In the case of the class A memory access 2520 instruction template, the alpha field 2552 is interpreted as the eviction hint field 2552B, and the content thereof differentiates which eviction hint to use (in Figure 25A respectively specify the transient 2552B.1 and non-transient 2552B.2 for the memory access, transient 2525 instruction template and the memory access, non-transient 2530 instruction template), and the beta field 2554 is interpreted as the data manipulation field 2554C, and the content thereof differentiates which one of the multiple data manipulation operations (also referred to as primitives) to perform (e.g., no manipulation; broadcast; up-conversion of the source; and down-conversion of the destination). The memory access 2520 instruction template includes a scale field 2560, and optionally includes a displacement field 2562A or a displacement scale field 2562B.

[0253] Vector memory instructions use conversion support to load vectors from memory and store vectors to memory. Similar to using conventional vector instructions, vector memory instructions transfer data to / from memory in terms of data elements, where the actually transferred elements are specified by the content of the vector mask selected as the write mask.

[0254] Instruction Template for Memory Access - Temporary

[0255] Transient data is data that has the potential to be reused quickly enough to benefit from caching. However, this is a hint, and different processors can implement it in different ways, including completely ignoring the hint.

[0256] Instruction Template for Memory Access - Non-Temporary

[0257] Non-temporary data is data that is not likely to be reused quickly enough to benefit from caching in a level 1 cache and should be given priority for eviction. However, this is a hint, and different processors may implement it in different ways, including completely ignoring the hint.

[0258] Instruction Template for Category B

[0259] In the case of the instruction template of category B, the alpha field 2552 is interpreted as a write mask control (Z) field 2552C, the content of which differentiates whether the write mask controlled by the write mask field 2570 should be merged or zeroed.

[0260] In the case of the non-memory access 2505 instruction template of category B, a part of the beta field 2554 is interpreted as an RL field 2557A, the content of which differentiates which one of different extension operation types is to be implemented (e.g., for the no-memory access, write mask control, partial rounding control type arithmetic 2512 instruction template and the no-memory access, write mask control, VSIZE type arithmetic 2517 instruction template, rounding 2557A.1 and vector length (VSIZE) 2557A.2 are specified respectively), while the remaining part of the beta field 2554 differentiates which one of the operations of the specified type is to be implemented. In the no-memory access 2505 instruction template, the scale field 2560, the displacement field 2562A, and the displacement scale field 2562B do not exist.

[0261] In the no-memory access, write mask control, partial rounding control type arithmetic 2510 instruction template, the remaining part of the beta field 2554 is interpreted as a rounding arithmetic field 2559A, and exception event reporting is disabled (the given instruction does not report any kind of floating-point exception flag and does not trigger any floating-point exception handler).

[0262] The rounding arithmetic control field 2559A - like the rounding arithmetic control field 2558, its content differentiates which one of the rounding arithmetic groups is to be implemented (e.g., round up, round down, round to zero, and round to nearest). Thus, the rounding arithmetic control field 2559A allows the rounding mode to be changed instruction by instruction. In one embodiment where the processor includes a control register for specifying the rounding mode, the content of the rounding arithmetic control field 2550 overrides the register value.

[0263] In the no-memory access, write mask control, VSIZE type arithmetic 2517 instruction template, the remaining part of the beta field 2554 is interpreted as a vector length field 2559B, the content of which differentiates which one of the multiple data vector lengths is to be implemented for it (e.g., 128, 256, or 512 bytes).

[0264] In the case of the memory access 2520 instruction template of category B, a portion of the beta field 2554 is interpreted as a broadcast field 2557B, the content of which differentiates whether to perform a broadcast type data manipulation operation, and the remaining portion of the beta field 2554 is interpreted as a vector length field 2559B. The memory access 2520 instruction template includes a scale field 2560, and optionally includes a displacement field 2562A or a displacement scale field 2562B.

[0265] Regarding the general vector friendly instruction format 2500, a full opcode field 2574 including a format field 2540, a base operation field 2542, and a data element width field 2564 is shown. Although one embodiment is shown in which the full opcode field 2574 includes all of these fields, in embodiments that do not support all of these fields, the full opcode field 2574 includes less than all of these fields. The full opcode field 2574 provides an operation code (opcode).

[0266] The extended operation field 2550, the data element width field 2564, and the write mask field 2570 allow these features to be specified instruction-by-instruction in the general vector friendly instruction format.

[0267] The combination of the write mask field and the data element width field creates typed instructions because they allow the application of masks based on different data element widths.

[0268] The various instruction templates found in category A and category B are beneficial in different scenarios. In some embodiments, different processors or different cores within a processor may support only category A, only category B, or both categories. For example, a high-performance general-purpose out-of-order core intended for general computing may support only category B, a core primarily intended for graphics and / or scientific (throughput) computing may support only category A, and a core intended for both may support both (of course, a core with some mix of templates and instructions from both categories is within the scope of the present invention, rather than all templates and instructions from both categories). Also, a single processor may include multiple cores, all of which support the same category or where different cores support different categories. For example, in a processor with a separate graphics component and general-purpose cores, one of the graphics cores primarily intended for graphics and / or scientific computing may support only category A, while one or more general-purpose cores may be high-performance general-purpose cores with out-of-order execution and register renaming intended for general computing, and they support only category B. Another processor without a separate graphics core may include one or more general-purpose in-order or out-of-order cores that support both category A and category B. Of course, features from one category may also be implemented in another category in different embodiments. A program written in a high-level language will be put into (e.g., just-in-time compiled or statically compiled) various different executable forms, including: 1) a form having only the instruction(s) of the category(ies) supported by the target processor for execution; or 2) a form having replacement routines written using different combinations of instructions of all categories and having control flow code that selects the routine to execute based on the instructions supported by the processor currently executing the code).

[0269] Exemplary Specific Vector-Friendly Instruction Format

[0270] Figure 26A is a block diagram illustrating an exemplary specific vector-friendly instruction format according to an embodiment. Figure 26A Illustrates a specific vector-friendly instruction format 2600, which is specific in the sense that the specific vector-friendly instruction format specifies the location, size, interpretation, and field order, as well as the values for some of those fields. The specific vector-friendly instruction format 2600 can be used to extend the x86 instruction set, and thus some fields are similar or identical to those used in the existing x86 instruction set and its extensions (e.g., AVX). This format is consistent with the prefix coding field, the actual opcode byte field, the MOD R / M field, the SIB field, the displacement field, and the immediate number field of the existing x86 instruction set with extensions. Fields from Figure 25 are illustrated, where fields from Figure 26A are mapped to fields from Figure 25.

[0271] It should be understood that although, for illustrative purposes, embodiments are described in the context of a general vector friendly instruction format 2500 with reference to a specific vector friendly instruction format 2600, the present invention is not limited to that specific vector friendly instruction format 2600 except where claimed. For example, while the specific vector friendly instruction format 2600 is shown as having fields of a particular size, the general vector friendly instruction format 2500 contemplates a variety of possible sizes for the various fields. As a specific example, while in the specific vector friendly instruction format 2600, the data element width field 2564 is illustrated as a one-bit field, the present invention is not so limited (i.e., the general vector friendly instruction format 2500 contemplates data element width fields 2564 of other sizes).

[0272] The general vector friendly instruction format 2500 includes the following fields listed in sub-sequence as illustrated below in Figure 26A the following fields listed in sub-sequence as illustrated in

[0273] EVEX prefix 2602 (bytes 0 - 3) - encoded in a four-byte form.

[0274] Format field 2540 (EVEX byte 0, bits [7:0]) - the first byte (EVEX byte 0) is the format field 2540, and it contains 0x62 (the only value used in one embodiment to distinguish the vector friendly instruction format).

[0275] The second - fourth bytes (EVEX bytes 1 - 3) include a plurality of bit fields that provide specific performance.

[0276] REX field 2605 (EVEX byte 1, bits [7 - 5]) - consists of the EVEX.R bit field (EVEX byte 1, bit [7] - R), the EVEX.X bit field (EVEX byte 1, bit [6] - X), and the EVEX.B bit field (EVEX byte 1, bit [5] - B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields and are encoded in 1s complement form, i.e., ZMM0 is encoded as 1111B and ZMM15 is encoded as 0000B. The other fields of the instruction encode the three lower bits (rrr, xxx, and bbb) of the register index as known in the art such that Rrrr, Xxxx, and Bbbb can be formed by adding EVEX.R, EVEX.X, and EVEX.B.

[0277] REX' Field 2510 - This is the first part of the REX' Field 2510 and is the EVEX.R' bit field (EVEX byte 1, bit [4] - R') that is used to encode the upper 16 or lower 16 of the extended 32 - register set. In one embodiment, this bit, along with other bits indicated below, is stored in bit - reversed format to distinguish (in the well - known x86 32 - bit mode) from the BOUND instruction, whose true opcode byte is 62 but does not accept the value 11 in the MOD field (described below) in the MOD R / M field; alternative embodiments do not store this and other bits indicated in reversed format below. The value 1 is used to encode the lower 16 registers. In other words, R'Rrrr is formed by combining EVEX.R', EVEX.R, and other RRR from other fields.

[0278] Opcode Map Field 2615 (EVEX byte 1, bits [3:0] - mmmm) - Its content encodes the implicit leading opcode byte (0F, 0F 38, or 0F 3).

[0279] Data Element Width Field 2564 (EVEX byte 2, bit [7] - W) - Represented by the symbol EVEX.W. EVEX.W is used to define the granularity (size) of the data type (32 - bit data element or 64 - bit data element).

[0280] EVEX.vvvv 2620 (EVEX byte 2, bits [6:3] - vvvv) - The role of EVEX.vvvv can include the following: 1) EVEX.vvvv encodes the first source register operand, specified in inverted (1s - complement) form, and is valid for instructions with two or more source operands; 2) EVEX.vvvv encodes the destination register operand, specified in 1s - complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, this field is reserved, and should contain 1111b. Thus, the EVEX.vvvv field 2620 encodes the 4 low - order bits of the first source register specifier stored in inverted (1s - complement) form. Depending on the instruction, additional different EVEX bit fields are used to extend the specifier size to 32 registers.

[0281] EVEX.U 2568 Class Field (EVEX byte 2, bit [2] - U) - If EVEX.U = 0, it indicates class A or EVEX.U0; if EVEX.U = 1, it indicates class B or EVEX.U1.

[0282] Prefix Encoding Field 2625 (EVEX byte 2, bits [1:0] - pp) - Provides additional bits for the base operation field. In addition to providing support for legacy SSE instructions in EVEX prefix format, this also has the benefit of compressing the SIMD prefix (instead of requiring a byte to express the SIMD prefix, the EVEX prefix only requires 2 bits). In one embodiment, to support legacy SSE instructions that use SIMD prefixes (66H, F2H, F3H) in both legacy format and EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and before providing them to the PLA of the decoder at runtime, they are extended to the legacy SIMD prefix (so that the PLA can execute both the legacy and EVEX formats of these legacy instructions without modification). Although newer instructions can directly use the content of the EVEX prefix encoding field as an opcode extension, some embodiments are extended in a similar way for consistency, but allow different meanings to be specified by these legacy SIMD prefixes. Alternative embodiments can redesign the PLA to support 2-bit SIMD prefix encoding and thus do not require extension.

[0283] Alpha Field 2552 (EVEX byte 3, bit [7] - EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.Write Mask Control, and EVEX.N; also illustrated as α) - As previously described, this field is context-specific.

[0284] Beta Field 2554 (EVEX byte 3, bits [6:4] - SSS, also known as EVEX.s 2-0 , EVEX.r 2-0 , EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated as βββ) - As previously described, this field is context-specific.

[0285] REX' Field 2510 - This is the remainder of the REX' field and is the EVEX.V' bit field (EVEX byte 3, bit [3] - V') that can be used to encode the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit-reversed format. The value 1 is used to encode the lower 16 registers. In other words, V'VVVV is formed by combining EVEX.V' and EVEX.vvvv.

[0286] Write mask field 2570 (EVEX byte 3, bits [2:0] - kkk) - whose content specifies the index of the register in the write mask register as described above. In one embodiment, the specific value EVEX.kkk = 000 has a special behavior, which means that no write mask is used for that particular instruction (this can be implemented in a variety of ways, including using a write mask hardwired to all ones or hardware that bypasses the masking hardware).

[0287] The real opcode field 2630 (byte 4) is also referred to as the opcode byte. The part of the opcode is specified in this field.

[0288] The MOD R / M field 2640 (byte 5) includes the MOD field 2642, the Reg field 2644, and the R / M field 2646. As described above, the content of the MOD field 2642 differentiates between memory access and non-memory access operations. The role of the Reg field 2644 can be summarized in two cases: encoding the destination register operand or the source register operand, or being regarded as an opcode extension and not being used to encode any instruction operand. The role of the R / M field 2646 can include the following: encoding an instruction operand that references a memory address or encoding the destination register operand or the source register operand.

[0289] Scale, Index, Base (SIB) byte (byte 6) - As described above, the content of the SIB 2650 is used for memory address generation. SIB.xxx 2654 and SIB.bbb 2656 - The content of these fields has been previously mentioned regarding the register indices Xxxx and Bbbb.

[0290] Displacement field 2562A (bytes 7 - 10) - When the MOD field 2642 contains 10, bytes 7 - 10 are the displacement field 2562A, and it works the same as the legacy 32-bit displacement (disp32) and works at the byte granularity.

[0291] Displacement Factor Field 2562B (Byte 7) - When the MOD field 2642 contains 01, Byte 7 is the displacement factor field 2562B. The position of this field is the same as that of the 8-bit displacement (disp8) in the legacy x86 instruction set, which works at the byte granularity. Since disp8 is sign-extended, it can only address offsets between (address) -128 and +127 bytes; for a 64-byte cache line, disp8 uses 8 bits and can only be set to 4 truly useful values: -128, -64, 0, and 64; because a larger range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 2562B is a reinterpretation of disp8; when the displacement factor field 2562B is used, the actual displacement is determined by multiplying the content of the displacement factor field by the size of the memory operand access (N). This type of displacement is called disp8*N. This reduces the average instruction length (a single byte is used for the displacement, but with a much larger range). Such a compressed displacement assumes that the effective displacement is a multiple of the memory access granularity and thus does not require encoding of redundant low-order bits of the address offset. In other words, the displacement factor field 2562B replaces the 8-bit displacement of the legacy x86 instruction set. Therefore, the displacement of the displacement factor field 2562B is encoded in the same way as the 8-bit displacement of the x86 instruction set (so there is no change in the ModRM / SIB encoding rules), with the only exception being that disp8 is reloaded as disp8*N. In other words, there is no change in the encoding rules or encoding length, but only a change in how the displacement value is interpreted by the hardware (which needs to scale the displacement according to the size of the memory operand to obtain the address offset in bytes). The immediate number field 2572 operates as previously described.

[0292] Full Opcode Field

[0293] Figure 26B is a block diagram showing the fields that make up a particular vector-friendly instruction format 2600 of the complete opcode field 2574 according to one embodiment. Specifically, the complete opcode field 2574 includes a format field 2540, a basic operation field 2542, and a data element width (W) field 2564. The basic operation field 2542 includes a prefix encoding field 2625, an opcode mapping field 2615, and a true opcode field 2630.

[0294] Register Index Field

[0295] Figure 26Cis a block diagram illustrating the fields of a particular vector-friendly instruction format 2600 that constitutes the register index field 2544. Specifically, the register index field 2544 includes a REX field 2605, a REX' field 2610, a MODR / M.reg field 2644, a MODR / M.r / m field 2646, a VVVV field 2620, an xxx field 2654, and a bbb field 2656.

[0296] Extended Op Field

[0297] Figure 26D is a block diagram illustrating the fields of a particular vector-friendly instruction format 2600 that constitutes the extended operation field 2550. When the class (U) field 2568 contains 0, it represents EVEX.U0 (class A 2568A); when it contains 1, it represents EVEX.U1 (class B 2568B). When U = 0 and the MOD field 2642 contains 11 (indicating no memory access operation), the alpha field 2552 (EVEX byte 3, bit [7] - EH) is interpreted as the rs field 2552A. When the rs field 2552A contains 1 (rounding 2552A.1), the beta field 2554 (EVEX byte 3, bits [6:4] - SSS) is interpreted as the rounding control field 2554A. The rounding control field 2554A includes a one-bit SAE field 2556 and a two-bit rounding operation field 2558. When the rs field 2552A contains 0 (data transformation 2552A.2), the beta field 2554 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a three-bit data transformation field 2554B. When U = 0 and the MOD field 2642 contains 00, 01, or 10 (indicating a memory access operation), the beta field 2552 (EVEX byte 3, bit [7] - EH) is interpreted as the eviction hint (EH) field 2552B, and the beta field 2554 (EVEX byte 3, bits [6:4] - SSS) is interpreted as a three-bit data manipulation field 2554C.

[0298] When U = 1, the alpha field 2552 (EVEX byte 3, bit [7] - EH) is interpreted as the write mask control (Z) field 2552C. When U = 1 and the MOD field 2642 contains 11 (indicating no memory access operation), a portion of the beta field 2554 (EVEX byte 3, bit [4] - S0) is interpreted as the RL field 2557A; when it contains 1 (rounding 2557A.1), the remainder of the beta field 2554 (EVEX byte 3, bits [6 - 5] - S 2-1) is interpreted as a rounding operation field 2559A, and when the RL field 2557A contains 0 (VSIZE 2557A.2), the beta field 2554 (EVEX byte 3, bits [6-5]-S 2-1 ) The remainder of is interpreted as a vector length field 2559B (EVEX byte 3, bits [6-5]-L 1-0 ). When U = 1 and the MOD field 2642 contains 00, 01, or 10 (indicating a memory access operation), the beta field 2554 (EVEX byte 3, bits [6:4]-SSS) is interpreted as a vector length field 2559B (EVEX byte 3, bits [6-5]-L 1-0 ) and a broadcast field 2557B (EVEX byte 3, bit [4]-B).

[0299] Exemplary Register Architecture

[0300] Figure 27 is a block diagram of a register architecture 2700 according to one embodiment. In the illustrated embodiment, there are 32 vector registers 2710 that are 512 bits wide; these registers are referred to as zmm0 through zmm31. The lower 256 bits of the lower 16 zmm registers are overlaid on the registers ymm0-16. The lower 128 bits of the lower 16 zmm registers (the lower 128 bits of the ymm registers) are overlaid on the registers xmm0-15. A particular vector-friendly instruction format 2600 operates on these overlaid register files as illustrated in the following table.

[0301]

[0302] In other words, the vector length field 2559B selects between a maximum length and one or more other shorter lengths, where each such shorter length is half of the previous length; and instruction templates without a vector length field 2559B operate on the maximum vector length. Additionally, in one embodiment, the class B instruction templates of the particular vector-friendly instruction format 2600 operate on packed or scalar single / double precision floating point data as well as packed or scalar integer data. Scalar operations are performed on the lowest-order data element lanes in the zmm / ymm / xmm registers; depending on the embodiment, the higher-order data element lanes remain the same as before the instruction or are set to zero.

[0303] Write Mask Register 2715 - In the illustrated embodiment, there are eight write mask registers (k0 through k7), each 64 bits in size. In an alternative embodiment, the write mask register 2715 is 16 bits in size. As previously mentioned, in one embodiment, vector mask register k0 cannot be used as a write mask; when the encoding that normally indicates k0 is used for a write mask, it selects a hard - wired write mask of 0xFFFF, effectively disabling write masking for that instruction.

[0304] General - Purpose Registers 2725 - In the illustrated embodiment, there are sixteen 64 - bit general - purpose registers that are used with existing x86 addressing modes to address memory operands. These registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0305] Scalar Floating - Point Stack Register File (x87 Stack) 2745, which aliases the MMX Packed Integer Flat Register File 2750 - In the illustrated embodiment, the x87 stack is an eight - element stack used to perform scalar floating - point operations on 32 / 64 / 80 - bit floating - point data using the x87 instruction set extensions; while the MMX registers are used to operate on 64 - bit packed integer data and to hold operands for certain operations performed between the MMX and XMM registers.

[0306] Alternative embodiments may use wider or narrower registers. Additionally, alternative embodiments may include more, fewer, or different register files and registers.

[0307] Exemplary Core Architecture, Processor, and Computer Architecture

[0308] Processor cores can be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores can include: 1) general-purpose in-order cores intended for general computing; 2) high-performance general-purpose out-of-order cores intended for general computing; 3) specialized cores primarily intended for graphics and / or scientific (throughput) computing. Implementations of different processors can include: 1) a CPU including one or more general-purpose in-order cores intended for general computing and / or one or more general-purpose out-of-order cores intended for general computing; and 2) a coprocessor including one or more specialized cores primarily intended for graphics and / or scientific (throughput). Such different processors result in different computer system architectures, which can include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die within the same package as the CPU; 3) the coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as specialized logic (such as integrated graphics and / or scientific (throughput) logic), or as a specialized core); and 4) a system-on-chip, which can include on the same die the described CPU (sometimes referred to as the (one or more) application core or (one or more) application processor), the aforementioned coprocessor, and additional functionality. Exemplary core architectures are described next, followed by exemplary processor and computer architectures.

[0309] Exemplary Core Architecture

[0310] Ordered and Unordered Core Block Diagrams

[0311] Figure 28A is a block diagram illustrating an exemplary in-order pipeline and an exemplary register renaming, out-of-order issue / execution pipeline, both according to an embodiment. Figure 28B is a block diagram illustrating an exemplary embodiment of an in-order architecture core to be included in a processor and an exemplary register renaming, out-of-order issue / execution architecture core, both according to an embodiment. Figure 28A The solid blocks in - B illustrate the in-order pipeline and in-order core, while the optional addition of the dashed blocks illustrates the register renaming, out-of-order issue / execution pipeline and core. Given that the in-order aspects are a subset of the out-of-order aspects, the out-of-order aspects will be described.

[0312] In Figure 28A processor pipeline 2800 includes a fetch stage 2802, a length decoding stage 2804, a decoding stage 2806, an allocation stage 2808, a renaming stage 2810, a scheduling (also referred to as dispatch or issue) stage 2812, a register read / memory read stage 2814, an execution stage 2816, a write-back / memory write stage 2818, an exception handling stage 2822, and a commit stage 2824.

[0313] Figure 28B A processor core 2890 is shown that includes a front-end unit 2830 coupled to an execution engine unit 2850, and both are coupled to a memory unit 2870. The core 2890 can be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core 2890 can be a specialized core, such as, for example, a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, and so on.

[0314] The front-end unit 2830 includes a branch prediction unit 2832 coupled to an instruction cache unit 2834, the instruction cache unit 2834 is coupled to an instruction translation lookaside buffer (TLB) 2836, the instruction translation lookaside buffer (TLB) 2836 is coupled to an instruction fetch unit 2838, and the instruction fetch unit 2838 is coupled to a decoding unit 2840. The decoding unit 2840 (or decoder) can decode instructions and generate, as output, one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals that are decoded from the original instructions, or that otherwise reflect or are derived from the original instructions. The decoding unit 2840 can be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), and the like. In one embodiment, the core 2890 includes a microcode ROM or other medium that stores microcode for certain macroinstructions (e.g., in the decoding unit 2840 or otherwise within the front-end unit 2830). The decoding unit 2840 is coupled to a rename / allocator unit 2852 in the execution engine unit 2850.

[0315] The execution engine unit 2850 includes a rename / allocator unit 2852 coupled to a retirement unit 2854 and a set of one or more scheduler units 2856. The (one or more) scheduler units 2856 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. The (one or more) scheduler units 2856 are coupled to the (one or more) physical register file(s) unit(s) 2858. Each of the (one or more) physical register file units 2858 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer which is the address of the next instruction to be executed), and the like. In one embodiment, the (one or more) physical register file units 2858 include a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architectural vector registers, vector mask registers, and general-purpose registers. The (one or more) physical register file(s) unit(s) 2858 are overlapped by the retirement unit 2854 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using the (one or more) reorder buffers and the (one or more) retirement register files; using the (one or more) future files, the (one or more) history buffers, and the (one or more) retirement register files; using register maps and register pools, etc.). The retirement unit 2854 and the (one or more) physical register file(s) unit(s) 2858 are coupled to the (one or more) execution clusters 2860. The (one or more) execution clusters 2860 include a set of one or more execution units 2862 and a set of one or more memory access units 2864. The execution units 2862 may perform various operations (such as shifts, additions, subtractions, multiplications) and are performed on various types of data (e.g., scalar floating points, packed integers, packed floating points, vector integers, vector floating points). While some embodiments may include many execution units dedicated to specific functions or function sets, other embodiments may include only one execution unit or multiple execution units that all perform all functions. The (one or more) scheduler units 2856, the (one or more) physical register file(s) unit(s) 2858, and the (one or more) execution clusters 2860 are shown as potentially plural because certain embodiments create separate pipelines for certain types of data / operations (e.g., a scalar integer pipeline, a scalar floating point / packed integer / packed floating point / vector integer / vector floating point pipeline, and / or a memory access pipeline that each have their own scheduler unit, (one or more) physical register file units, and / or execution cluster, and in the case of a separate memory access pipeline, certain embodiments are implemented where only the execution cluster of this pipeline has the (one or more) memory access units 2864).It should also be understood that, in the case of using separate pipelines, one or more of these pipelines can be out-of-order issue / execution while the rest are in-order.

[0316] A set of memory access units 2864 is coupled to a memory unit 2870, which includes a data TLB unit 2872 coupled to a data cache unit 2874, and the data cache unit 2874 is coupled to a level 2 (L2) cache unit 2876. In one exemplary embodiment, the memory access units 2864 can include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 2872 in the memory unit 2870. An instruction cache unit 2834 is further coupled to the level 2 (L2) cache unit 2876 in the memory unit 2870. The L2 cache unit 2876 is coupled to one or more other levels of cache and ultimately to the main memory.

[0317] As an example, an exemplary register renaming, out-of-order issue / execution core architecture can implement the pipeline 2800 as follows: 1) Instruction fetch 2838 performs the fetch and length decoding stages 2802 and 2804; 2) The decode unit 2840 performs the decode stage 2806; 3) The rename / allocator unit 2852 performs the allocation stage 2808 and the rename stage 2810; 4) The (one or more) scheduler unit(s) 2856 performs the schedule stage 2812; 5) The (one or more) physical register file(s) unit(s) 2858 and the memory unit 2870 perform the register read / memory read stage 2814; The execution cluster 2860 performs the execution stage 2816; 6) The memory unit 2870 and the (one or more) physical register file(s) unit(s) 2858 perform the write-back / memory write stage 2818; 7) Each unit may be involved in the exception handling stage 2822; and 8) The retirement unit 2854 and the (one or more) physical register file(s) unit(s) 2858 perform the commit stage 2824.

[0318] The core 2890 can support one or more instruction sets (e.g., the x86 instruction set (with some extensions that have been added with updated versions); the MIPS instruction set of MIPS Technologies in Sunnyvale, California; the ARM instruction set of ARM Holdings in Sunnyvale, California (with optional additional extensions such as NEON)), including the (one or more) instructions described herein. In one embodiment, the core 2890 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0319] It should be understood that the core can support multithreading (two or more parallel sets of executing operations or threads), and can do so in a variety of ways, including time-sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads, the physical core being simultaneously multithreaded), or combinations thereof (e.g., time-sliced fetching and decoding, and subsequent simultaneous multithreading such as in hyperthreading technology).

[0320] Although register renaming has been described in the context of out-of-order execution, it should be understood that register renaming can be used in an in-order architecture. Although the illustrated embodiments of the processor also include separate instruction and data cache units 2834 / 2874 and a shared L2 cache unit 2876, alternative embodiments can have a single internal cache for both instructions and data, such as, for example, a level 1 (L1) internal cache or a multi-level internal cache. In some embodiments, the system can include a combination of an internal cache and an external cache outside the core and / or the processor. Alternatively, all caches can be outside the core and / or the processor.

[0321] Specific Exemplary Ordered Core Architecture

[0322] Figure 29A -FIG. B illustrates a block diagram of a more specific exemplary in-order core architecture, which would be one of several logical blocks (including other cores of the same type and / or different types) in a chip. Depending on the application, the logical blocks communicate with some fixed function logic, a memory I / O interface, and other necessary I / O logic via a high bandwidth interconnect network (e.g., a ring network).

[0323] Figure 29A is a block diagram of a single processor core according to an embodiment, and its connection to the on-die interconnect network 2902 and its connection to a local subset 2904 of its level 2 (L2) cache. In one embodiment, the instruction decoder 2900 supports the x86 instruction set with packed data instruction set extensions. The L1 cache 2906 allows low latency access to cache memory into scalar and vector units. Although in one embodiment (for simplicity of design), the scalar unit 2908 and the vector unit 2910 use separate register sets (scalar registers 2912 and vector registers 2914, respectively), and the data passed between them is written to memory and then read back from the level 1 (L1) cache 2906, alternative embodiments can use different methods (e.g., using a single register set or including a communication path that allows data to be passed between two register files without being written and read back).

[0324] The local subset 2904 of the L2 cache is part of the global L2 cache, which is partitioned into separate local subsets, one for each processor core. Each processor core has a direct access path to its own local subset 2904 of the L2 cache. Data read by a processor core is stored in its L2 cache subset 2904 and can be accessed quickly, in parallel with other processor cores accessing their own local L2 cache subsets. Data written by a processor core is stored in its own L2 cache subset 2904 and, if necessary, flushed from other subsets. The ring network ensures the consistency of shared data. The ring network is bidirectional to allow agents such as processor cores, L2 caches, and other logic blocks to communicate with each other within the chip. Each ring data path is 1012 bits wide in each direction.

[0325] Figure 29B is according to an embodiment Figure 29A is an expanded view of a portion of the processor core in Figure 29B includes a portion of the L1 data cache 2906A that includes the L1 cache 2904, and more details regarding the vector unit 2910 and the vector registers 2914. Specifically, the vector unit 2910 is a 16-wide vector processing unit (VPU) (see the 16-wide ALU 2928) that executes one or more of integer, single-precision floating, and double-precision floating instructions. The VPU supports dispatching register inputs with the dispatching unit 2920, digital conversion with the digital conversion units 2922A-B, and replicating memory inputs with the replication unit 2924. The write mask register 2926 allows prediction of the resulting vector writes.

[0326] Figure 30 is a block diagram of a processor 3000 that can have more than one core, can have an integrated memory controller, and can have integrated graphics components, according to an embodiment. Figure 30 The solid blocks in

[0327] Accordingly, different implementations of the processor 3000 can include: 1) a CPU with dedicated logic 3008, which is integrated graphics and / or scientific (throughput) logic (which can include one or more cores), and the cores 3002A-N are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, a combination of both); 2) a coprocessor with cores 3002A-N, which are a large number of dedicated cores primarily intended for graphics and / or scientific (throughput); and 3) a coprocessor with cores 3002A-N, which are a large number of general-purpose in-order cores. Accordingly, the processor 3000 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as, for example, a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, and so on. The processor can be implemented on one or more chips. The processor 3000 can be part of one or more substrates, or the processor 3000 can be implemented on one or more substrates using any of a variety of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

[0328] The memory hierarchy includes one or more levels of on-core caches, a set of one or more shared cache units 3006, and external memory (not shown) coupled to the set of integrated memory controller units 3014. The set of shared cache units 3006 can include one or more mid-level caches, such as a level 2 (L2), level 3 (L3), level 4 (L4), or other level cache, a last-level cache (LLC), and / or a combination thereof. While in one embodiment, the ring-based interconnect unit 3012 interconnects the dedicated logic 3008 (integrated graphics logic is an example of dedicated logic and is also referred to as dedicated logic herein), the set of shared cache units 3006, and the system agent unit 3010 / (one or more) integrated memory controller units 3014, alternative embodiments can use any number of well-known techniques for interconnecting such units. In one embodiment, coherence is maintained between one or more cache units 3006 and the cores 3002A-N.

[0329] In some embodiments, one or more of the cores 3002A-N have the ability to be multithreaded. The system agent 3010 includes those components that coordinate and operate the cores 3002A-N. The system agent unit 3010 can include, for example, a power control unit (PCU) and a display unit. The PCU can be or can include the components and logic required to regulate the power states of the cores 3002A-N and the dedicated logic 3008. The display unit is used to drive one or more externally connected displays.

[0330] In terms of the architectural instruction set, cores 3002A-N can be homogeneous or heterogeneous; that is, two or more of cores 3002A-N may be capable of executing the same instruction set, while other cores may only be capable of executing a subset of the instruction set or executing a different instruction set.

[0331] Exemplary Computer Architecture

[0332] Figure 31-34 is a block diagram of an exemplary computer architecture. Other system designs and configurations known in the art for laptop computers, desktop computers, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, cellular telephones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a wide variety of systems or electronic devices that can incorporate a processor and / or other execution logic as disclosed herein are generally suitable.

[0333] Now referring to Figure 31 , shown is a block diagram of a system 3100 according to an embodiment of the present invention. System 3100 may include one or more processors 3110, 3115 coupled to a controller hub 3120. In one embodiment, controller hub 3120 includes a Graphics Memory Controller Hub (GMCH) 3190 and an Input / Output Hub (IOH) 3150 (which may be on separate chips); GMCH 3190 includes a memory and a graphics controller, to which memory 3140 and a coprocessor 3145 are coupled; IOH 3150 couples input / output (I / O) devices 3160 to GMCH 3190. Alternatively, one or both of the memory and graphics controllers are integrated into the processor (as described herein), memory 3140 and coprocessor 3145 are directly coupled to processor 3110, and controller hub 3120 is directly coupled to IOH 3150 in a single chip.

[0334] In Figure 31 , the optional nature of additional processor 3115 is indicated by dashed lines. Each of processors 3110, 3115 may include one or more of the processing cores described herein and may be a version of processor 3000.

[0335] The memory 3140 can be, for example, a dynamic random access memory (DRAM), a phase change memory (PCM), or a combination of both. For at least one embodiment, the controller hub 3120 communicates with the processor(s) 3110, 3115 via a multi-drop bus such as a front side bus (FSB), a point-to-point interface such as a QuickPath Interconnect (QPI), or a similar connection 3195.

[0336] In one embodiment, the coprocessor 3145 is a special-purpose processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like. In one embodiment, the controller hub 3120 may include an integrated graphics accelerator.

[0337] There can be various differences between the physical resources 3110, 3115 in terms of a series of value metrics including architecture characteristics, microarchitecture characteristics, thermal characteristics, power consumption characteristics, and so on.

[0338] In one embodiment, the processor 3110 executes instructions that control general types of data processing operations. Coprocessor instructions can be embedded in the instructions. The processor 3110 recognizes these coprocessor instructions as being of a type that should be executed by the attached coprocessor 3145. Accordingly, the processor 3110 issues these coprocessor instructions (or control signals representing the coprocessor instructions) to the coprocessor 3145 on a coprocessor bus or other interconnect. The coprocessor(s) 3145 receives and executes the received coprocessor instructions.

[0339] Now referring to Figure 32 , shown is a block diagram of a first more specific exemplary system 3200 in accordance with an embodiment of the present invention. As Figure 32 shown, the multi-processor system 3200 is a point-to-point interconnect system and includes a first processor 3270 and a second processor 3280 coupled via a point-to-point interconnect 3250. Each of the processors 3270 and 3280 can be a version of the processor 3000. In one embodiment, the processors 3270 and 3280 are the processors 3110 and 3115 respectively, and the coprocessor 3238 is the coprocessor 3145. In another embodiment, the processors 3270 and 3280 are the processor 3110, the coprocessor 3145 respectively.

[0340] Processors 3270 and 3280 are shown as including integrated memory controller (IMC) units 3272 and 3282, respectively. Processor 3270 also includes point-to-point (P-P) interfaces 3276 and 3278 as part of its bus controller unit; similarly, the second processor 3280 includes P-P interfaces 3286 and 3288. Processors 3270, 3280 can exchange information via point-to-point (P-P) interfaces 3250, using P-P interface circuits 3278, 3288. As Figure 32 shown, IMCs 3272 and 3282 couple the processors to respective memories, namely memories 3232 and 3234, which may be portions of main memories locally attached to the respective processors.

[0341] Both processors 3270, 3280 can exchange information with chipset 3290 via point-to-point interface circuits 3276, 3294, 3286, 3298, via a single P-P interface 3252, 3254. Chipset 3290 can optionally exchange information with coprocessor 3238 via high performance interface 3292. In one embodiment, coprocessor 3238 is a special-purpose processor, such as, for example, a high throughput MIC processor, a network or communication processor, a compression engine, a graphics processor, a GPGPU, an embedded processor, and the like.

[0342] A shared cache (not shown) may be included in either processor, or outside of both processors but still connected to the processors via a P-P interconnect, such that if a processor is placed in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0343] Chipset 3290 can be coupled to a first bus 3216 via interface 3296. In one embodiment, first bus 3216 can be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I / O interconnect bus, although the scope of the present invention is not so limited.

[0344] As in Figure 32As shown in, various I / O devices 3214 can be coupled to a first bus 3216, along with a bus bridge 3218 that couples the first bus 3216 to a second bus 3220. In one embodiment, one or more additional processors 3215, such as a coprocessor, a high-throughput MIC processor, a GPGPU, an accelerator (such as, for example, a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array, or any other processor, are coupled to the first bus 3216. In one embodiment, the second bus 3220 can be a low pin count (LPC) bus. In one embodiment, various devices can be coupled to the second bus 3220, which includes, for example, a keyboard and / or mouse 3222, a communication device 3227, and a storage unit 3228 such as a disk drive or other mass storage device, which can include instructions / code and data 3230. Additionally, audio I / O 3224 can be coupled to the second bus 3220. Note that other architectures are possible. For example, instead of Figure 32 a point-to-point architecture, the system can implement a multi-drop bus or other such architecture.

[0345] Now referring to Figure 33 , shown is a block diagram of a second more specific exemplary system 3300 according to an embodiment of the present invention. Figure 32 And 33 similar elements in Figure 33 have similar reference numerals, and certain aspects of Figure 32 have been omitted to avoid obscuring other aspects of Figure 33 .

[0346] Figure 33 Illustrated is that processors 3270, 3280 can respectively include integrated memory and I / O control logic ("CL") 3372 and 3382. Thus, CL 3372, 3282 includes an integrated memory controller unit and includes I / O control logic. Figure 33 Illustrated is that not only memories 3232, 3234 are coupled to CL 3372, 3382, but also I / O devices 3314 are coupled to control logic 3372, 3382. Legacy I / O devices 3315 are coupled to a chipset 3290.

[0347] Now referring to Figure 34 , shown is a block diagram of an SoC 3400 according to an embodiment of the present invention. Figure 30 Similar elements in Figure 34In [the figure], one or more interconnect units 3402 are coupled to: an application processor 3410, which includes a set of one or more cores 3002A-N (which includes cache units 3004A-N) and one or more shared cache units 3006; a system agent unit 3010; one or more bus controller units 3016; one or more integrated memory controller units 3014; a set of one or more coprocessors 3420, which may include integrated graphics logic, an image processor, an audio processor, and a video processor; a static random access memory (SRAM) unit 3430; a direct memory access (DMA) unit 3432; and a display unit 3440 for coupling to one or more external displays. In one embodiment, one or more coprocessors 3420 include: dedicated processors such as, for example, a network or communication processor, a compression engine, a GPGPU, a high throughput MIC processor, an embedded processor, and the like.

[0348] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation methods. An embodiment may be implemented as a computer program or program code executed on a programmable system that includes at least one processor, a storage system (including volatile and nonvolatile memory and / or storage units), at least one input device, and at least one output device.

[0349] Program code such as Figure 32 the code 3230 illustrated in [the figure] may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in a known manner. For the purposes of this application, a processing system includes any system having a processor such as, for example: a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), or a microprocessor.

[0350] The program code may be implemented in a high-level procedural programming language or an object-oriented programming language to communicate with the processing system. If desired, the program code may also be implemented in assembly language or machine language. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled language or an interpreted language.

[0351] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which when read by the machine cause the machine to fabricate the logic for performing the techniques described herein. Such a representation, referred to as an “IP core,” may be stored on a tangible machine-readable medium and provided to various customers or manufacturing facilities to be loaded into a manufacturing machine that actually fabricates the logic or processor.

[0352] Such a machine-readable storage medium may include, without limitation, a non-transitory tangible arrangement of articles manufactured or formed by a machine or device, including: storage media such as hard disks, any other type of disk, including floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM), random access memory (RAM) (such as dynamic random access memory (DRAM), static random access memory (SRAM)), erasable programmable read-only memory (EPROM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change memory (PCM), magnetic cards or optical cards, or any other type of medium for storing electronic instructions.

[0353] Accordingly, embodiments also include a non-transitory tangible machine-readable medium that contains instructions or contains design data (such as a hardware description language (HDL)) that defines the structures, circuits, devices, processors, and / or system features described herein. Such embodiments may also be referred to as program products.

[0354] Emulation (Including Binary Translation, Code Morphing, etc.)

[0355] In some cases, an instruction converter may be used to convert instructions from a source instruction set to a target instruction set. For example, the instruction converter may translate (e.g., using static binary translation, dynamic binary translation including dynamic compilation), transform, emulate, or otherwise convert the instructions into one or more other instructions to be processed by the core. The instruction converter may be implemented in software, hardware, firmware, or a combination thereof. The instruction converter may be on the processor, under the processor, or partly on the processor and partly under the processor.

[0356] Figure 35 is a block diagram that illustrates contrasting the use of a software instruction converter to convert binary instructions in a source instruction set to binary instructions in a target instruction set. In the illustrated embodiment, the instruction converter is a software instruction converter, although alternatively the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 35It is shown that a program using a high-level language 3502 can be compiled using an x86 compiler 3504 to generate x86 binary code 3506, which can be natively executed by a processor 3516 having at least one x86 instruction set core. The processor 3516 having at least one x86 instruction set core represents any processor that can perform substantially the same functions as an Intel processor having at least one x86 instruction set core, either by compatibly executing or otherwise processing (1) a large portion of the instruction set of the Intel x86 instruction set core or (2) an application or other software in a version of object code targeted to run on an Intel processor having at least one x86 instruction set core, so as to achieve substantially the same results as an Intel processor having at least one x86 instruction set core. The x86 compiler 3504 represents a compiler operable to generate x86 binary code 3506 (e.g., object code), which can be executed on a processor 3516 having at least one x86 instruction set core with or without additional linking processing. Similarly, Figure 35 It is shown that a program using a high-level language 3502 can be compiled using a replacement instruction set compiler 3508 to generate replacement instruction set binary code 3510, which can be natively executed by a processor 3514 not having at least one x86 instruction set core (e.g., a processor having a core that executes the MIPS instruction set of MIPS Technologies of Sunnyvale, California and / or the ARM instruction set of ARM Holdings of Sunnyvale, California). An instruction converter 3512 is used to convert the x86 binary code 3506 into code that can be natively executed by a processor 3514 not having an x86 instruction set core. The converted code may not be the same as the replacement instruction set binary code 3510 because it is difficult to make an instruction converter that can do so; however, the converted code will perform general operations and be composed of instructions from the replacement instruction set. Thus, the instruction converter 3512 represents software, firmware, hardware, or a combination thereof that allows a processor or other electronic device not having an x86 instruction set processor or core to execute the x86 binary code 3506 through emulation, simulation, or any other process.

[0357] Additional Examples

[0358] Example 1 provides an exemplary processor, including: an acquisition circuit to acquire an instruction having a field that specifies an opcode and the positions of an M×N destination matrix having single-precision elements, an M×K first source matrix, and a K×N second source, where the elements of the specified source matrices include a pair of 16-bit floating-point values, and the opcode is to instruct an execution circuit that for each element (m, n) of the specified destination matrix, it is to convert K pairs of elements from row m of the specified first source matrix and K pairs of elements from column n of the specified second source matrix into single precision, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then add those products to a sum of even products and a sum of odd products respectively with the previous content of element (m, n); a decoding circuit to decode the acquired instruction; and an execution circuit to respond to the decoded instruction as specified by the opcode.

[0359] Example 2 includes the substance of the exemplary processor of Example 1, where the 16-bit floating-point format is bfloat16 or binary16, and this format is to be specified by the instruction.

[0360] Example 3 includes the substance of the exemplary processor of Example 1, where M, N, and K are specified by the instruction or are programmed using a matrix configuration instruction before acquiring the instruction.

[0361] Example 4 includes the substance of the exemplary processor of Example 1, where the execution circuit further saturates the execution result if necessary.

[0362] Example 5 includes the substance of the exemplary processor of Example 1, where the instruction further specifies a write mask including M×N bits, each bit to control whether to mask the corresponding element of the specified destination matrix, and the masked elements of the destination matrix are to be set to zero or merged.

[0363] Example 6 includes the substance of the exemplary processor of Example 1, where the specified source and destination matrix positions are both in one of a register set and multiple memory locations to represent the matrices.

[0364] Example 7 includes the substance of the exemplary processor of Example 1, where the execution circuit is further to generate a fault when a fault condition occurs, and the fault condition includes one or more of the following: one or more of the first and second specified source matrices have a VALID parameter that is not set to TRUE; the specified destination matrix has a number of rows different from the number of rows of the specified first source matrix; the specified destination matrix has a number of columns different from the number of columns of the specified first source matrix; and the size of one or more of the specified first source, second source, and destination matrices exceeds a maximum size, where the size includes the number of rows and columns of the matrix.

[0365] Example 8 provides an exemplary method that includes: using an acquisition circuit to acquire an instruction having a field that specifies an opcode and the locations of an M×N destination matrix having single-precision elements, an M×K first source matrix, and a K×N second source matrix, where the specified source matrices have elements that include a pair of 16-bit floating-point values, the opcode is to direct an execution circuit to, for each element (m, n) of the specified destination matrix, convert K pairs of elements from row m of the specified first source matrix and K pairs of elements from column n of the specified second source matrix to single precision, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then accumulate those products with the previous contents of the elements into a sum of even products and a sum of odd products respectively; using a decoding circuit to decode the acquired instruction, and utilizing the execution circuit to respond to the decoded instruction as specified by the opcode.

[0366] Example 9 includes the substance of the exemplary method of Example 8, where the 16-bit floating-point format is bfloat16 or binary16, and the format is to be specified by the instruction.

[0367] Example 10 includes the substance of the exemplary method of Example 8, where M, N, and K are specified by the instruction, or are programmed using matrix configuration instructions prior to acquiring the instruction.

[0368] Example 11 includes the substance of the exemplary method of Example 8, where the execution circuit further saturates the execution result when necessary.

[0369] Example 12 includes the substance of the exemplary method of Example 8, where the instruction further specifies a write mask that includes M×N bits, each bit to control whether to mask the corresponding element of the specified destination matrix, and where the masked elements of the destination matrix are to be set to zero or merged.

[0370] Example 13 includes the substance of the exemplary method of Example 8, where the specified source and destination matrix locations are each in one of a register set and a plurality of memory locations to represent the matrices.

[0371] Example 14 includes the substance of the exemplary method of Example 8, where the execution circuit is further to generate a fault when a fault condition occurs, the fault condition including one or more of the following: one or more of the first and second specified source matrices have a VALID parameter that is not set to TRUE; the specified destination matrix has a number of rows different from the number of rows of the specified first source matrix; the specified destination matrix has a number of columns different from the number of columns of the specified first source matrix; and the size of one or more of the specified first source, second source, and destination matrices exceeds a maximum size, the size including the number of matrix rows and columns.

[0372] Example 15 provides an exemplary system including a memory and a processor. The processor includes: an acquisition circuit configured to acquire an instruction having fields that specify an opcode and the locations of an M×N destination matrix having single-precision elements, an M×K first source matrix, and a K×N second source matrix. The specified source matrices have elements including a pair of 16-bit floating-point values. The opcode is to instruct an execution circuit that for each element (m, n) of the specified destination matrix, it is to convert K pairs of elements from row m of the specified first source matrix and K pairs of elements from column n of the specified second source matrix to single precision, multiply the converted even elements from the two specified source matrices (tiles), and multiply the converted odd elements from the two specified source matrices (tiles) separately, and then add those products to the previous contents of element (m, n) separately to form a sum of the even products and a sum of the odd products; a decoding circuit configured to decode the acquired instruction; and an execution circuit configured to respond to the decoded instruction as specified by the opcode.

[0373] Example 16 includes the substance of the exemplary system of Example 15, wherein the 16-bit floating-point format is bfloat16 or binary16, and this format is to be specified by the instruction.

[0374] Example 17 includes the substance of the exemplary system of Example 15, wherein M, N, and K are specified by the instruction or programmed using matrix configuration instructions before acquiring the instruction.

[0375] Example 18 includes the substance of the exemplary system of Example 15, wherein the execution circuit further saturates the execution result if necessary.

[0376] Example 19 includes the substance of the exemplary system of Example 15, wherein the instruction further specifies a write mask including M×N bits, each bit being to control whether to mask the corresponding element of the specified destination matrix, and the masked elements of the destination matrix are to be set to zero or merged.

[0377] Example 20 includes the substance of the exemplary system of Example 15, wherein the specified source and destination matrix locations are both in one of a register set and multiple memory locations to represent the matrices.

Claims

1. A processing unit, comprising: An acquisition circuit for acquiring instructions; A decoding circuit for decoding the instructions, the instructions having an opcode, a first field, a second field, and a third field, the first field being used to specify a first storage location of a plurality of data elements corresponding to a first matrix having 32-bit single-precision floating-point data elements of M rows by N columns, the second field being used to specify a second storage location of a plurality of data elements corresponding to a second matrix having 16-bit floating-point data elements of bfloat16 format of M rows by K columns, and the third field being used to specify a third storage location of a plurality of data elements corresponding to a third matrix having 16-bit floating-point data elements of bfloat16 format of K rows by N columns; And An execution circuit coupled to the decoding circuit, the execution circuit being configured to perform an operation corresponding to the instruction for each row m of the M rows of the second matrix and for each column n of the N columns of the third matrix to: Generate a dot product from K 16-bit floating-point data elements corresponding to row m of the second matrix and K 16-bit floating-point data elements corresponding to column n of the third matrix; Accumulate the dot product with a 32-bit single-precision floating-point data element corresponding to row m of the M rows of the first matrix and corresponding to column n of the N columns to generate a result 32-bit single-precision floating-point data element; And Store the result 32-bit single-precision floating-point data element in a position corresponding to row m and column n of the first storage location of the first matrix, Wherein the execution circuit is configured to perform an operation corresponding to the instruction to process non-normal values of the second matrix and the third matrix as zero.

2. The processing unit according to claim 1, further comprising a control register for specifying a rounding mode, wherein, Generating the dot product and accumulating the dot product each include: applying a single rounding mode regardless of the rounding mode specified by the control register.

3. The processing unit according to claim 2, wherein, The processing unit will not consult the control register due to the instruction.

4. The processing unit according to any one of claims 1 to 3, wherein, The processing unit will not update the control register due to the instruction.

5. The processing unit according to any one of claims 1 to 3, wherein, The processing unit will not indicate an exception due to the instruction.

6. The processing unit according to any one of claims 1 to 3, wherein, The execution circuit is configured to perform an operation corresponding to the instruction to clear non-normal value dumps to zero.

7. The processing unit according to any one of claims 1 to 3, wherein, The M rows of the second matrix and the N columns of the third matrix are equal in number.

8. The processing unit according to any one of claims 1 to 3, wherein, The first storage location, the second storage location, and the third storage location are in a 128-bit vector register.

9. The processing unit according to any one of claims 1 to 3, wherein, Each dot product is a 32-bit single-precision floating-point dot product.

10. The processing unit according to any one of claims 1 to 3, further comprising: A branch prediction circuit; A register renaming circuit; And A scheduler circuit for scheduling the decoded instructions for execution.

11. The processing unit according to any one of claims 1 to 3, wherein, The processing unit is a general-purpose central processing unit core.

12. The processing unit according to any one of claims 1 to 3, wherein, The processing unit is a reduced instruction set computing RISC core.

13. The processing unit according to claim 2, wherein, The single rounding mode is fixed for the instruction.

14. A system-on-chip, the system-on-chip comprising: A memory controller; And A general-purpose central processing unit core, coupled to the memory controller, the general-purpose central processing unit core being the processing unit according to any one of claims 1 to 13.

15. The system on a chip as claimed in claim 14, further comprising one or more of the following: a network processor coupled to the general-purpose central processing unit core, a coprocessor coupled to the general-purpose central processing unit core, and an image processor coupled to the general-purpose central processing unit core.

16. A system for processing data, comprising: a memory; and a general-purpose central processing unit core, coupled to the memory, the general-purpose central processing unit core being a processing unit as claimed in any one of claims 1 to 13.

17. The system as claimed in claim 16, further comprising one or more of the following: a mass storage device coupled to the general-purpose central processing unit core, a peripheral component interconnect PCI express bus coupled to the general-purpose central processing unit core, a communication device coupled to the general-purpose central processing unit core.

18. A method for processing data in a processing unit, comprising: obtaining an instruction; decoding the instruction, the instruction having an opcode, a first field, a second field, and a third field, the first field specifying a first storage location of a plurality of data elements corresponding to a first matrix having 32-bit single-precision floating-point data elements of M rows by N columns, the second field specifying a second storage location of a plurality of data elements corresponding to a second matrix having 16-bit floating-point data elements of M rows by K columns in bfloat16 format, the third field specifying a third storage location of a plurality of data elements corresponding to a third matrix having 16-bit floating-point data elements of K rows by N columns in bfloat16 format; for each row m of the M rows of the second matrix and for each column n of the N columns of the third matrix, performing an operation corresponding to the instruction: generating a dot product from K 16-bit floating-point data elements corresponding to row m of the second matrix and K 16-bit floating-point data elements corresponding to column n of the third matrix; accumulating the dot product with a 32-bit single-precision floating-point data element corresponding to row m of the M rows of the first matrix and column n of the N columns to generate a result 32-bit single-precision floating-point data element; and storing the result 32-bit single-precision floating-point data element in a location corresponding to row m and column n of the first matrix in the first storage location, wherein performing the operation includes: performing an operation corresponding to the instruction to handle non-normal values of the second matrix and the third matrix as zeros.

19. A computer-readable medium having instructions stored thereon, the instructions when executed by a processor cause the processor to perform the method as claimed in claim 18.

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