Non-volatile memory with multi-level memory cell array and programming control method

Abstract

A non-volatile memory with a multi-level memory cell array and a programming control method. The non-volatile memory includes a memory cell array, a current supply circuit, a path selection circuit, a verification circuit and a control circuit. During a sampling interval of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the n verification elements and converts them into n reference voltages. During a verification interval of the verification action, the control circuit controls n multi-level memory cells in a selected row to generate n memory cell currents to the n verification elements and convert them into n sensing voltages. The n verification elements generate the n verification signals according to the corresponding reference voltages and the corresponding sensing voltages, so that the control circuit determines whether the n multi-level memory cells have reached an M-th storage state.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory and a related control method thereof, and in particular to a non-volatile memory with a multi-level memory cell array and a related programming control method thereof. Background Art

[0002] As we all know, non-volatile memory can continue to record data after the power supply is cut off, so non-volatile memory has been widely used in various electronic devices. Generally speaking, non-volatile memory can be divided into one-time programmable non-volatile memory (OTP non-volatile memory) and multi-time programmable non-volatile memory (MTP non-volatile memory). Figures 1A to 1E Various non-volatile memory cells.

[0003] Please refer to Figure 1A , which is a schematic diagram of an OTP memory cell. The OTP memory cell c1 includes a floating gate transistor F and a switch transistor M. The first end of the OTP memory cell c1 is connected to a source line (source line, SL), the second end of the OTP memory cell c1 is connected to a bit line (bit line, BL), and the control end of the OTP memory cell c1 is connected to a word line (wordline, WL).

[0004] like Figure 1A As shown, a first source / drain terminal of the switch gate transistor M is connected to the source line SL, and a gate terminal of the switch gate transistor M is connected to the word line WL. A first source / drain terminal of the floating gate transistor F is connected to a second source / drain terminal of the switch transistor M, and a second source / drain terminal of the floating gate transistor F is connected to the bit line BL.

[0005] During a write action, a proper bias voltage is provided to the OTP memory cell c1, and the OTP memory cell c1 can be programmed or inhibited. Programming the OTP memory cell c1 means controlling the hot carrier to be injected into the floating gate of the floating gate transistor F, and inhibiting the OTP memory cell c1 means controlling the hot carrier not to be injected into the floating gate of the floating gate transistor F. In addition, hot carriers are electrons.

[0006] For example, when programming the OTP memory cell c1, a program voltage is provided to the source line SL, an on voltage is provided to the word line WL, and a ground voltage is provided to the bit line BL. Therefore, hot carriers are injected into the floating gate through the channel region of the floating gate transistor F. Conversely, when programming the suppressed OTP memory cell c1, a program voltage is provided to the source line SL, an on voltage is provided to the word line WL, and the bit line BL is floated. Therefore, hot carriers cannot be injected into the floating gate of the floating gate transistor F. Of course, in addition to floating the bit line, when programming the suppressed OTP memory cell c1, a program voltage can also be provided to the bit line BL so that hot carriers cannot be injected into the floating gate of the floating gate transistor F.

[0007] Furthermore, when the floating gate of the floating gate transistor F does not store hot carriers, the OTP memory cell c1 will present a first storage state (i.e., an off state). When the floating gate of the floating gate transistor F stores hot carriers, the OTP memory cell c1 will present a second storage state (i.e., an on state). In other words, after programming the OTP memory cell c1, the OTP memory cell c1 will present a first storage state, and after programming the OTP memory cell c1, the OTP memory cell c1 will present a second storage state.

[0008] In addition, during a read action, an appropriate bias voltage is provided to the OTP memory cell c1 so that the OTP memory cell c1 generates a cell current. The storage state of the OTP memory cell c1 can be determined according to the size of the cell current.

[0009] During the reading operation, a read voltage is provided to the source line SL, a turn-on voltage is provided to the word line WL, and a ground voltage is provided to the bit line BL. When the OTP memory cell c1 is in the first storage state (off state), the memory cell current is almost zero. When the OTP memory cell c1 is in the second storage state (on state), the memory cell current will be larger. Therefore, by connecting the bit line BL of the OTP memory cell c1 to the sensing circuit, it can be determined whether the OTP memory cell c1 is in the first storage state (off state) or the second storage state (on state).

[0010] Since the programming voltage is very high, in order to prevent the switch transistor M from being damaged during the writing operation, a following transistor can be added to the OTP memory cell. Figure 1B, which is a schematic diagram of another OTP memory cell. The OTP memory cell c2 includes a floating gate transistor F, a follower transistor Mg and a switch transistor M. Among them, the first end of the OTP memory cell c2 is connected to the source line SL, the second end of the OTP memory cell c2 is connected to the bit line BL, the first control end of the OTP memory cell c2 is connected to the word line WL, and the second control end of the OTP memory cell c2 is connected to the following line (FL).

[0011] like Figure 1B As shown, the first source / drain terminal of the switch transistor M is connected to the source line SL, and the gate terminal of the switch transistor M is connected to the word line WL. The first source / drain terminal of the follower transistor Mg is connected to the second source / drain terminal of the switch transistor M, and the gate terminal of the follower transistor Mg is connected to the follower line FL. The first source / drain terminal of the floating gate transistor F is connected to the second source / drain terminal of the follower transistor Mg, and the second source / drain terminal of the floating gate transistor F is connected to the bit line BL.

[0012] Basically, the switch transistor M and the follower transistor Mg have the same operating relationship. When the switch transistor M is turned on, the follower transistor Mg is also turned on; when the switch transistor M is turned off, the follower transistor Mg is also turned off. In addition, the bias and operating principles of the write and read actions of the OTP memory cells c1 and c2 are similar and will not be repeated here.

[0013] Please refer to Figure 1C , which shows a schematic diagram of an MTP memory cell. Figure 1A The MTP memory cell c3 further includes an erase capacitor C connected between the floating gate of the floating gate transistor F and an erase line (EL). During the writing and reading operations, a ground voltage is provided to the erase line EL, and the bias voltages of other terminals of the MTP memory cell c3 are similar to those of the OTP memory cell c1, and the detailed operation thereof will not be described again.

[0014] During the erase operation, an erase voltage is provided to the erase line EL, so that the hot carriers move to the erase line EL through the erase capacitor C and eject the floating gate.

[0015] Please refer to Figure 1D , which shows another schematic diagram of an MTP storage cell. Figure 1BThe MTP memory cell c4 further includes an erase capacitor C connected between the floating gate of the floating gate transistor F and an erase line (EL). During the write and read operations, a ground voltage is provided to the erase line EL, and the bias voltages of other terminals of the MTP memory cell c4 are similar to those of the OTP memory cell c2, and the detailed operation thereof will not be described again.

[0016] Similarly, during the erase operation, an erase voltage is provided to the erase line EL, so that the hot carriers move to the erase line EL through the erase capacitor C and exit the floating gate.

[0017] Above Figures 1A to 1D The memory cells in the present invention are all described by taking P-type transistors as an example. In fact, OTP memory cells and MTP memory cells can also be realized by using N-type transistors.

[0018] Please refer to Figure 1E , which is another schematic diagram of an MTP memory cell. The MTP memory cell c5 includes a switch transistor M and a resistor R. The first end of the MTP memory cell c5 is connected to the source line SL, the second end of the MTP memory cell c5 is connected to the bit line BL, and the control end of the MTP memory cell c5 is connected to the word line WL.

[0019] Furthermore, a first source / drain terminal of the switch transistor M is connected to a source line SL, a gate terminal of the switch transistor M is connected to a word line WL, a second source / drain terminal of the switch transistor M is connected to a first end of a resistor R, and a second end of the resistor R is connected to a bit line BL. The resistor R may be formed of a transition metal oxide (TMO).

[0020] Basically, the voltage difference received by the two ends of the control resistor R can determine the storage state of the resistor R. For example, when the two ends of the resistor R receive a voltage difference of a first polarity (e.g., a negative polarity), the resistor R presents a first storage state with a high resistance value. When the two ends of the resistor R receive a voltage difference of a second polarity (e.g., a positive polarity), the resistor R presents a second storage state with a low resistance value. In other words, during a write action, providing an appropriate bias voltage to the MTP memory cell c5 can control the storage state of the MTP memory cell c5.

[0021] Figure 2 A memory cell array is a non-volatile memory. Figure 2 As shown, the memory cell array 200 of the nonvolatile memory includes m×n memory cells c11-cmn. The structure of each memory cell c11-cmn is the same as Figure 1A Of course, the memory cells c11-cmn of the memory cell array 200 can also be composed of Figures 1B to 1E It is composed of one of the memory cells c2~c5.

[0022] Each memory cell c11-cmn includes a switch transistor M 1，1 ~M m，n and a floating gate transistor F 1，1 ~F m，n Furthermore, the structure of each memory cell c11-cmn is the same as Figure 1A The detailed structure of the memory cell c1 is omitted. In addition, the first end of each memory cell c11-cmn is connected to the source line SL, and m and n are positive integers.

[0023] In the memory cell array 200, the control terminals of the n memory cells c11-c1n in the first row are all connected to the word line WL1, and the second terminals of the n memory cells c11-c1n in the first row are connected to the corresponding bit lines BL1-BLn. The control terminals of the n memory cells c21-c2n in the second row are all connected to the word line WL2, and the second terminals of the n memory cells c21-c2n in the second row are connected to the corresponding bit lines BL1-BLn. Similarly, the memory cells in other rows have similar connection relationships, which will not be repeated here.

[0024] Basically, during a write action or a read action of a non-volatile memory, only one of the m word lines WL1 to WLm in the memory cell array 200 will be activated, and the other word lines will not be activated. For example, during a write action, the word line WL1 is activated, so that the first row is the selected row. At this time, various bias voltages are provided to the bit lines BL1 to BLn, so that the corresponding memory cells on the selected row can be programmed or the corresponding memory cells can be programmed and inhibited. For the memory cells that are programmed and inhibited, the floating gate of the floating gate transistor will not be injected with hot carriers and become the first storage state. In addition, for the programmed memory cells, the floating gate of the floating gate transistor will be injected with hot carriers and become the second storage state. For example, if a ground voltage is provided to the bit line BL1, the memory cell c11 will become the second storage state. If the bit line BL2 is floated, the memory cell c12 will become the first storage state.

[0025] The memory cells in the known memory cell array are single level cells. That is, one memory cell stores 1 bit of data, which can be in a first storage state or a second storage state. Therefore, during the writing operation, the memory cell can present two different storage states by only controlling the hot carrier injection or not injecting the floating gate.

[0026] Furthermore, when the known memory cell is used as a multi-level memory cell, one memory cell must store at least 2 bits of data. Taking a multi-level memory cell storing 2 bits as an example, the data of each memory cell can be a first storage state, a second storage state, a third storage state, or a fourth storage state. Similarly, a multi-level memory cell storing 3 bits has eight types (2 3 ) storage state, there are sixteen (2 4 ) storage status.

[0027] In order to allow the multi-level memory cell to present different storage states, the number of hot carriers injected into the floating gate needs to be further controlled during the write operation. However, due to the process variation of the memory cell and the difference in the load on the bit lines BL1-BLn, even if the same number of hot carriers are injected into two memory cells, it is possible that the two memory cells may present different storage states. Summary of the invention

[0028] The present invention relates to a non-volatile memory, comprising: a memory cell array, comprising m×n multi-level memory cells, connected to m word lines and n bit lines, wherein each of the multi-level memory cells can be in one of X storage states, and X is greater than or equal to 4; a current supply circuit; a path selection circuit, connected to the current supply circuit and the n bit lines, wherein the path selection circuit comprises n path selectors, and the n path selectors are connected to the current supply circuit and the corresponding n bit lines; a verification circuit, connected to the path selection circuit, wherein the verification circuit comprises n verification elements connected to the corresponding n path selectors to generate n verification signals; and a control circuit, receiving the n verification signals; wherein, in a verification action During a sampling interval of the verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the n path selectors, which are transmitted to the n verification elements via the n path selectors and converted into n reference voltages; wherein, during a verification interval of the verification action, the control circuit controls n multi-level memory cells of a selected row to generate n memory cell currents, which are transmitted to the n verification elements via the n bit lines and the n path selectors and converted into n sensing voltages; wherein the n verification elements generate the n verification signals according to the corresponding reference voltages and the corresponding sensing voltages, so that the control circuit determines whether the n multi-level memory cells have reached an M-th storage state, wherein m, n, M and X are positive integers, and M is less than or equal to X.

[0029] The present invention relates to a programming control method for the above-mentioned non-volatile memory, comprising the following steps: determining a selected row in the memory cell array and starting an Mth programming cycle for the selected row; setting M equal to 1; (a) the current supply circuit provides n Mth reference currents to the path selection circuit; (b) among the n memory cells in the selected row, the memory cells that have reached a target storage state are inhibited from programming; (c) among the n memory cells in the selected row, the memory cells that have not reached the target storage state are subjected to an Mth programming process; and (d) determining whether M is equal to X, wherein when M is not equal to X, M is increased by 1 and the process returns to step (a); and when M is equal to X, the Mth programming cycle is terminated.

[0030] In order to better understand the above and other aspects of the present invention, preferred embodiments are specifically described below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1A to 1E Schematic diagrams of various memory cells;

[0032] Figure 2 is a schematic diagram of a memory cell array;

[0033] Figure 3 The non-volatile memory of the present invention;

[0034] Figure 4A and Figure 4B A detailed circuit diagram and related signal diagram of the current supply circuit;

[0035] FIG. 5A to FIG. 5C is a schematic diagram of the operation of the replication unit;

[0036] Fig. 6A and Figure 6B The detailed structure and related signal diagram of the path selection circuit and verification circuit;

[0037] 7A to 7D It is a schematic diagram of the operation of the path selector and the verification component during the verification action;

[0038] FIG. 8A to FIG. 8C The present invention is applied to the programming control method and example of a multi-level memory cell array;

[0039] Fig.9A and Fig. 9B The method of shortening the programming process and the example of searching the table of the present invention;

[0040] Fig. 10A and Fig. 10B Other embodiments of the voltage clamping circuit and the path selection circuit; and

[0041] Fig.11 Another embodiment of the current supply circuit.

[0042]

Explanation of symbols

[0043] 200, 300: memory cell array

[0044] 310: Current supply circuit

[0045] 313, 314: Voltage clamping circuit

[0046] 315, 316, 341, 34n: Operational amplifier

[0047] 320, 320a, 320b: path selection circuit

[0048] 321~32n, 321a~32na, 321b~32nb: Path selector

[0049] 330: Verification circuit

[0050] 331~33n: Verification element

[0051] 410: Current replication circuit

[0052] 411~41n: Replication unit

[0053] 420: Current generator

[0054] 422: Switch Group DETAILED DESCRIPTION

[0055] According to an embodiment of the present invention, the present invention utilizes Figures 1A to 1E The memory cells in the memory cell array are used to form a multi-level memory cell array. Since all memory cells in the memory cell array are multi-level memory cells, the memory cells have at least four storage states, and memory cells in different storage states will generate memory cell currents of different magnitudes.

[0056] by Figure 1A Taking the memory cell c1 shown as an example, according to the number of hot carriers injected into the floating gate from small to large, the memory cell c1 can be in the first storage state to the Xth storage state, and X is greater than or equal to 4. For example, when the multi-level memory cell c1 can store two bits of data, X=4, that is, the memory cell c1 is one of the first storage state to the fourth storage state. Similarly, when the multi-level memory cell c1 can store three bits of data, X=8, that is, the memory cell c1 can be one of the first storage state to the eighth storage state. When the multi-level memory cell c1 can store four bits of data, X=16, that is, the memory cell c1 can be one of the first storage state to the sixteenth storage state.

[0057] For example, assuming a multi-level memory cell c1 storing two-bit data, during a read operation, the memory cell current in the first storage state is 0.1 μA, the memory cell current in the second storage state is 0.6 μA, the memory cell current in the third storage state is 1.1 μA, and the memory cell current in the fourth storage state is 1.6 μA.

[0058] According to an embodiment of the present invention, multiple write actions and verify actions are performed in a program cycle. Each write action is very short, for example, 100ns, so that a small amount of hot carriers are injected into the floating gate of the memory cell. When the write action is completed, a verify action is immediately performed to determine whether the memory cell current generated by the memory cell reaches a predetermined storage state. If the memory cell has not reached the predetermined storage state, the write action is continued to inject a small amount of hot carriers into the floating gate of the memory cell again. The write action and the verify action will continue until the memory cell current generated by the memory cell meets the predetermined storage state.

[0059] Furthermore, the following description is made by taking a multi-level memory cell storing two-bit data as an example, but the present invention is certainly not limited thereto, and those skilled in the art can also apply the present invention to memory cells storing more bits.

[0060] Please refer to Figure 3 , which shows the non-volatile memory of the present invention. The non-volatile memory includes a memory cell array 300, a current supply circuit 310, a path selection circuit 320, a verification circuit 330 and a control circuit 340. The structure of the m×n memory cell array 300 is the same as Figure 2 Of course, the memory cells in the memory cell array 300 may be OTP memory cells or MTP memory cells.

[0061] The current supplying circuit 310 receives a control signal Ctrl M The current supply circuit 310 includes a plurality of current sources and controls the current supply circuit 310 according to the control signal Ctrl. MTo provide one of the X reference currents. For example, assuming that in a multi-level memory cell storing two bits of data, the memory cell current of the first storage state is 0.1μA, the memory cell current of the second storage state is 0.6μA, the memory cell current of the third storage state is 1.1μA, and the memory cell current of the fourth storage state is 1.6μA, then the current supply circuit 310 can generate four (X=4) reference currents corresponding to different storage states. That is, the first reference current is 0.1μA, the second reference current is 0.6μA, the third reference current is 1.1μA, and the fourth reference current is 1.6μA.

[0062] Similarly, when used in a multi-level memory cell storing three bits of data, the current supply circuit 310 can provide eight reference currents. When used in a multi-level memory cell storing four bits of data, the current supply circuit 310 can provide sixteen reference currents.

[0063] The path selecting circuit 320 includes n path selectors 321-32n. Furthermore, the verification circuit 330 includes n verification devices 331-33n connected to the corresponding n path selectors 321-32n and generates n verification signals Vok1-Vokn. The structure of each path selector 321-32n is the same, and the structure of each verification device 331-33n is the same.

[0064] According to an embodiment of the present invention, the current supply circuit 310 can output one of the X reference currents to the n path selectors 321-32n. For example, the current supply circuit 310 can simultaneously supply n first reference currents of 0.1 μA to the n path selectors 321-32n. Alternatively, the current supply circuit 310 can simultaneously supply n second reference currents of 0.6 μA to the n path selectors 321-32n, and so on.

[0065] Taking the path selector 321 and the verification element 331 as an example, the path selector 321 includes a reference current path and a memory cell current path. The reference current path is connected to the current supply circuit 310, and the memory cell current path is connected to the bit line BL1. Furthermore, the reference current path is controlled by the reference current enable signal ENsa, and the memory cell current path is controlled by the memory cell current enable signal ENcell. That is, when the reference current enable signal ENsa is activated, the reference current path of the path selector 321 is connected between the current supply circuit 310 and the verification element 331; when the memory cell current enable signal ENcell is activated, the memory cell current path of the path selector 321 is connected between the bit line BL1 and the verification element 331.

[0066] During the verification operation, the verification element 331 first receives the reference current provided by the current supply circuit 310 and converts it into a reference voltage. Afterwards, the verification element 331 receives the memory cell current on the bit line BL1 and converts it into a sensed voltage. Finally, the verification element 331 generates a verification signal Vok1 according to the reference voltage and the sensed voltage.

[0067] The control circuit 340 is connected to the verification circuit 330 to receive n verification signals Vok1-Vokn. Furthermore, the control circuit 340 can output multiple signals (for example, the control signal Ctrl M , reference current enable signal ENsa, memory cell current enable signal ENcell, etc.). The control circuit 340 can control the operation of the non-volatile memory in the write operation and the verification operation, and confirm whether the memory cells on the selected row have reached a predetermined storage state according to the verification signals Vok1-Vokn.

[0068] Please refer to Figure 4A and Figure 4B , which depicts a detailed circuit diagram and related signal diagram of the current supply circuit. The current supply circuit 310 includes a current copy circuit 410 and a current generator 420. The current copy circuit 410 can receive one of the X reference currents output by the current generator 420, and copy it into n identical reference currents to be transmitted to the n path selectors 321-32n in the path selection circuit 320.

[0069] The current copy circuit 410 includes n copy units 411-41n, and the current output terminals oi1-oin of the n copy units 411-41n are connected to the corresponding path selectors 321-32n. Moreover, the structure of each copy unit 411-41n is the same. Only the copy unit 411 is introduced below, and the rest are not repeated.

[0070] The replica unit 411 includes transistors m11-m14, switches w11-w12, and capacitor c1. The first source / drain terminal of transistor m11 receives the power supply voltage Vdd. The first source / drain terminal of transistor m13 receives the power supply voltage Vdd, and the gate terminal of transistor m13 is connected to the gate terminal of transistor m11. The first source / drain terminal of transistor m12 is connected to the second source / drain terminal of transistor m11. The first source / drain terminal of transistor m14 is connected to the second source / drain terminal of transistor m13, the gate terminal of transistor m14 is connected to the gate terminal of transistor m12, and the second source / drain terminal of transistor m14 is the current output terminal oi1. The first end of capacitor c1 is connected to the gate terminal of transistor m11. The first end of switch w11 is connected to the second source / drain terminal of transistor m12, and the second end of switch w11 is connected to the second end of capacitor c1. The first end of switch w12 is connected to the second source / drain terminal of transistor m12, and the second end of switch w12 is connected to node c.

[0071] The current generator 420 is connected between the node c and the ground GND. The current generator 420 includes X current sources Iref1 to Irefx and a switch set 422. The switch set 422 includes X switches w1 to wx. The current source Iref1 and the switch w1 are connected in series between the node c and the ground GND. The current source Iref2 and the switch w2 are connected in series between the node c and the ground GND. Similarly, the current source Irefx and the switch wx are connected in series between the node c and the ground GND. Furthermore, the control signal Ctrl M The switch group 422 is controlled so that one of the X switches w1-wx is in a closed state and the others are in an open state. M When is 1, the switch w1 is in a closed state, the switches w2 to wx are in an open state, and the current source Iref1 is connected between the node c and the ground terminal GND.

[0072] According to the embodiment of the present invention, the n activated periods T1-Tn in the replication units 411-41n will be activated in sequence. Figure 4BAs shown, the time between time points ta and tb is the first action interval. After n action intervals T1 to Tn, the capacitors c1 to cn in the replica units 411 to 41n will store the driving voltage. In other words, after the action intervals T1 to Tn in the replica units 411 to 41n are sequentially operated, the capacitors c1 to cn in the replica units 411 to 41n have stored the corresponding driving voltage, and the current output terminals oi1 to oin of the replica units 411 to 41n can output the reference current of the same magnitude.

[0073] like FIG. 5A to FIG. 5C , which is a schematic diagram of the operation of the replication unit. The following only takes the replication unit 411 as an example for explanation, and the operation of the other replication units 412-41n is similar, which will not be repeated here.

[0074] Please refer to Figure 4B and Figure 5A , before time point ta, the control signal Ctrl M is 1, switches w11 and w12 are receiving a turn off level, i.e., a low level. At this time, switches w11 and w12 are in an open state. Inside the current generator 420, the current source Iref1 is connected between the node c and the ground terminal GND.

[0075] Please refer to Figure 4B and Figure 5B , between time point ta and time point tb, the control signal Ctrl M is 1. In the first action interval T1, switches w11 and w12 are at a turn on level, i.e., a high level. At this time, switches w11 and w12 are in a closed state. Therefore, the first reference current Iref1 generated by the current source Iref1 flows through transistors m11 and m12, and a driving voltage Vd1 is generated on the capacitor c1.

[0076] Please refer to Figure 4B and Figure 5C , after time point tb, the control signal Ctrl M is 1, and the first action interval T1 ends. At this time, the switch w11 receives the closing level and is in the closed state, and the switch w12 receives the opening level and is in the open state. Furthermore, the current source Iref1 does not flow through the transistors m11 and m12, and the driving voltage Vd1 is stored on the capacitor c1.

[0077] Similarly, the other replica units 412 ˜ 41 n will also operate during the corresponding action periods T2 ˜ Tn. Therefore, after all the action intervals T2 ˜ Tn, the capacitors c2 ˜ cn in the replica units 412 ˜ 41 n will store the corresponding driving voltages.

[0078] During the verification operation of the non-volatile memory, the current output terminals oi1 - oin of the replica units 411 - 41 n can output the first reference current Iref1 to the n path selectors 321 - 32 n of the path selection circuit 320 according to the driving signals on the capacitors c1 - cn.

[0079] Furthermore, the control signal Ctrl M It can be any value from 1 to X, so that the current generator 410 generates reference currents Iref1-Irefx accordingly. M When the value is 2, the switch w2 is closed, and the current generator 410 connects the current source Iref2 between the node c and the ground terminal GND. Therefore, during the verification operation of the non-volatile memory, the current output terminals oi1-oin of the replica units 411-41n can output the second reference current Iref2 to the n path selectors 321-32n of the path selection circuit 320.

[0080] Furthermore, since the action intervals T1-Tn are sequentially operated, it takes a long time for the copy units 411-41n in the current copy circuit 410 to prepare the driving voltage. Therefore, those skilled in the art can further modify the current supply circuit 310 to shorten the time for preparing the driving voltage.

[0081] For example, the power supply circuit 310 includes two current replicating circuits with the same structure. Under the control of the control circuit 340, when the n replicating units of the first current replicating circuit output n first reference currents Iref1, the n replicating units of the second current replicating circuit prepare a driving voltage corresponding to the second reference current Iref2. Similarly, when the n replicating units of the second current replicating circuit output n second reference currents Iref2, the n replicating units of the first current replicating circuit prepare a driving voltage corresponding to the third reference current Iref3. And so on.

[0082] Please refer to Fig. 6A and Figure 6B , which shows the detailed structure of the path selection circuit and the verification circuit and the schematic diagram of the related signals. Fig. 6A In FIG. 3 , the memory cell array 300 only shows a row of memory cells cj1 ˜cjn connected to a word line WLj, and the rest are not shown.

[0083] The path selection circuit 320 includes n path selectors 321 ˜ 32n , and the verification circuit 330 includes n verification elements 331 ˜ 33n . Only the path selector 321 and the verification element 331 are described below.

[0084] The reference current path in the path selector 321 includes a switch transistor s11. A first source / drain terminal of the switch transistor s11 is connected to the current supply circuit 310, a second source / drain terminal of the switch transistor s11 is connected to the node a1, and a gate terminal of the switch transistor s11 receives the reference current enable signal ENsa. Furthermore, the memory cell current path in the path selector 321 includes a switch transistor s12. A first source / drain terminal of the switch transistor s12 is connected to the bit line BL1, a second source / drain terminal of the switch transistor s12 is connected to the node a1, and a gate terminal of the switch transistor s12 receives the memory cell current enable signal ENcell.

[0085] The verification element 331 includes an operational amplifier 341, switches s13, s14, and capacitors C11 and C12. The first end of the switch s13 is connected to the node a1, the second end of the switch s13 is connected to the ground terminal GND, and the control end of the switch s13 receives a discharge enable signal ENdisc. The first end of the capacitor C11 is connected to the node a1, and the second end of the capacitor C11 is connected to the ground terminal GND. The first end of the capacitor C12 is connected to the negative input terminal of the operational amplifier, and the second end of the capacitor C12 is connected to the ground terminal GND. The positive input terminal of the operational amplifier 341 is connected to the node a1, and the output terminal of the operational amplifier 341 generates a verification signal Vok1. The first end of the switch s14 is connected to the output terminal of the operational amplifier 341, the second end of the switch s14 is connected to the negative input terminal of the operational amplifier 341, and the control end of the switch s14 receives a close loop enable signal ENcls. The switches s13 and s14 can be implemented by transistors, and the control circuit 340 outputs a discharge enable signal ENdisc and a closed-loop enable signal ENcls.

[0086] like Fig. 6A When the word line WLj is activated, the memory cells cj1-cjn of the selected row can be programmed. During the verification operation after the writing operation, the control circuit 340 determines whether the memory cells cj1-cjn of the selected row are programmed to a predetermined storage state according to the verification signals Vok1-Vokn.

[0087] like Figure 6B As shown, the verification operation includes a reference current sampling phase and a cell current sampling phase. In the reference current sampling phase, the reference current enable signal ENsa and the closed-loop enable signal ENcls are activated.

[0088] exist Figure 6B In the embodiment, time point t0 to time point t2 is the reference current sampling phase, and time point t2 to time point t4 is the memory cell current sampling phase. Furthermore, the reference current sampling phase includes a discharge period and a sampling period, and the memory cell current sampling phase includes a discharge period and a verification period. Among them, time point t0 to time point t1 is the discharge period, time point t1 to time point t2 is the sampling period, time point t2 to time point t3 is the discharge period, and time point t3 to time point t4 is the verification period.

[0089] According to an embodiment of the present invention, the time lengths Ts and Tv of the sampling interval (Sample) and the verification interval (Verify) in the reference current sampling phase can be adjusted according to actual needs to determine the relationship between the reference current and the memory cell current. Basically, the verification interval Tv is greater than or equal to the sampling interval Ts.

[0090] like 7A to 7D , which is a schematic diagram of the operation of the path selector 321 and the verification element 331 during the verification operation. The following description is based on the assumption that the sampling interval time length Ts is equal to the verification interval time length Tv (ie, Ts=Tv).

[0091] Please refer to Figure 6B and Fig. 7A In the discharge interval (Discharge) from time point t0 to t1, only the discharge enable signal ENdisc is activated. Therefore, the switch s13 in the verification element 331 is in a closed state, so that the capacitor C11 is discharged to the ground voltage (0V).

[0092] Please refer to Figure 6B and Figure 7B, in the sampling interval (Sample) from time point t1 to t2, the reference current enable signal ENsa and the closed-loop enable signal ENcls are activated. Therefore, the reference current path in the path selector 321 is connected between the current supply circuit 310 and the verification element 331, and the switch s14 in the verification element 331 is in a closed state, so that the operational amplifier 341 becomes a unit gain buffer. At this time, the reference current Iref1 provided by the current supply circuit 310 charges the capacitor C11. At the same time, the unit gain buffer duplicates the voltage of the capacitor C11 to the capacitor C12. In other words, at time point t2, the capacitor C11 will be charged to the first reference voltage Vref1, and the voltage of the capacitor C12 will also be the first reference voltage Vref1. Similarly, at time point t2, the two capacitors in the other verification elements 322 to 32n in the verification circuit 330 will also be charged to the corresponding reference voltage. For example, the two capacitors Cn1 and Cn2 in the verification element 32n will be charged to the nth reference voltage.

[0093] In other words, at the time point t2 after the reference current sampling phase, the capacitors C12 - Cn2 in all the verification elements 331 - 33 n store the corresponding reference voltages.

[0094] Furthermore, please refer to Figure 6B and Figure 7C , time point t2-t3 is the discharge interval (Discharge) of the memory cell current sampling phase, and the discharge enable signal ENdisc is activated. Therefore, the switch s13 in the verification element 331 will discharge the capacitor C11 to the ground voltage (0V) according to the discharge enable signal ENdisc, and only the capacitor C12 is left to store the first reference voltage Vref1. Similarly, at time point t3, only one capacitor in the other verification elements 322-32n in the verification circuit 330 is left to store the reference voltage.

[0095] like Figure 6B As shown, time points t3-t4 are the verification interval (Verify) of the memory cell current sampling phase, and the memory cell current enable signal ENcell is activated. Therefore, the memory cell current paths in all path selectors 321-32n connect the corresponding bit lines BL1-BLn to the corresponding verification elements 331-33n. At this time, all memory cells cj1-cjn on the selected row generate memory cell currents to the corresponding verification elements 331-33n.

[0096] Take verification element 331 as an example for illustration. Fig.7DAs shown, the memory cell current path of the path selector 321 is connected between the bit line BL1 and the verification element 331. Therefore, the memory cell cj1 on the selected row generates a memory cell current Icell1 to the verification element 331 and charges the capacitor C11.

[0097] At the end of the memory cell current sampling phase, that is, at time point t4, the operational amplifier 341 can be regarded as a comparator, which is used to compare the first sensed voltage Vcell1 on the capacitor C11 and the first reference voltage Vref1 on the capacitor C12. When the first sensed voltage Vcell1 is less than the first reference voltage Vref1, the verification signal Vok1 is at a low level, indicating that the memory cell current Icell1 is less than the reference current Iref1. In other words, the memory cell cj1 has not yet reached the predetermined storage state, and the memory cell cj1 needs to continue to be programmed. On the contrary, when the first sensed voltage Vcell1 is greater than the first reference voltage Vref1, the verification signal Vok1 is at a high level, indicating that the memory cell current Icell1 is greater than the reference current Iref1. In other words, the memory cell cj1 has reached the predetermined storage state, and it is necessary to program and inhibit this memory cell cj1.

[0098] Similarly, the verification signals Vok2 ˜Vokn generated by the other verification elements 332 ˜ 33 n respectively represent whether the corresponding memory cells cj2 ˜ cjn on the selected row have reached a predetermined storage state.

[0099] For example, assuming that the predetermined storage state is the first storage state, the reference current provided by the current supply circuit 310 is 0.1 μA. Therefore, when the verification operation is completed, it can be determined whether the corresponding memory cell in the selected row can generate a memory cell current of 0.1 μA according to the verification signals Vok1 to Vokn.

[0100] Taking the verification element 331 as an example, if the verification signal Vok1 is at a low level, it means that the memory cell cj1 generates a memory cell current less than 0.1 μA, and it is confirmed that the memory cell has not yet reached the first storage state. Conversely, if the verification signal Vok1 is at a high level, it means that the memory cell cj1 generates a memory cell current greater than 0.1 μA, and it can be confirmed that the memory cell cj1 reaches the first storage state.

[0101] Similarly, assuming that the predetermined storage state is the second storage state, the reference current provided by the current supply circuit 310 is 0.6μA. Assuming that the predetermined storage state is the third storage state, the reference current provided by the current supply circuit 310 is 1.1μA. Assuming that the predetermined storage state is the fourth storage state, the reference current provided by the current supply circuit 310 is 1.6μA. During the verification operation, it can be confirmed whether the memory cell reaches the predetermined storage state according to the verification signals Vok1 to Vokn.

[0102] In addition, the control circuit 430 can adjust the time lengths Ts and Tv of the sampling interval (Sample) and the verification interval (Verify) to determine the proportional relationship between the reference current Iref and the memory cell current Icell. The following describes:

[0103] Assume that the ratio of the sampling interval Ts to the verification interval Tv is 3:4, that is, Ts = (3 / 4) Tv. At the end of the memory cell current sampling phase, the relationship between the reference current Iref1 and the memory cell current Icell1 can be determined based on the verification signal Vok1 output by the operational amplifier 341. For example, when the verification signal Vok1 is at a high level, it means that the memory cell current Icell1 has reached (3 / 4) times the reference current Iref1, that is, Icell1 = (3 / 4) Iref1. Conversely, when the verification signal Vok1 is at a low level, it means that the memory cell current Icell1 has not yet reached (3 / 4) times the reference current Iref1, that is, Icell1 < (3 / 4) Iref1.

[0104] Similarly, other verification elements 332 ˜ 33 n in the verification circuit 330 may also output verification signals Vok2 ˜Vokn to indicate the relationship between the corresponding memory cell current Icell and the reference current Iref1 .

[0105] Of course, the present invention does not limit the ratio of the sampling interval Ts to the verification interval Tv. For example, assuming that the ratio of the sampling interval Ts to the verification interval Tv is b:a, and a is greater than or equal to b, it can be determined based on the verification signal Vok1 whether the memory cell current Icell1 reaches (b / a) times the reference current Iref1.

[0106] As can be seen from the above description, the present invention performs multiple write operations to program the multi-level memory cells multiple times, so that the multi-level memory cells reach a predetermined storage state. Furthermore, due to the difference in characteristics of the n memory cells on the selected row, it is impossible to make all the memory cells in the selected row reach the predetermined storage state at the same time. Therefore, the present invention proposes a programming control method applied to a multi-level memory cell array.

[0107] Please refer to FIG. 8A to FIG. 8C , which illustrates a programming control method and an example thereof of the present invention applied to a multi-level memory cell array. Under the control of the control circuit 340, a selected row can be determined in the memory cell array 300 during a program cycle. The programming cycle includes X programming procedures, so that n memory cells in the selected row are gradually programmed from a first storage state to a target storage state. According to the control signal Ctrl of the control circuit 340, M The corresponding programming process can be determined.

[0108] like Fig. 8A As shown, at the beginning of the programming cycle, M is set to 1 (step S604), and the current supply circuit 310 provides the Mth reference current (step S606).

[0109] Next, among the memory cells in the selected row, the memory cells that have reached the target storage state are inhibited from programming (step S608). In addition, among the memory cells in the selected row, the memory cells that have not reached the target storage state undergo the Mth programming process (step S610). For example, among the n memory cells in the selected row, a portion of the memory cells have reached the target storage state, and these portion of the memory cells will be inhibited from programming. The other portion of the memory cells that have not reached the Mth storage state will undergo the Mth programming process.

[0110] After the step S610 of the M-th programming process is completed, the n memory cells in the selected row either reach the target storage state or the M-th storage state. Afterwards, determine whether M is equal to X (step S614). When M is not equal to X, increase M by 1 (step S616) and return to step S606. On the contrary, when M is equal to X, it means that all memory cells in the selected row have reached the target storage state and the programming cycle is ended. Wherein, X and M are both positive integers, and M is greater than, less than or equal to X.

[0111] The following Figure 8B and Figure 8C Similarly, the following description is made by taking a multi-level memory cell storing two-bit data as an example, that is, X=4.

[0112] like Figure 8BAs shown, the selected row in the memory cell array includes six memory cells ci1-ci6, and their target storage states are respectively the fourth storage state (4th), the second storage state (2nd), the first storage state (1st), the third storage state (3rd), the second storage state (2nd), and the third storage state (3rd). That is, during a program cycle, the six memory cells in the selected row need to be programmed to the target storage state.

[0113] like Figure 8C As shown, after the programming cycle starts, in the first programming process when M is equal to 1, the current supply circuit 310 provides a first reference current. Furthermore, the memory cells ci1-ci6 on the selected row all reach the first storage state after multiple write operations and verification operations. In addition, since the memory cell ci3 has reached the target storage state, the memory cell ci3 will be inhibited from programming in the subsequent steps.

[0114] Of course, due to the difference in characteristics of the memory cells ci1~ci6, not all memory cells ci1~ci6 can reach the first storage state at the same time. Therefore, the memory cells that reach the first storage state first will be inhibited from programming during the next write operation, and only the memory cells that have not yet reached the first storage state will be programmed.

[0115] Next, M=2 is set. In the second programming process, the current supply circuit 310 provides a second reference current. Therefore, except for the memory cell ci3, the other five memory cells ci1-ci2, ci4-ci6 on the selected row reach the second storage state after multiple write operations and verification operations. In addition, since the memory cells ci2 and ci5 have reached the target storage state, the memory cells ci2 and ci5 will be inhibited from programming in the subsequent steps.

[0116] Next, M=3 is set. In the third programming process, the current supply circuit 310 provides a third reference current. Except for the memory cells ci2, ci3, and ci5, the other three memory cells ci1, ci4, and ci6 reach the third storage state after multiple write operations and verification operations. Since the memory cells ci4 and ci6 have reached the target storage state, the memory cells ci4 and ci6 will be inhibited from programming in the subsequent steps.

[0117] Finally, M=4 is set. In the fourth programming process, the current supply circuit 310 provides a fourth reference current. After only the remaining memory cell ci1 reaches the fourth storage state (ie, the target storage state) after multiple write operations and verification operations, the program cycle of the selected row ends.

[0118] Furthermore, after four programming processes are completed, all memory cells in the selected row have reached the target storage state. Therefore, a new programming cycle can be performed on the next selected row of the memory cell array.

[0119] From the above description, it can be seen that for a multi-level memory cell array storing two-bit data, four (X=4) programming processes are required during the programming cycle to confirm that all memory cells in the selected row are programmed to the target storage state. Similarly, for a multi-level memory cell array storing three-bit data, eight (X=8) programming processes are required during the programming cycle to confirm that all memory cells in the selected row are programmed to the target storage state. For a multi-level memory cell array storing four-bit data, sixteen (X=16) programming processes are required during the programming cycle to confirm that all memory cells in the selected row are programmed to the target storage state.

[0120] Since a programming cycle will perform X programming processes, and multiple write operations and multiple verification operations are required in each programming process, the programming cycle will take a considerable amount of time. For example, a verification operation will be performed after each write operation to determine whether the memory cell has reached the Mth storage state. However, in actual experience, each programming process may perform more than 100 write operations and verification operations to confirm that the memory cell is programmed to the Mth storage state.

[0121] In order to reduce the time of the programming cycle, the present invention further proposes a method for shortening the Mth programming process. Fig.9A and Fig. 9B , which illustrates an example of a method for shortening the programming process and a lookup table of the present invention. The number in the lookup table is defined as the number of write operations, and the ratio (b / a) is defined as the ratio of the sampling interval Ts to the verification interval Tv.

[0122] like Fig.9A As shown, when starting the Mth programming process in step S610, P and a ratio (b / a) are first set (step S802), where P is a positive integer and the ratio (b / a) is greater than zero and less than or equal to 1.

[0123] Next, the memory cells that have reached the Mth storage state are inhibited from being programmed (step S804). Furthermore, the memory cells that have not reached the Mth storage state undergo P write operations (step S806). In other words, in the selected row, the memory cells that need to be programmed to the Mth storage state will be inhibited from being programmed if they have reached the Mth storage state, while the memory cells that have not reached the Mth storage state will continue to undergo P write operations.

[0124] Next, a verification operation is performed to determine whether a memory cell current Icell of a memory cell in the programmed memory cells reaches (b / a) times the reference current Iref (step S808). Basically, during the verification operation, the ratio of the sampling period Ts and the verification period Tv is adjusted to (b / a) to determine whether Icell=(b / a)Iref is established. For example, when the memory cell current Icell of no memory cell in the selected row reaches (b / a) times the reference current Iref, it means that all memory cells in the selected row are not close to the Mth storage state, and the process returns to step S806.

[0125] In addition, when the memory cell current Icell of a memory cell in the selected row reaches (b / a) times the reference current Iref (i.e., Icell is greater than or equal to (b / a)Iref), it means that there is a memory cell in the selected row close to the Mth storage state. At this time, the number of write operations needs to be reduced to prevent the memory cell from being over-programmed.

[0126] Next, it is determined whether P is equal to 1 and the ratio (b / a) is equal to 1 (step S810). When P and the ratio (b / a) are not equal to 1, P is reduced and the ratio (b / a) is increased (step S812), and then the process returns to step S804. On the contrary, when both P and the ratio (b / a) are equal to 1 (step S810), step S814 is performed.

[0127] In step S814, it is determined whether all memory cells have reached the Mth storage state (step S814). In other words, it is determined whether all memory cells that should be programmed to the Mth storage state in the selected memory cells have reached the Mth storage state. If the determination is not established, the process returns to step S804; if established, the Mth programming process ends.

[0128] Basically, P and the ratio (b / a) can be set in a lookup table. Fig. 9B The search table example is introduced Fig.9A The Mth programming process.

[0129] After starting the programming process, first set P to 5 and the ratio (b / a) to (2 / 3). Then, perform 5 write operations on the memory cells that have not yet reached the Mth storage state. Furthermore, after the 5 write operations are completed, a verification operation is performed to determine whether the memory cell current Icell of any memory cell reaches (2 / 3) times the reference current Iref.

[0130] According to an embodiment of the present invention, if the memory cell current Icell of all memory cells does not reach (2 / 3) times the reference current Iref, it means that all memory cells need to perform multiple write operations to reach the Mth storage state. Therefore, all memory cells continue to perform 5 write operations before performing the verification operation. Conversely, if the memory cell current Icell of any memory cell reaches (2 / 3) times the reference current Iref, it means that a memory cell is gradually approaching the Mth storage state, so it is necessary to reduce the number of write operations of the memory cell and increase the ratio.

[0131] Therefore, according to the content of the search table, P is set to 2 and the ratio (b / a) is set to (4 / 5). Furthermore, after performing two write operations on the memory cells that have not yet reached the Mth storage state, a verification operation is performed to determine whether the memory cell current Icell of any memory cell reaches (4 / 5) times the reference current Iref.

[0132] Similarly, after the verification operation, if it is confirmed that the memory cell current Icell of all memory cells has not reached (4 / 5) times the reference current Iref, it means that all memory cells need to perform multiple write operations to reach the Mth storage state. Therefore, all memory cells continue to perform two write operations before performing the verification operation. Conversely, if the memory cell current Icell of any memory cell reaches (4 / 5) times the reference current Iref, it means that a memory cell is gradually approaching the Mth storage state. Therefore, it is necessary to reduce the number of write operations on the memory cells.

[0133] Therefore, according to the content of the search table, P is set equal to 1 and the ratio (b / a) is set equal to 1. Next, after performing a write operation on the memory cells that have not yet reached the Mth storage state, a verification operation is performed to determine whether the memory cell current Icell of any memory cell reaches the reference current Iref.

[0134] When the memory cell current Icell of one of the memory cells reaches the reference current Iref, it means that one memory cell has been programmed to the Mth storage state. At this time, a single write operation must be performed in combination with a verification operation to program all memory cells to the Mth storage state.

[0135] As can be seen from the above description, in the programming process of the present invention, the relationship between the memory cell current and the reference current is used to determine whether the memory cell is close to the Mth storage state, and the number of write operations is changed. In the above embodiment, P and the ratio (b / a) are changed three times in total. However, the present invention is not limited to the number of times P and the ratio (b / a) are changed. Technicians in this field can modify the number of changes of P and the ratio (b / a) according to actual needs.

[0136] That is, in the early stage of the programming process, a first number and a first ratio are set, wherein the first number is an integer greater than 1, and the first ratio is less than 1. That is, after performing the first number of write operations, during the verification operation, it is determined according to the first ratio whether there is a programmed memory cell close to the Mth storage state, and the number of subsequent write operations is determined.

[0137] In the later stage of the programming process, a second number and a second ratio are set, wherein the second number is 1 and the second ratio is 1. That is, after performing a write operation, it is determined during the verification operation that the memory cell is programmed to the Mth storage state, and all programmed memory cells are continuously programmed to the Mth storage state.

[0138] In addition, in order to allow the memory cell to generate a more accurate memory cell current, a voltage clamping circuit may be added to fix the reference current path and the memory cell current path at a specific bias voltage.

[0139] Please refer to Fig. 10A and Fig. 10B , which illustrate other embodiments of the voltage clamping circuit and the path selection circuit.

[0140] like Fig. 10A As shown, the path selection circuit 320a includes n path selectors 321a-32na and a voltage clamping circuit 313. The structure of each path selector 321a-32na is the same, and only the path selector 321a is described below.

[0141] The reference current path in the path selector 321a includes a switch transistor s11 and a control transistor s15. A first source / drain terminal of the control transistor s15 is connected to the current supply circuit 310, a gate terminal of the control transistor s15 receives a clamping voltage Vclamp, a first source / drain terminal of the switch transistor s11 is connected to a second source / drain terminal of the control transistor s15, a second source / drain terminal of the switch transistor s11 is connected to a node a1, and a gate terminal of the switch transistor s11 receives a reference current enable signal ENsa.

[0142] The memory cell current path in the path selector 321a includes a switch transistor s12 and a control transistor s16. A first source / drain terminal of the control transistor s16 is connected to the bit line BL1, a gate terminal of the control transistor s16 receives the clamping voltage Vclamp, a first source / drain terminal of the switch transistor s12 is connected to a second source / drain terminal of the control transistor s16, a second source / drain terminal of the switch transistor s12 is connected to the node a1, and a gate terminal of the switch transistor s12 receives the memory cell current enable signal ENcell.

[0143] Furthermore, the voltage clamp circuit 313 includes an operational amplifier 315, a switch transistor sc2, and a control transistor sc1. The positive input terminal of the operational amplifier 315 receives a bias voltage Vb, the negative input terminal of the operational amplifier 315 is connected to the first source / drain terminal of the control transistor sc1, and the output terminal of the operational amplifier 315 generates a clamp voltage Vclamp. The first source / drain terminal of the control transistor sc1 is connected to the current supply circuit 310, the gate terminal of the control transistor sc1 is connected to the output terminal of the operational amplifier 315, the first source / drain terminal of the switch transistor sc2 is connected to the second source / drain terminal of the control transistor sc1, the second source / drain terminal of the switch transistor sc2 is connected to a power supply voltage Vss, and the gate terminal of the switch transistor sc2 receives a clamp enable signal (ENclamp).

[0144] When the path selection circuit 320a operates, the clamp enable signal ENclamp is activated, and the negative input terminal of the operational amplifier 315 in the voltage clamp circuit 313 is fixed at the bias voltage Vb, and the bias voltage Vb differs from the clamp voltage Vclamp by a threshold voltage Vt. The threshold voltage Vt is the threshold voltage of the control transistor sc1, that is, Vb=Vclamp+Vt. Similarly, since the gate terminals of the other control transistors s15~sn5, s16~sn6 in the path selection circuit 320a also receive the clamp voltage Vclamp, the first source / drain terminals of the control transistors s15~sn5, s16~sn6 can also be fixed at about the bias voltage Vb.

[0145] like Fig. 10B As shown, the path selection circuit 320b includes n path selectors 321b-32nb and a voltage clamp circuit 314. The structure of each path selector 321b-32nb is the same, and only the path selector 321b is described below.

[0146] The reference current path in the path selector 321b includes a switch transistor s11 and a control transistor s15. A first source / drain terminal of the switch transistor s11 is connected to the current supply circuit 310, a gate terminal of the switch transistor s11 receives a reference current enable signal ENsa, a first source / drain terminal of the control transistor s15 is connected to a second source / drain terminal of the switch transistor s11, a second source / drain terminal of the control transistor s15 is connected to a node a1, and a gate terminal of the control transistor s15 receives a clamping voltage Vclamp.

[0147] The memory cell current path in the path selector 321b includes a switch transistor s12 and a control transistor s15. A first source / drain terminal of the switch transistor s12 is connected to the bit line BL1, a second source / drain terminal of the switch transistor s12 is connected to a first source / drain terminal of the control transistor s15, and a gate terminal of the switch transistor s12 receives a memory cell current enable signal ENcell.

[0148] Furthermore, the voltage clamp circuit 314 includes an operational amplifier 316, a switch transistor sc3 and a control transistor sc4. The positive input terminal of the operational amplifier 316 receives a bias voltage Vb, the negative input terminal of the operational amplifier 316 is connected to the first source / drain terminal of the control transistor sc4, and the output terminal of the operational amplifier 316 generates a clamp voltage Vclamp. The first source / drain terminal of the switch transistor sc3 is connected to the current supply circuit 310, the gate terminal of the switch transistor sc3 receives the clamp enable signal ENclamp, the first source / drain terminal of the control transistor sc4 is connected to the second source / drain terminal of the switch transistor sc3, the second source / drain terminal of the control transistor sc4 is connected to a power supply voltage Vss, and the gate terminal of the control transistor sc4 is connected to the output terminal of the operational amplifier 316.

[0149] When the path selection circuit 320b operates, the clamp enable signal ENclamp is activated, and the negative input terminal of the operational amplifier 316 in the voltage clamp circuit 314 is fixed at the bias voltage Vb, and the bias voltage Vb differs from the clamp voltage Vclamp by a threshold voltage Vt. The threshold voltage Vt is the threshold voltage of the control transistor sc4, that is, Vb=Vclamp+Vt. Similarly, since the gate terminals of the other control transistors s15~sn5 in the path selection circuit 320b also receive the clamp voltage Vclamp, the first source / drain terminals of the control transistors s15~sn5 can also be fixed at about the bias voltage Vb.

[0150] Similarly, the current supply circuit 310 can also receive the clamping voltage Vclamp output by the voltage clamping circuit 313 or the voltage clamping circuit 314. Fig.11 , which shows another embodiment of the current supply circuit. Figure 4A The current supply circuit 310 has the difference that a transistor mp is added between the node c and the current generator 420, the first source / drain terminal of the transistor mp is connected to the node c, the second source / drain terminal of the transistor mp is connected to the current generator 420, and the gate terminal of the transistor mp receives the clamping voltage Vclamp.

[0151] From the above description, it can be seen that the present invention provides a non-volatile memory with a multi-level memory cell array and a related programming control method. The present invention continuously performs write operations and verification operations during the programming cycle, so that when the programming cycle is completed, it can be confirmed that all memory cells on the selected row have reached the target storage state and can generate corresponding memory cell currents.

[0152] In summary, although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Those skilled in the art to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A non-volatile memory, comprising: A memory cell array, comprising m×n multi-level memory cells connected to m word lines and n bit lines, wherein each of the multi-level memory cells can be in one of X storage states, and X is greater than or equal to 4; a current supply circuit; A path selection circuit connected to the current supply circuit and the n bit lines, wherein the path selection circuit includes n path selectors, and the n path selectors are connected to the current supply circuit and the corresponding n bit lines; A verification circuit connected to the path selection circuit, wherein the verification circuit includes n verification elements connected to the corresponding n path selectors to generate n verification signals; as well as A control circuit receives the n verification signals; Wherein, during the sampling interval of the verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the n path selectors, which are transmitted to the n verification elements via the n path selectors and converted into n reference voltages; Wherein, during the verification interval of the verification action, the control circuit controls the n multi-level memory cells of the selected row to generate n memory cell currents, which are transmitted to the n verification elements via the n bit lines and the n path selectors and converted into n sensing voltages; The n verification elements generate the n verification signals according to the corresponding reference voltage and the corresponding sensing voltage, so that the control circuit determines whether the n multi-level memory cells reach the Mth storage state, wherein m, n, M and X are positive integers, and M is less than or equal to X.

2. The nonvolatile memory as claimed in claim 1, wherein the current supply circuit comprises: A first current replication circuit is connected between a power supply voltage and a node, wherein the first current replication circuit comprises n replication units connected between the power supply voltage and the node, each of the replication units comprises a current output terminal, and the n current output terminals of the n replication units are connected to the corresponding n path selectors; as well as A current generator is coupled to the node; The current generator selects the Mth reference current among the X reference currents to the n replication units, and during the verification operation, the first current replication circuit generates n Mth reference currents to the n path selectors.

3. The nonvolatile memory of claim 2, wherein a first copy unit among the n copy units comprises: a first transistor, a first source / drain terminal of the first transistor receiving the power supply voltage; a second transistor having a first source / drain terminal connected to a second source / drain terminal of the first transistor; a third transistor, a first source / drain terminal of the third transistor receiving the power supply voltage, and a gate terminal of the third transistor connected to the gate terminal of the first transistor; a fourth transistor, wherein a first source / drain terminal of the fourth transistor is connected to a second source / drain terminal of the third transistor, a gate terminal of the fourth transistor is connected to the gate terminal of the second transistor, and a second source / drain terminal of the fourth transistor is a current output terminal of the first replica unit; a capacitor having a first terminal connected to the gate terminal of the first transistor; a first switch, a first terminal of the first switch connected to the second source / drain terminal of the second transistor, and a second terminal of the first switch connected to the second terminal of the capacitor; as well as A second switch, a first terminal of the second switch is connected to the second source / drain terminal of the second transistor, and a second terminal of the second switch is connected to the node. 4 . The nonvolatile memory device as claimed in claim 3 , wherein the current generator receives a control signal and enables the Mth reference current among the X reference currents to be input to the node.

5. The nonvolatile memory as claimed in claim 3, wherein the current supply circuit further comprises a fifth transistor, a first source / drain terminal of the fifth transistor is connected to the node, a second source / drain terminal of the fifth transistor is connected to the current generator, and a gate terminal of the fifth transistor receives a clamping voltage.

6. The nonvolatile memory as claimed in claim 2, wherein the current supply circuit further comprises: A second current replication circuit includes n replication units connected to the corresponding n path selectors; as well as The current generator is coupled to the n copy units of the second current copy circuit; When the first current replication circuit outputs n of the Mth reference currents to the n path selectors, the second current replication circuit receives the (M+1)th reference current output by the current generator, so that the n replication units prepare n driving voltages for outputting n of the (M+1)th reference currents.

7. The nonvolatile memory as claimed in claim 1, wherein a first path selector among the n path selectors comprises a reference current path and a memory cell current path; The reference current path is controlled by a reference current enable signal; The memory cell current path is controlled by a memory cell current enable signal; When the reference current enable signal is activated, the reference current path is connected between the current supply circuit and the first verification element among the n verification elements; and when the memory cell current enable signal is activated, the memory cell current path is connected between the first bit line among the n bit lines and the first verification element.

8. A nonvolatile memory as described in claim 7, wherein the reference current path includes a first switch transistor; the memory cell current path includes a second switch transistor; the first source / drain terminal of the first switch transistor is connected to the current supply circuit, the second source / drain terminal of the first switch transistor is connected to the first verification element, and the gate terminal of the first switch transistor receives the reference current enable signal; and, the first source / drain terminal of the second switch transistor is connected to the first bit line, the second source / drain terminal of the second switch transistor is connected to the first verification element, and the gate terminal of the second switch transistor receives the memory cell current enable signal.

9. The nonvolatile memory as claimed in claim 7, further comprising a voltage clamping circuit connected to the current supply circuit and the path selection circuit, the voltage clamping circuit providing a clamping voltage to the path selection circuit to fix the reference current path of the first path selector and the memory cell current path at a bias voltage.

10. The nonvolatile memory as claimed in claim 9, wherein the reference current path comprises a first switch transistor and a first control transistor; the memory cell current path comprises a second switch transistor and a second control transistor; the voltage clamping circuit comprises an operational amplifier, a third switch transistor and a third control transistor; the first input terminal of the operational amplifier receives the bias voltage, the second input terminal of the operational amplifier is connected to the first source / drain terminal of the third control transistor, and the output terminal of the operational amplifier generates the clamping voltage; the first source / drain terminal of the third control transistor is connected to the current supply circuit, the gate terminal of the third control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the third switch transistor is connected to the second source / drain terminal of the third control transistor, the second source / drain terminal of the third switch transistor is connected to the power supply voltage, and the third switch transistor The gate terminal of the first control transistor receives the clamp enable signal; the first source / drain terminal of the first control transistor is connected to the current supply circuit, and the gate terminal of the first control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the first switch transistor is connected to the second source / drain terminal of the first control transistor, the second source / drain terminal of the first switch transistor is connected to the first verification element, and the gate terminal of the first switch transistor receives the reference current enable signal; and, the first source / drain terminal of the second control transistor is connected to the first bit line, and the gate terminal of the second control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the second switch transistor is connected to the second source / drain terminal of the second control transistor, the second source / drain terminal of the second switch transistor is connected to the first verification element, and the gate terminal of the second switch transistor receives the memory cell current enable signal.

11. The nonvolatile memory as claimed in claim 9, wherein the reference current path comprises a first switch transistor and a first control transistor; the memory cell current path comprises a second switch transistor and the first control transistor; the voltage clamping circuit comprises an operational amplifier, a third switch transistor and a second control transistor; the first input terminal of the operational amplifier receives the bias voltage, the second input terminal of the operational amplifier is connected to the first source / drain terminal of the second control transistor, and the output terminal of the operational amplifier generates the clamping voltage; the first source / drain terminal of the third switch transistor is connected to the current supply circuit, and the gate terminal of the third switch transistor receives the clamping enable signal; the first source / drain terminal of the second control transistor is connected to the second source / drain terminal of the third switch transistor, and the second The source / drain terminal is connected to the power supply voltage, and the gate terminal of the second control transistor is connected to the output terminal of the operational amplifier; the first source / drain terminal of the first switch transistor is connected to the current supply circuit, the gate terminal of the first switch transistor receives the reference current enable signal, the first source / drain terminal of the first control transistor is connected to the second source / drain terminal of the first switch transistor, the second source / drain terminal of the first control transistor is connected to the first verification element, and the gate terminal of the first control transistor is connected to the output terminal of the operational amplifier; and the first source / drain terminal of the second switch transistor is connected to the first bit line, the gate terminal of the second switch transistor receives the memory cell current enable signal, and the second source / drain terminal of the second switch transistor is connected to the first source / drain terminal of the first control transistor.

12. The non-volatile memory of claim 7, wherein the first verification element comprises: an operational amplifier having a first input terminal connected to the first path selector and an output terminal generating the first verification signal; A first switch having a first terminal connected to the first input terminal of the operational amplifier, a second terminal connected to a ground terminal, and a control terminal receiving a discharge enabling signal; A second switch having a first end connected to the output end of the operational amplifier, a second end connected to the second input end of the operational amplifier, and a control end receiving a closed-loop enabling signal; A first capacitor having a first end connected to the first input terminal of the operational amplifier and a second end connected to the ground terminal; as well as The second capacitor has a first end connected to the second input terminal of the operational amplifier and a second end connected to the ground terminal.

13. The nonvolatile memory as described in claim 12, wherein during the reference current sampling phase of the verification action, the Mth reference current charges the first capacitor to a first reference voltage, the closed-loop enable signal operates, so that the operational amplifier copies the first reference voltage to the second capacitor; during the memory cell current sampling phase of the verification action, the first memory cell current charges the first capacitor to a first sensing voltage; and the operational amplifier generates a first verification signal among the n verification signals based on the first reference voltage and the first sensing voltage. 14 . The nonvolatile memory as claimed in claim 13 , wherein during a discharge interval of the reference current sampling phase and a discharge interval of the memory cell current sampling phase, the discharge enable signal is activated so that the first capacitor is discharged to a ground voltage.

15. A method for controlling programming of a non-volatile memory as claimed in claim 1, comprising the following steps: Determining a selected row in the memory cell array and starting an Mth programming cycle for the selected row; Set M equal to 1; (a) the current supply circuit provides n M-th reference currents to the path selection circuit; (b) among the n memory cells in the selected row, inhibiting programming of the memory cells that have reached the target storage state; (c) among the n memory cells in the selected row, performing an Mth programming process on the memory cells that have not yet reached the target storage state; as well as (d) determining whether M is equal to X, wherein when M is not equal to X, increasing M by 1 and returning to step (a); and when M is equal to X, ending the Mth programming cycle.

16. The program control method as claimed in claim 15, wherein performing the Mth programming process further comprises the following steps: (c1) setting a first number and a first ratio, wherein the first number is a positive integer, and the first ratio is greater than zero and less than or equal to 1; (c2) programming the memory cell that inhibits reaching the Mth storage state; (c3) programming memory cells that have not yet reached the Mth storage state and performing the first number of write operations; (c4) determining whether a memory cell current of a memory cell reaches the first ratio multiplied by the Mth reference current among the memory cells being programmed; (c5) When step (c4) is not true, jump to step (c3); (c6) when step (c4) is satisfied, determining whether the first number and the first ratio are both not equal to 1; (c7) when both the first number and the first ratio are not equal to 1, reduce the first number and increase the first ratio, and jump to step (c2); (c8) when the first number and the first ratio are both equal to 1, determining whether all programmed memory cells have reached the Mth storage state; (c9) when step (c8) is not satisfied, jump to step (c2); and (c10) When step (c8) is established, the Mth programming process is ended. 17 . The program control method as claimed in claim 16 , wherein the first ratio is obtained by dividing the sampling interval by the verification interval.

18. The program control method as claimed in claim 16, wherein step (c7) further comprises the following steps: The first number is decreased and the first ratio is increased according to the content of the lookup table.

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