Semiconductor device and display device

Abstract

To improve an operation speed of a circuit.SOLUTION: There are provided: a first transistor; a second transistor in which a first terminal is connected to a gate of the first transistor, and has a function for setting a value of a potential of the gate of the first transistor to a value where the first transistor is ON; a third transistor that sets a value of the potential of the gate of the second transistor to a value where the second transistor is ON, and has a function for setting the gate of the second transistor to be in a floating state; and a fourth transistor that has a function for setting a value of the potential of the gate of the second transistor to a value where the second transistor is OFF. By such a construction, a potential difference between the gate and a source of the second transistor can be maintained so as to be a value that is larger than a threshold value voltage of the second transistor, and can improve an operation speed.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device, a display module, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Another aspect of the present invention relates to a semiconductor device, a display device, , a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof do. [Background technology]

[0003] Development of circuits that can be applied to drive circuits for memory devices, image sensors, display devices, etc. In particular, development of circuits consisting of transistors of the same polarity is active. A technology relating to such a circuit is disclosed in Patent Document 1.

[0004] In Patent Document 1, the potential difference between the gate and source of the transistor gradually decreases. The potential difference between the gate and source of the transistor is equal to the threshold voltage of the transistor. When this happens, the transistor turns off and the node inside the circuit becomes floating. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-050502 Summary of the Invention [Problem to be solved by the invention]

[0006] In a conventional circuit, the potential difference between the gate and source of a transistor gradually decreases. As a result, the drain current of the transistor also gradually decreases. It takes a long time for the potential to change, making it difficult to operate at high speed. It is necessary to increase the W / L ratio of the capacitor, making it difficult to reduce the layout area. In addition, it is difficult to shorten the rise time or fall time of the signal.

[0007] An object of one embodiment of the present invention is to provide a novel semiconductor device. One aspect of the present invention aims to provide a configuration that allows high-speed operation. Alternatively, one aspect of the present invention is to reduce or enable the layout area. Another object of one embodiment of the present invention is to provide a structure in which a driving voltage is reduced. It is an object of the present invention to provide a configuration that enables this. Aspects include a configuration that shortens the rise time or fall time of a signal or enables the same. One of our goals is to provide the following.

[0008] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but It is sufficient if the invention can solve one of the problems. Problems other than these will be obvious from the description, drawings, claims, etc. It becomes clear that the above-mentioned problems are not present in the specification, drawings, claims, etc. It is possible to extract it. [Means for solving the problem]

[0009] One embodiment of the present invention is a semiconductor device including first to fourth transistors. One of the source and drain of the transistor is electrically connected to the first wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the third transistor is electrically connected to a fourth wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the fourth transistor is electrically connected to the fifth wiring. The other of the source and drain of the fourth transistor is connected to the gate of the second transistor. It is electrically connected to the

[0010] One embodiment of the present invention is a semiconductor device including first to fourth transistors. One of the source and drain of the transistor is electrically connected to the first wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the third transistor is electrically connected to a third wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the fourth transistor is electrically connected to the fourth wiring. The other of the source and drain of the fourth transistor is connected to the gate of the second transistor. It is electrically connected to the

[0011] One embodiment of the present invention is a semiconductor device including first to fourth transistors. One of the source and drain of the transistor is electrically connected to the first wiring. The other of the source and drain of the second transistor is electrically connected to the second wiring. One of the source and drain of the second transistor is electrically connected to the third wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. One of the source and the drain of the third transistor is electrically connected to a fourth wiring. The other of the source and drain of the first transistor is electrically connected to the gate of the second transistor. The source or the drain of the fourth transistor is connected to the third wiring or the fourth wiring. The other of the source and drain of the fourth transistor is electrically connected to the line of the second transistor. The gate of the transistor is electrically connected to the gate of the transistor.

[0012] In the above embodiment of the present invention, the gate of the fourth transistor is connected to the first wiring or the second wiring. It may be connected to the wiring of 2.

[0013] One embodiment of the present invention is a display module including the above semiconductor device and an FPC.

[0014] One aspect of the present invention is a display device having the above-mentioned display module, an antenna, an operation button, or a speaker. It is an electronic device. [Effects of the Invention]

[0015] One embodiment of the present invention can provide a novel semiconductor device. It is possible to provide a configuration that allows high speed operation or high speed operation. One aspect of the invention is to reduce the layout area or to provide a configuration that makes it possible. Alternatively, one aspect of the present invention is to reduce the driving voltage or to make it possible to reduce the driving voltage. Alternatively, one aspect of the present invention can provide a configuration in which the rise time or A shorter fall time or a configuration that allows this can be provided.

[0016] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0017] [Figure 1] 1A to 1C illustrate an example of a semiconductor device. [Figure 2] 1A to 1C illustrate an example of a semiconductor device. [Figure 3] 1A to 1C illustrate an example of a semiconductor device. [Figure 4] 1A to 1C illustrate an example of a semiconductor device. [Figure 5] 1A to 1C illustrate an example of a semiconductor device. [Figure 6] 1A to 1C illustrate an example of a semiconductor device. [Figure 7] 1A to 1C illustrate an example of a semiconductor device. [Figure 8] 1A to 1C illustrate an example of a semiconductor device. [Figure 9] 1A to 1C illustrate an example of a semiconductor device. [Figure 10] 1A to 1C illustrate an example of a semiconductor device. [Figure 11]1A to 1C illustrate an example of a semiconductor device. [Figure 12] 1A to 1C illustrate an example of a semiconductor device. [Figure 13] 1A to 1C illustrate an example of a semiconductor device. [Figure 14] 1A to 1C illustrate an example of a semiconductor device. [Figure 15] 1A to 1C illustrate an example of a semiconductor device. [Figure 16] 1A to 1C illustrate an example of a semiconductor device. [Figure 17] 1A to 1C illustrate an example of a semiconductor device. [Figure 18] 1A to 1C illustrate an example of a semiconductor device. [Figure 19] 1A and 1B illustrate an example of a display device. [Figure 20] 1A to 1C illustrate an example of a semiconductor device. [Figure 21] 1A to 1C illustrate an example of a semiconductor device. [Figure 22] 1A to 1C illustrate an example of a semiconductor device. [Figure 23] 1A to 1C illustrate an example of a semiconductor device. [Figure 24] FIG. 2 is a diagram illustrating an example of a display module. [Figure 25] 1A to 1C illustrate examples of electronic devices. [Figure 26] 1A to 1C illustrate an example of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the embodiments, and should not be construed as departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications can be made to the form and details. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0019] Furthermore, one aspect of the present invention is applicable to any device including an RF tag, a display device, an integrated circuit, in addition to an imaging device. The device is included in its scope. In addition, display devices include liquid crystal display devices, light-emitting devices having light-emitting elements typified by organic light-emitting elements in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Pa nel), FED (Field Emission Display), etc., and display devices having integrated circuits are included in its scope.

[0020] In explaining the configuration of the invention using drawings, the same reference numerals may be commonly used among different drawings to indicate the same components.

[0021] Also, in this specification and the like, in the figures or sentences described in a certain embodiment, it is possible to extract a part thereof to form an aspect of the invention. Therefore, when a figure or sentence describing a certain part is described, the content obtained by extracting a part of that figure or sentence is also disclosed as an aspect of the invention and can form an aspect of the invention. And it can be said that that aspect of the invention is clear. Therefore, for example, in a figure or sentence in which an active element (such as a transistor), a wiring, a passive element (such as a capacitor element), a conductive layer, an insulating layer, a semiconductor layer, a component, a device, an operation method, a manufacturing method, etc. are described singly or plurally, it is possible to extract a part thereof to form an aspect of the invention. For example, from a circuit diagram configured with N (N is an integer) circuit elements (such as transistors, capacitor elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitor elements, etc.) to form an aspect of the invention. As another example, ​​​​​​​​​In the case of a sentence that reads "A has B, C, D, E, or F," By arbitrarily extracting elements from the above, we can say, "A has B and E," "A has E and F," , "A has C, E, and F," or "A has B, C, D, and E," etc. It is possible to constitute one aspect of the invention.

[0022] In addition, in this specification and the like, in a drawing or text that describes one embodiment, If at least one specific example is described, it is not possible to derive a generic concept of that specific example. This will be easily understood by those skilled in the art. When at least one specific example is described in a figure or text, the general outline of that specific example is The invention is also disclosed as an aspect of the invention and may constitute an aspect of the invention. Therefore, one aspect of the invention can be said to be clear.

[0023] In this specification, at least the contents shown in the drawings (or even a part of the drawings) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if something is shown in a diagram, it is not necessarily stated in words. However, the content is disclosed as one aspect of the invention and constitutes one aspect of the invention. Similarly, even if a part of the drawings is taken out, it can be regarded as one embodiment of the invention. This is disclosed as an embodiment of the present invention. It can be said that one aspect of the invention is clear.

[0024] In addition, regarding the contents not specified in the text or drawings in the specification, Alternatively, the upper limit of a certain value can be set. When a numerical range is listed, such as a lower limit, you can narrow the range arbitrarily. Or, by excluding one point within the scope, one aspect of the invention that excludes part of the scope is defined. As a result, for example, the prior art can be included within the technical scope of one aspect of the present invention. It can be stipulated that it will not be included.

[0025] In addition, in this specification, active elements (transistors, etc.), passive elements (capacitance elements, etc.) ) and the like, a person skilled in the art can easily identify the terminals to which they are connected without specifying the terminals. It may be possible to configure one aspect of the invention. It can be said that one aspect of the specification is clear. If the above is stated, it is understood that one aspect of the invention that does not specify the connection destination is described in this specification, etc. In particular, when there are multiple candidates for the terminal connection, There is no need to limit the connection of the terminal to a specific location. Only some terminals of passive elements (e.g., capacitors) and passive elements (e.g., capacitors) are connected. By specifying the destination, it may be possible to constitute one aspect of the invention.

[0026] In addition, in this specification and the like, if at least the connection destination of a certain circuit is specified, it is understood by those skilled in the art. It may be possible for a person skilled in the art to identify an invention. A person skilled in the art may be able to identify an invention by at least specifying the function. In other words, if the function is specified, it can be said that one aspect of the invention is clear. It may be possible to determine that one aspect of the invention is described in the present specification. Therefore, even if the function of a circuit is not specified, specifying the connection destination can be considered an aspect of an invention. and can constitute one aspect of the invention. Even if the connection destination of a certain circuit is not specified, if the function is specified, it can be considered as one aspect of the invention. What is disclosed can constitute an aspect of the invention.

[0027] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. do.

[0028] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, etc.). , etc.).

[0029] An example of a direct connection between X and Y is a circuit that allows electrical connection between X and Y. The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, When no external device (such as a diode, display element, light-emitting element, or load) is connected between X and Y, The elements that allow electrical connection between X and Y (e.g., switches, transistors, capacitors) elements, inductors, resistors, diodes, display elements, light-emitting elements, loads, etc.) , X and Y are connected.

[0030] An example of an electrical connection between X and Y is The elements to be considered (e.g., switches, transistors, capacitance elements, inductors, resistance elements, One or more devices (such as diodes, display elements, light-emitting elements, and loads) can be connected between X and Y. It is possible. The switch has a function to control on / off. A switch can be in a conducting state (ON state) or a non-conducting state (OFF state), allowing current to flow. The switch has the function of controlling whether or not the current flows. When X and Y are electrically connected, This includes the case where Y is directly connected.

[0031] An example of a functional connection between X and Y is a function that allows the functional connection between X and Y. Circuits that perform the above functions (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (voltage power supply circuits (voltage boost circuits, voltage drop circuits, etc.), level shifter circuits that change the signal potential level, etc.) , voltage source, current source, switching circuit, amplifier circuit (which can increase the signal amplitude or current amount, etc.) circuits, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation One or more circuits (e.g., memory circuits, control circuits, etc.) can be connected between X and Y. For example, even if another circuit is inserted between X and Y, the signal output from X If X is transmitted to Y, then X and Y are considered to be functionally connected. When X and Y are functionally connected, there is a direct connection between X and Y and a direct connection between X and Y. This also includes the case where the and are electrically connected.

[0032] In addition, if it is explicitly stated that X and Y are electrically connected, are electrically connected (i.e., there is another element or circuit between X and Y) X and Y are functionally connected (i.e., X and Y are functionally connected) and (When there is a functional connection between them via another circuit) and when X and Y are directly connected (i.e., when X and Y are connected without any other element or circuit between them) is considered to be disclosed in the present specification. If it is explicitly stated that it is connected, The same content is considered to be disclosed in the present specification.

[0033] For example, if the source (or first terminal, etc.) of the transistor is connected via Z1 (or (not shown), electrically connected to X, and the drain (or second terminal, etc.) of the transistor is connected to Z 2 (or not), and is electrically connected to Y, or the source of the transistor (or the first terminal, etc.) is directly connected to a part of Z1, and another part of Z1 is directly connected to X. The drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2. and another part of Z2 is directly connected to Y, It is possible to do so.

[0034] For example, "X and Y and the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor" The terminals of the transistor (or the first terminal) are electrically connected to each other. 1 terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y. It can be expressed as "connected to the source (or the first The first terminal of the transistor is electrically connected to X, and the drain of the transistor is electrically connected to the second terminal of the transistor. The transistor source (or first terminal, etc.) is electrically connected to Y, and the transistor source (or first terminal, etc.) is electrically connected to X. The drain (or second terminal, etc.) of the transistor, Y, is electrically connected in this order. " Alternatively, "X is the source (or first terminal, etc.) of the transistor. and the drain (or second terminal, etc.) are electrically connected to Y, and X, the source (or first terminal, etc.) of a transistor, the drain (or second terminal, etc.) of a transistor ), Y is provided in this order of connection. By specifying the order of connections in the circuit configuration using a simple expression method, Distinguish between the source (or first terminal, etc.) and the drain (or second terminal, etc.) of a transistor. The technical scope can be determined by the above.

[0035] Alternatively, for example, "the source (or first terminal, etc.) of a transistor" is electrically connected to X through at least a first connection path, and the first connection path is , and the second connection path is a transistor through a transistor. The source (or first terminal, etc.) of the transistor and the drain (or second terminal, etc.) of the transistor The first connection path is a path via Z1, and the second connection path is a path between the first and second transistors. The drain (or second terminal, etc.) of the capacitor is electrically connected to Y through at least a third connection path. the third connection path does not have the second connection path, and the third connection path The connection path is the path via Z2. The source (or first terminal, etc.) of the resistor is connected to the resistor via Z1 by at least the first connection path. and electrically connected to X, and the first connection path does not have a second connection path; The second connection path has a connection path through a transistor, and (or the second terminal, etc.) is connected to Y via Z2 by at least a third connection path. The third connection path does not have the second connection path. Alternatively, the source (or first terminal, etc.) of the transistor may be at least The first electrical path is electrically connected to X through Z1. The primary path does not have a second electrical path, and the second electrical path is a From the source (or first terminal, etc.) to the drain (or second terminal, etc.) of the transistor The drain (or second terminal, etc.) of the transistor is connected to at least a third The third electrical path is electrically connected to Y through Z2. , does not have a fourth electrical path, and the fourth electrical path is (or second terminal, etc.) to the source (or first terminal, etc.) of the transistor. Using the same expression as these examples, the circuit configuration By defining the connection path in Distinguishing between the first terminal (or the second terminal, etc.) and the drain (or the second terminal, etc.) to determine the technical scope. can be done.

[0036] These representation methods are merely examples, and the present invention is not limited to these representation methods. , Y, Z1, Z2 are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layer, etc.).

[0037] In addition, the circuit diagram shows independent components as if they are electrically connected to each other. Even if the components are different, one component may have the functions of multiple components. For example, when a part of the wiring also functions as an electrode, one conductive film functions as both the wiring and the electrode. Therefore, the electrode in this specification has the functions of both components. The term "electromagnetic connection" refers to a case where one conductive film has the functions of multiple components. This also falls within the scope of the above.

[0038] (Embodiment 1) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0039] The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. One embodiment of the invention is not limited to the configuration described below.

[0040] The semiconductor device illustrated in FIG. 1 includes a circuit 100. The circuit 100 includes a wiring 111, a wiring 113, and a The potential of the wiring 112 is controlled based on the potentials of the wirings 114 and 115. The circuit 100 is configured to operate based on the potentials of the wirings 111, 113, 114, and 115. The signal is output to the wiring 112. The potential of the wiring 112 is controlled by the signal. In this way, the circuit 100 has a function as a logic circuit or a sequential circuit.

[0041] The circuit 100 includes a transistor 101, a transistor 102, a transistor 103, a transistor The transistor 101 includes a transistor 104, a capacitor 105, and a capacitor 106. The first terminal (also referred to as one of the source and the drain) is connected to the wiring 111, and the second terminal The other of the source and the drain of the transistor 102 is connected to the wiring 112. The first terminal of the transistor 101 is connected to the wiring 113, and the second terminal of the transistor 101 is connected to the gate of the transistor 101. The transistor 103 has a first terminal connected to a wiring 114 and a second terminal connected to a transistor 105. The gate of the transistor 102 is connected to the wiring 114. The first terminal of the transistor 104 is connected to the wiring 115, and the second terminal of the transistor 102 is connected to the gate of the transistor 102. The capacitor 105 has a first terminal connected to the wiring 112 and a second terminal connected to the wiring 112. The first terminal of the capacitor 106 is connected to the gate of the transistor 101. The first terminal is connected to the gate of transistor 101, and the second terminal is connected to the gate of transistor 102.

[0042] The semiconductor device of this embodiment provides a novel configuration by having the above-described connection relationship. It is possible.

[0043] Note that the gate of the transistor 101, the second terminal of the transistor 102, and the capacitor 105 The second terminal of the transistor 102 or the first terminal of the capacitor 106 is referred to as a node ND1. the gate of transistor 102, the second terminal of transistor 103, the second terminal of transistor 104 The second terminal of the capacitor 106 is denoted as a node ND2.

[0044] The potentials of the wirings 111, 113, 114, and 115 are connected to the respective wirings by signals or The wiring 111, the wiring 113 and the wiring 114 are controlled by inputting a voltage or the like. The potential of the wiring 114 has a high level and a low level. 11, the wiring 113 and the wiring 114 are connected to a signal line having a high level and a low level. Then, the high level potential is VH and the low level potential is VL (VH The potential of the wiring 115 is VL. In other words, the wiring 115 may have a high level and a low level. A signal having a high level and a low level may be input.

[0045] The wiring 111, the wiring 113, and the wiring 114 may be called input terminals. The wiring 111, the wiring 112, the wiring 113, and the wiring 114 may be called output terminals. The wiring 114 may be called a signal line, and the wiring 115 may be called a power supply line.

[0046] Transistor 101, transistor 102, transistor 103, and transistor 104 However, one embodiment of the present invention is a transistor that can be used in the following cases. The transistors are not limited to those described below.

[0047] Transistor 101, transistor 102, transistor 103, and transistor 104 Examples of such transistors include those with amorphous silicon in the channel formation region, A transistor having polycrystalline silicon in the channel formation region, and a transistor having single-crystalline silicon in the channel formation region a transistor having an oxide semiconductor in a channel formation region; It is possible to use a transistor having a compound semiconductor in the composition region. A transistor having an oxide semiconductor in a channel formation region (also called an OS transistor) The mobility is higher than that of a transistor having amorphous silicon in the channel forming region, and The off-state current is extremely small. This allows the layout area to be reduced.

[0048] Transistor 101, transistor 102, transistor 103, and transistor 104 However, one embodiment of the present invention is a conductive type or polarity described below. Nor is it limited to polarity.

[0049] Transistor 101, transistor 102, transistor 103, and transistor 104 Preferably, all of the transistors in the circuit 100 have the same conductivity type. Preferably, the transistors are of the same conductivity type. Alternatively, the transistors may be provided on the same substrate as the circuit 100. It is preferable that all the transistors have the same conductivity type. This simplifies the manufacturing process and This can improve yield and reduce manufacturing costs.

[0050] In particular, transistor 101, transistor 102, transistor 103 and transistor The transistor 104 is preferably an N-channel transistor. are preferably all N-channel. Alternatively, they may be provided on the same substrate as the circuit 100. It is preferable that all the transistors are N-channel type. A transistor including an oxide semiconductor (also called an OS transistor) can be used for the FIG. 1 shows a transistor 101, a transistor 102, a transistor 103, and a The transistor 104 is an N-channel transistor. The transistor 101, the transistor 102, the transistor 103 and the transistor 104 are P-channel Alternatively, all the transistors in the circuit 100 may be P-channel. Alternatively, all transistors provided on the same substrate as the circuit 100 may be P-channel. 26 shows the transistor 101, the transistor 102, and the transistor 103 shown in FIG. The transistors 103 and 104 are connected to the transistors 101p and 101b. 10. The configuration shown is when the transistors 102p, 103p, and 104p are replaced with The transistor 101p, the transistor 102p, the transistor 103p, and the transistor 1. The capacitor 104p is a P-channel type. The N-channel transistors may be replaced with P-channel transistors.

[0051] For convenience, the transistors 101, 102, and 103 are N The description will be given assuming that it is a channel type.

[0052] Transistor 101, transistor 102, transistor 103, transistor 104, The functions of the capacitors 105 and 106 will be described. The aspects are not limited to the functions described below.

[0053] The transistor 101 controls conduction or non-conduction between the wiring 111 and the wiring 112. When the wiring 111 and the wiring 112 are electrically connected, the potential of the wiring 111 is supplied to the wiring 112, and the potential of the wiring 11 The potential of the wiring 111 is controlled based on the potential of the wiring 111. In particular, when the potential of the node ND1 is higher than the high level of the wiring 111, the potential of the wiring 112 increases. If the potential of the wiring 112 is higher than the sum of the potential of the transistor 101 and the threshold voltage of the transistor 101, If the potential of the wiring 111 is at a low level, the potential of the wiring 112 rises to VH. Descend to L.

[0054] The transistor 102 controls conduction or non-conduction between the wiring 113 and the node ND1. When the wiring 113 and the node ND1 are electrically connected, the potential of the wiring 113 is supplied to the node ND1. The potential of the node ND1 is controlled based on the potential of the wiring 113. In particular, the potential of the node ND2 increases when the potential of the wiring 113 If the value is higher than the sum of the high-level potential of the transistor 102 and the threshold voltage of the transistor 102, The potential of the node ND1 rises to VH. When the potential of the wiring 113 is at a low level, the node ND The potential of the node ND1 drops to VL. It is set to a value that turns it off.

[0055] The transistor 103 controls conduction or non-conduction between the wiring 114 and the node ND2. When the wiring 114 and the node ND2 are electrically connected, the potential of the wiring 114 is supplied to the node ND2. The potential of the node ND2 is controlled based on the potential of the wiring 114. If the gate of the transistor 103 is Since the node ND2 is connected to the wiring 114, the potential of the node ND2 is the high-level potential of the wiring 114. When the voltage rises to a value obtained by subtracting the threshold voltage of the transistor 103, the transistor 103 turns on. Then, the node ND2 is in a floating state. Thus, the potential of the node ND2 is The transistor 102 is set to a value that turns on, and the node ND2 is in a floating state. In addition, when the potential of the wiring 114 is at a low level, the transistor 103 is turned off. , the wiring 114 and the node ND2 are brought out of conduction.

[0056] As shown in FIG. 2A, the first terminal of the transistor 103 is connected to the wiring 116. The gate of the transistor 103 may be connected to the wiring 114. It is preferable that the potential of the wiring 116 is VH. In FIG. 2A, the transistor 103 is connected to the wiring 116 and the node N When the wiring 116 and the node ND2 are electrically connected, the wiring 1 The potential of the node ND2 is supplied to the node ND2 based on the potential of the wiring 116. When the potential of the wiring 116 is VH or a high level, the potential of the node ND2 is However, since the gate of the transistor 103 is connected to the wiring 114, The potential of the node ND2 is changed from the high level potential of the wiring 114 to the threshold voltage of the transistor 103. When the voltage rises to the value subtracted from the value of ND1, the transistor 103 turns off. Thus, the potential of the node ND2 becomes a value at which the transistor 102 is turned on. At the same time, node ND2 is set to a floating state.

[0057] As shown in FIG. 2B, the first terminal of the transistor 103 is connected to the wiring 114. In this case, the gate of the transistor 103 may be connected to the wiring 116. The transistor 103 controls conduction or non-conduction between the wiring 114 and the node ND2. When the wiring 114 and the node ND2 are electrically connected, the potential of the wiring 114 is supplied to the node ND2. The potential of the node ND2 is controlled based on the potential of the wiring 114. If the gate of the transistor 103 is connected to the node ND2, the potential of the node ND2 increases. Since the node ND2 is connected to the line 116, the potential of the node ND2 is changed from the potential of the wiring 116 to the potential of the transistor. When the voltage rises to a value less the threshold voltage of transistor 103, transistor 103 turns off. As a result, the node ND2 is in a floating state. The value of ND02 is set to ON, and the node ND2 is set to a floating state. If the potential of node ND14 is at a low level, the potential of node ND2 drops to VL. The potential of the node ND2 is set to a value that turns off the transistor 102.

[0058] As shown in FIG. 3A, the first terminal and the gate of the transistor 103 are connected to the wiring 11. 3. In FIG. 3A, the transistor 103 may be connected to the wiring 113 and the node N When the wiring 113 and the node ND2 are electrically connected, the wiring 1 The potential of the node ND2 is supplied to the node ND13 based on the potential of the wiring 113. When the potential of the wiring 113 is at a high level, the potential of the node ND2 increases. However, since the gate of the transistor 103 is connected to the wiring 113, the node ND The potential of 2 is the value obtained by subtracting the threshold voltage of the transistor 103 from the high-level potential of the wiring 113. When the voltage rises to , the transistor 103 is turned off. Then, the node ND2 is in a floating state. In this way, the potential of the node ND2 is set to a value that turns on the transistor 102. At the same time, the node ND2 is in a floating state. In this case, the transistor 104 is turned off, and therefore, the wiring 113 and the node ND2 are not electrically connected to each other. .

[0059] As shown in FIG. 3B, the first terminal of the transistor 103 is connected to the wiring 116. In this case, the gate of the transistor 103 may be connected to the wiring 113. The transistor 103 controls conduction or non-conduction between the wiring 116 and the node ND2. When the wiring 116 and the node ND2 are electrically connected, the potential of the wiring 116 is supplied to the node ND2. The potential of the node ND2 is controlled based on the potential of the wiring 116. When the potential of the wiring 116 is VH or If it is at a high level, the potential of the node ND2 increases. Since the port is connected to the wiring 113, the potential of the node ND2 is set to the high level of the wiring 113. When the potential of the transistor 103 is increased to a value obtained by subtracting the threshold voltage of the transistor 103 from the potential of the transistor 103, 3 is turned off, and the node ND2 is in a floating state. The potential is set to a value that turns on the transistor 102 and the node ND2 is in a floating state. becomes.

[0060] Although not shown, a first terminal of the transistor 103 is connected to a wiring 114. The gate of the transistor 103 may be connected to the wiring 113 .

[0061] Although not shown, a first terminal of the transistor 103 is connected to a wiring 113. The gate of the transistor 103 may be connected to the wiring 116 .

[0062] The transistor 104 controls conduction or non-conduction between the wiring 115 and the node ND2. When the wiring 115 and the node ND2 are electrically connected, the potential of the wiring 115 is supplied to the node ND2. The potential of the node ND2 is controlled based on the potential of the wiring 115. If V is at a low level, the potential of the node ND2 drops to VL. The potential of the second terminal is set to a value that turns off the transistor 102.

[0063] As shown in FIG. 4A, the first terminal of the transistor 104 is connected to the wiring 113. In FIG. 4A, the transistor 104 is connected to the wiring 113 and the node ND2. When the wiring 113 and the node ND2 are brought into electrical conduction, the potential of the wiring 113 is supplied to the node ND2, and the potential of the node ND2 is controlled based on the potential of the wiring 113. When the potential of the wiring 113 is VL or a low level, the potential of the node ND2 decreases to VL. In this way, the potential of the node ND2 is set to a value at which the transistor 102 is turned off. can be.

[0064] As shown in FIG. 4B, the first terminal of the transistor 104 is connected to the wiring 114. In FIG. 4B, the transistor 104 is connected to the wiring 114 and the node ND2. When the wiring 114 and the node ND2 are brought into electrical conduction, the potential of the wiring 114 is supplied to the node ND2, and the potential of the node ND2 is controlled based on the potential of the wiring 114. When the potential of the wiring 114 is VL or a low level, the potential of the node ND2 decreases to VL. In this way, the potential of the node ND2 is set to a value at which the transistor 102 is turned off. can be.

[0065] As shown in FIG. 5A, the gate of the transistor 104 is connected to the wiring 111. Good too.

[0066] As shown in FIG. 5B, the gate of the transistor 104 is connected to the wiring 112. Good too.

[0067] The capacitor 105 holds the potential difference between the wiring 112 and the node ND1. In the floating state, the potential of the node ND1 changes based on the change in the potential of the wiring 112. Therefore, if the potential of the node ND1 rises with the rise in the potential of the wiring 112, The potential of the first line is higher than the sum of the high-level potential of the wiring 111 and the threshold voltage of the transistor 101. It will become more expensive.

[0068] As shown in FIG. 6A, the capacitor 105 may be omitted. The parasitic capacitance between the second terminal and the gate of the The position difference is maintained.

[0069] The capacitor 106 holds the potential difference between the node ND1 and the node ND2. If it is in a floating state, the potential of node ND2 changes based on the change in the potential of node ND1. Therefore, if the potential of the node ND2 rises in accordance with the rise in the potential of the node ND1, The potential of the node ND2 is the sum of the high-level potential of the wiring 113 and the threshold voltage of the transistor 102. It will be higher than.

[0070] 6B, the capacitor 106 may be omitted. The parasitic capacitance between the second terminal of The potential difference is maintained.

[0071] Note that transistor 101, transistor 102, transistor 103, and transistor 1 04, the capacitor 105 and the capacitor 106 do not need to have all of the above functions.

[0072] The circuit 100 illustrated and described in FIGS. 1, 2, 3, 4, 5, and 6, etc., and Although not shown, the circuits 100 described above can be combined as appropriate.

[0073] The operation of the semiconductor device of this embodiment will be described using the configuration of FIG. One aspect of the invention is not limited to the operations described below.

[0074] The timing chart in FIG. 7 shows the potential of the wiring 111, the potential of the wiring 113, the potential of the wiring 114, and the potential, on / off of the transistor 104, the potential of the node ND1, the potential of the node ND2, 11 and an example of the potential of the wiring 112.

[0075] For convenience, the explanation will be divided into four periods: Period T1, Period T2, Period T3, and Period T4. For example, one frame period has periods T1 to T4.

[0076] For convenience, in the period T0 immediately before the period T1, the potential of the wiring 111 is low. The potential of the wiring 113 is at a low level, the potential of the wiring 114 is at a low level, and the potential of the node The potential of the node ND1 is VL, the potential of the node ND2 is VL, and the potential of the wiring 112 is VL In addition, since the potential of the node ND1 is VL, the transistor 101 In addition, since the potential of the node ND2 is VL, the transistor 102 is off. be.

[0077] The operation in the period T1 will be described with reference to FIG. The potential of the wiring 113 remains at a low level, and the potential of the wiring 114 remains at a high level. changes from low to high, and transistor 104 remains off.

[0078] The potential of the wiring 114 becomes high, turning on the transistor 103. Since the high-level potential of the wiring 114 is supplied to the node ND2, the potential of the node ND2 Rise from VL.

[0079] After that, the potential of the node ND2 becomes equal to the potential (VL) of the first terminal of the transistor 102. The sum of the threshold voltage of the resistor 102 (Vth102) and the voltage of the resistor 103 (VL+Vth102) becomes higher. Therefore, the low-level potential of the wiring 113 is applied to the node Since the potential of the node ND1 is supplied to the node ND1, the potential of the node ND1 remains at VL. The potential of the wiring remains at VL, so the transistor 101 remains off. The potential of 112 remains at VL.

[0080] After that, the potential of the node ND2 changes from the potential (VH) of the gate of the transistor 103 to the potential (VH) of the transistor 104. The voltage rises to a value (VH-Vth103) obtained by subtracting the threshold voltage (Vth103) of the transistor 103. Therefore, the node ND2 is in a floating state, and the node The potential of ND2 is maintained at VH-Vth103.

[0081] In FIG. 2A, the first terminal of the transistor 103 is connected to the wiring 116. Therefore, the potential of the wiring 116 (for example, VH) is supplied to the node ND2.

[0082] The operation in the period T2 will be described with reference to FIG. The potential of the wiring 113 changes from low to high, and the potential of the wiring 114 changes from low to high. The potential of 14 changes from high to low, and transistor 104 remains off. do.

[0083] Since the potential of the wiring 114 becomes low, the transistor 103 remains off. As a result, the node ND2 remains in a floating state, and the potential of the node ND2 is VH-Vth103 In addition, the potential of the node ND2 remains at VH-Vth103. Therefore, the high-level potential of the wiring 113 is applied to the node N Since the potential of the node ND1 is supplied to the capacitor element 1, the potential of the node ND1 rises from VL. 06 maintains the potential difference between the node ND1 and the node ND2, and the node ND2 is floating. Therefore, as the potential of the node ND1 rises, the potential of the node ND2 falls to VH- It rises from Vth103.

[0084] After that, the potential of the node ND1 becomes equal to the potential (VL) of the first terminal of the transistor 101. The sum of the threshold voltage of the resistor 101 (Vth101) and the voltage of the resistor 102 (VL+Vth101) becomes higher. Therefore, the low-level potential of the wiring 111 is applied to the wiring 1 12, the potential of the wiring 112 remains at VL.

[0085] Thereafter, as the potential of the node ND1 rises, the potential of the node ND2 rises The sum of the potential (VH) of the first terminal of the transistor 102 and the threshold voltage (Vth102) of the transistor 102 is When the voltage rises to a value higher than the threshold voltage (VH+Vth102+α (α is a positive number)), the voltage at node ND1 The potential rises to VH.

[0086] In FIG. 2B, in order to keep the transistor 103 off, Therefore, it is preferable that the potential of the wiring 114 remains at a high level.

[0087] 3A and 3B, the transistor 103 is turned on during the period T2. Specifically, when the potential of the wiring 113 becomes high, 3A, the high level of the wiring 113 is The potential of the node ND2 is supplied to the node ND2, and the potential of the node ND2 rises from VL. In (B), the potential of the wiring 116 (for example, VH) is supplied to the node ND2. After that, the potential of the node ND2 rises from VL. As a result, the high-level potential of the wiring 113 The potential of the node ND1 rises from VL. When the potential of node ND2 becomes VH-Vth103, the transistor 103 is turned off, and 2 is in a floating state. At this time, the potential of the node ND1 rises. 106 holds the potential difference between the node ND1 and the node ND2. As the potential at node ND1 rises, the potential at node ND2 rises from VH-Vht103. When the potential of the node ND1 becomes higher than VL+Vth101, the transistor 101 is turned on. Therefore, the low-level potential of the wiring 111 is supplied to the wiring 112. The potential of the node ND1 then rises, and the potential of the node ND2 also rises. When the potential of ND2 rises to VH+Vth102+α, the potential of node ND1 rises to VH. In this way, in Fig. 3(A) and Fig. 3(B), the Therefore, the operation speed can be improved. This can be achieved.

[0088] The operation in the period T3 will be described with reference to FIG. The potential of the wiring 113 changes from high level to low level. However, the potential of the wiring 114 remains at a low level, and the transistor 104 changes from off to on. Change.

[0089] Since the potential of the wiring 114 remains at a low level, the transistor 103 remains off. In addition, the transistor 104 is turned on. Therefore, the potential of the wiring 115 is increased to the potential of the node ND2 , the potential of the node ND2 drops from VH+Vth102+α to VL. The potential of the node ND2 becomes VL, so that the transistor 102 is turned off. The node ND1 is in a floating state, and the potential of the node ND1 remains at VH. Since the potential remains at VH, the transistor 101 remains on. Since a high-level potential of 1 is supplied to the wiring 112, the potential of the wiring 112 rises from VL. At this time, the capacitor 105 holds the potential difference between the wiring 112 and the node ND1. The node ND1 is in a floating state. The potential of the node ND1 rises from VH.

[0090] After that, as the potential of the wiring 112 increases, the potential of the node ND1 increases to the first potential of the transistor 101. than the sum of the potential of the terminal (VH) of transistor 101 and the threshold voltage (Vth101) of transistor 101. When the potential of the wiring 112 rises to a high value (VH+Vth101+β (β is a positive number)), It rises to VH.

[0091] In FIG. 4A, the first terminal of the transistor 104 is connected to the wiring 113. Therefore, the low-level potential of the wiring 113 is supplied to the node ND2. Since the first terminal of the transistor 104 is connected to the wiring 114, A low level potential is supplied to the node ND2.

[0092] The operation in the period T4 will be described with reference to FIG. 9B. The potential of the wiring 113 changes from high to low, and the potential of the wiring 113 remains low. The potential of 14 changes from low to high, and the transistor 104 changes from on to off. Change.

[0093] The potential of the wiring 114 becomes high, turning on the transistor 103. The high-level potential of the wiring 114 is supplied to the node ND2, and the potential of the node ND2 rises. At this time, the potential of the node ND1 is VH+Vth101+β, so that the transistor Therefore, the low-level potential of the wiring 111 is supplied to the wiring 112. Therefore, the potential of the wiring 112 drops from VH to VL.

[0094] After that, the potential of the node ND2 becomes equal to the potential (VL) of the first terminal of the transistor 102. When the voltage Vth102 exceeds the sum of the threshold voltages (Vth102) of the transistors 102, Therefore, the low-level potential of the wiring 113 is supplied to the node ND1. , the potential of the node ND1 drops from VH+Vth101+β to VL. Since the potential of 1 becomes VL, the transistor 101 is turned off.

[0095] After that, the potential of the node ND2 changes from the potential (VH) of the gate of the transistor 103 to the potential (VH) of the transistor 104. When the voltage rises to a value obtained by subtracting the threshold voltage (Vth103) of the transistor 103, Therefore, the node ND2 is in a floating state, and the potential of the node ND2 is VH-V Maintained in ht103.

[0096] In FIG. 2A, the first terminal of the transistor 103 is connected to the wiring 116. Therefore, the potential of the wiring 116 (for example, VH) is supplied to the node ND2.

[0097] The semiconductor device of this embodiment has a connection relationship that enables the above-described operation. , the potential of the node ND2 can be set to VH+Vth102+α.

[0098] In the semiconductor device of this embodiment, the potential of the node ND2 is set to VH+Vth102+α. This reduces the potential difference between the gate and source of transistor 102 to the threshold voltage of transistor 102. The voltage can be maintained at a value greater than the threshold voltage.

[0099] In the semiconductor device of this embodiment, the potential difference between the gate and source of the transistor 102 is By maintaining the potential of the node ND1 at a value greater than the threshold voltage of the transistor 102, can be increased to VH.

[0100] In the semiconductor device of this embodiment, the potential difference between the gate and source of the transistor 102 is By keeping the voltage at node ND1 greater than the threshold voltage of transistor 102, This can shorten the time required for the potential to change.

[0101] In the semiconductor device of this embodiment, the potential of the node ND1 is increased to VH, The potential difference between the gate and source of the transistor 101 can be increased.

[0102] In the semiconductor device of this embodiment, the potential difference between the gate and source of the transistor 101 is large. By increasing the value of the potential difference, the time required for the potential change in the wiring 112 can be shortened. That is, a signal with a short rise time and fall time is output to the wiring 112. can be done.

[0103] The semiconductor device of this embodiment has a gate and a solenoid of a transistor 101 and a transistor 102. By increasing the potential difference between the source and the electrode, the driving voltage can be reduced. This makes it possible to reduce power consumption.

[0104] The semiconductor device of this embodiment has a gate and a solenoid of a transistor 101 and a transistor 102. By increasing the potential difference between the transistor 101 and the transistor 10 This allows the channel width of MOSFET 2 to be reduced, thereby reducing the layout area. This can be done.

[0105] The semiconductor device of this embodiment has a time required for the potential at the node ND1 to change and a wiring The time required for the potential change in 112 can be shortened, which improves the operating speed. This can be achieved.

[0106] Transistor 101, transistor 102, transistor 103, and transistor 104 The W (W is the channel width) / L (L is the channel length) will be explained. The embodiment is not limited to the W / L described below.

[0107] The transistor 101 drives the wiring 112, and the transistor 102 drives the node ND1. The transistors 103 and 104 drive the node ND2. The load on 112 is often larger than the load on nodes ND1 and ND2. , the W / L of the transistor 101 is It is preferable that the W / L of the transistor 104 is larger than that of the transistor 104. It is preferable that the W / L of the transistor 101 is the largest among the other transistors. Among the transistors mounted on the same substrate as 100, transistor 101 has the highest W / L. However, it is preferable that the W / L of the transistor 101 is the same as or approximately the same as that of the transistor 101. In this way, the driving capability of the transistor 101 can be increased. Therefore, the load on the wiring 112 can be increased. Since the sizes of the transistors 102, 103, and 104 can be reduced, the layout The out area can be reduced.

[0108] Even if the potential of the node ND1 rises, the potential difference between the gate and source of the transistor 102 can be maintained at a value equal to or greater than the threshold voltage of transistor 102. On the other hand, when the potential of node ND2 rises, The potential difference between the gate and source of transistor 103 gradually decreases, It is preferable that the W / L of the transistor 103 is large. Therefore, the W / L of the transistor 103 is It is preferable that the W / L of the transistor 102 is larger than that of the transistor 10. 3 can be increased, so that the time required for the potential change at node ND2 can be reduced. Furthermore, the size of the transistor 102 can be reduced. Therefore, the layout area can be reduced. The W / L may be greater than the W / L of the transistor 103 .

[0109] The circuit 100 shown and described in FIGS. 1, 2, 3, 4, 5, 6, etc. The transistors that can be added to the circuit 100 described above and to combinations thereof are However, one embodiment of the present invention is not limited to the configuration described below. .

[0110] A transistor 107 may be added to the circuit 100 described above. The circuit 100 is configured to include a transistor 107. , the first terminal is connected to the wiring 115B, and the second terminal is connected to the wiring 112. The potential of the wiring 115B is preferably VL. However, the potential of the wiring 115B is set to a high level. The transistor 107 may have a low level. When the transistor 107 is turned on, the wiring 115B and the wiring The potential of the wiring 112 is controlled based on the potential of the wiring 115B. When the potential of 115B is VL or a low level, the potential of the wiring 112 becomes VL. The transistor 107 preferably has the same polarity as the transistors 101 to 104. .

[0111] In the period T1, the transistor 107 is turned on. Therefore, the potential of the wiring 115B is Since the potential of the wiring 112 is supplied to the wiring 112, the potential of the wiring 112 becomes VL. , transistor 107 may be off.

[0112] In the period T2, the transistor 107 is turned on. Therefore, the potential of the wiring 115B is Since the potential of the wiring 112 is supplied to the wiring 112, the potential of the wiring 112 becomes VL. , transistor 107 may be off.

[0113] During period T3, transistor 107 is turned off.

[0114] In the period T4, the transistor 107 is turned on. Since the potential of the wiring 112 is supplied to the wiring 112, the potential of the wiring 112 becomes VL. The transistor 107 may be off.

[0115] In FIG. 10A, the circuit 100 includes the transistor 107, and the wiring 112 is floating. This prevents the wiring 112 from becoming loose and stabilizes the potential of the wiring 112. This can help prevent such acts.

[0116] Note that the first terminal of the transistor 107 is connected to the wiring 111, the wiring 113, the wiring 114, or the wiring 115. The gate of the transistor 107 may be connected to a wiring 113 or a wiring 115. It may be connected to line 114.

[0117] A transistor 108 may be added to the circuit 100 described above. The circuit 100 is configured to include a transistor 108. , a first terminal is connected to the wiring 115C, and a second terminal is connected to the node ND1. The potential of the wiring 115C is preferably VL. However, the potential of the wiring 115C is high level. and a low level. When the transistor 108 is turned on, it controls conduction or non-conduction between the wiring 115C and the The potential of the node ND1 is controlled based on the potential of the wiring 115C. If the potential of the wiring 115C is VL or low, the potential of the node ND1 becomes VL. In this way, the potential of the node ND1 is set to a value that turns off the transistor 101. The transistor 108 has the same polarity as the transistors 101 to 104. preferable.

[0118] In the period T1, the transistor 108 is turned on. Therefore, the potential of the wiring 115C is The potential of the node ND1 becomes VL. However, during the period T1, The transistor 108 may be off.

[0119] During period T2, transistor 108 is turned off.

[0120] During period T3, transistor 108 is turned off.

[0121] In the period T4, the transistor 108 is turned on. The potential of the node ND1 becomes VL. However, during the period T4, The transistor 108 may be off.

[0122] FIG. 10B shows that the circuit 100 includes the transistor 108, and the node ND1 This prevents the node ND1 from being in a floating state, and stabilizes the potential of the node ND1. Malfunctions can be prevented.

[0123] Note that the first terminal of the transistor 108 is connected to the wiring 111, the wiring 113, the wiring 114, or the wiring 115. The gate of the transistor 108 may be connected to the line 115. The gate of the transistor 108 may be connected to the wiring 114. This may be done.

[0124] Note that when both the transistor 107 and the transistor 108 are added to the circuit 100, Alternatively, the gate of the transistor 107 and the gate of the transistor 108 may be connected. Alternatively, the first terminal of the transistor 107 and the first terminal of the transistor 108 are connected together. That's fine.

[0125] The circuit 100 described above may include the addition of either or both of a transistor 107 and a transistor 108. In addition, a transistor 109 and a transistor 110 may be added. (A) shows a circuit 100 shown in FIG. 1, to which a transistor 107 and a transistor 108 are added. 10A and 10B, and also shows a configuration in which a transistor 109 and a transistor 110 are added. The first terminal of the transistor 109 is connected to the wiring 116, and the second terminal of the transistor 109 is connected to the wiring 116. The gate of the transistor 107 is connected to the gate of the transistor 108, and the gate is connected to the wiring 114. The transistor 110 has a first terminal connected to a wiring 114 and a second terminal connected to a transistor 115. The gate of the transistor 107 is connected to the gate of the transistor 108, and the gate is connected to the node The gate of transistor 107, the gate of transistor 108, and the gate of transistor ND1 are connected to each other. The second terminal of the transistor 109 or the second terminal of the transistor 110 is designated as a node ND3. The transistor 109 controls conduction or non-conduction between the wiring 116 and the node ND3. When the transistor 109 is turned on, the wiring 116 and the node ND3 are electrically connected, and the node ND3 The potential of the wiring 116 is controlled based on the potential of the wiring 116. If the gate of the transistor 109 is connected to the node ND3, the potential of the node ND3 increases. Since the node ND3 is connected to the line 114, the potential of the node ND3 is lower than the high-level potential of the line 114. When the voltage rises to a value obtained by subtracting the threshold voltage of the transistor 109 from the voltage, the transistor 109 turns off. Then, the node ND3 is in a floating state. The transistor 107 or the transistor 108 is set to a value that turns on, and the node The transistor 110 is connected between the wiring 114 and the node ND3. When the transistor 110 is turned on, the wiring 114 and the node ND The potential of the node ND3 is controlled based on the potential of the wiring 114. If the potential of node ND4 is at a low level, the potential of node ND3 drops to VL. The potential of the node ND3 is set to a value that turns off the transistor 107 or the transistor 108. The transistor 109 and the transistor 110 are the same as the transistors 101 to 106. It is preferably of the same polarity as 104.

[0126] In the period T1, the wiring 114 is at a high level, and the transistor 109 is turned on. In addition, the potential of the node ND1 becomes VL, so that the transistor 110 is turned off. As a result, the potential of the wiring 116 is supplied to the node ND3, and the potential of the node ND3 rises from VL. After that, the potential of the node ND3 becomes equal to the potential (VL) of the first terminal of the transistor 107. When the voltage becomes higher than the sum of the threshold voltage (Vth107) of the transistor 107, The potential of the node ND3 is turned on. When the voltage VL becomes higher than the sum of the potential VL and the threshold voltage Vth108 of the transistor 108, The transistor 108 is turned on. After that, the potential of the node ND3 is The gate potential (VH) is subtracted from the threshold voltage (Vth109) of transistor 109. Therefore, the node ND3 is in a floating state, and the transistor 109 is turned off. The potential of the node ND3 is maintained at VH-Vth109.

[0127] In the period T2, the potential of the wiring 114 becomes low, and the transistor 109 is turned on. In addition, the potential of the node ND1 becomes equal to the potential (VL) of the first terminal of the transistor 110. and the threshold voltage (Vth110) of the transistor 110, Therefore, the low-level potential of the wiring 114 is supplied to the node ND3. As a result, the potential of the node ND3 drops from VH-Vth109 to VL. Transistor 107 and transistor 108 are turned off.

[0128] In the period T3, the potential of the wiring 114 remains at a low level. 9 remains off. Also, the potential of node ND1 becomes VH+Vth110+β. Therefore, the low-level potential of the wiring 114 is The potential of the node ND3 remains at VL. 107 and transistor 108 remain off.

[0129] In the period T4, the potential of the wiring 114 becomes high, and the transistor 109 is turned on. In addition, the potential of the node ND1 becomes VL, and the transistor 110 is turned off. Therefore, the potential of the wiring 116 is supplied to the node ND3, and the potential of the node ND3 is increased from VL. After that, the potential of the node ND3 rises to the potential of the first terminal of the transistor 107 (V When the voltage Vth107 exceeds the sum of the threshold voltage (Vth107) of the transistor 107, The potential of the node ND3 is applied to the first terminal of the transistor 108. The potential (VL) of the transistor 108 is higher than the sum of the threshold voltage (Vth108) of the transistor 108. This turns on transistor 108.

[0130] FIG. 11A shows that the circuit 100 includes a transistor 109 and a transistor 110. This generates a signal in the circuit 100 that controls the transistor 107 or the transistor 108. Therefore, the number of signals can be reduced.

[0131] As shown in FIG. 11B, the gate of the transistor 109 and the gate of the transistor 110 The first terminal of the wiring 117 may be connected to the wiring 117. The potential of the wiring 117 is at a high level (for example, VH) and a low level (for example, VL).

[0132] Note that the gate of the transistor 109 is connected to the wiring 117, and the first The terminal of the transistor 109 may be connected to the wiring 114. 14, and the first terminal of the transistor 110 may be connected to the wiring 117.

[0133] The second terminal of the transistor 109 and the second terminal of the transistor 110 are connected to the transistor The gate of the transistor 107 and the gate of the transistor 108 are Alternatively, the second terminal of the transistor 109 and the second terminal of the transistor 108 may be connected to the The second terminal of 110 is connected to the gate of transistor 107 and the gate of transistor 108. Of these, only the gate of the transistor 108 may be connected.

[0134] The first terminal of the transistor 110 is connected to the wiring 115, the wiring 115B, the wiring 115C, or the It may be connected to the wiring 117.

[0135] A transistor 121 may be added to the circuit 100 described above. The circuit 100 shown in FIG. 1 includes a transistor 121. 1 has a first terminal connected to the wiring 112, a second terminal connected to the node ND1, and a gate The transistor 121 is connected to the wiring 112 and the node ND1. When the transistor 121 is turned on, the wiring 112 and the node ND For example, in a period T3, the potential of the wiring 112 rises from VL and When the potential of the node ND1 rises from VH, the rise in the potential of the node ND1 is suppressed. In both cases, the time required for the potential of the wiring 112 to change is shortened. Since the gate of the wiring 112 is connected to the wiring 111, the potential of the wiring 112 is the high level of the wiring 111. When the potential of the transistor 121 is equal to the potential of the capacitor minus the threshold voltage of the transistor 121, the transistor 121 Also, the transistor 121 is turned off with the same polarity as the transistors 101 to 104. It is preferable that there is.

[0136] In the period T1, the wiring 111 is at a low level, so that the transistor 121 is turned off. do.

[0137] In the period T2, the wiring 111 is at a low level, so that the transistor 121 is turned off. do.

[0138] In the period T3, the wiring 111 is at a high level, and the transistor 121 is turned on. However, when the potential of the wiring 112 is changed from the potential (VH) of the gate of the transistor 121 to the potential (VH) of the transistor 122, When the voltage rises to a value obtained by subtracting the threshold voltage (Vth121) of transistor 121, 1 is turned off.

[0139] In the period T4, the wiring 111 is at low level, and the transistor 121 is turned off. do.

[0140] 12A, the circuit 100 includes the transistor 121, and thus the Therefore, the potential connected to the node ND1 can be prevented from becoming too high. This makes it possible to suppress deterioration of the transistor or prevent breakdown of the transistor.

[0141] A transistor 122 may be added to the circuit 100 described above. The circuit 100 shown in FIG. 1 includes a transistor 122. 2 has a first terminal connected to a node ND1, a second terminal connected to a node ND2, and The output terminal of the transistor 122 is connected to the wiring 113. The transistor 122 is connected to the nodes ND1 and ND2. When the transistor 122 is turned on, the node ND1 and the node For example, during a period T2, the potential of the node ND1 rises from VL. When the potential of the node ND2 rises from VH-Vth103, The rise in potential is suppressed, and the time required for the potential of the node ND1 to change is shortened. However, since the gate of the transistor 122 is connected to the wiring 113, the node ND1 The potential of the wiring 113 becomes equal to the high-level potential of the wiring 113 minus the threshold voltage of the transistor 122. When this happens, the transistor 122 is turned off. It is preferable that the polarity is the same as that of 101 to 104.

[0142] In the period T1, the wiring 113 is at a low level, and the transistor 122 is turned off. do.

[0143] In the period T2, the wiring 113 is set to a high level, and the transistor 122 is turned on. However, when the potential of the node ND1 is changed from the potential (VH) of the gate of the transistor 122, When the voltage rises to a value obtained by subtracting the threshold voltage (Vth122) of transistor 122, 22 will be turned off.

[0144] In the period T3, the wiring 113 is at a low level, and the transistor 122 is turned off. do.

[0145] In the period T4, the wiring 113 is at a low level, and the transistor 122 is turned off. do.

[0146] FIG. 12B shows that the circuit 100 includes the transistor 122, which reduces the Therefore, the potential connected to the node ND2 can be prevented from becoming too high. This makes it possible to suppress deterioration of the transistor or prevent breakdown of the transistor.

[0147] A transistor 123 may be added to the circuit 100 described above. The circuit 100 shown in FIG. 1 includes a transistor 123. 3 has a first terminal connected to the wiring 111 and a second terminal connected to the node ND1. The transistor 123 controls conduction or non-conduction between the wiring 111 and the node ND1. When the resistor 123 is turned on, the wiring 111 and the node ND1 are brought into electrical continuity, and the potential of the wiring 111 When the potential of the wiring 111 is at a low level, the potential of the node ND1 is supplied to the node ND1. In this way, the potential of the node ND1 becomes VL. The transistor 123 is set to the same value as the transistors 101 to 104. It is preferably polar.

[0148] In the period T0, the transistor 123 is turned on. The potential of the node ND1 is supplied to the node ND1, and the potential of the node ND1 becomes VL.

[0149] During periods T1, T2, T3, and T4, the transistor 123 is turned off. .

[0150] 13A, the circuit 100 includes the transistor 123, and thus the The potential can be set to VL, thereby preventing malfunction.

[0151] A transistor 124 may be added to the circuit 100 described above. The circuit 100 shown in FIG. 1 includes a transistor 124. 4 has a first terminal connected to the wiring 113 and a second terminal connected to the node ND2. The transistor 124 controls conduction or non-conduction between the wiring 113 and the node ND2. When the resistor 124 is turned on, the wiring 113 and the node ND2 are brought into electrical continuity, and the potential of the wiring 113 When the potential of the wiring 113 is at a low level, the potential of the node ND2 is supplied to the node ND2. In this way, the potential of the node ND2 becomes VL. The transistor 124 is set to the same value as the transistors 101 to 104. It is preferably polar.

[0152] In the period T0, the transistor 124 is turned on. The potential of the node ND2 is supplied to the node ND2, and the potential of the node ND2 becomes VL.

[0153] During periods T1, T2, T3, and T4, transistor 124 is turned off. .

[0154] FIG. 13B shows that the circuit 100 includes the transistor 124, which reduces the The potential can be set to VL, thereby preventing malfunction.

[0155] Note that when both the transistor 123 and the transistor 124 are added to the circuit 100, The gate of the transistor 123 and the gate of the transistor 124 may be connected together.

[0156] 1, 2, 3, 4, 5, 6, 10, 11, 12, 13, etc. The circuits 100 described as well as circuits 100 not shown can be freely combined. It is possible.

[0157] FIG. 14A shows a transistor in which the first terminal and the gate of the transistor 103 are connected to the wiring 113. 3A) and a structure in which the gate of the transistor 104 is connected to the wiring 111. (See FIG. 5(A)) and the above.

[0158] FIG. 14B shows a configuration in which the gate of the transistor 104 is connected to the wiring 111 (FIG. 5A). )), a configuration in which the transistor 108 is added (see FIG. 10B), and a configuration in which the transistor 11B) and a combination of the above. This is the case configuration.

[0159] Note that this embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. The contents (or even a part of the contents) described in this embodiment may be used in conjunction with other embodiments described in the embodiment. The content (or even part of the content) and / or the content described in one or more other embodiments To apply, combine, or replace the content (or even part of the content) The contents described in the embodiments are various in each embodiment. This refers to content that is described using figures or text in the specification. In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, This also applies to the following embodiments. is.

[0160] (Embodiment 2) In this embodiment, a semiconductor device according to one embodiment of the present invention will be described.

[0161] The structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIG. One embodiment of the present invention is not limited to the configuration described below.

[0162] The semiconductor device illustrated in FIG. 15 includes a circuit 200. The circuit 200 includes a wiring 212, a wiring 21 3. Based on the potential of the wiring 214 and the wiring 215, N (N is a natural number equal to or greater than 3) wirings 2 The circuit 20 has a function of controlling the potential of the wirings 211[1] to 211[N]. 0 is a signal based on the potential of the wiring 212, the wiring 213, the wiring 214, and the wiring 215. 211[1] to [N]. The potentials of the respective electrodes [1] to [N] are controlled.

[0163] Specifically, the circuit 200 controls the potentials of the wirings 212, 213, 214, and 215. The function of sequentially activating the potentials of the wirings 211[1] to [N] based on 211[1] to [N] have the function of sequentially setting the potentials of the transistors 211[1] to 211[N] to a high level or a low level. In FIG. 16, the circuit 200 is connected to the potentials of the wiring 212, the wiring 213, the wiring 214, and the wiring 215. Based on this, the timing when the potentials of the wirings 211[1] to 211[N] are sequentially set to a high level is As shown in the chart, the circuit 200 functions as a shift register.

[0164] The potentials of the wirings 212, 213, 214, and 215 are connected to the respective wirings by signals or For example, a signal CK1 is input to the wiring 212. A signal CK2 is input to the wiring 213, a signal CK3 is input to the wiring 214, and A signal SP is input to the line 215, and a signal OU is input to each of the wirings 211[1] to [N]. That is, the signals OUT[1] to [N] are output in accordance with the signals CK1, The signal CK1 has a value based on the signal CK2, the signal CK3, and the signal SP. The signal CK1 and the signal CK2 are clock signals having different phases. There is a start pulse.

[0165] The circuit 200 includes N circuits 201 (also referred to as circuits 201[1] to [N]). Each of the circuits 201[1] to [N] corresponds to the circuit 100 described in the first embodiment. In FIG. 15, each of the circuits 201[1] to [N] corresponds to the circuit 1 shown in FIG. 00 is used.

[0166] In the circuit 201[2m+1] (m is 0 or a positive integer), the first The terminal and the gate of the transistor 104 are connected to a wiring 214. The second terminal of the transistor 101 corresponds to the wiring 111. The second terminal of the transistor 101 corresponds to the wiring 211[2m+1 ]. Therefore, the wiring 211[2m+1] corresponds to the wiring 112. The first terminal of the transistor 102 is connected to the wiring 215 or the wiring 211[2m]. The wiring 215 or the wiring 211[2m] corresponds to the wiring 113. The first terminal and gate of the transistor 03 are connected to the wiring 212. The first terminal of the transistor 104 corresponds to the first terminal 114. The first terminal of the transistor 104 is connected to the wiring 213. Therefore, the wiring 213 corresponds to the wiring 115 .

[0167] In the circuit 201[2m+2], the first terminal of the transistor 101 and the The gate of 04 is connected to the wiring 212. Therefore, the wiring 212 corresponds to the wiring 111. The second terminal of the transistor 101 is connected to the wiring 211[2m+2]. , the wiring 211[2m+2] corresponds to the wiring 112. The terminal is connected to the wiring 211[2m+1]. The first terminal and the gate of the transistor 103 correspond to the wiring 213. Therefore, the wiring 213 corresponds to the wiring 114. The first terminal of the wiring 214 is connected to the wiring 214. Therefore, the wiring 214 corresponds to the wiring 115.

[0168] In the circuit 201[2m+3], the first terminal of the transistor 101 and the The gate of 04 is connected to the wiring 213. Therefore, the wiring 213 corresponds to the wiring 111. The second terminal of the transistor 101 is connected to the wiring 211[2m+3]. , the wiring 211[2m+3] corresponds to the wiring 112. The terminal is connected to the wiring 211[2m+2]. The first terminal and the gate of the transistor 103 correspond to the wiring 214. Therefore, the wiring 214 corresponds to the wiring 114. The first terminal of the wiring 212 is connected to the wiring 212. Therefore, the wiring 212 corresponds to the wiring 115.

[0169] As shown in FIG. 17, in each of the circuits 201[1] to [N], The first terminal of the stator 104 may be connected to the wiring 216. The wiring 216 corresponds to the wiring 115. The wiring 216 may be supplied with a voltage VSS. The voltage VSS may be, for example, The values ​​(equal or approximately equal values).

[0170] As shown in FIG. 18, in the circuit 201[2m+1], The terminal and gate of the circuit 201[2m+2] may be connected to the wiring 213. In the example shown in FIG. 1, the first terminal and the gate of the transistor 103 may be connected to a wiring 214. In the circuit 201[2m+3], the first terminal and the gate of the transistor 103 are connected to each other. The terminals may be connected to wiring 212. That is, the circuits 201[i] (i is any one of 2 to N) In (1), the first terminal and the gate of the transistor 103 are connected to the wiring 212 and the wiring 21 3 and the wiring 214 to which the first terminal of the transistor 101 in the circuit 201[i-1] is connected. The wiring may be connected to the wiring.

[0171] Note that the first terminal or gate of the transistor 103 is connected to each of the circuits 201[1] to [N]. The circuit 100 (for example, as shown in FIGS. 2(A), 2(B), and 3(B)) in which the port is connected to the wiring 116 ) is adopted, the transistors 103 of each of the circuits 201[1] to [N] A new wiring may be provided to which the first terminal or the gate is connected.

[0172] Note that this embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. The contents (or even a part of the contents) described in this embodiment may be used in conjunction with other embodiments described in the embodiment. The content (or even part of the content) and / or the content described in one or more other embodiments To apply, combine, or replace the content (or even part of the content) The contents described in the embodiments are various in each embodiment. This refers to content that is described using figures or text in the specification. In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, This also applies to the following embodiments. is.

[0173] (Embodiment 3) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0174] The structure of a display device according to one embodiment of the present invention will be described with reference to FIG. One embodiment of the invention is not limited to the configuration described below.

[0175] The display device shown in FIG. 19 includes a pixel portion 301, a scanning line driver circuit 302, and a signal line driver circuit 303. It has 3.

[0176] In the pixel portion 301, N scanning lines GL (also shown as scanning lines GL[1] to [N]) and M ( M is a natural number of 2 or more) signal lines SL (also shown as signal lines SL[1] to [M]) intersect with each other. In addition, a pixel 310 is disposed at each intersection.

[0177] The pixel 310 includes at least a display element and a transistor. There are elements and liquid crystal elements. An example of a light-emitting element is an EL element.

[0178] For example, in this specification, a display element, a display device which is a device having a display element, a light-emitting device, A light-emitting device, which is a device having an element and a light-emitting element, can be used in various forms or in various The display element, the display device, the light-emitting element or the light-emitting device can have, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic materials, organic EL elements) LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) , transistors (transistors that emit light according to current), electron-emitting devices, liquid crystal devices, electrons Ink, electrophoretic element, grating light valve (GLV), plasma display (PDP), display element using MEMS (microelectromechanical systems) Digital Micromirror Device (DMD), DMS (Digital MicroShutter) , IMOD (Interference Modulation) element, shutter type MEMS display element, optical interference type MEMS display element, electrowetting element, pressure At least one of the following is a display element using electroceramic displays, carbon nanotubes, etc. In addition to these, there are also other features such as contrast, brightness, etc., which can be achieved by electrical or magnetic effects. The display medium may have a variable reflectance, transmittance, etc. An example of such a device is an EL display. Examples include field emission displays (FED) or SED flat panel displays. Spray (SED: Surface-conduction Electron-emissive An example of a display device using a liquid crystal element is a liquid crystal display. LCD displays (transmissive LCD displays, semi-transmissive LCD displays, reflective LCD displays) LCDs include spray, direct-view LCDs, and projection LCDs. An example of a display device using an electrophoretic element is electronic paper. When realizing a semi-transmissive or reflective LCD, one of the pixel electrodes For example, a part of the pixel electrode or the whole of the pixel electrode may be made to function as a reflective electrode. A part or all of the poles may be made of aluminum, silver, etc. In this case, it is possible to provide a memory circuit such as an SRAM under the reflective electrode. This further reduces power consumption. Graphene or graphite may be placed under the electrode or nitride semiconductor. In this way, graphene and graphite can be used as multilayer films by stacking multiple layers. By providing graphite, a nitride semiconductor, for example, an n-type semiconductor having a crystal It is possible to easily form a GaN semiconductor layer. An LED can be constructed by providing a GaN semiconductor layer. An AlN layer may be provided between the graphite and the crystalline n-type GaN semiconductor layer. The GaN semiconductor layer of the LED may be formed by MOCVD. By providing a GaN semiconductor layer, the LED can be formed by sputtering. It is possible.

[0179] The scan line driver circuit 302 has a function of controlling the potentials of the scan lines GL[1] to GL[N]. The scanning line driving circuit 302 outputs scanning signals to each of the scanning lines GL[1] to GL[N]. The potential of each of the scanning lines GL[1] to GL[N] is controlled by the scanning signal. The scanning line driver circuit 302 may be the same as the circuit 100 described in Embodiment 1 or It is possible to have the circuit 200 described in form 2. In such a case, for example, Each of the scanning lines GL[1] to GL[N] corresponds to the wiring 112. The scanning line driving circuits 211[1] to 211[N] correspond to the wirings 211[1] to 211[N], respectively. A signal for controlling the circuit 302 (such as a clock signal and a start pulse, or a signal CK1, The signals CK2, CK3 and SP, etc. are provided by the circuit 304.

[0180] The signal line driver circuit 303 has a function of controlling the potential or current of the signal lines SL[1] to SL[M]. The signal line driver circuit 303 supplies video signals to the signal lines SL[1] to SL[M]. Then, the potentials of the signal lines SL[1] to SL[M] are changed by the video signal. The signal line driver circuit 303 is controlled in accordance with the circuit 10 described in the first embodiment. 0 or the circuit 200 described in the second embodiment. Signals for controlling the line driving circuit 303 (for example, a clock signal, a start pulse, a video The signal, etc., is provided by circuit 304.

[0181] The circuit 304 supplies signals to the scanning line driver circuit 302 and the signal line driver circuit 303. Therefore, the circuit 304 functions as a timing controller. A voltage may be supplied to the circuit 302 and the signal line driver circuit 303. In such a case, the circuit 3 04 functions as a power supply circuit.

[0182] The operation speed of the scanning line driver circuit 302 is slower than that of the signal line driver circuit 303. The transistors included in the scan line driver circuit 302 are made of an oxide semiconductor, polycrystalline silicon, or non-crystalline silicon. It is preferable that the channel forming region is made of amorphous silicon. The transistor in 3 preferably has a channel formation region made of single crystal silicon. Therefore, the pixel portion 301 and the scanning line driver circuit 302 are provided on the same substrate, and the signal line driver circuit 3 However, the pixel portion 301 and the scanning line driver circuit 302 are preferably provided on different substrates. The signal line driver circuit 303 may be provided on the same substrate.

[0183] The scanning line driving circuit 302 may be the circuit 100 described in the first embodiment or the circuit 100 described in the second embodiment. By adopting the circuit 200 described in 2, the transistors of the scanning line driving circuit 302 Therefore, the pixel section 301 and the scanning line driving circuit If the transistors 302 are provided on the same substrate, all of the transistors provided on the substrate are the same. It is preferably polar.

[0184] The scanning line driving circuit 302 may be the circuit 100 described in the first embodiment or the circuit 100 described in the second embodiment. By adopting the circuit 200 described in Section 2, the layout of the scanning line driving circuit 302 can be Therefore, the resolution of the pixel 310 can be increased. Also, the frame can be made smaller.

[0185] Note that this embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. The contents (or even a part of the contents) described in this embodiment may be used in conjunction with other embodiments described in the embodiment. The content (or even part of the content) and / or the content described in one or more other embodiments To apply, combine, or replace the content (or even part of the content) The contents described in the embodiments are various in each embodiment. This refers to content that is described using figures or text in the specification. In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, This also applies to the following embodiments. is.

[0186] (Fourth embodiment) In this embodiment, the structure of the semiconductor device described in the first embodiment will be described.

[0187] 20 is a top view of the semiconductor device shown in FIG. 5(A). FIG. 23 is a top view of the semiconductor device shown in FIG. However, one embodiment of the present invention is not limited to the configuration described below. do not have.

[0188] The semiconductor device shown in FIG. 20 includes conductive layers 401A to 401D, semiconductor layers 402A to 402D, and a 21 shows the conductive layer 403D, conductive layers 403A to 403I, and insulating layer 404. Only conductive layers 401A to 401D are shown. In FIG. 22, only conductive layers 403A to 403I are shown. The X direction is a direction substantially perpendicular to the Y direction. Alternatively, the X direction is a direction intersecting the Y direction. is.

[0189] The insulating layer 404 is a region that will be the gate insulating layer of the transistor 101 and a region that will be the gate insulating layer of the transistor 102. a region that will become the gate insulating layer of the transistor 102; a region that will become the gate insulating layer of the transistor 103; The insulating layer 404 has a region that will become the gate insulating layer of the transistor 104. The region sandwiched between conductive layer 401A and semiconductor layer 402A, and the region sandwiched between conductive layer 401B and semiconductor layer 402B a region sandwiched between the conductive layer 401C and the semiconductor layer 402C; The region is sandwiched between the conductive layer 401D and the semiconductor layer 402D. The circles indicate contact holes in the insulating layer 404 .

[0190] The insulating layer 404 may be formed by plasma enhanced chemical vapor deposition (PECVD). Chemical Vapor Deposition (CVA) method, sputtering Silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, etc. film, aluminum oxide film, hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film An insulating layer containing at least one of a tungsten oxide film and a neodymium oxide film can be used.

[0191] The conductive layers 401A to 401D are the same layer. Alternatively, the conductive layers 401A to 401D may be formed by processing the same conductive film. It was formed by

[0192] The conductive layers 401A to 401D may be made of chromium (Cr), copper (Cu), aluminum (A l), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta) , titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (F e), cobalt (Co), or a composite containing the above-mentioned metal elements. They can be formed using gold or an alloy combining the above-mentioned metal elements.

[0193] The conductive layers 401A to 401D may have a single layer structure or a stacked structure of two or more layers. For example, a single layer structure of aluminum film containing silicon, a titanium film stacked on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film; a two-layer structure in which a titanium film is laminated on a titanium nitride film; Two-layer structure with tantalum nitride or tungsten nitride film laminated on top of tungsten nitride film A two-layer structure in which a titanium film is laminated on top of the titanium film, and an aluminum film is laminated on top of the titanium film. There are also three-layer structures in which a titanium film is formed on top of the aluminum. One or more metals selected from the group consisting of tantalum, tungsten, molybdenum, chromium, neodymium, and scandium Alternatively, an alloy film or a nitride film made by combining a plurality of layers may be used.

[0194] The conductive layers 401A to 401D are formed of indium tin oxide or tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing titanium oxide Indium oxide containing titanium oxide, indium tin oxide, indium zinc oxide, Applying a transparent conductive material such as indium tin oxide doped with silicon dioxide. It is also possible.

[0195] The conductive layers 401A to 401D are made of a Cu-X alloy film (X is Mn, Ni, Cr, F The Cu-X alloy film may be used. Since it can be processed by a wet etching process, it is possible to reduce manufacturing costs. do.

[0196] The conductive layer 401A is a region that serves as the gate electrode of the transistor 101 and a first region that serves as the capacitor 105. The conductive layer 401A has an opening 401A1 and an opening The opening 401A1 and the opening 401A2 are arranged along substantially the Y direction. It has a long length.

[0197] The conductive layer 401B is a region that will be the gate electrode of the transistor 102 and a first region of the capacitor 106. The conductive layer 401B has an opening 401B1. The opening 401B1 has a length extending substantially along the Y direction.

[0198] The conductive layer 401C has a region that becomes the gate electrode of the transistor 103.

[0199] The conductive layer 401D has a region that will become the gate electrode of the transistor 104.

[0200] The area of ​​conductive layer 401A is the area of ​​conductive layer 401B, conductive layer 401C, and conductive layer 401D. The area of ​​the conductive layer 401B is larger than that of the conductive layer 401C and the conductive layer 401D. is larger than the area of

[0201] The areas of the openings 401A1 and 401A2 are larger than the area of ​​the opening 401B1. The widths of the openings 401A1 and 401A2 are larger than the width of the opening 401B1. The longitudinal lengths of the openings 401A1 and 401A2 are It is longer than the longitudinal length of 401B1.

[0202] It should be noted that three or more openings may be provided in conductive layer 401A, and two or more openings may be provided in conductive layer 401B. However, the number of openings in the conductive layer 401A is limited to the number of openings in the conductive layer 401A. It is preferable that the number of openings is greater than that of 1B.

[0203] The semiconductor layers 402A to 402D are the same layer. The semiconductor layers 402A to 402D have the same material. Alternatively, the semiconductor layers 402A to 402D are formed from the same semiconductor film. It is formed through a process.

[0204] The semiconductor layers 402A to 402D may be made of a single-crystal semiconductor or a non-single-crystal semiconductor. Crystalline semiconductors include non-single-crystal silicon and non-single-crystal germanium. The silicon can be amorphous, microcrystalline or polycrystalline silicon, and non-monocrystalline silicon The germanium may be amorphous germanium, microcrystalline germanium, or polycrystalline germanium. etc.

[0205] In particular, it is preferable to use an oxide semiconductor film as the semiconductor layers 402A to 402D. The oxide semiconductor film is made of In-M (where M is Ti, Ga, Sn, Y, Zr, La, or Ce). In-Zn oxides, especially In-Mn-Zn oxides, can be used. In particular, it is preferable to use In-M-Zn oxide as the oxide semiconductor film. When the film is an In-M-Zn oxide, the sputtering agent used to form the In-M-Zn oxide film is The atomic ratio of the metal elements in the plating target preferably satisfies In≧M, Zn≧M. The atomic ratio of the metal elements in such a sputtering target is In:M:Zn. =1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In: The preferred ratios are M:Zn=3:1:2 and In:M:Zn=4:2:4.1. When the film is In-M-Zn oxide, the sputtering target is polycrystalline In. It is preferable to use a target containing polycrystalline In-M-Zn oxide. By using a target containing the compound, a crystalline oxide semiconductor film can be easily formed. The atomic ratio of the oxide semiconductor film to be formed is determined by the above sputtering method as an error. The atomic ratio of the metal elements contained in the target can vary by ±40%. For example, a sputtering target with an atomic ratio of In:Ga:Zn=4:2:4.1 is used. When using In, the atomic ratio of the oxide semiconductor film to be formed is approximately In:Ga:Zn=4:2:3. It may be adjacent.

[0206] The oxide semiconductor film has an energy gap of 2 eV or more, preferably 2.5 eV or more. Preferably, the energy gap is 3 eV or more. By using the gate insulating film, the off-state current of the transistor can be reduced.

[0207] The thickness of each oxide semiconductor film is 3 nm to 200 nm, preferably 3 nm to 100 nm. 00 nm or less, and more preferably 3 nm or more and 50 nm or less.

[0208] As the oxide semiconductor film, an oxide semiconductor film with low carrier density is used. The semiconductor film has a carrier density of 1×10 17 pieces / cm 3 Less than 1 × 10 15 pieces / cm 3 or less, more preferably 1 × 10 13 pieces / cm 3 Less than or equal to 1×101 1 pieces / cm 3 The oxide semiconductor film has a carrier density of 1×10 or less. 5 pieces / cm 3 or more, more preferably 1×10 7 pieces / cm 3 It may be more than that.

[0209] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use an appropriate composition depending on the required properties (mobility, threshold voltage, etc.). In order to obtain semiconductor characteristics of a transistor, the carrier density, impurity concentration, It is preferable to set the defect density, atomic ratio of metal element to oxygen, interatomic distance, density, etc. appropriately. I wish.

[0210] The oxide semiconductor films are formed of oxides having a low impurity concentration and a low density of defect states. By using a semiconductor film, it is possible to manufacture a transistor with even better electrical characteristics. Here, the impurity concentration is low and the defect level density is low (there is little oxygen vacancy). This is called high purity authentic or substantially high purity authentic. Since the oxide semiconductor film has a low carrier generation source, the carrier density can be reduced. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film can be It is rare for the electrical characteristics to become negative at low voltages (also known as normally-on). Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. In addition, the trap level density may be low due to the high purity intrinsic or substantially high purity. The intrinsic oxide semiconductor film has a significantly small off-state current and a channel width of 1×10 6μm Even if the channel length L of the device is 10 μm, the voltage between the source electrode and the drain electrode (drain The off-state current is measured in the range of 1V to 10V. below the measurement limit, i.e., 1×10 -13 It can achieve a characteristic of A or below.

[0211] Therefore, the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a channel region. The transistors in which this region is formed have small fluctuations in electrical characteristics and are highly reliable. Note that charges trapped in the trap states of the oxide semiconductor film are lost. It takes a long time for the charge to reach a certain level, and it may behave as if it were a fixed charge. A transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states is electrically Impurities include hydrogen, nitrogen, alkali metals, and alkali metals. Examples include alkaline earth metals.

[0212] Hydrogen contained in the oxide semiconductor film reacts with oxygen that is bonded to metal atoms to form water. Oxygen vacancies are formed in the lattice from which oxygen has been desorbed (or in the portion from which oxygen has been desorbed). When hydrogen enters, electrons, which act as carriers, may be generated. It can bond with oxygen atoms that bond with atomic atoms to generate electrons, which are carriers. A transistor using an oxide semiconductor film containing hydrogen tends to be normally on. Therefore, it is preferable that the amount of hydrogen in the oxide semiconductor film be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor film obtained by SIMS analysis is 2×10 20 atoms / cm 3 Less than or equal to 5 x 1019 atoms / cm 3 Below, more preferred Preferably 1 x 10 19 atoms / cm 3 Below, 5 x 10 18 atoms / cm 3 below, Preferably 1 x 10 18 atoms / cm 3 Less than or equal to 5 × 10 17 atom s / cm 3 In addition, in the oxide semiconductor film, the following may be obtained by SIMS analysis. The hydrogen concentration is 1×10 16 atoms / cm 3 or more, more preferably 1×10 17 a toms / cm 3 It may be more than that.

[0213] When silicon or carbon, which is one of the group 14 elements, is contained in an oxide semiconductor film, oxidation The oxide semiconductor film becomes n-type due to the increase in oxygen vacancies. The concentration of silicon and carbon in the oxide semiconductor film and the concentration of silicon and carbon near the interface with the oxide semiconductor film ( The concentration obtained by SIMS analysis was 2 × 10 18 atoms / cm 3 The following applies. In addition, the concentration of silicon or carbon in the oxide semiconductor film and the concentration of silicon near the interface with the oxide semiconductor film are The silicon and carbon concentrations (obtained by SIMS analysis) were 1×10 17 atoms / cm 3 More preferably, 3×10 17 atoms / cm 3 More preferably, 1× 10 18 atoms / cm 3 It may be more than that.

[0214] In the oxide semiconductor film, alkali metal or alkaline earth metals obtained by SIMS analysis The metal concentration is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atom s / cm 3 Alkali metals and alkaline earth metals bond with oxide semiconductors. This can generate carriers, increasing the off-state current of the transistor. Therefore, it is possible to reduce the concentration of alkali metal or alkaline earth metal in the oxide semiconductor film. In addition, in the oxide semiconductor film, it is preferable that an alkali metal oxide film obtained by SIMS analysis is The concentration of alkaline earth metals is 5×10 15 atoms / cm 3 Above, preferably 1×10 16 atoms / cm 3 It may be more than that.

[0215] When nitrogen is contained in the oxide semiconductor film, electrons that serve as carriers are generated, and the carrier density increases. As a result, transistors using oxide semiconductor films containing nitrogen can be easily made n-type. Therefore, nitrogen is not formed in the oxide semiconductor film. For example, the nitrogen concentration obtained by SIMS analysis is , 5×10 18 atoms / cm 3 It is preferable to set the value to the following value. The resulting nitrogen concentration is 1×10 16 atoms / cm 3 More preferably, 5 × 10 16 atoms / cm 3 or more, more preferably 1×10 17 atoms / cm 3 That's all. More preferably 5 x 1017 atoms / cm 3 It may be more than that.

[0216] The oxide semiconductor films may each have a non-single-crystal structure. CAAC-OS(C Axis Aligned Crystalline Oxide Semiconductor), including polycrystalline, microcrystalline, or amorphous structures. In the non-single-crystal structure, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states. The density of recessed levels is low.

[0217] The structure of the oxide semiconductor film will be described below.

[0218] Oxide semiconductor films are classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Alternatively, oxide semiconductors can be divided into, for example, crystalline oxide semiconductors and amorphous oxide semiconductors. do.

[0219] Note that as a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide Semiconductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. The materials include single-crystalline oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxides. Semiconductors, etc.

[0220] First, the CAAC-OS film will be described.

[0221] The CAAC-OS film is one of oxide semiconductor films having a plurality of crystal parts aligned along the c-axis.

[0222] Transmission Electron Microscope (TEM) A bright-field image and a combined analysis image of the diffraction pattern of the CAAC-OS film were obtained by using a microscope. By observing the TEM image, multiple crystalline regions can be identified. On the other hand, high-resolution TEM images also reveal clear boundaries between crystalline parts, i.e., grain boundaries. Therefore, the CAAC-OS film is It can be said that the decrease in electron mobility caused by grain boundaries is unlikely to occur.

[0223] When a high-resolution TEM image of the cross section of the CAAC-OS film was observed from a direction approximately parallel to the sample surface, It can be seen that the metal atoms are arranged in layers in the crystalline part. Each layer of metal atoms is The CAAC-OS film is formed on a surface (also called a surface to be formed) or on a surface that reflects the unevenness of the surface. The CAAC-OS film has a shape and is aligned parallel to the surface on which the film is formed or the upper surface.

[0224] On the other hand, a high-resolution TEM image of the plane of the CAAC-OS film was observed from a direction approximately perpendicular to the sample surface. It was confirmed that the metal atoms in the crystals were arranged in a triangular or hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

[0225] X-ray diffraction (XRD) was performed on the CAAC-OS film. For example, a CAAC-OS film with InGaZnO4 crystals was found by structural analysis using the device. In the out-of-plane analysis, a peak was observed at a diffraction angle (2θ) of approximately 31°. This peak is attributed to the (009) plane of the InGaZnO4 crystal. Therefore, the crystals of the CAAC-OS film have a c-axis orientation, and the c-axis is approximately aligned on the surface on which the film is formed or on the upper surface. You can see that it is oriented vertically.

[0226] In addition, the out-of-plane method of CAAC-OS film with InGaZnO4 crystals In the analysis by , in addition to the peak at 2θ around 31°, a peak also appeared at 2θ around 36°. The peak at 2θ around 36° is due to the presence of c-axis orientation in part of the CAAC-OS film. The CAAC-OS film contains crystals that do not have a 2θ of around 31°. It is preferable that the peak is exhibited at 2θ of around 36° and that the peak is not exhibited at 2θ of around 36°.

[0227] The CAAC-OS film is an oxide semiconductor film with a low concentration of impurities. These are elements other than the main components of the oxide semiconductor film, such as silicon and transition metal elements. The elements that bond to oxygen more strongly than the metal elements that constitute the oxide semiconductor film, such as fluorine, are oxidized. By removing oxygen from the oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disrupted, reducing its crystallinity. In addition, heavy metals such as iron and nickel, argon, and carbon dioxide have an atomic radius (or molecular radius) is large, and when it is contained inside the oxide semiconductor film, The impurities contained in the oxide semiconductor film are likely to disturb the atomic arrangement and cause a decrease in crystallinity. Objects can act as carrier traps or carrier sources.

[0228] The CAAC-OS film is an oxide semiconductor film with a low density of defect states. Oxygen vacancies in the semiconductor film can become carrier traps or trap hydrogen, It can be a source of carrier generation.

[0229] Low impurity concentration and low defect level density (low oxygen vacancies) are called high purity intrinsic or The term "substantially highly purified intrinsic" refers to a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film. Since there are fewer carrier generation sources, the carrier density can be reduced. The transistor using the oxide semiconductor film has electrical characteristics ( It is also called normally-on.) It is rare for it to become a high-purity intrinsic or substantially high-purity The intrinsic oxide semiconductor film has few carrier traps. Transistors using this film have little fluctuation in electrical characteristics and are highly reliable. Note that it takes time for the charges trapped in the carrier traps in the oxide semiconductor film to be released. The impurity concentration is high and the charge is stable for a long time, so the charge may behave like a fixed charge. Therefore, a transistor using an oxide semiconductor film with a high density of defect states has unstable electrical characteristics. This may occur.

[0230] In addition, transistors using CAAC-OS films show improved electrical characteristics when irradiated with visible light or ultraviolet light. The fluctuation is small.

[0231] Next, a microcrystalline oxide semiconductor film will be described.

[0232] The microcrystalline oxide semiconductor film has a region where crystals can be confirmed in a high-resolution TEM image. The microcrystalline oxide semiconductor film has a crystal structure including a crystal region and a crystal region where no clear crystal part can be identified. The crystal part contained in the crystal has a size of 1 nm to 100 nm or 1 nm to 10 nm. In particular, the fine particles are often between 1 nm and 10 nm, or between 1 nm and 3 nm. The oxide semiconductor film having nanocrystals (nc) is called nc -OS(nanocrystalline oxide semiconductor) In addition, the nc-OS film has clearly defined grain boundaries in high-resolution TEM images. It may not be possible to recognize it.

[0233] The nc-OS film is a microscopic region (e.g., a region of 1 nm to 10 nm, especially a region of 1 nm or more). The nc-OS film has a periodic atomic arrangement in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystal parts. Therefore, no orientation is observed throughout the film. Therefore, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on the analysis method. For example, X-ray diffraction (XR) using X-rays with a diameter larger than that of the crystals is used for nc-OS films. When structural analysis is performed using the D device, the crystal plane is In addition, the peaks indicating the probes larger than the crystalline part were not detected in the nc-OS film. Electron diffraction (also called selected area electron diffraction) using an electron beam with a diameter (for example, 50 nm or more) When the diffraction pattern is changed to 0.05μm, a halo-like diffraction pattern is observed. Nanobeam electrons are used, which use an electron beam with a probe diameter close to or smaller than the size of the crystal part. When diffraction is performed, spots are observed. If you do this, you may observe a circular (ring-shaped) area of ​​high brightness. When nanobeam electron diffraction was performed on the nc-OS film, multiple spots were observed within the ring-shaped region. It may be observed.

[0234] The nc-OS film is an oxide semiconductor film with higher order than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. In the nc-OS film, there is no regularity in the crystal orientation between different crystal parts. The S film has a higher defect state density than the CAAC-OS film.

[0235] Next, the amorphous oxide semiconductor film will be described.

[0236] The amorphous oxide semiconductor film has an irregular atomic arrangement in the film and is an oxide film that does not have a crystalline portion. An example is an oxide semiconductor film that has an amorphous state, such as quartz.

[0237] In the amorphous oxide semiconductor film, no crystalline portion can be confirmed in a high-resolution TEM image.

[0238] When the structure of the amorphous oxide semiconductor film is analyzed using an XRD device, out-of-p In the analysis by the Lane method, no peaks indicating crystal planes were detected. When electron diffraction is performed on a conductive film, a halo pattern is observed. When nanobeam electron diffraction is performed on a conductive film, no spots are observed, and a halo pattern is observed. It is observed.

[0239] The oxide semiconductor film has a structure that exhibits physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure may be used, particularly, for amorphous-like oxidation. Amorphous-like Oxide Semiconductor (a-like OS) The membrane is called a conductor membrane.

[0240] In the a-like OS film, voids are observed in high-resolution TEM images. In addition, crystals can be clearly seen in high-resolution TEM images. The a-like OS film has a region where the crystal part is not observed and a region where the crystal part is not observed. Crystallization occurs due to the small amount of electron irradiation, which is the level observed with a TEM, and the growth of the crystals can be seen. On the other hand, if the nc-OS film is of good quality, the small amount of charge observed by TEM can be detected. Almost no crystallization due to electron irradiation is observed.

[0241] The size of the crystalline parts of the a-like OS film and the nc-OS film was measured using a high-resolution T This can be done using EM images. For example, InGaZnO4 crystals have a layered structure, There are two Ga-Zn-O layers between the In-O layers. The structure has three In-O layers and six Ga-Zn-O layers, for a total of nine layers aligned in the c-axis direction. Therefore, the spacing between these adjacent layers is The lattice spacing (also called the d value) is approximately the same as the value of 0.29 nm from crystal structure analysis. Therefore, we focused on the lattice fringes in high-resolution TEM images and calculated the spacing between the lattice fringes. In the region where the distance is between 0.28 nm and 0.30 nm, each lattice fringe is InG aIt corresponds to the ab plane of the ZnO4 crystal.

[0242] In addition, the density of an oxide semiconductor film may differ depending on the structure. If the composition of the membrane is known, the density can be determined by comparing it with that of a single crystal with the same composition. The structure of the oxide semiconductor film can be estimated. The density of the OS-like film is 78.6% or more and less than 92.3%. The density of the nc-OS film and the CAAC-OS film was 92.3% or more. Note that an oxide semiconductor film having a density of less than 78% of the density of a single crystal is The film formation itself is difficult.

[0243] The above will be explained using a specific example. For example, In:Ga:Zn=1:1:1 [atomic In the oxide semiconductor film that satisfies the numerical ratio, single crystal InGaZnO4 with a rhombohedral crystal structure The density of 3 Therefore, for example, In:Ga:Zn=1:1:1 In an oxide semiconductor film that satisfies the atomic ratio, the density of the a-like OS film is 5.0g / cm 3 More than 5.9g / cm 3 For example, In:Ga:Zn=1:1: In the oxide semiconductor film satisfying the atomic ratio of 1, the density and CAAC- The density of the OS film is 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0244] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, it is possible to calculate the density corresponding to a single crystal of the desired composition. The density of a single crystal of a desired composition can be determined by the ratio of the single crystals of different compositions combined. However, the density should be calculated using as few types of single crystals as possible. It is preferable to calculate them in combination.

[0245] The oxide semiconductor film may be, for example, an amorphous oxide semiconductor film, an a-like OS film, or a finely crystalline oxide semiconductor film. The film may be a stacked film including two or more of a crystalline oxide semiconductor film and a CAAC-OS film.

[0246] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0247] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0248] The semiconductor layer 402A includes a channel formation region of the transistor 101.

[0249] The semiconductor layer 402B includes a channel formation region of the transistor 102.

[0250] The semiconductor layer 402C includes a channel formation region of the transistor 103.

[0251] The semiconductor layer 402D includes a channel formation region of the transistor 104.

[0252] The area of ​​the semiconductor layer 402A is the area of ​​the semiconductor layer 402B, the semiconductor layer 402C, and the semiconductor layer 402D. The area of ​​the semiconductor layer 402B is larger than that of the semiconductor layer 402C and the semiconductor layer 402D. The area is larger than that of the conductor layer 402D.

[0253] The semiconductor layer 402A is provided inside the end of the conductive layer 401A. B is provided inside the end of the conductive layer 401B. The semiconductor layer 402D is provided inside the end of the conductive layer 401D. This eliminates steps in the semiconductor layers 402A to 402D, thereby suppressing the occurrence of defects. It is possible.

[0254] The conductive layers 403A to 403I are the same layer. Alternatively, the conductive layers 403A to 403I may be formed by processing the same conductive film. It was formed by

[0255] The conductive layers 403A to 403I may be made of a material that can be used for the conductive layers 401A to 401D or can be appropriately selected from the structures.

[0256] The conductive layer 403A is a region that will become one of the source electrode and the drain electrode of the transistor 101. The conductive layer 403A is connected to the semiconductor layer 402A. The conductive layer 403A has a region in contact with the semiconductor layer 402A. The conductive layer 401D is connected to the conductive layer 401D through a contact hole in the conductive layer 404. 3A has a region in contact with the conductive layer 401D. Each of the plurality of regions 403A1 has a length extending substantially along the Y direction, and The conductive layer 403A overlaps the conductive layer 401A via the conductor layer 402A. The region 403A2 has an elongated length extending substantially along the X direction, and includes the semiconductor layer 402A and the conductive layer 402B. It does not overlap with the conductive layer 401A.

[0257] The conductive layer 403B is a region that will become the other of the source electrode and the drain electrode of the transistor 101. 1, a region to be the first electrode of the capacitor 105, and a region to be the wiring 113. In addition, the conductive layer 403B is connected to the semiconductor layer 402A. The conductive layer 403B has a region in contact with the semiconductor layer 402A. The plurality of regions 403B1 have an elongated length extending substantially along the Y direction, and The conductive layer 403B overlaps with the conductive layer 401A via a region 403B2. The region 403B2 has an elongated length extending substantially along the X direction, and is connected to the conductive layer 40 without the semiconductor layer 402A. 1A. The conductive layer 403B has an opening 403B3 and an opening 403B4. The opening 403B3 and the opening 403B4 are elongated substantially along the Y direction.

[0258] The conductive layer 403C is a region that will become one of the source electrode and the drain electrode of the transistor 102. and a region that will become the wiring 113. The conductive layer 403C is connected to the semiconductor layer 402B. Alternatively, the conductive layer 403C has a region in contact with the semiconductor layer 402B. The conductive layer 403C has a plurality of regions 403C1. It has a length along the Y direction and overlaps with the conductive layer 401B via the semiconductor layer 402B. The conductive layer 403C has a region 403C2. The region 403C2 has a length extending substantially along the X direction. However, it does not overlap with the semiconductor layer 402B and the conductive layer 401B.

[0259] The conductive layer 403D is a region that will become the other of the source electrode and the drain electrode of the transistor 102. and a region to be a first electrode of the capacitor 106. The conductive layer 403D is a semiconductor Alternatively, the conductive layer 403D is in contact with the semiconductor layer 402B. The conductive layer 403D has a region where the conductive layer 403D is electrically connected to the insulating layer 404 through a contact hole. Alternatively, the conductive layer 403D is connected to the conductive layer 401A. The conductive layer 403D also has a plurality of regions 403D1. 1 has an elongated length extending substantially along the Y direction and overlaps with the conductive layer 401B via the semiconductor layer 402B. The conductive layer 403D also has a region 403D2. The region 403D2 is aligned approximately along the X direction. The conductive layer 403 has a long length and overlaps with the conductive layer 401B without the semiconductor layer 402B in between. D has an opening 403D3. The opening 403D3 has a length extending substantially along the Y direction.

[0260] The conductive layer 403E is a region that will become one of the source electrode and the drain electrode of the transistor 103. The conductive layer 403E is connected to the semiconductor layer 402C. The conductive layer 403E has a region in contact with the semiconductor layer 402C. O1C is connected to the insulating layer 404 through a contact hole. has a region in contact with the conductive layer 401C.

[0261] The conductive layer 403F is a region that will become the other of the source electrode and the drain electrode of the transistor 103. and a region to be the other of the source electrode and the drain electrode of the transistor 104. In addition, the conductive layer 403F is connected to the semiconductor layer 402C and is connected to the semiconductor layer 402D. Alternatively, the conductive layer 403F has a region in contact with the semiconductor layer 402C and a region in contact with the semiconductor layer 402D. The conductive layer 403F is connected to the insulating layer 404 through a contact hole. Alternatively, the conductive layer 403F is in contact with the conductive layer 401B. It has an area.

[0262] The conductive layer 403G has a region that will become the wiring 111. The conductive layer 403G also has a region that will become the insulating layer 4. 4. The conductive layer 403G is connected to the conductive layer 401D through the contact hole 404. has a region in contact with conductive layer 401D.

[0263] The conductive layer 403H has a region that will become the wiring 114. The conductive layer 403H also has a region that will become the insulating layer 4. The conductive layer 403H is connected to the conductive layer 401C through the contact hole 404. has a region in contact with the conductive layer 401C.

[0264] The conductive layer 403I is a region that will become the wiring 115 and a region that will become the source electrode or drain of the transistor 104. The conductive layer 403I has a region that will become one of the in-electrodes. Alternatively, the conductive layer 403I has a region in contact with the semiconductor layer 402D.

[0265] The area of ​​the opening 403B3 is larger than the area of ​​the opening 401A1. The area of ​​opening 401A1 is larger than the area of ​​opening 401A2. 3B3, and opening 401A2 is provided inside opening 403B4. This eliminates the step of the conductive layer 403B caused by the conductive layer 401A, and prevents the occurrence of defects. It can be suppressed.

[0266] The area of ​​the opening 403D3 is larger than the area of ​​the opening 401B1. The conductive layer 401B is formed on the inner side of the opening 403D3. This can eliminate steps in the conductive layer 403D caused by the above, thereby suppressing the occurrence of defects.

[0267] Note that the region 403A2 of the conductive layer 403A does not overlap with the conductive layer 401A and the semiconductor layer 402A. On the other hand, the region 403B2 of the conductive layer 403B is connected to the conductive layer 4 without the semiconductor layer 402A. However, the region 403B2 of the conductive layer 403B overlaps with the semiconductor layer 402A. The conductive layer 403A may overlap with the conductive layer 401A. The area is smaller than the area where conductive layer 403B and conductive layer 401A overlap. The parasitic capacitance between the layer 403A and the conductive layer 401A is reduced, and the parasitic capacitance between the layer 403B and the conductive layer 401B is reduced. Therefore, the parasitic capacitance between the wiring 111 and the layer 401A can be increased. The influence on the gate of the resistor 101 is reduced, and the capacitance value of the capacitor 105 is reduced. This allows the layout area to be reduced.

[0268] Note that the region 403C2 of the conductive layer 403C does not overlap with the conductive layer 401B and the semiconductor layer 402B. On the other hand, the region 403D2 of the conductive layer 403D is connected to the conductive layer 4 without the semiconductor layer 402B. However, the region 403D2 of the conductive layer 403D overlaps with the semiconductor layer 402B. The conductive layer 403C may overlap with the conductive layer 401B. The area is smaller than the area where conductive layer 403D and conductive layer 401B overlap. The parasitic capacitance between the layer 403C and the conductive layer 401B is reduced, and the parasitic capacitance between the layer 403D and the conductive layer 401C is reduced. Therefore, the parasitic capacitance between the wiring 113 and the layer 401B can be increased. The influence on the gate of the resistor 102 is reduced, and the capacitance value of the capacitor 106 is reduced. This allows the layout area to be reduced.

[0269] The conductive layers 401A to 401D, the semiconductor layers 402A to 402D, and the conductive layer 403A There is no significant limitation on the materials of the substrate on which the insulating layer 403I and the insulating layer 404 are formed. At the very least, it must have sufficient heat resistance to withstand subsequent heat treatment. A plate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate. Single crystal semiconductor substrates, polycrystalline semiconductor substrates, and silicon substrates made of silicon or silicon carbide It is also possible to apply compound semiconductor substrates such as silicon germanium, SOI substrates, etc. A substrate having a semiconductor element provided thereon may be used as the substrate. When using a glass substrate, the 6th generation (1500mm x 1850mm) and 7th generation (1 870mm x 2200mm), 8th generation (2200mm x 2400mm), 9th generation (2 400mm x 2800mm), 10th generation (2950mm x 3400mm) and other large area substrates By using a plate, a large display device can be manufactured.

[0270] Alternatively, a flexible substrate may be used as the substrate, and a transistor may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and used to transfer it to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. Cut.

[0271] For example, in this specification and the like, it is possible to form transistors using various substrates. The type of substrate is not limited to a specific one. Conductor substrates (e.g., single crystal substrates or silicon substrates), SOI substrates, glass substrates, quartz substrates, Plastic substrates, metal substrates, stainless steel substrates, stainless steel foils Substrate with tungsten foil, tungsten substrate, substrate with tungsten foil, flexible substrate, adhesive Examples include laminated films, paper containing fibrous materials, and base films. Examples include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass. Examples of flexible substrates, laminated films, and base films include glass. Examples include polyethylene terephthalate (PET), polyethylene terephthalate (PE ... Polyethylene naphthalate (PEN), Polyethersulfone (PES), Polytetrafluoroethylene Plastics such as PTFE (Polyethylene) are also used. Examples of the resin include synthetic resins such as polypropylene, polyester, and polyethylene. Examples include vinyl fluoride or polyvinyl chloride. Alternatively, for example, polyester , polyamide, polyimide, aramid, epoxy, inorganic vapor deposition film, paper, etc. In particular, when a transistor is manufactured using a semiconductor substrate, a single crystal substrate, an SOI substrate, or the like, This results in less variation in characteristics, size, or shape, a high current capacity, and It is possible to manufacture transistors with low circuit noise. By configuring a circuit, it is possible to reduce the power consumption of the circuit or to increase the integration density of the circuit.

[0272] In addition, a flexible substrate is used as the substrate, and a transistor is formed directly on the flexible substrate. Alternatively, a separation layer may be provided between the substrate and the transistor. After a semiconductor device is partially or completely completed, it is separated from the substrate and transferred to another substrate. In this case, the transistor can be transferred to a substrate with poor heat resistance or a flexible substrate. The above-mentioned peeling layer may be formed of an inorganic film such as a tungsten film and a silicon oxide film. It uses a laminated film structure or a structure in which an organic resin film such as polyimide is formed on a substrate. It is possible.

[0273] That is, a transistor is formed using one substrate, and then the transistor is transferred to another substrate. The transistor may be placed on one of the substrates to which the transistor is transferred. Examples include substrates on which the above-mentioned transistors can be formed, as well as paper substrates, ceramic substrates, and the like. Fan substrate, aramid film substrate, polyimide film substrate, stone substrate, wood substrate, fabric substrate Board (natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester) or Recycled fibers (including acetate, cupra, rayon, recycled polyester, etc.), leather Leather substrates or rubber substrates are available. By using these substrates, it is possible to obtain a transistor with good characteristics. the formation of low-power transistors, the manufacture of durable devices, and the manufacture of heat-resistant It is possible to provide a lighter or thinner structure.

[0274] Note that this embodiment mode can be combined with the descriptions of other embodiment modes as appropriate. The contents (or even a part of the contents) described in this embodiment may be used in conjunction with other embodiments described in the embodiment. The content (or even part of the content) and / or the content described in one or more other embodiments To apply, combine, or replace the content (or even part of the content) The contents described in the embodiments are various in each embodiment. This refers to content that is described using figures or text in the specification. In addition, a drawing (or a part thereof) described in one embodiment may be different from another part of the drawing, Another figure (or a part thereof) described in the embodiment, and / or one or more By combining with the figure (or a part thereof) described in another embodiment of the present invention, This also applies to the following embodiments. is.

[0275] (Embodiment 5) In this embodiment, a display module and an electronic device including a semiconductor device according to one embodiment of the present invention will be described. This will be explained with reference to FIGS. 24 and 25.

[0276] The display module 8000 shown in FIG. 24 is made up of an upper cover 8001 and a lower cover 8002. In between, touch panel 8004 connected to FPC8003, and touch panel 8005 connected to FPC8005 Display panel 8006, backlight 8007, frame 8009, printed circuit board 8010 , and has a battery 8011.

[0277] The semiconductor device or the display device of one embodiment of the present invention can be used for, for example, a display panel 8006. can be done.

[0278] The upper cover 8001 and the lower cover 8002 are connected to the touch panel 8004 and the display panel 8005. The shape and dimensions can be changed appropriately to match the size of 006.

[0279] The touch panel 8004 is a resistive or capacitive touch panel. 8006. In addition, the opposing substrate (sealing substrate) of the display panel 8006 ) can also be equipped with a touch panel function. It is also possible to provide an optical sensor in each pixel of the 06 to create an optical touch panel.

[0280] The backlight 8007 has a light source 8008. In FIG. Although the configuration in which the light source 8008 is arranged on the 8007 has been exemplified, the present invention is not limited to this. For example, a light source 8008 is arranged at the end of a backlight 8007, and a light diffusion plate is further used. In addition, when a self-luminous light emitting element such as an organic EL element is used, or when a reflective In the case of a panel or the like, the backlight 8007 may not be provided.

[0281] The frame 8009 protects the display panel 8006 and also prevents the operation of the printed circuit board 8010. It also functions as an electromagnetic shield to block electromagnetic waves generated by the frame. The frame 8009 may also function as a heat sink.

[0282] The printed circuit board 8010 includes a power supply circuit, a signal circuit for outputting a video signal and a clock signal. The power supply to the power supply circuit can be an external commercial power supply or Alternatively, the power source may be a separately provided battery 8011. This can be omitted if a commercial power source is used.

[0283] In addition, the Display Module 8000 adds components such as a polarizing plate, a retardation plate, and a prism sheet. It may also be provided as follows.

[0284] 25(A) to 25(G) are diagrams showing electronic devices. These electronic devices are 9000, a display unit 9001, a speaker 9003, an operation key 9005 (power switch or including operation switches), connection terminal 9006, sensor 9007 (force, displacement, position, speed, acceleration Speed, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field , current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared measurement equipment The device may have a microphone 9008, etc.

[0285] The electronic devices shown in Figures 25(A) to 25(G) can have various functions. For example, functions to display various information (still images, videos, text images, etc.) on the display, Panel function, calendar, date or time display function, various software (program It has a function to control processing by a program, a wireless communication function, and various controls using the wireless communication function. Functions for connecting to computer networks, transmitting various data using wireless communication functions, The function to receive, read and display programs or data recorded on a recording medium. It is possible to have a function to display the information in the area shown in Figs. The functions that electronic devices can have are not limited to these, and they may have a variety of functions. Although not shown in FIGS. 25(A) to 25(G), the electronic device may have multiple The electronic device may be provided with a camera or the like to take still images. The function to take pictures, record videos, and store the images on a recording medium (external or built-in to the camera) The image capturing unit may have a function to store the captured image in a memory, a function to display the captured image on a display unit, etc.

[0286] The electronic devices shown in FIGS. 25A to 25G will be described in detail below.

[0287] FIG. 25A is a perspective view showing a mobile information terminal 9100. The display unit 9001 is flexible and can be moved along the curved surface of the curved housing 9000. The display portion 9001 can be incorporated by using a touch sensor. It can be operated by touching the screen with a finger or a stylus. You can start the application by touching the icon displayed on part 9001. Cut.

[0288] 25(B) is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 is For example, it has one or more functions selected from a telephone, a notebook, an information viewing device, etc. In practice, it can be used as a smartphone. Although the peaker 9003, the connection terminal 9006, the sensor 9007, etc. are omitted in the illustration, 5(A) can be provided in the same position as the portable information terminal 9100 shown in FIG. The information terminal 9101 can display text and image information on multiple screens. Two operation buttons 9050 (also called operation icons or simply icons) are provided on the display unit 9001. In addition, information 9051 shown in a dashed rectangle can be displayed on one side of the display unit 900. 1. An example of the information 9051 is an email or Displays to notify you of incoming calls and SNS (social networking services), Subject of email or SNS, sender name of email or SNS, date and time, time, The remaining battery power, antenna reception strength, etc. Or, information 9051 is displayed. In place of the information 9051, operation buttons 9050 or the like may be displayed.

[0289] 25(C) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 is The display unit 9001 has a function of displaying information on three or more surfaces. 9053 and 9054 are displayed on different sides. The user of the information terminal 9102 has the mobile information terminal 9102 stored in the breast pocket of his / her clothes. You can check the display (information 9053 in this case) by A position where the caller's telephone number or name can be observed from above the mobile information terminal 9102 The user can view the display without taking the mobile information terminal 9102 out of his pocket. You can check and decide whether to accept the call or not.

[0290] FIG. 25(D) is a perspective view showing a wristwatch-type mobile information terminal 9200. 200 is for mobile phone calls, e-mail, document viewing and creation, music playback, internet communication, It can run various applications such as computer games. The display surface of the unit 9001 is curved, and the display can be performed along the curved display surface. In addition, the portable information terminal 9200 can perform short-distance wireless communication according to a communication standard. For example, by communicating with a wireless headset, The mobile information terminal 9200 has a connection terminal 9006. It is also possible to exchange data directly with other information terminals via a connector. Charging can also be performed via the connection terminal 9006. Alternatively, power may be supplied wirelessly without going through a power supply.

[0291] 25(E), (F), and (G) are perspective views showing a foldable mobile information terminal 9201. 25(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, and FIG. F) The mobile information terminal 9201 changes from one of the unfolded state and the folded state to the other. 25(G) is a perspective view of the portable information terminal 9201 in a folded state. The portable information terminal 9201 is highly portable when folded, and is unfolded. In this state, the seamless, wide display area provides excellent visibility of the display. The display unit 9001 of the display device 1 is attached to three housings 9000 connected by hinges 9055. The hinge 9055 allows the two housings 9000 to bend. , and the mobile information terminal 9201 can be reversibly transformed from an unfolded state to a folded state. For example, the portable information terminal 9201 can be bent with a curvature radius of 1 mm or more and 150 mm or less. It is possible.

[0292] The electronic device described in this embodiment has a display unit for displaying some information. However, the semiconductor device of one embodiment of the present invention is not limited to an electronic device that does not have a display portion. In addition, the present invention can be applied to the display unit of the electronic device described in this embodiment. In the case of a display device, it is possible to provide a display along a curved display surface, or a display device that can be folded. Although the configuration of the display unit is exemplified as being foldable, the present invention is not limited to this. The display may be displayed on the display unit.

[0293] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can. [Explanation of symbols]

[0294] CK1 signal CK2 signal CK3 signal ND1 node ND2 node ND3 node OUT signal SP signal T0 period T1 period T2 period T3 period T4 period 100 circuits 101 Transistor 102 transistor 103 Transistor 104 transistors 105 Capacitive element 106 Capacitor element 107 Transistor 108 transistors 109 Transistor 110 Transistor 101p transistor 102p transistor 103p transistor 104p transistor 111 Wiring 112 Wiring 113 Wiring 114 Wiring 115 Wiring 115B wiring 115C wiring 116 Wiring 117 Wiring 121 Transistor 122 transistors 123 Transistor 124 transistors 200 circuits 201 circuits 211 Wiring 212 Wiring 213 Wiring 214 Wiring 215 Wiring 216 Wiring 301 Pixel section 302 Scanning line driving circuit 303 Signal line driver circuit 304 circuits 310 pixels 401A Conductive layer 401A1 opening 401A2 opening 401B Conductive layer 401B1 opening 401C conductive layer 401D Conductive layer 402A Semiconductor layer 402B Semiconductor layer 402C Semiconductor layer 402D Semiconductor layer 403A Conductive Layer 403A1 area 403A2 area 403B Conductive layer 403B1 area 403B2 area 403B3 opening 403B4 opening 403C conductive layer 403C1 area 403C2 area 403D conductive layer 403D1 area 403D2 area 403D3 Opening 403E conductive layer 403F conductive layer 403G Conductive layer 403H conductive layer 403I Conductive layer 404 Insulation Layer 404A1 opening 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery 9000 chassis 9001 Display section 9003 Speaker 9005 Operation key 9006 Connection terminal 9007 Sensor 9008 Microphone 9050 Operation button 9051 Information 9052 Information 9053 Information 9054 Information 9055 Hinge 9100 Mobile Information Terminal 9101 Mobile Information Terminal 9102 Mobile Information Terminal 9200 Mobile Information Terminal 9201 Mobile Information Terminal

Claims

1. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a semiconductor device including, in a plan view, a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor, the first conductive layer having a function as the other of the source electrode and the drain electrode of the second transistor, the first conductive layer having a function as the other of the source electrode and the drain electrode of the second transistor, and a second conductive layer having a function as the gate electrode of the second transistor, the first conductive layer not overlapping with the semiconductor layer having a function as a channel formation region of the second transistor.

2. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; The semiconductor device, wherein the area of ​​the third conductive layer functioning as the gate electrode of the first transistor is larger than the area of ​​the second conductive layer.

3. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; The semiconductor device includes a region in contact with a third conductive layer that functions as a gate electrode of the first transistor.

4. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; In a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect with each other.

5. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; The semiconductor device includes a region in contact with the third conductive layer.

6. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; In a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect with each other.

7. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; the first conductive layer has a region in contact with a third conductive layer that functions as a gate electrode of the first transistor; In a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect with each other.

8. A semiconductor device comprising first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; the first conductive layer has a region in contact with the third conductive layer, In a plan view, the channel length direction of the first transistor and the channel length direction of the third transistor intersect with each other.

9. A liquid crystal display device comprising: a scanning line drive circuit; and pixels formed on the same substrate as the scanning line drive circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

10. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

11. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; the first conductive layer has a region in contact with a third conductive layer that functions as a gate electrode of the first transistor; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

12. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; a channel length direction of the first transistor and a channel length direction of the third transistor intersect with each other in a plan view; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

13. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; the first conductive layer has a region in contact with the third conductive layer, the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

14. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; a channel length direction of the first transistor and a channel length direction of the third transistor intersect with each other in a plan view; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

15. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; the first conductive layer has a region in contact with a third conductive layer that functions as a gate electrode of the first transistor; a channel length direction of the first transistor and a channel length direction of the third transistor intersect with each other in a plan view; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

16. A liquid crystal display device comprising: a scanning line driving circuit; and pixels formed on the same substrate as the scanning line driving circuit; the scanning line driving circuit has first to third transistors, one of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring to which a signal is output; one of a source electrode and a drain electrode of the second transistor is electrically connected to a scanning line; the other of the source electrode and the drain electrode of the second transistor is electrically connected to the gate of the first transistor; one of a source electrode and a drain electrode of the third transistor is electrically connected to a clock signal line; the other of the source electrode and the drain electrode of the third transistor is electrically connected to the gate of the second transistor; a gate of the third transistor is electrically connected to a second wiring to which a high-level potential is input; a first conductive layer functioning as the other of the source electrode and the drain electrode of the second transistor has a region that overlaps with a second conductive layer functioning as a gate electrode of the second transistor in a region that does not overlap with a semiconductor layer functioning as a channel formation region of the second transistor in a plan view; an area of ​​the third conductive layer functioning as a gate electrode of the first transistor is larger than an area of ​​the second conductive layer; the first conductive layer has a region in contact with the third conductive layer, a channel length direction of the first transistor and a channel length direction of the third transistor intersect with each other in a plan view; the pixel includes a fourth transistor; The fourth transistor includes an oxide semiconductor in a channel formation region.

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