Apparatus and method for checking errors of a non-volatile memory device

Abstract

The present invention relates to a memory system. The memory system includes a memory device including a plurality of memory banks each including a plurality of nonvolatile memory cells, and a controller configured to transmit a command to the memory device so that the memory device performs a data input / output operation within at least one memory bank among the plurality of memory banks, receive a response to the command and status data regarding the at least one memory bank from the memory device, and determine whether the data input / output operation has succeeded or has failed based on the response and the status data.

Description

[0001] Cross-references to related applications

[0002] This patent application claims the benefit of Korean Patent Application No. 10-2020-0132607, filed on October 14, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more embodiments described herein relate to a memory system, apparatus, and method for detecting errors occurring in a non-volatile memory device. Background Technology

[0004] Recently, the paradigm for computing environments has shifted towards ubiquitous computing, enabling computer systems to be accessed virtually anytime, anywhere. Consequently, the use of portable electronic devices (e.g., mobile phones, digital cameras, and laptops) is rapidly increasing. These portable electronic devices can use or include memory systems with at least one memory device, such as a data storage device. The data storage device can serve as either the primary or secondary storage device for the portable electronic device.

[0005] Unlike hard drives, data storage devices using non-volatile semiconductor memory exhibit improved stability and durability, lack mechanical actuation components (e.g., robotic arms), and operate with high data access speeds and relatively low power consumption. Examples of these types of data storage devices include, but are not limited to, Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and solid-state drives (SSDs). Summary of the Invention

[0006] Embodiments of this disclosure may provide a data processing system and a method for operating the data processing system, the data processing system including components and resources such as a memory system and a host, and capable of dynamically allocating multiple data paths for data communication between components based on the use of the components and resources.

[0007] Furthermore, if the memory device notifies the controller of successful operation even if an operation performed within a memory device including non-volatile memory cells is not successfully completed or an error occurs during operation, then the memory system according to embodiments of this disclosure can detect errors, abnormal operations, or operation failures occurring within the memory device.

[0008] In a memory system according to an embodiment of the disclosure, a controller can be configured to transmit a command for a data input / output operation to a memory device including a non-volatile memory unit, and receive a result of the data input / output operation from the memory device. In addition, the controller can include a device capable of improving reliability of the data input / output operation. The device can receive information about a storage block or a page related to the data input / output operation in the device, and compare the result of the data input / output operation with the information to perform a double check about the data input / output operation.

[0009] In addition, even if an error occurs in the transmitted result of the data input / output operation performed by the memory device due to a failure of the memory device including a non-volatile memory unit, the memory system according to an embodiment of the disclosure can reconfirm the result of the data input / output operation based on separate information.

[0010] In an embodiment of the disclosure, a memory system can include a memory device including a plurality of memory banks each including a plurality of non-volatile memory units, and a controller configured to transmit a command to the memory device so that the memory device performs a data input / output operation within at least one memory bank among the plurality of memory banks, receive a response to the command and state data about the at least one memory bank from the memory device, and determine whether the data input / output operation is successful or failed based on the response and the state data.

[0011] The controller can determine whether the data input / output operation has been successful or has failed by comparing the state data and a physical-to-logical (P2L) mapping data item associated with the data input / output operation. The controller can be further configured to update a logical-to-physical (L2P) mapping data item based on the P2L mapping data item depending on whether the data input / output operation has been successful.

[0012] When a result of a first determination of success or failure based on the state data is different from a result of a second determination of success or failure based on the response, the controller can determine whether the data input / output operation has been successful or has failed by assigning a higher priority to the first determination than to the second determination.

[0013] For example, each memory bank among the plurality of memory banks can be a page. The state data can include bitmap information indicating whether the page is blank or empty.

[0014] For another example, each memory bank among the plurality of memory banks can be a storage block, and the state data includes a page count indicating how many pages of the storage block in which data items are stored.

[0015] The memory device can be configured to transmit the response to the controller immediately after completion of the data input / output operation corresponding to the command. When the metadata is updated by the data input / output operation, the memory device can be configured to transmit the status data to the controller.

[0016] The data input / output operation can include data programming, data erasing, or data reading for the plurality of memory groups. The memory device can be further configured to update the status data associated with the data programming, the data erasing, or the data reading.

[0017] In another embodiment of the disclosure, a method of operating a memory system can include performing a data input / output operation within at least one memory group of a memory device including a plurality of memory groups, each memory group including a plurality of non-volatile memory cells, receiving a response from the memory device, the response including a result of the data input / output operation, receiving status data regarding the at least one memory group from the memory device, and determining whether the data input / output operation has succeeded or has failed based on the response and the status data.

[0018] Determining whether the data input / output operation has succeeded or has failed can include comparing the status data and a physical-to-logical (P2L) mapping data item associated with the data input / output operation. The method can further include updating a logical-to-physical (L2P) mapping data item based on the P2L mapping data item according to whether the data input / output operation has succeeded.

[0019] Determining whether the data input / output operation has succeeded or has failed can include assigning a higher priority to a first determination based on the status data than to a second determination based on the response when the first determination and the second determination have different results of success or failure.

[0020] For example, each memory group among the plurality of memory groups can be a page. The status data can include bitmap information indicating whether the page is blank or empty.

[0021] For another example, each memory group among the plurality of memory groups can be a memory block. The status data can include a valid page count indicating how many pages of the memory block store data items.

[0022] The method can further include the memory device transmitting the response immediately after completion of the data input / output operation corresponding to the command, and the memory device transmitting the status data when the metadata is updated by the data input / output operation.

[0023] The data input / output operation can include data programming, data erasing, or data reading for the plurality of memory groups. The method can further include updating status data associated with the data programming, data erasing, or data reading.

[0024] In another embodiment of the disclosure, a controller can be coupled to a memory device including a plurality of memory groups via at least one data path, each memory group including a plurality of non-volatile memory cells. The controller can include at least one processor and at least one memory including computer program code, wherein, with the at least one processor, the at least one memory, and the computer program code, the controller is configured to cause the controller to perform a data input / output operation within at least one memory group in the memory device; receive a response from the memory device, the response including a result of the data input / output operation; receive status data from the memory device regarding the at least one memory group; and determine whether the data input / output operation has succeeded or has failed based on the response and the status data.

[0025] With the at least one processor, the at least one memory, and the computer program code, the controller is configured to cause the controller to determine whether the data input / output operation has succeeded or has failed by comparing the status data and a physical-to-logical (P2L) mapping data item associated with the data input / output operation. With the at least one processor, the at least one memory, and the computer program code, the controller can be further configured to cause the controller to update a logical-to-physical (L2P) mapping data item based on the P2L mapping data according to whether the data input / output operation has succeeded or has failed.

[0026] With the at least one processor, the at least one memory, and the computer program code, the controller is configured to cause the controller to determine whether the data input / output operation has succeeded or has failed by assigning a higher priority to a first determination based on a result of a success or failure of the status data than a second determination based on a result of a success or failure of the response when the first determination and the second determination are different.

[0027] For example, each memory group among the plurality of memory groups can be a page. The status data can include bitmap information indicating whether the page is empty or blank.

[0028] For another example, each memory group among the plurality of memory groups can be a memory block. The status data can include a page count indicating how many pages of the memory block in which a data item is stored.

[0029] With the at least one processor, the at least one memory, and the computer program code are further configured to cause the controller to receive the response from the memory device immediately after the data input / output operation corresponding to the command is completed, and receive state data from the memory device when the metadata is updated by the data input / output operation.

[0030] In another embodiment of the disclosure, a memory system can include a memory device configured to perform an access operation to store data into or erase data from a non-volatile memory cell in response to a command and provide a response indicating successful storage or erasure of the data, and a controller configured to provide the command to the memory device, reflect the response into a physical-to-logical (P2L) mapping data item, control the memory device to generate information about the data stored in the memory cell, control the memory device to perform the access operation again when the P2L mapping data item is different from the information, and reflect the response into a logical-to-physical (L2P) mapping data item when the P2L mapping data item is the same as the information. BRIEF DESCRIPTION OF DRAWINGS

[0031] The description herein makes reference to the accompanying drawings, wherein like reference numerals may refer to like parts throughout the several views, and wherein:

[0032] Figure 1 A memory system according to an embodiment of the disclosure is illustrated.

[0033] Figure 2 A data processing system according to an embodiment of the disclosure is illustrated.

[0034] Figure 3 A memory system according to an embodiment of the disclosure is illustrated.

[0035] Figure 4 An example of bitmap information illustrating page information in a non-volatile memory device is illustrated.

[0036] Figure 5 A first example of a method of operating a memory system according to an embodiment of the disclosure is illustrated.

[0037] Figure 6 A second example of a method of operating a memory system according to an embodiment of the disclosure is illustrated. DETAILED DESCRIPTION

[0038] Various embodiments of the disclosure are described hereinafter, with reference to the drawings. However, elements and features of the disclosure can be differently configured or arranged from those described specifically herein to form other embodiments which can be a variation of any of the disclosed embodiments.

[0039] In the present disclosure, the terms "comprise", "comprising", "include", "including", "contain", "containing", "comprises" and "comprising" are open-ended. As used in the appended claims as well as in the following

[0040] In the present disclosure, reference to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in "one embodiment", "an exemplary embodiment", "an embodiment", "a further embodiment", "some embodiments", "various embodiments", "other embodiments", "optional embodiments", etc. is intended to represent that any such features are included in one or more embodiments of the present disclosure, but can or can not necessarily be in combination with each other in the same embodiment.

[0041] In the present disclosure, various units, circuits, or other components can be described or claimed as "configured to" perform a task or tasks. In such contexts, "configured to" is used to connote structure by indicating that a block / circuit / component includes structure (e.g., circuitry) that performs the task or tasks during operation. As such, the block / component can be said to be configured to perform the task or tasks even if the task or tasks are not performed during all device operating modes. A block / circuit / component used with "configured to" can include hardware such as circuitry, software, or combinations thereof, for example. The block / circuit / component used with "configured to" can also include a structure that is made during the fabrication of the device and that is not easily removed, for example, a molecule of a chemical as a structure, or as an example, a specific structure of biological material such as genetic material. In this context, a structure is meant to be the material, if any, that forms one or more structures of hardware during the fabrication of the device, including structural materials such as semiconductor materials, conductive materials, insulating materials, etc.

[0042] As used in this disclosure, the term “circuitry” can refer to all of the following: (a) hardware-only circuitry such as only analog and / or digital circuitry, (b) a combination of circuits and software (and / or firmware), such as (as applicable): (i) a combination of processor(s) or (ii) portions of storage that store software or firmware to be executed by the processor(s), and (c) circuits, such as a microprocessor(s) or a portion of the microprocessor(s), that require software or firmware for operation, even if the software or firmware is not physically present. This definition of “circuitry” applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term “circuitry” also covers an implementation that includes both a processor (or multiple processors) and memory coupled with the processor(s) so as to store the software or firmware. For example, and if applicable to the particular claim element, the term “circuitry” also covers an implementation that includes integrated circuitry.

[0043] As used, the terms “first,” “second,” “third,” etc. are used as labels for nouns that they follow, and are not meant to literally imply a sequence or order (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must be written before the second value. Moreover, while these terms can be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that also has the same or similar names. For example, a first circuit can be distinguished from a second circuit.

[0044] Moreover, the term “based on” is used to describe one or more factors to which determination of results is based. This term is not used to denote causal relationship, wherein the determining result is caused by the factor. That is, the determining result can be based on only those factors or based on at least those factors. Consider the phrase “determine A based on B.” While B is a factor to which a determining result of A is based in this case, this phrase does not exclude the determining result of A based on C as well. In other cases, A can be determined based on B only.

[0045] In this document, a piece of data or a data item can be a sequence of bits. For example, a data item can include the contents of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video signal or an audio signal, or any other entity that can be represented by a sequence of bits. According to an embodiment, a data item can include a discrete object. According to another embodiment, a data item can include a unit of information within a transmission packet between two different components.

[0046] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, wherein like reference numerals refer to like elements.

[0047] Figure 1 A memory system according to an embodiment of the present disclosure is illustrated.

[0048] Referring to Figure 1 The memory system 110 can include a memory device 150 and a controller 130. The memory device 150 and the controller 130 in the memory system 110 can be considered as components or elements physically separated from each other. The memory device 150 and the controller 130 can be connected via at least one data path. For example, the data path can include a channel and / or a lane.

[0049] According to an embodiment, the memory device 150 and the controller 130 can be components or elements divided by function. Further, according to an embodiment, the memory device 150 and the controller 130 can be implemented with a single chip or a plurality of chips. The controller 130 can perform a data input / output operation in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0050] As Figure 1 illustrated, the memory device 150 can include a plurality of memory blocks 60. The memory block 60 can be understood as a group of non-volatile memory cells that data is removed together by a single erase operation. Although not illustrated, the memory block 60 can include a page, which is a group of non-volatile memory cells that data is stored together during a single programming operation or data is output together during a single read operation. For example, one memory block can include a plurality of pages.

[0051] For example, the memory device 150 can include a plurality of memory planes or a plurality of memory dies. According to an embodiment, the memory plane can be considered as a logical or physical partition including at least one memory block, a driving circuit capable of controlling an array including a plurality of non-volatile memory cells, and a buffer that can temporarily store data input to or output from the non-volatile memory cells.

[0052] In addition, according to an embodiment, the memory die can include at least one memory plane. The memory die can be understood as a group of components implemented on a physically distinguishable substrate. Each memory die can be connected to the controller 130 through a data path. Each memory die can include an interface to exchange data words and signals with the controller 130.

[0053] According to an embodiment, the memory device 150 can include at least one memory block 60, at least one memory plane, or at least one memory die. According to the performance of the memory system 110, Figure 1 The internal configuration of the memory device 150 illustrated can be different. Embodiments of the present disclosure are not limited to Figure 1 the internal configuration illustrated.

[0054] Referring to Figure 1 , the memory device 150 can include a voltage supply circuit 70 capable of supplying at least some voltages to the memory block. The voltage supply circuit 70 can supply a read voltage Vrd, a program voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the nonvolatile memory cells included in the memory block. For example, during a read operation of reading data stored in the nonvolatile memory cells included in the memory block, the voltage supply circuit 70 can supply the read voltage Vrd to the selected nonvolatile memory cells. During a program operation of storing data in the nonvolatile memory cells included in the memory block, the voltage supply circuit 70 can supply the program voltage Vprog to the selected nonvolatile memory cells. Also, during the read operation or the program operation performed on the selected nonvolatile memory cells, the voltage supply circuit 70 can supply the pass voltage Vpass to the unselected nonvolatile memory cells. During an erase operation of erasing data stored in the nonvolatile memory cells included in the memory block, the voltage supply circuit 70 can supply the erase voltage Vers to the memory block.

[0055] The memory device 150 can store information about various voltages supplied to the memory block 60 based on which operation is performed. For example, when the nonvolatile memory cells in the memory block can store multi-bit data, a plurality of levels of read voltages Vrd for identifying or reading the multi-bit data can be required. The memory device 150 can include a table including information about the plurality of levels of read voltages Vrd corresponding to the multi-bit data. For example, the table can include bias values stored in a register, each of which corresponds to a level of a specific read voltage Vrd. The number of bias values for the read voltage Vrd for the read operation can be limited to a preset range. Also, the bias values can be quantized.

[0056] The controller 130 can perform a data input / output operation in response to a request input from an external device. For example, when the controller 130 performs a read operation with respect to a read request input from an external device, data stored in a plurality of nonvolatile memory cells included in the memory device 150 can be transferred to the controller 130. For the read operation, the input / output (I / O) controller 192 can transmit a read command to the memory device 150 through the transceiver 198. The transceiver 198 can transmit the read command to the memory device 150 and receive data output from the memory device 150. The transceiver 198 can store the data output from the memory device 150 in the memory 144. The input / output (I / O) controller 192 can output the data stored in the memory 144 to the external device as a response to the read request.

[0057] In addition, the input / output controller 192 can transmit data input from the external device along with a write request to the memory device 150 through the transceiver 198. After storing the data in the memory device 150, the input / output controller 192 can transmit a response of the write request to the external device, the response of the write request showing that the data is successfully programmed.

[0058] In general, when no malfunction occurs in an internal operation performed within the memory device 150 or in a process of data communication (e.g., transmission / reception of data, commands, responses, etc.) between the controller 130 and the memory device 150, the controller 130 can be configured to determine whether a data input / output operation is successful or failed based on a response provided from the memory device 150 about the data input / output operation. However, when the memory device 150 transmits an incorrect response to the controller 130 due to a malfunction or an error occurring in the data communication between the controller 130 and the memory device 150, the success or failure of the data input / output operation performed within the memory device 150 can be different from the success or failure of the data input / output operation identified by the controller 130. In this case, the operational reliability of the memory system 110 can be deteriorated.

[0059] According to embodiments, the operation status checker 196 in the controller 130 can collect status data regarding a storage block 60 or a page associated with a data input / output operation performed within the memory device 150 and perform a recheck whether the data input / output operation is successful or failed based on the status data. As described above, the memory device 150 can include a plurality of memory banks each including a plurality of non-volatile memory cells. Here, the memory bank can correspond to various structural components such as a storage block 60, a page, a plane, a die, a super block, etc., which can be associated with a data input / output operation or a type of operation performed within the memory device 150. For example, when a read operation or a program operation is performed page by page, the memory bank can be understood as a page. When an erase operation is performed block by block, the memory bank can be a storage block 60.

[0060] After performing a data input / output operation in response to a command transmitted from the controller 130, the memory device 150 transmits operation information such as status data related to the data input / output operation or a changed mapping data item associated with the data item in response to another command of the controller 130. In addition to the response that has been transmitted after the data input / output operation, the operation status checker 196 can determine whether the data input / output operation is successful based on the operation information transmitted from the memory device 150. According to embodiments, the operation information can be transmitted from the memory device 150 to the controller 130 along with a response regarding the data input / output operation.

[0061] For example, the controller 130 transmits a program command for storing data in a particular page to the memory device 150. If a program operation in response to the program command is successfully performed, the memory device 150 can transmit a response indicating that the program operation has been successfully completed to the controller 130. Due to the program operation, a data item is stored at a blank page in an open storage block of the memory device 150, and status data regarding the page can indicate that data is stored in the page. According to embodiments, the number of valid pages in the corresponding storage block can change. When the memory device 150 transmits status data regarding the corresponding page or the number of valid pages of the corresponding open storage block to the controller 130 based on a command of the controller 130, the operation status checker 196 performs a recheck of the program operation based on the received status data. The operation status checker 196 can reconfirm whether the program operation is successfully completed.

[0062] According to an embodiment, the controller 130 can compare the state data transmitted from the memory device 150 with second mapping items (e.g., P2L mapping data items for linking physical addresses to logical addresses), and check whether the programming operation on the data item has been successfully performed. After checking again that the programming operation is successfully performed, the controller 130 can update the first mapping items (e.g., L2P mapping data items for linking logical addresses to physical addresses) based on the second mapping items.

[0063] Even if the respective programming operations within the memory device 150 fail, the controller 130 recognizes that the programming operation for storing the data item has been successful. Because the programming operation fails in the memory device 150, the state data regarding the respective page can indicate that the data item is not stored in the respective page. Alternatively, the number of valid pages in the respective memory block can not have changed. When the memory device 150 transmits the state data at the request of the controller 130, the operation state checker 196 can recognize that the programming operation has not been successfully performed based on the received state data. In this case, the controller 130 can perform an operation for correcting the error that occurred during the programming operation instead of updating the first mapping items (e.g., L2P mapping data items for linking logical addresses to physical addresses). For example, to correct the error, the controller 130 can perform a re-programming operation on the data item in a different page or a different block of the memory device 150.

[0064] Through the above-described process, even if the memory device 150 and the controller 130 in the memory system 110 recognize different data input / output operation results from each other, the controller 130 can collect operation information such as state data regarding the memory banks within the memory device 150. Based on the operation information, the controller 130 can recheck whether the data input / output operation is successful or fails. On the other hand, when the result of the data input / output operation is determined to be different based on the response and the state data regarding the data input / output operation transmitted from the memory device 150, the operation state checker 196 can determine whether the operation is successful or fails based on the state data. That is, the operation state checker 196 can give a higher priority to the determination based on the state data than the determination based on the response.

[0065] Figure 2 And Figure 3 Some operations that can be performed by the memory system 110 according to one or more embodiments of the disclosure are illustrated.

[0066] Referring to Figure 2The data processing system 100 can include a host 102 interfaced or coupled with a memory system such as a memory system 110. The host 102 can include a portable electronic device (e.g., a mobile phone, an MP3 player, a laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, a game console, a television, a projector, etc.).

[0067] The host 102 can also include at least one operating system (OS) that can control functions and operations performed in the host 102. The OS can provide interoperability between the host 102 operatively interfaced with the memory system 110 and a user who wants to store data in the memory system 110. The OS can support functions and operations corresponding to a user request. By way of example and not limitation, the OS can be classified as a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified as a personal operating system and an enterprise operating system according to system requirements or a user environment. The enterprise operating system can be specialized to secure and support high-performance computing compared to the personal operating system.

[0068] The mobile operating system can be used to support services or functions for mobility (e.g., power saving functions). The host 102 can include a plurality of operating systems. The host 102 can run a plurality of operating systems interlocked with the memory system 110 corresponding to a user request. The host 102 can transmit a plurality of commands corresponding to a user request to the memory system 110, thereby performing operations corresponding to the commands within the memory system 110.

[0069] The controller 130 in the memory system 110 can control the memory device 150 in response to a request or a command input from the host 102. For example, the controller 130 can perform a read operation to provide the host 102 with data blocks read from the memory device 150, and can perform a write operation (or a program operation) to store data blocks input from the host 102 in the memory device 150. To perform data input / output (I / O) operations, the controller 130 can control and manage internal operations for data read, data program, data erase, etc.

[0070] According to an embodiment, the controller 130 can include a host interface (I / F) 132, a processor 134, an error correction circuit 138, a power management unit (PMU) 140, a memory interface 142, and a memory 144. Regarding the memory system 110 in the embodiment, as Figure 2The components included in the illustrated controller 130 can vary according to structure, function, operational performance, etc. For example, according to a protocol of a host interface, the memory system 110 can be implemented with any one of various types of storage devices that can be electrically coupled with the host 102. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro type MMC, a secure digital (SD) card, a mini SD, a micro SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, etc. Components in the controller 130 can be added or omitted based on an implementation of the memory system 110.

[0071] The host 102 and the memory system 110 can include a controller or an interface to transmit and receive signals, data items, etc. according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 can include a device capable of transmitting signals, data items, etc. to the host 102 or receiving signals, data items, etc. input from the host 102.

[0072] The host interface 132 included in the controller 130 can receive signals, commands (or requests), or data items input from the host 102. For example, the host 102 and the memory system 110 can transmit and receive data items between each other using a predetermined protocol. Examples of protocols or interfaces supported by the host 102 and the memory system 110 for transmitting and receiving data items include a universal serial bus (USB), a multimedia card (MMC), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an electronic integrated drive (IDE), a peripheral component interconnect express (PCIE), a serial SCSI (SAS), a serial advanced technology attachment (SATA), a mobile industry processor interface (MIPI), etc. According to an embodiment, the host interface 132 is a layer for exchanging data items with the host 102 and is implemented with or driven by firmware referred to as a host interface layer (HIL).

[0073] An electronic integrated drive (IDE) or an advanced technology attachment (ATA) can be used as one of the interfaces for transmitting and receiving data strips, for example, an electronic integrated drive (IDE) or an advanced technology attachment (ATA) can use a cable including wiring of 40 parallel connections to support data transmission and reception between the host 102 and the memory system 110. When a plurality of memory systems 110 are connected to a single host 102, the plurality of memory systems 110 can be divided into a master and a slave by using a location or a dip switch connected with the plurality of memory systems 110. The memory system 110 set as the master can be used as a master memory device. For example, the IDE (ATA) can include a fast ATA, an ATAPI, and an enhanced IDE (EIDE).

[0074] A serial advanced technology attachment (SATA) is a serial data communication interface compatible with the parallel data communication interfaces of various ATA standards used by an electronic integrated drive (IDE) device. The 40 wirings in the IDE interface can be reduced to six wirings in the SATA interface. For example, 40 parallel signals for the IDE can be converted into 6 serial signals for the SATA to be transmitted between each other. The SATA has been widely used due to its faster data transmission and reception rate and less resource consumption for data transmission and reception in the host 102. The SATA can support up to 30 external devices to be connected with a single transceiver included in the host 102. In addition, the SATA can support hot plugging that allows an external device to be attached to or detached from the host 102 even while data communication between the host 102 and another device is being performed. Accordingly, the memory system 110 can be connected or disconnected as an additional device like a universal serial bus (USB) supported device even when the host 102 is powered on. For example, in the host 102 having an eSATA port, the memory system 110 can be freely detached like an external hard disk.

[0075] A small computer system interface (SCSI) is a serial data communication interface for connection between a computer, a server, and / or a peripheral device thereof. The SCSI can provide a high transmission speed compared to other interfaces such as the IDE and the SATA. In the SCSI, the host 102 and at least one peripheral device (for example, the memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In the SCSI, it is easy to connect or disconnect a device such as the memory system 110 to or from the host 102. The SCSI can support 15 other devices to be connected with a single transceiver included in the host 102.

[0076] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, not only are the host 102 and the plurality of peripheral devices connected in series, but data transmission and reception between the host 102 and each of the peripheral devices can be performed in a serial data communication scheme. SAS can support connection between the host 102 and the peripheral devices through a serial cable instead of a parallel cable to easily manage devices using SAS and enhance or improve operational reliability and communication performance. SAS can support connecting eight external devices with a single transceiver included in the host 102.

[0077] Non-Volatile Memory Express (NVMe) is an interface based on at least Peripheral Component Interconnect Express (PCIe) designed to improve performance and design flexibility of a host 102, a server, a computing device, etc. equipped with a non-volatile memory system 110. PCIe can use a slot or a dedicated cable to connect the host 102 (e.g., a computing device) and the memory system 110 (e.g., a peripheral device). For example, PCIe can use a plurality of pins (e.g., 18 pins, 32 pins, 49 pins, 82 pins, etc.) and at least one wire (e.g., x1, x4, x8, x16, etc.) to achieve high-speed data communication of several hundreds of MB (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, 1969 MB / s, etc.) per second. According to an embodiment, the PCIe scheme can achieve a bandwidth of several tens to several hundreds of gigabits per second. A system using NVMe can maximize the running speed of a non-volatile memory system 110 such as an SSD, which runs at a higher speed than a hard disk.

[0078] According to an embodiment, the host 102 and the memory system 110 can be connected through a Universal Serial Bus (USB). The Universal Serial Bus (USB) is an extensible, hot-pluggable, plug-and-play serial interface that can provide an economical and efficient standard connection between the host 102 and a peripheral device such as a keyboard, a mouse, a joystick, a printer, a scanner, a storage device, a modem, a video camera, etc. A plurality of peripheral devices such as the memory system 110 can be coupled to a single transceiver included in the host 102.

[0079] Referring to Figure 2The error correction circuit 138 can correct error bits of data to be processed (e.g., output from the memory device 150) in the memory device 150, and can include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder can perform error correction encoding on data to be programmed in the memory device 150 to generate encoded data with parity bits added, and store the encoded data in the memory device 150. When the controller 130 reads data stored in the memory device 150, the ECC decoder can detect and correct errors contained in the data read from the memory device 150. For example, after performing error correction decoding on data read from the memory device 150, the error correction circuit 138 can determine whether the error correction decoding has been successful and output an indication signal (e.g., a correction success signal or a correction failure signal). The error correction circuit 138 can use the parity bits generated during the ECC encoding process to correct error bits of the read data. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the error correction circuit 138 can not correct the error bits, but can output a correction failure signal indicating a failure to correct the error bits.

[0080] According to embodiments, the error correction circuit 138 can perform error correction operations based on encoding modulation such as a low-density parity-check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a Turbo code, a Reed-Solomon (RS) code, a convolutional code, a recursive systematic code (RSC), a trellis coded modulation (TCM), or a block coded modulation (BCM), etc. The error correction circuit 138 can include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above codes.

[0081] For example, the ECC decoder can perform hard decision decoding or soft decision decoding on data transmitted from the memory device 150. Hard decision decoding can be understood as one of two methods broadly classified for error correction. Hard decision decoding can include an operation of correcting errors by reading digital data from non-volatile memory cells in the memory device 150 as "0" or "1". Because hard decision decoding processes binary logic signals, the design or configuration of the circuit / algorithm can be simpler than soft decision decoding, and the processing speed can be faster than soft decision decoding.

[0082] Soft decision decoding can quantize threshold voltages of non-volatile memory cells in the memory device 150 by two or more quantized values (e.g., multi-bit data, approximations, analog values, etc.) to correct errors based on the two or more quantized values. The controller 130 can receive the two or more quantized values from the plurality of non-volatile memory cells in the memory device 150 and then perform decoding based on information generated by representing the quantized values as a combination of information such as conditional probabilities or likelihoods.

[0083] According to embodiments, among methods designed for soft decision decoding, the ECC decoder can use a low-density parity-check and generator matrix (LDPC-GM) code. A low-density parity-check (LDPC) code uses an algorithm that can read values of data from the memory device 150 in several bits according to reliability, rather than simply reading data 1 or 0 as in hard decision decoding, and iteratively repeats the process through message passing to improve reliability of the values. The values are then finally determined as data 1 or 0. For example, a decoding algorithm using the LDPC code can be understood as a probabilistic decoding. But in hard decision decoding, values output from the non-volatile memory cells are encoded as 0 or 1. Compared to hard decision decoding, soft decision decoding can determine values stored in the non-volatile memory cells based on stochastic information. Regarding bit flips (which can be considered as errors that can occur in the memory device 150), soft decision decoding can improve the possibility of correcting errors and recovering data, as well as providing reliability and stability of the corrected data. The LDPC-GM code can have a scheme in which an inner LDGM code can be concatenated with a high-speed LDPC code.

[0084] According to embodiments, for example, the ECC decoder can use a low-density parity-check convolutional code (LDPC-CC) for soft decision decoding. The LDPC-CC can have a scheme using linear-time encoding and pipelined decoding based on a variable block length and a shift register.

[0085] According to embodiments, for example, the ECC decoder can use a log-likelihood ratio Turbo code (LLR-TC) for soft decision decoding. A log-likelihood ratio (LLR) can be calculated as a non-linear function of a distance between a sampled value and an ideal value. In addition, a Turbo code (TC) can include a simple code (e.g., a Hamming code) in two or three dimensions, and decoding is repeated in a row direction and a column direction to improve reliability of the values.

[0086] A power management unit (PMU) 140 can control power provided in the controller 130. The PMU 140 can monitor power supplied to the memory system 110 (e.g., voltage supplied to the controller 130) and provide power to components included in the controller 130. When power supplied to the memory system 110 is unstable, the PMU 140 can not only detect power-on or power-off, but also generate a trigger signal enabling the memory system 110 to urgently back up a current state. According to an embodiment, the PMU 140 can include a device or component capable of accumulating power that can be used in an emergency.

[0087] The memory interface 142 can serve as an interface for handling commands and data transferred between the controller 130 and the memory device 150 to allow the controller 130 to control the memory device 150 in response to a command or request input from the host 102. In the case when the memory device 150 is a flash memory, the memory interface 142 can generate a control signal for the memory device 150 under the control of the processor 134 and can process data input to or output from the memory device 150. For example, when the memory device 150 includes a NAND flash memory, the memory interface 142 includes a NAND flash controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented by or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0088] According to an embodiment, the memory interface 142 can support an open NAND flash interface (ONFi), a toggle mode, etc. to perform data input / output with the memory device 150. For example, the ONFi can use a data path (e.g., channel, lane, etc.) including at least one signal line capable of supporting bidirectional transmission and reception in units of 8-bit or 16-bit data. Data communication between the controller 130 and the memory device 150 can be implemented through at least one interface regarding an asynchronous single data rate (SDR), a synchronous double data rate (DDR), and a toggle double data rate (DDR).

[0089] The memory 144 can be a working memory in the memory system 110 or the controller 130, while storing temporary data or transaction data generated or transferred for operations in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data output from the memory device 150 before the read data is output to the host 102 in response to a request from the host 102. Also, the controller 130 can temporarily store write data input from the host 102 in the memory 144 before the write data is programmed into the memory device 150. When the controller 130 controls operations such as data read, data write, data program, data erase, etc. of the memory device 150, data items transmitted or generated between the controller 130 and the memory device 150 of the memory system 110 can be stored in the memory 144.

[0090] In addition to read data or write data, the memory 144 can store information (e.g., mapping data, read requests, program requests, etc.) for inputting or outputting data between the host 102 and the memory device 150. According to an embodiment, the memory 144 can include a command queue, a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, a mapping buffer / cache, etc. The controller 130 can allocate some storage spaces in the memory 144 for components set up to perform data input / output operations. For example, a write buffer set up in the memory 144 can be used to temporarily store target data for a program operation.

[0091] In an embodiment, the memory 144 can be implemented with volatile memory. For example, the memory 144 can be implemented with static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 It is illustrated that, for example, the memory 144 is disposed within the controller 130, but embodiments are not limited thereto. The memory 144 can be located inside or outside the controller 130. For example, the memory 144 can be implemented by an external volatile memory having a memory interface that transmits data and / or signals between the memory 144 and the controller 130.

[0092] The processor 134 can control overall operations of the memory system 110. For example, the processor 134 can control a program operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 102. According to an embodiment, the processor 134 can run firmware to control the program operation or the read operation in the memory system 110. Herein, the firmware can be referred to as a flash translation layer (FTL). Later, with reference to FIG. 2, the firmware will be described in detail. Figure 3Detailed description of an example of FTL. According to an embodiment, the processor 134 can be implemented with a microprocessor or a central processing unit (CPU).

[0093] According to an embodiment, the memory system 110 can be implemented with at least one multi-core processor. A multi-core processor is a circuit or chip that integrates two or more cores that are considered as different processing regions. For example, when the multiple cores in the multi-core processor independently drive or run multiple flash translation layers (FTLs), the data input / output speed (or performance) of the memory system 110 can be improved. According to an embodiment, data input / output (I / O) operations in the memory system 110 can be independently performed by different cores in the multi-core processor.

[0094] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Also, the memory system 110 can independently perform operations from commands or requests input from an external device such as the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, and operations performed by the controller 130 independently (e.g., regardless of requests or commands input from the host 102) can be considered background operations. The controller 130 can perform foreground operations or background operations regarding reading, writing or programming, erasing, etc. of data blocks in the memory device 150. In addition, parameter setting operations corresponding to setting parameter commands or setting feature commands that are setting commands transmitted from the host 102 can be considered foreground operations. As background operations that are commands not transmitted from the host 102, the controller 130 can perform garbage collection (GC), wear leveling (WL), bad block management for identifying and processing bad blocks, etc. The background operations can be performed on multiple memory blocks 152, 154, 156 included in the memory device 150.

[0095] According to an embodiment, substantially similar operations can be performed as both foreground operations and background operations. For example, when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or a command input from the host 102, the garbage collection can be considered a foreground operation. When the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102, the garbage collection can be considered a background operation.

[0096] When the memory device 150 includes multiple dies (or multiple chips) having non-volatile memory cells, the controller 130 can be configured to perform parallel processing with respect to multiple requests or commands input from the host 102 to improve performance of the memory system 110. For example, the transmitted requests or commands can be divided and processed in parallel in at least some of the multiple planes, dies, or chips included in the memory device 150. The memory interface 142 in the controller 130 can be connected to the multiple planes, dies, or chips in the memory device 150 through at least one channel and at least one lane. When the controller 130 allocates and stores data stripes in the multiple dies through each channel or each lane in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed individually or in parallel. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of the memory system 110 operating with the interleaving method can be faster than that of a memory system not operating with the interleaving method, the data I / O performance of the memory system 110 can be improved.

[0097] By way of example and not limitation, the controller 130 can identify a status with respect to multiple channels (or lanes) associated with multiple memory dies included in the memory device 150. The controller 130 can determine a status of each channel or each lane as, for example, one of: a busy status, a ready status, an active status, an idle status, a normal status, and / or an abnormal status. The controller determining through which channel or lane to pass an instruction (and / or data) can be associated with a physical block address, e.g., into which die(s) to pass the instruction (and / or data). The controller 130 can refer to a descriptor passed from the memory device 150. The descriptor can include block parameters or page parameters describing some information about the memory device 150, each parameter being data having a set format or structure. For example, the descriptor can include a device descriptor, a configuration descriptor, a cell descriptor, etc. The controller 130 can refer to or use the descriptor to determine via which channel or lane(s) to exchange an instruction or data.

[0098] Referring to Figure 2As shown, the memory devices 150 in the memory system 110 can include a plurality of memory blocks 152, 154, 156. Each of the plurality of memory blocks 152, 154, 156 includes a plurality of non-volatile memory cells. According to embodiments, the memory blocks 152, 154, 156 can be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, 156 can include a plurality of pages that are a group of non-volatile memory cells that are read or programmed together. In one embodiment, each memory block 152, 154, 156 can have a three-dimensional stacked structure for high integration. Further, the memory device 150 can include a plurality of dies, each die including a plurality of planes, each plane including a plurality of memory blocks 152, 154, 156. The configuration of the memory device 150 can be different for performance of the memory system 110.

[0099] In Figure 2 As shown in the memory device 150, a plurality of memory blocks 152, 154, 156 are included. The plurality of memory blocks 152, 154, 156 can be any one of a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, etc., according to the number of bits that can be stored or represented in one memory cell. The SLC memory block includes a plurality of pages implemented by memory cells that each store one bit of data. The SLC memory block can have higher data I / O operation performance and higher endurance. The MLC memory block includes a plurality of pages implemented by memory cells that each store multiple bits of data (e.g., two bits or more). The MLC memory block can have greater storage capacity than the SLC memory block for the same space. The MLC memory block can be highly integrated in terms of storage capacity.

[0100] In embodiments, the memory device 150 can be implemented with MLC memory blocks such as double-level cell (DLC) memory blocks, triple-level cell (TLC) memory blocks, quad-level cell (QLC) memory blocks, or a combination thereof. The double-level cell (DLC) memory block can include a plurality of pages implemented by memory cells that each are capable of storing two bits of data. The triple-level cell (TLC) memory block can include a plurality of pages implemented by memory cells that each are capable of storing three bits of data. The quad-level cell (QLC) memory block can include a plurality of pages implemented by memory cells that each are capable of storing four bits of data. In another embodiment, the memory device 150 can be implemented with blocks including a plurality of pages implemented by memory cells that each are capable of storing five or more bits of data.

[0101] According to an embodiment, the controller 130 can use a multi-level cell (MLC) memory block included in the memory device 150 as an SLC memory block that stores one bit of data in one memory cell. The data input / output speed of the MLC memory block can be lower than that of the SLC memory module. That is, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. When an MLC memory block is used as an SLC memory block, the controller 130 can utilize the faster data input / output speed of the MLC memory block. For example, because a buffer may require a higher data input / output speed to improve the performance of the memory system 110, the controller 130 can use the MLC memory block as a buffer for temporarily storing data strips.

[0102] Furthermore, according to an embodiment, the controller 130 can program multiple data entries into a multi-level cell (MLC) multiple times without performing an erase operation on a specific MLC memory block included in the memory device 150. Non-volatile memory cells are characterized by not supporting data rewriting. However, the controller 130 can utilize the characteristic of a multi-level cell (MLC) that can store multiple bits of data to program multiple 1-bit data entries into the MLC multiple times. For MLC rewrite operations, when a single 1-bit data entry is programmed into a non-volatile memory cell, the controller 130 can store the number of programming entries as separate operation information. According to an embodiment, an operation to uniformly equalize the threshold voltage of the non-volatile memory cell can be performed before rewriting another data entry into the same non-volatile memory cell.

[0103] In embodiments, the memory device 150 is implemented as a non-volatile memory such as flash memory, e.g., NAND flash memory, NOR flash memory, etc. In embodiments, the memory device 150 may be implemented using at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0104] Reference Figure 3 The controller 130 in the memory system operates together with the host 102 and the memory device 150. As shown in the figure, in addition to the previously combined Figure 2 In addition to the identified memory interface 142 and memory 144, controller 130 includes host interface 132 and flash translation layer (FTL) 240.

[0105] According to an embodiment, Figure 2The illustrated error correction circuit 138 can be included in a flash translation layer (FTL) 240. In another embodiment, the error correction circuit 138 can be implemented as a separate module, circuit, firmware, etc. included in or associated with the controller 130.

[0106] The host interface 132 can process commands, data, etc. transmitted from the host 102. By way of example and not limitation, the host interface 132 can include a command queue 56, a buffer manager 52, and an event queue 54. The command queue 56 can sequentially store commands, data, etc. received from the host 102, and output the commands, data, etc. to the buffer manager 52, for example, in the order in which the commands, data, etc. are stored. The buffer manager 52 can sort, manage, or adjust the commands, data, etc. received from the command queue 56. The event queue 54 can sequentially transmit events for processing the commands, data, etc. received from the buffer manager 52.

[0107] Multiple commands or data of the same characteristic (e.g., read commands or write commands) can be transmitted from the host 102, or multiple commands or data of different characteristics can be transmitted to the memory system 110 after the host 102 mixes or scrambles the multiple commands and data of different characteristics. For example, multiple commands for reading data (read commands) can be transmitted to the memory system 110, or commands for reading data (read commands) and commands for programming / writing data (write commands) can be alternately transmitted to the memory system 110. The host interface 132 can sequentially store the commands, data, etc. transmitted from the host 102 to the command queue 56. Thereafter, the host interface 132 can estimate or predict which type of internal operation the controller 130 will perform according to the characteristics of the commands, data, etc. that have been input from the host 102. The host interface 132 can determine the processing order and priority of the commands, data, etc. based at least on the characteristics of the commands, data, etc.

[0108] The buffer manager 52 in the host interface 132 is configured to determine whether the buffer manager should store the commands, data, etc. in the memory 144 or determine whether the buffer manager should pass the commands, data, etc. to the flash translation layer (FTL) 240 according to the characteristics of the commands, data, etc. transmitted from the host 102. The event queue 54 receives events input from the buffer manager 52, which will be internally executed and processed by the memory system 110 or the controller 130 in response to the commands, data, etc. transmitted from the host 102 to pass the events to the flash translation layer (FTL) 240 in the order of reception.

[0109] According to an embodiment, Figure 3The illustrated flash translation layer (FTL) 240 can implement a multi-threading scheme to perform data input / output (I / O) operations. The multi-threading FTL can be implemented by using a multi-core processor with multi-threading included in the controller 130.

[0110] According to embodiments, the flash translation layer (FTL) 240 can include a host request manager (HRM) 46, a mapping manager (MM) 44, a state manager 42, and a block manager 48. The host request manager (HRM) 46 can manage events input from the event queue 54. The mapping manager (MM) 44 can process or control mapping data. The state manager 42 can perform garbage collection (GC) or wear leveling (WL). The block manager 48 can run commands or instructions on blocks in the memory device 150.

[0111] By way of example and not limitation, the host request manager (HRM) 46 can handle or process requests using the mapping manager (MM) 44 and the block manager 48 according to read commands and program commands and events passed from the host interface 132. The host request manager (HRM) 46 can transmit a query request to the mapping manager (MM) 44 to determine a physical address corresponding to a logical address input with an event. The host request manager (HRM) 46 can send a read request to the memory interface 142 with the physical address to process the read request (process the event). In embodiments, the host request manager (HRM) 46 can send a program request (write request) to the block manager 48 to program data to a particular free page (a page without data) in the memory device 150, and then can transmit a mapping update request corresponding to the program request to the mapping manager (MM) 44 to update an item related to the program data in information mapping logical-physical addresses to each other.

[0112] The block manager 48 can convert program requests passed from the host request manager (HRM) 46, the mapping manager (MM) 44, and / or the state manager 42 to flash program requests for the memory device 150 to manage flash blocks in the memory device 150. To maximize or improve program or write performance of the memory system 110 (e.g., see Figure 2 The block manager 48 can collect program requests and send flash program requests for multi-plane and one-shot program operations to the memory interface 142 to improve or maximize parallel processing of a multi-channel and multi-direction flash controller. In embodiments, the block manager 48 sends several flash program requests to the memory interface 142 to improve or maximize parallel processing of a multi-channel and multi-direction flash controller.

[0113] In an embodiment, the block manager 48 can be configured to manage the blocks in the memory device 150 according to the number of valid pages, select and erase a block having no valid pages when a free block is needed, and select a block including the least number of valid pages when it is determined that garbage collection will be performed. The state manager 42 can perform garbage collection to move valid data to a free block and erase a block including the moved valid data, so that the block manager 48 can have enough free blocks (empty blocks having no data). When the block manager 48 provides information about a block to be erased to the state manager 42, the state manager 42 can check all flash pages of the block to be erased to determine whether each page is valid.

[0114] For example, to determine the validity of each page, the state manager 42 can identify a logical address recorded in an out-of-band (OOB) region of each page. To determine whether each page is valid, the state manager 42 can compare a physical address of the page with a physical address mapped to the logical address obtained from the query request. The state manager 42 sends a program request to the block manager 48 for each valid page. When the program operation is completed, the mapping table can be updated by an update of the mapping manager 44.

[0115] The mapping manager 44 can manage a logical-physical mapping table. The mapping manager 44 can process various requests, e.g., queries, updates, etc., generated by the host request manager (HRM) 46 or the state manager 42. The mapping manager 44 can store the entire mapping table in the memory device 150 (e.g., flash memory / non-volatile memory) and cache mapping entries according to the storage capacity of the memory 144. When a mapping cache miss occurs while processing a query or update request, the mapping manager 44 can send a read request to the memory interface 142 to load the relevant mapping table stored in the memory device 150. When the number of dirty cache blocks in the mapping manager 44 exceeds a certain threshold, a program request can be sent to the block manager 48, thereby forming clean cache blocks and the dirty mapping table can be stored in the memory device 150.

[0116] When garbage collection is performed, the state manager 42 copies the valid page(s) to the free block, and the host request manager (HRM) 46 can program the latest version of data for the page of the same logical address and immediately issue an update request. When the state manager 42 requests a mapping update in a state in which the copying of the valid page(s) is not normally completed, the mapping manager 44 can not perform a mapping table update. This is because when the state manager 42 requests a mapping update and later completes the valid page copying, a mapping request with old physical information is issued. The mapping manager 44 can perform a mapping update operation to ensure accuracy only when or only in the case that the latest mapping table still points to the old physical address.

[0117] Figure 4 An example of bitmap information illustrating page information in a non-volatile memory device is shown. Figure 4 The bitmap information 194 described in the middle is an example of information that can reflect the operating state of the memory banks included in the memory device 150 (see Figures 1 to 3 ).

[0118] Referring to Figure 4 , the memory device 150 can include a plurality of memory blocks 60_1, 60_2. Each of the memory blocks 60_1, 60_2 can include a plurality of pages. Each page can include a data area Page_1, Page_2, Page_3, or Page_4 for storing a data item, and a spare area SP_1, SP_2, SP_3, or SP_4 for storing state data corresponding to each data area Page_1, Page_2, Page_3, or Page_4. According to an embodiment, the spare area SP_1, SP_2, SP_3, or SP_4 can store metadata. Examples of the metadata include bad block information. Further, according to an embodiment, information related to an error correction code can be stored in the spare area SP_1, SP_2, SP_3, or SP_4. The controller 130 and the memory device 150 can use the spare areas SP_1, SP_2, SP_3, SP_4 to store various types of data.

[0119] According to an embodiment, the memory device 150 can generate bitmap information 194 indicating whether data items stored in a page are valid. The controller 130 receiving the bitmap information 194 from the memory device 150 can store the bitmap information 194 in the memory 144 and control the bitmap information 194 in the memory 144. For example, if a bit "1" is recorded in the bitmap information 194, this can indicate that a data item stored in a page corresponding to the bit is valid. Here, valid data means that the stored data is the latest data requested by an external device (e.g., the host 102), and invalid data means that the stored data is old (has been updated with other data). The bitmap information 194 can be used to determine the validity of data items stored in the memory device 150 or in other operations such as garbage collection.

[0120] In addition, according to an embodiment, the controller 130 can perform a data input / output operation within the memory device 150. The controller 130 can receive state data from the memory device 150 to configure the bitmap information 194. The controller 130 can first determine whether the data input / output operation is successful or failed based on a response transmitted from the memory device 150 after transmitting a command for the data input / output operation to the memory device 150. Thereafter, the controller 130 can request information about the operation state from the memory device 150, and the memory device 150 can transmit information (e.g., metadata, etc.) stored in the spare area SP_1, SP_2, SP_3, SP_4 to the controller 130. The controller 130 can configure the bitmap information 194 based on the information transmitted from the memory device 150.

[0121] The controller 130 can compare the bitmap information 194 with second mapping items (e.g., P2L mapping items for associating physical addresses with logical addresses) to determine whether the data input / output operation has been successfully performed. For example, if the validity of data items does not match through the bitmap information 194 and the second mapping items, the controller 130 can determine that the data input / output operation corresponding to the page has not been successfully performed. When the validity of data items matches through the bitmap information 194 and the second mapping information, the controller 130 can determine that the data input / output operation has been successfully performed, and then the controller 130 can update the first mapping items (e.g., L2P mapping items for associating logical addresses with physical addresses) based on the second mapping items.

[0122] Figure 5 A first example of a method of operating a memory system according to an embodiment of the disclosure is illustrated.

[0123] Referring to Figure 5The method of operating a memory system can include performing a data input / output operation within a non-volatile memory device (342), checking whether the data input / output operation is completed (344), determining an operating state of a memory block included in the non-volatile memory device (346), and determining success / failure of the data input / output operation based on the operating state of the memory block and a response indicating whether the data input / output operation is completed (348).

[0124] Referring to Figures 1 to 3 To perform an operation requested by an external device (e.g., the host 102) or a background operation, the controller 130 can transmit a command for a data input / output operation to the memory device 150. The data input / output operation corresponding to the command input from the controller 130 can be performed on the memory device 150 (342).

[0125] The memory device 150 can transmit a result or a response of the data input / output operation to the controller 130, and the controller 130 can check whether the data input / output operation is completed based on the result or the response (344). For example, in response to a program command of the controller 130, the memory device 150 can transmit a success signal indicating that a data item has been programmed or a failure signal indicating that the data item has not been programmed to the controller 130. When the controller 130 sends a read command to the memory device 150, the memory device 150 can transmit a data item corresponding to the read command or a failure signal indicating that the read operation has failed to the controller 130.

[0126] The controller 130 can request information about an operating state of the memory device 150, which is separate from a result or a response of a data input / output operation performed within the memory device 150. The controller 130 can generate bitmap information 194 (refer to FIG. 2) based on the information about the operating state transmitted from the memory device 150 (346), or obtain page information of a corresponding memory block in the memory device 150 (346). The page information can indicate whether a page is blank or empty or how many pages in a particular block store data items. According to an embodiment, the page information can indicate which one of a user data item and a dummy data item is stored in a page. Figure 4

[0127] ​The controller 130 can check whether the data input / output operation was successfully executed (348) not only based on the result or response indicating whether the data input / output operation was completed, but also based on the status data of the memory device 150 (e.g., page information, memory block information, etc.). For example, the controller 130 can compare the operating status of the memory device 150 with a second mapping item (e.g., a P2L mapping data item that associates physical addresses with logical addresses) to check again whether the programming operation on a specific data item was successfully executed. After the result or response indicating whether the data input / output operation was completed and the operating information or status data of the memory device 150 are transmitted from the memory device 150, the first determination based on the result or response may differ from the second determination based on the operating information or status data. In this case, the controller 130 can assign a higher priority to the second determination based on the status data than to the first determination based on the result or response.

[0128] According to an embodiment, the controller 130 can generate valid page information indicating whether a data item stored in a corresponding page is valid. Here, a valid data item is the latest data among the data items stored in the memory device 150 that corresponds to a specific logical address. A valid page is a page that stores valid data items.

[0129] Figure 6 A second example of a method for operating a memory system according to embodiments of the present disclosure is shown. Specifically, Figure 6 Description of controller 130 (see) Figures 1 to 3 Flash Translation Layer (FTL) 240 in ) (see Figure 3 ) and memory device (NAND) 150 (see Figures 1 to 3 An example of data communication between ( ).

[0130] Reference Figure 6 The flash translation layer (FTL) 240 can initiate operations requested by the host 102 (512). Before executing the host-requested operations, the memory device 150 can generate information about multiple memory blocks or pages for bitmap initialization (530).

[0131] The flash memory translation layer 240 can decode the request from the host 102 and transmit commands to the memory device 150 to perform an operation corresponding to the request (514). Data input / output operations (e.g., write, erase, etc.) can be performed on the memory device 150 in response to the commands transmitted by the flash memory translation layer 240 (532).

[0132] While or after the data input / output operation is performed on the memory device 150, the flash translation layer 240 can check the progress of the data input / output operation performed in the memory device 150 (516). In Figure 6 In the middle of the process of performing the data input / output operation (e.g., write, erase, etc.) in the memory device 150 in response to the command transmitted from the flash translation layer 240, an abnormal situation has occurred.

[0133] Despite the abnormal situation (e.g., unknown error), the memory device 150 can inform the flash translation layer 240 that the data input / output operation has been completed (534). The flash translation layer 240 can monitor whether the memory device 150 is ready to perform another operation or the data input / output operation corresponding to the command is completed (518). When the memory device 150 is not ready to perform another operation or the data input / output operation corresponding to the transmitted command is not completed (NO at operation 518), the flash translation layer 240 can monitor the data input / output operation performed in the memory device 150 (516).

[0134] When the memory device 150 is ready to perform another operation or the data input / output operation corresponding to the transmitted command is completed (YES at operation 518), the corresponding storage block in which the data input / output operation is performed can be changed and the change can be reflected into the physical block / page bitmap table. In addition, the controller 130 can generate a second mapping data item (e.g., P2L mapping data item) that associates a physical address with a logical address. For example, when a write operation is performed in a certain storage block, a mapping data item (e.g., P2L mapping data item) of the corresponding storage block can be newly added. Then, the flash translation layer 240 can request bitmap information from the memory device 150 and collect the bitmap information (520). The memory device 150 can update the physical block / page bitmap table and transmit the bitmap information in response to the request from the flash translation layer 240 (536). According to an embodiment, the bitmap information such as the physical block / page bitmap table can be generated by the memory device 150. Alternatively, according to another embodiment, the bitmap information can be generated by the flash translation layer 240 based on the information input from the memory device 150.

[0135] In addition, according to an embodiment, the bitmap information and operation information about the storage block can be requested by the flash translation layer 240 and transmitted from the memory device 150 to the flash translation layer 240. In addition, according to an embodiment, when a preset time elapses after the data input / output operation is completed in the memory device 150, the memory device 150 can transmit the bitmap information or operation information about the storage block to the flash translation layer 240 even without the request from the flash translation layer 240.

[0136] The flash translation layer 240 can compare the change in the respective storage block that performed the data input / output operation with the bitmap information (522). According to an embodiment, the change in the respective storage block that performed the data input / output operation can be estimated based on the second mapping data item (e.g., the P2L mapping data item that associates the physical address with the logical address). For example, when a write operation is performed in a particular storage block, a mapping data item (e.g., the P2L mapping data item) of the respective storage block can be newly added. If a particular storage block is erased, the mapping data item about the respective storage block can be removed. The flash translation layer 240 can compare the change in the respective storage block with the bitmap information transmitted from the memory device 150 (522).

[0137] The flash translation layer 240 compares the change of the storage block with the bitmap information transmitted from the memory device 150 to check whether the change is the same as or different from the bitmap information about the location (e.g., a particular page) where the data input / output operation is performed (524). If the change is the same as the bitmap information (‘Yes’ in operation 524), the flash translation layer 240 can determine that there is no problem in the data input / output operation performed within the memory device 150, and then the flash translation layer 240 can update the first mapping data item (e.g., the L2P mapping data item that associates the logical address with the physical address) based on the second mapping data item (526). If the change is different from the bitmap information (‘No’ in operation 524), the flash translation layer 240 can determine that there is a problem in the data input / output operation performed within the memory device 150, and then perform a process of correcting the error without updating the first mapping data item (528). To correct the error, the flash translation layer 240 can perform the respective data input / output operation again.

[0138] For example, in response to a write request transmitted from the host 102, the controller 130 can cause the memory device 150 to perform a program operation corresponding to the write request, and the memory device 150 can transmit a result or response regarding the program operation to the controller 130. The controller 130 can further receive bitmap information from the memory device 150. Before updating the first mapping data item (L2P mapping data item) based on the second mapping data item (P2L mapping data item) in response to the result or response regarding the program operation, the controller 130 can compare the bitmap information with the second mapping data item (P2L mapping data item). When it is determined that there is no error based on the comparison result, the controller 130 can update the first mapping data item (L2P mapping data item) based on the second mapping data item (P2L mapping data item). Through these operations, the controller 130 can have an opportunity to perform a recovery process in response to an unexpected error in the memory device 150. According to this recheck process, the operation reliability of the memory system 110 can be improved or enhanced.

[0139] As described above, the memory system according to an embodiment of the present disclosure can increase the reliability of data input / output operations performed within a nonvolatile memory device.

[0140] Also, the memory system according to an embodiment of the present disclosure can detect or check a failure of a nonvolatile memory device.

[0141] While the present teachings have been illustrated and described relative to particular embodiments, various changes and modifications can occur to those skilled in the art after reading this disclosure, which consequently forms part of the present disclosure.

Claims

1. A memory system, comprising: A memory device includes multiple memory groups, each memory group including multiple non-volatile memory cells; as well as Controller: Commands are transmitted to the memory device, thereby enabling the memory device to perform data input / output operations within at least one of the plurality of memory groups. The system receives a response to the command and outputs it from the memory device, as well as status data output from the memory device in response to an operation that changes data in the at least one memory group. The response includes a result of the operation that changes data in the at least one memory group corresponding to the command. The status data includes current operation information related to the at least one memory group whose data was changed during the operation that changed data in the at least one memory group. The state data is compared with the physical-to-logical (P2L) mapping data item associated with the data input / output operation to perform a first determination as to whether the data input / output operation has succeeded or failed. Based on the response, a second determination is made regarding whether the data input / output operation has succeeded or failed. Based on both the first and second determinations, it is determined whether the data input / output operation has succeeded or failed, and Based on the first determination and the second determination regarding whether the data input / output operation has succeeded or failed, the logical-to-physical mapping data item, i.e., the L2P mapping data item, is updated based on the P2L mapping data item.

2. The memory system of claim 1, wherein when the result of the first determination differs from the result of the second determination, the controller determines whether the data input / output operation has succeeded or failed by assigning a higher priority to the first determination than to the second determination.

3. The memory system according to claim 1, Each of the plurality of memory groups is a page, and The status data includes bitmap information indicating that the page corresponding to the at least one memory group is blank or empty.

4. The memory system according to claim 1, Each of the plurality of memory groups is a memory block, and The status data includes a page count, which indicates how many pages of the data item are stored in the memory block corresponding to the at least one memory group.

5. The memory system of claim 1, wherein the memory device: After the data input / output operation corresponding to the command is completed, the response is transmitted to the controller, and When the metadata is updated through the data input / output operation, the status data is transmitted to the controller.

6. The memory system according to claim 5, The data input / output operations include data programming operations or data erasure operations performed within the at least one memory group, and The memory device further updates the status data according to the data programming operation or the data erasure operation performed within the at least one memory group.

7. A method for operating a memory system, comprising: Transmit commands for data input / output operations to the memory device; Perform a data input / output operation that changes data within at least one memory group of a memory device comprising multiple memory groups, each memory group comprising multiple non-volatile memory cells; Receive a response to the command and output from the memory device, the response including the result of the data input / output operation; Based on the response, a second determination is made regarding whether the data input / output operation has succeeded or failed. Receive status data about the at least one memory group output from the memory device in response to the data input / output operation, the status data including current operation information related to the at least one memory group whose data is changed during the data input / output operation; The state data is compared with the physical-to-logical mapping data item (P2L mapping data item) associated with the data input / output operation to perform a first determination as to whether the data input / output operation has succeeded or failed. Based on both the first determination and the second determination, it is determined whether the data input / output operation has succeeded or failed; as well as Based on the first determination and the second determination regarding whether the data input / output operation has succeeded or failed, the logical-to-physical mapping data item, i.e., the L2P mapping data item, is updated based on the P2L mapping data item.

8. The method of claim 7, wherein determining whether the data input / output operation has succeeded or failed comprises: When the first determined result differs from the second determined result, the first determined result is assigned a higher priority than the second determined result.

9. The method according to claim 7, Each of the plurality of memory groups is a page, and The status data includes bitmap information indicating that the page corresponding to the at least one memory group is blank or empty.

10. The method according to claim 7, Each of the plurality of memory groups is a memory block, and The status data includes a page count, which indicates how many pages a data item is stored in within the memory block corresponding to the at least one memory group.

11. The method according to claim 7, wherein: After the metadata has been updated via the data input / output operation, the memory device transmits the status data.

12. The method according to claim 7, The data input / output operations include data programming operations or data erasure operations performed within the at least one memory group, and The method further includes updating the status data based on the data programming operation or the data erasure operation performed within the at least one memory group.

13. A controller coupled to a memory device via at least one data path, the memory device comprising a plurality of memory groups, each memory group comprising a plurality of non-volatile memory cells, wherein the controller comprises at least one processor and at least one memory, the at least one memory comprising computer program code, wherein the at least one processor and the at least one memory comprising the computer program code enable the controller to: Transmit commands for data input / output operations to the memory device; The data input / output operation that modifies data is performed within at least one memory group in the memory device; Receive a response to the command and output from the memory device, the response including the result of the data input / output operation; Based on the response, a second determination is made regarding whether the data input / output operation has succeeded or failed. Receive status data about the at least one memory group output from the memory device in response to the data input / output operation, the status data including current operation information related to the at least one memory group whose data is changed during the data input / output operation; The state data is compared with the physical-to-logical mapping data item (P2L mapping data item) associated with the data input / output operation to perform a first determination as to whether the data input / output operation has succeeded or failed. Based on both the first determination and the second determination, it is determined whether the data input / output operation has succeeded or failed; as well as Based on the first determination and the second determination regarding whether the data input / output operation has succeeded or failed, the logical-to-physical mapping data item, i.e., the L2P mapping data item, is updated based on the P2L mapping data item.

14. The controller of claim 13, wherein the at least one processor, including the at least one memory containing the computer program code, further enables the controller to determine whether the data input / output operation has succeeded or failed by assigning a higher priority to the first determination than the second determination when the first determination result differs from the second determination result.

15. The controller according to claim 13, Each of the plurality of memory groups is a page, and The status data includes bitmap information indicating that the page corresponding to the at least one memory group is empty or blank.

16. The controller according to claim 13, Each of the plurality of memory groups is a memory block, and The status data includes a page count, which indicates how many pages of the data item are stored in the memory block corresponding to the at least one memory group.

17. The controller of claim 13, wherein the at least one memory including the computer program code, utilizing the at least one processor, further enables the controller to: The response is received from the memory device after the data input / output operation is completed, and When the metadata is updated through the data input / output operation, the status data is received from the memory device.

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