Semiconductor device

Abstract

A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, and the first dielectric layer surrounds a first metal interconnect. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer surrounds a plug and a second metal interconnect, the second metal interconnect directly contacting the first metal interconnect. The third dielectric layer is disposed on the second dielectric layer, and the third dielectric layer surrounds a first magnetic tunnel junction structure and a third metal interconnect, the third metal interconnect directly contacting the first magnetic tunnel junction structure and the second metal interconnect, the first magnetic tunnel junction structure directly contacting the plug. The semiconductor device of the present invention can integrate a logic area of a general magnetic random access memory device and a dummy magnetic random access memory device area, effectively reducing a layout pattern.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a magnetoresistive random access memory (MRAM). Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated. Its advantage is that it can retain stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One object of the present invention is to provide a semiconductor device having a specially structured dummy magnetic tunnel junction sensing element that can be directly disposed within a logic region, thereby simplifying the layout pattern of the semiconductor device and improving device performance.

[0005] To achieve the above objectives, a preferred embodiment of the present invention provides a semiconductor device including a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate and surrounds a first metal interconnect. The second dielectric layer is disposed on the first dielectric layer and surrounds a plug and a second metal interconnect, the second metal interconnect directly contacting the first metal interconnect. The third dielectric layer is disposed on the second dielectric layer and surrounds a first magnetic tunneling junction structure and a third metal interconnect, the third metal interconnect directly contacting the first magnetic tunneling junction structure and the second metal interconnect, the first magnetic tunneling junction structure directly contacting the plug.

[0006] In general, this invention directly integrates a dummy magnetic random access memory (MRMemory) device into the logic region of a conventional MRMemory device, and utilizes a metal interconnect layer within this logic region to create a short circuit or open circuit in the magnetic tunnel junction structure, thus forming a dummy structure. In this way, the semiconductor device of this invention can integrate the logic region of a conventional MRMemory device and the dummy MRMemory region, effectively reducing the layout pattern and allowing for significant area savings and improved leakage current reduction in the component configuration design of the MRMemory device. Attached Figure Description

[0007] Figure 1 This is a top view of the layout of the semiconductor device in the first embodiment of the present invention;

[0008] Figure 2 This is a top view of the layout of the semiconductor device in the second embodiment of the present invention;

[0009] Figure 3 This is a cross-sectional schematic diagram of the semiconductor device in the second embodiment of the present invention;

[0010] Figure 4 This is another cross-sectional schematic diagram of the semiconductor device in the second embodiment of the present invention;

[0011] Figure 5 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention;

[0012] Figure 6 This is another cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0013] Explanation of main component symbols

[0014] 100 Semiconductor Devices

[0015] 101 Magnetic Random Access Memory Area

[0016] 103 Logical Region

[0017] 105. Dummy Magnetic Random Access Memory Area

[0018] 120 Metal-Oxide-Semiconductor Transistor

[0019] 121 doped region

[0020] 123 Gate Structure

[0021] 131, 133, 135 Plugs

[0022] Metal layers 141, 143, and 145

[0023] 150 Magnetic Tunneling Structure

[0024] 160. Feigned magnetic tunneling structure

[0025] 300 Semiconductor Devices

[0026] 301 Magnetic Random Access Memory Area

[0027] 303 Dummy Magnetic Random Access Memory Area

[0028] 310 substrate

[0029] 350 Magnetic Tunneling Structure

[0030] 351 Lower Electrode

[0031] 353 Upper Electrode

[0032] 355 Magnetic tunneling stack

[0033] 355a Fixed Layer

[0034] 355b Barrier Layer

[0035] 355c Free Layer

[0036] 357 Spacer wall

[0037] 360, 360a, 360b False magnetic tunneling structure

[0038] 361 Lower electrode

[0039] 363 Upper Electrode

[0040] 365 Magnetic Tunneling Stack

[0041] 365a Fixed Layer

[0042] 365b barrier layer

[0043] 365c Free Layer

[0044] 367, 467 spacer

[0045] 371 Stop Layer

[0046] 373 Intermetallic Dielectric Layer

[0047] 375 Metal Internal Wiring

[0048] 381 Stop Layer

[0049] 382 Intermetallic Dielectric Layer

[0050] 383 Intermetallic Dielectric Layer

[0051] 384 plug

[0052] 385 Metal Internal Wiring

[0053] 386 Metal Internal Wiring

[0054] 390 Stop Layer Detailed Implementation

[0055] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.

[0056] Please see Figure 1 The diagram shown is a top view of the layout of a semiconductor device 100 according to a first embodiment of the present invention. The semiconductor device 100 is, for example, a magnetic random access memory (MRAM), which mainly includes a substrate (not shown), such as a substrate made of a semiconductor material. The semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composites, silicon carbide, gallium arsenide, etc. Preferably, a magnetic random access memory region (MRAM region) 101 and a logic region 103 are defined on the substrate. In this embodiment, the magnetic random access memory (MRMemory) region 101 is disposed on at least one outer side of the logic region 103. Multiple magnetic tunneling junction (MTJ) structures 150 are disposed within the MRMemory region 101. Furthermore, a dummy MRMemory region 105 is additionally disposed between the MRMemory region 101 and the logic region 103, and multiple dummy MTJ structures 160 are disposed within the dummy MRMemory region 105. In other words, the semiconductor device 100 of this embodiment separates the MRMemory region 101 and the logic region 103 by providing the dummy MRMemory region 105.

[0057] The magnetic random access memory region 101 of the substrate further includes a plurality of metal-oxide-semiconductor (MOS) transistors 120, which are, for example, planar or non-planar (such as fin structure transistors) transistor elements. Specifically, the MOS transistors 120 include a plurality of doped regions 121 and a plurality of gate structures (e.g., metal gates) 123 spanning the doped regions 121. Each doped region 121 extends parallel to each other along the same direction (e.g., the X direction), such that the doped regions 121 located on both sides of each gate structure 123 can serve as the source / drain (not shown) of each gate structure 123, respectively. The fabrication processes of planar or non-planar transistor elements are well known in the art and will not be described in detail here.

[0058] An inter-layer dielectric layer (not shown) is also disposed on the substrate to cover the metal-oxide-semiconductor transistor 120. Multiple plugs 131, 133, and 135, and metal layers 141, 143, and 145 are further disposed within this inter-layer dielectric layer. In one embodiment, the metal layers 141, 143, and 145, and the plugs 131, 133, and 135 can be embedded in the inter-layer dielectric layer using a single-damascene fabrication process or a dual-damascene fabrication process. Both single-damascene and dual-damascene fabrication processes are well-known technologies in the art and will not be described in detail here. In this embodiment, the metal layers 141, 143, and 145 serve as a first metal interconnect layer (metal 1, M1), and other metal interconnect layers (not shown) can be disposed above this first metal interconnect layer. However, Figure 1 For the sake of simplicity, only the first metal interconnect layer is shown.

[0059] The plug 131 and the metal layer 141 are electrically connected to the source of the metal-oxide-semiconductor transistor 120, allowing the metal layer 141 to serve as a common source line connecting adjacent sources of the metal-oxide-semiconductor transistor 120. These sources can then be connected to an external voltage through other interconnect layers subsequently provided. These other interconnect layers may include, for example, a first contact hole layer (via 1, V1), a second metal interconnect layer (metal 2, M2), a second contact hole layer (via 2, V2), and a third metal interconnect layer (metal 3, M3) disposed above the first metal interconnect layer, but are not limited thereto. The plug 133 and the metal layer 143 are electrically connected to the drains of the metal-oxide-semiconductor transistor 120, such as... Figure 1As shown. On the other hand, the plug 135 and the metal layer 145 are disposed in the logic region 103 to electrically connect to the gate structure 123 of the metal oxide semiconductor transistor 120. Subsequently, the metal oxide semiconductor transistor 120 can be further connected to a word line (WL, not shown) and a bit line (BL, not shown) through the aforementioned interconnect layers, and receive voltage signals from the word line and the bit line respectively.

[0060] In short, the semiconductor device 100 of this embodiment additionally provides a dummy magnetic random access memory (MRMemory) region 105 between the magnetic random access memory (MRMemory) region 101 and the logic region 103. For example, the dummy MRMemory region 105 has two rows of staggered dummy magnetic tunneling structures 160, while the logic region 103 does not have any magnetic tunneling structures, including magnetic tunneling structures 150 or dummy magnetic tunneling structures 160. Thus, the layout pattern of the semiconductor device 100, composed of the MRMemory region 101, the dummy MRMemory region 105, and the logic region 103, avoids contamination or even leakage caused by the upper metal interconnects, thereby improving device performance. Furthermore, the number of rows of the aforementioned dummy magnetic tunneling structures 160 is merely illustrative; those skilled in the art should understand that the specific number of rows of dummy magnetic tunneling structures 160 within the dummy MRMemory region 105 can be adjusted according to actual component requirements and is not limited thereto.

[0061] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of the present invention may have other forms, and is not limited to those described above. For example, in the aforementioned embodiments, the layout pattern of the semiconductor device 100 occupies a large space, which may affect the overall operating performance of the device. Therefore, according to another embodiment of the present invention, another semiconductor device can be provided, which can effectively integrate the dummy magnetic random access memory region 105 and the logic region 103, thereby significantly saving space and improving device performance. Other embodiments or variations of the semiconductor device will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments and does not repeat the same points. In addition, the same elements in the embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.

[0062] Please see Figures 2 to 4 As shown, it illustrates a schematic diagram of a semiconductor device 300 in a second embodiment of the present invention. Figure 2 This is a top view of the semiconductor device 300. Figure 3 as well as Figure 4 They are respectively Figure 2The diagram shows cross-sectional views along tangents A-A' and B-B'. The semiconductor device 300 is, for example, a magnetic random access memory device, which includes a substrate 310, also made of the semiconductor material. Furthermore, the substrate 310 also has a plurality of metal-oxide-semiconductor transistors 120 and a plurality of plugs 131 and 133 electrically connected to the metal-oxide-semiconductor transistors 120. The similarities will not be repeated here. It should be noted that, for the sake of simplicity, Figure 2 The first metal interconnect layer of the semiconductor device 300 (i.e., the aforementioned metal layers 141, 143, and 145) is omitted from the drawing. Only the second contact hole layer (i.e., metal interconnect 385), the third metal interconnect layer (i.e., metal interconnect 386), and the magnetic tunneling structure (including magnetic tunneling structure 350 and dummy magnetic tunneling structure 360) disposed above the first metal interconnect layer are shown. Figure 3 and Figure 4 The first metal interconnect layer, metal oxide semiconductor transistor 120, and plugs 131 and 133 of the semiconductor device 300 are omitted from the drawing. Instead, only the second metal interconnect layer (i.e., metal interconnect 375), the second contact hole layer, the third metal interconnect layer, and the magnetic tunnel junction structure disposed above the first metal interconnect layer are drawn.

[0063] In this embodiment, the substrate 310 preferably defines a magnetic random access memory (MRMemory) region 301 and a dummy magnetic random access memory (MRMemory) region 303. The dummy MRMemory region 303 integrates the dummy MRMemory region 105 and the logic region 103 described in the previous embodiment. Specifically, the dummy magnetic tunneling structures in the dummy MRMemory region 105 and the interconnect layers in the logic region 103 are both located in the same region (i.e., the dummy MRMemory region 303). Specifically, the magnetic random access memory region 301 also contains multiple magnetic tunneling structures 350, while the dummy MRMemory region 303 contains multiple staggered dummy magnetic tunneling structures 360. The dummy magnetic tunneling structures 360 can be repeatedly arranged with the multiple metal interconnects 385 located in the dummy MRMemory region 303, with one dummy magnetic tunneling structure 360 ​​adjacent to one metal interconnect 385. Figure 2 As shown.

[0064] like Figure 3 as well as Figure 4As shown, a stop layer 371, an inter-metal dielectric layer 373, and a plurality of metal interconnects 375 are also disposed on the substrate 310. Specifically, the stop layer 371 and the inter-metal dielectric layer 373 sequentially cover the first metal interconnect layer and other active (not shown) or passive (not shown) components disposed within / on the substrate 310, and surround each metal interconnect 375. In addition, a plurality of plugs 384 and the metal interconnects 385 located in the dummy magnetic random access device region 303 are further disposed on the inter-metal dielectric layer 373, respectively electrically connecting the underlying metal interconnects 375. Furthermore, a magnetic tunneling structure 350, a dummy magnetic tunneling structure 360, and / or a metal interconnect 386 are disposed above the plug 384 and the metal interconnect 385. A stop layer 381 and an intermetallic dielectric layer 382 surround the plug 384 and the metal interconnect 385. Simultaneously, another intermetallic dielectric layer 383, disposed above the intermetallic dielectric layer 382, ​​surrounds the magnetic tunneling structure 350, the dummy magnetic tunneling structure 360, and the metal interconnect 386. Thus, the metal interconnect 386 can be electrically connected to the metal interconnect 375 through the metal interconnect 385. In addition, another stop layer 390 is disposed on the substrate 310, covering the magnetic tunneling structure 350, the dummy magnetic tunneling structure 360, the metal interconnect 386, and the intermetallic dielectric layer 383.

[0065] In this embodiment, the aforementioned metal interconnects 375, 385, 386, etc., can be embedded in the inter-metal dielectric layers (such as inter-metal dielectric layers 373, 382, ​​383) and / or the stop layers (such as stop layers 371, 381) and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. Preferably, metal interconnect 375 includes a trench conductor as the second metal interconnect layer, metal interconnect 385 preferably includes a contact hole conductor as the second contact hole layer, and metal interconnect 386 preferably includes a trench conductor as the third metal interconnect layer, but is not limited thereto.

[0066] Furthermore, each of the metal interconnects 375, 385, and 386 includes a barrier layer (not shown) and a conductive layer (not shown) sequentially deposited within the trench / contact hole. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the conductive layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), and cobalt tungsten phosphide (CoWP), preferably including copper, but not limited thereto. On the other hand, the plug 384 may be made of the group consisting of tungsten, copper, aluminum, titanium-aluminum alloy, and cobalt tungsten phosphide, preferably a material different from the conductive layer, but not limited thereto. In this embodiment, the intermetallic dielectric layers 373 and 383 preferably comprise ultra-low dielectric constant dielectric materials, the intermetallic dielectric layer 382 preferably comprises tetraethyl orthosilicate (TEOS), and the stop layers 371, 381, and 390 may be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but are not limited thereto.

[0067] In this embodiment, each magnetic tunneling junction structure 350 and each dummy magnetic tunneling junction structure 360 ​​may respectively include a lower electrode 351, 361, an upper electrode 353, 363, a magnetic tunneling junction stack 355, 365, and a spacer wall 357, 367. Specifically, the lower electrodes 351, 361 of the magnetic tunneling junction structure 350 and the dummy magnetic tunneling junction structure 360 ​​are disposed above the plug 384 or the intermetallic dielectric layer 382, ​​and the magnetic tunneling junction stack 355, 365 and the upper electrodes 353, 363 are sequentially stacked above the lower electrodes 351, 361. The spacer walls 357 and 367 then cover the top and sidewalls of the upper electrodes 353 and 363, the magnetic tunneling stacks 355 and 365, and the lower electrodes 351 and 361. The spacer walls 357 and 367 can further extend to the intermetallic dielectric layer 382, ​​covering a portion of the sidewalls of the plug 384 and the metal interconnect 385. Figure 3 and Figure 4As shown. Preferably, the magnetic tunneling junction stacks 355 and 365 comprise, from bottom to top, a pinned layer 355a, 365a, a barrier layer 355b, 365b, and a free layer 355c, 365c. The lower electrodes 351, 361 and the upper electrodes 353, 363 preferably comprise a conductive material, such as, but not limited to, tantalum, platinum (Pt), copper, gold (Au), or aluminum; the pinned layers 355a and 365a can be composed of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc., to fix or restrict the magnetic moment direction of adjacent layers; the barrier layers 355b and 365b can be composed of an insulating material containing oxides, such as aluminum oxide (AlO). x The free layers 355c and 365c may be made of ferromagnetic materials, such as iron, cobalt, nickel or their alloys such as cobalt-iron-boron (CoFeB); while the spacer walls 357 and 367 may include a dielectric material, preferably silicon nitride, but are not limited thereto.

[0068] It should be noted that, with Figure 3 and Figure 4 From a cross-sectional perspective, the magnetic tunneling structure 350, the dummy magnetic tunneling structure 360, and the third metal interconnect layer (i.e., metal interconnect 386) are preferably disposed together within the same inter-metal dielectric layer 383, while the plug 384 and the second contact hole layer (i.e., metal interconnect 385) are preferably disposed together within the inter-metal dielectric layer 382. The plug 384 is disposed directly below the magnetic tunneling structure 350, and is covered directly above by the stop layer 390; alternatively, the plug 384 can also be disposed directly below the dummy magnetic tunneling structure 360 ​​(e.g., ...). Figure 4 The virtual magnetic tunneling junction structure 360a shown on the left, or the direct contact between the intermetallic dielectric layer 382 without any metal interconnects (as shown on the left). Figure 4 The dummy magnetic tunneling structure 360b shown on the right is further covered by the metal interconnect 386 directly above it. Both the dummy magnetic tunneling structure 360a and dummy magnetic tunneling structure 360b can be selected in one direction (e.g., Figure 4The interconnects are arranged alternately along the tangent B-B' direction in the structure, or other arrangements can be selected (such as only setting the dummy magnetic tunneling junction structure 360a or dummy magnetic tunneling junction structure 360b), but are not limited thereto. Since part of the intermetallic dielectric layer 383 and part of the spacer wall 367 are etched during the formation of the metal interconnects 386, the metal interconnects 386 can directly contact the upper electrode 363 of the dummy magnetic tunneling junction structure 360a, and then directly conduct to the metal interconnects 375 below through the metal interconnects 385 and / or the plug 384, causing a short circuit.

[0069] Furthermore, it should be noted that the etching degree of the spacer wall 367 can be adjusted according to the actual component requirements during the fabrication process of the metal interconnect 386. For example, in one embodiment, during the etching process, the portion of the spacer wall 367 covering the upper electrode 363 can be completely removed, and the portion of the spacer wall 367 covering the magnetic tunneling stack 365 and the lower electrode 361 can be partially removed, without directly exposing the sidewalls of the magnetic tunneling stack 365 or the lower electrode 361. In this way, the spacer wall 367 can be etched into a stepped structure, exposing the upper electrode 363 of the dummy magnetic tunneling structure 360, so that the upper metal interconnect 386 can directly contact the upper electrode 363, such as... Figure 4 As shown, but not limited to. In the dummy magnetic tunneling structure 360a, the spacer wall 367 is arranged around the sidewalls of the magnetic tunneling stack 365, the lower electrode 361, and a portion of the plug 384, while the spacer wall 367 of the dummy magnetic tunneling structure 360b can be arranged around the magnetic tunneling stack 365, the lower electrode 361, and a portion of the intermetallic dielectric layer 382, ​​as shown. Figure 4 As shown. However, in another embodiment, it is also possible to completely remove all portions of the spacer wall covering the upper electrode 363 and the magnetic tunneling junction stack 365 during the etching process, forming a spacer wall 467 only disposed on the lower electrode 361, the plug 384, and / or the intermetallic dielectric layer 382, ​​as shown. Figure 5 as well as Figure 6 As shown. In this configuration, a top surface of the second gap wall 467 can be flush with a bottom surface of the magnetic tunneling stack 365, allowing the metal interconnect 386 to be completely covered and disposed on the upper electrode 363 and the magnetic tunneling stack 365 of the dummy magnetic tunneling structure 360, as shown. Figure 6 As shown.

[0070] In short, in this embodiment, the semiconductor device 300 has metal interconnects 386 and plugs 384 respectively disposed above and below the dummy magnetic tunneling junction structure 360, so that the dummy magnetic tunneling junction structure 360a can be directly connected to the metal interconnect 375 below through the metal interconnects 385 and / or plugs 384, causing a short circuit. On the other hand, the dummy magnetic tunneling junction structure 360b can also be directly disposed in the inter-metal dielectric layer 382, ​​forming an open circuit. With this configuration, new dummy magnetic tunneling junction structures can be provided, including dummy magnetic tunneling junction structures 360a and dummy magnetic tunneling junction structures 360b. These dummy magnetic tunneling junction structures can be directly disposed in the logic region of a general magnetic random access memory device (such as the logic region 103 in the aforementioned embodiment), and the interconnect layer in the logic region can be used to create a short circuit or open circuit in the dummy magnetic tunneling junction structure. Thus, the semiconductor device 300 of this embodiment can integrate the logic area of ​​a general magnetic random access memory device and the virtual magnetic random access memory device area, simplifying the layout pattern of the semiconductor device 300.

[0071] In general, this invention directly integrates a dummy magnetic random access memory (MRMemory) device into the logic region of a conventional MRMemory device, and utilizes a metal interconnect layer within this logic region to create a short circuit or open circuit in the magnetic tunnel junction structure, thus forming a dummy structure. In this way, the semiconductor device of this invention can integrate the logic region of a conventional MRMemory device and the dummy MRMemory region, effectively reducing the layout pattern and allowing for significant area savings and improved leakage current reduction in the component configuration design of the MRMemory device.

[0072] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: Base; A first dielectric layer is disposed on the substrate, the first dielectric layer surrounding the first metal interconnect; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer surrounds the plug and the second metal interconnect, the second metal interconnect directly contacts the first metal interconnect; as well as A third dielectric layer is disposed on the second dielectric layer. The third dielectric layer surrounds the first magnetic tunneling junction structure and the third metal interconnect. The third metal interconnect is a continuous single integral structure. The plug and the second metal interconnect respectively contact the first magnetic tunneling junction structure and the third metal interconnect, and the third metal interconnect directly contacts the first magnetic tunneling junction structure.

2. The semiconductor device according to claim 1, characterized in that, The second and third metal interconnects are made of the same conductive material.

3. The semiconductor device according to claim 1, characterized in that, The plug and the second metal interconnect include different conductive materials.

4. The semiconductor device according to claim 1, characterized in that, The first magnetic tunneling structure includes a first magnetic tunneling stack and a first gap wall surrounding the first magnetic tunneling stack and the plug.

5. The semiconductor device according to claim 4, characterized in that, The first gap wall has a stepped structure.

6. The semiconductor device according to claim 4, characterized in that, The first gap wall also covers the second dielectric layer.

7. The semiconductor device according to claim 4, characterized in that, The first gap wall is disposed on the side wall of the plug.

8. The semiconductor device according to claim 1, characterized in that, It also includes a logic region, in which multiple first magnetic tunnel junction structures and multiple second metal interconnects are alternately arranged.

9. The semiconductor device according to claim 1, characterized in that, The first magnetic tunneling structure includes a dummy magnetic tunneling structure.

10. The semiconductor device according to claim 1, characterized in that, The first dielectric layer also surrounds the fourth metal interconnect, and the third dielectric layer also surrounds the second magnetic tunneling junction structure and the fifth metal interconnect. The bottom surface of the second magnetic tunneling junction structure directly contacts the second dielectric layer, and the fifth metal interconnect directly contacts the second magnetic tunneling junction structure and the fourth metal interconnect.

11. The semiconductor device according to claim 10, characterized in that, The second magnetic tunneling structure includes a dummy magnetic tunneling structure.

12. The semiconductor device according to claim 10, characterized in that, The second magnetic tunneling junction structure includes a second magnetic tunneling junction stack and a second gap wall surrounding the second magnetic tunneling junction stack and a portion of the second dielectric layer.

13. The semiconductor device according to claim 12, characterized in that, The second gap wall has a stepped structure.

14. The semiconductor device according to claim 12, characterized in that, The top surface of the second gap wall is coplanar with the bottom surface of the second magnetic tunnel junction stack.

15. The semiconductor device according to claim 11, characterized in that, It also includes a logic region, in which multiple first magnetic tunneling junction structures, multiple second magnetic tunneling junction structures, and multiple second metal interconnects are alternately arranged.

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