Display device

Abstract

A display device includes a first light emitting element in a first display region, a first pixel circuit connected to the first light emitting element in a first non-display region spaced apart from the first display region, an insulating layer covering the first pixel circuit, a metal wiring on the insulating layer, connected to the first pixel circuit, and extending from the first non-display region to a second non-display region between the first display region and the first non-display region, and a transparent wiring on the insulating layer, connecting the first light emitting element and the metal wiring, and extending from the first display region to a surface of the metal wiring, wherein a trench is defined in the second non-display region in a surface of the insulating layer, and the metal wiring is in the trench in the second non-display region.

Description

Technical Field

[0001] The embodiments relate to display devices. More specifically, the embodiments relate to display devices including narrow bezels and methods of manufacturing the display device. Background Technology

[0002] A display device can convert electrical signals to display images, thereby providing visual information to the user. The display device may include a transmission area that allows incident external light to pass through it. Functional modules such as camera modules and sensor modules, located on the back surface of the display device, can detect or identify targets, users, etc., located on the front surface of the display device through the transmission area.

[0003] To increase the transmittance of the transmission region, the display device may include transparent wiring disposed in the transmission region. Summary of the Invention

[0004] Because transparent wiring has a relatively small thickness compared to opaque metal wiring, breakage defects can occur in transparent wiring due to the step underneath it.

[0005] The embodiments provide a display device for preventing defects in transparent wiring.

[0006] The embodiments provide a method for manufacturing a display device to prevent defects in transparent wiring.

[0007] The display device in this embodiment includes: a substrate, the substrate including a first display area, a first non-display area spaced apart from the first display area, and a second non-display area disposed between the first display area and the first non-display area; a first light-emitting element disposed in the first display area and on the substrate; a first pixel circuit disposed in the first non-display area, on the substrate, and electrically connected to the first light-emitting element; a first insulating layer disposed on the substrate, covering the first pixel circuit, and including a first surface facing the substrate; a metal wiring disposed on the first insulating layer, connected to the first pixel circuit, extending from the first non-display area to the second non-display area, and including a first surface facing the first insulating layer; and a transparent wiring disposed on the first insulating layer, connecting the first light-emitting element and the metal wiring, and extending from the first display area to a second surface of the metal wiring opposite to the first surface of the metal wiring. A trench is defined in the second non-display area, in the second surface of the first insulating layer opposite to the first surface of the first insulating layer. The metal wiring is disposed in the trench in the second non-display area.

[0008] In an embodiment, the depth of the trench may be less than the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

[0009] In an embodiment, the depth of the trench may be substantially equal to the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

[0010] In an embodiment, the depth of the trench may be greater than the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

[0011] In an embodiment, the depth of the trench may be less than the thickness of the metal wiring in a direction perpendicular to the main plane of the substrate.

[0012] In an embodiment, the depth of the trench can be substantially equal to the thickness of the metal wiring in a direction perpendicular to the main plane of the substrate.

[0013] In an embodiment, the thickness of the transparent wiring can be less than the thickness of the metal wiring in the direction perpendicular to the main plane of the substrate.

[0014] In an embodiment, the first insulating layer may include an inorganic insulating material.

[0015] In an embodiment, the display device may further include a second insulating layer disposed between the substrate and the first insulating layer.

[0016] In one embodiment, the trench may be recessed from the second surface of the first insulating layer into at least a portion of the second insulating layer.

[0017] In this embodiment, the second insulating layer may include an inorganic insulating material.

[0018] In an embodiment, the first insulating layer may include an organic insulating material.

[0019] In one embodiment, the first light-emitting element may include a pixel electrode, an emitting layer disposed on the pixel electrode, and a counter electrode disposed on the emitting layer. Transparent wiring may be connected to the pixel electrode.

[0020] In embodiments, the transparent wiring may include at least one of indium tin oxide (“ITO”), indium zinc oxide (“IZO”), indium gallium oxide (“IGO”), tin oxide (SnO2) and zinc oxide (ZnO).

[0021] In an embodiment, the substrate may further include a second display area surrounding at least a portion of the first display area. The display device may further include a second light-emitting element disposed in the second display area and on the substrate, and a second pixel circuit overlapping with and electrically connected to the second light-emitting element.

[0022] In this embodiment, the transmittance of the first display area may be greater than that of the second display area.

[0023] The method of manufacturing a display device in the embodiments includes: forming a first pixel circuit on a substrate in a first non-display region spaced apart from a first display region; forming a first insulating layer on the substrate covering the first pixel circuit and including a first surface facing the substrate; defining a trench in a second surface of the first insulating layer opposite to the first surface of the first insulating layer in a second non-display region disposed between the first display region and the first non-display region; forming a metal wiring on the first insulating layer that is connected to the first pixel circuit, extends from the first non-display region to the second non-display region, is in the trench, and includes the first surface facing the first insulating layer; forming a transparent wiring on the first insulating layer that extends from the first display region to the second surface of the metal wiring opposite to the first surface of the metal wiring; and forming a first light-emitting element connected to the transparent wiring on the first insulating layer in the first display region.

[0024] In an embodiment, a halftone mask or a slit mask may be used to define the trench.

[0025] In an embodiment, the first insulating layer may include an inorganic insulating material.

[0026] In an embodiment, the first insulating layer may include an organic insulating material.

[0027] In the display device of the embodiment, a groove recessed downward from the upper surface of the first insulating layer can be defined in the second non-display area and within the first insulating layer, and a metal wiring can be disposed in the second non-display area and within the groove to reduce the step caused by the metal wiring. Therefore, defects in the transparent wiring connecting the first light-emitting element and the metal wiring, which extends from the first display area to the upper surface of the metal wiring, can be prevented due to the step of the metal wiring.

[0028] In the method of manufacturing the display device in the embodiment, a trench recessed downward from the upper surface of the first insulating layer can be defined in a second non-display area, and a metal wiring in the trench, connected to the first pixel circuit and extending from the first non-display area to the second non-display area, can be disposed on the first insulating layer to reduce steps caused by the metal wiring. Therefore, breakage defects in the transparent wiring can be prevented. Furthermore, a halftone mask or a slit mask can be used to define the trench so that no additional process for forming the trench is required. Attached Figure Description

[0029] Illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a plan view illustrating an embodiment of the display device.

[0031] Figure 2It's a diagram. Figure 1 An enlarged planar view of region I in the image.

[0032] Figure 3 It is illustrated along Figure 2 The cross-sectional view of the display device is taken from line II-II'.

[0033] Figure 4 This is a cross-sectional view illustrating an embodiment of the display device.

[0034] Figure 5 This is a cross-sectional view illustrating an embodiment of the display device.

[0035] Figure 6 This is a cross-sectional view illustrating an embodiment of the display device.

[0036] Figure 7 This is a cross-sectional view illustrating an embodiment of the display device.

[0037] Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional view illustrating an embodiment of a method for manufacturing a display device.

[0038] Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view illustrating an embodiment of a method for manufacturing a display device. Detailed Implementation

[0039] The display device and the method of manufacturing the display device in the embodiments will be explained in detail below with reference to the accompanying drawings.

[0040] It will be understood that when an element is referred to as "on" another element, it can be directly on that other element, or an intermediary element can be between them. Conversely, when an element is referred to as "directly" on another element, there is no intermediary element.

[0041] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited to these terms. These terms are used only to distinguish one element, component, area, layer, or section from another element, component, area, layer, or section. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first section” discussed below may be referred to as a second element, second component, second area, second layer, or second section.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the context clearly indicates otherwise. “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and / or “comprising” or “includes” and / or “including” as used in this specification indicate the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0043] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another illustrated in the figures. It will be understood that these relative terms are intended to cover different orientations of the device other than those depicted in the figures. In an embodiment, when a device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can cover both “down” and “up” orientations. Similarly, when a device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can cover both “up” and “down” orientations.

[0044] As used herein, “about” or “approximately” includes stated values ​​and means within an acceptable range of deviation from a particular value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0045] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this invention, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0046] Figure 1 This is a plan view illustrating an embodiment of the display device.

[0047] Reference Figure 1 The display device 100 may include a display area DA and a non-display area NDA. The non-display area NDA may surround at least a portion of the display area DA. The display area DA may include a first display area DA1 and a second display area DA2. The second display area DA2 may surround at least a portion of the first display area DA1.

[0048] Figure 2 It's a diagram. Figure 1 An enlarged planar view of region I in the image.

[0049] Reference Figure 1 and Figure 2 The non-display area NDA may include a first non-display area NDA1 and a second non-display area NDA2. The first non-display area NDA1 may be spaced apart from the first display area DA1, and the second non-display area NDA2 may be located between the first display area DA1 and the first non-display area NDA1.

[0050] The first light-emitting element EL1 may be disposed in the first display area DA1. In an embodiment, each of the first light-emitting elements EL1 may emit at least one of red light, green light, and blue light.

[0051] The first pixel circuit PC1 can be disposed in the first non-display area NDA1. The first light-emitting element EL1 can be connected to the first pixel circuit PC1 through the metal wiring 200 and the transparent wiring 210. The first pixel circuit PC1 can provide driving current to the first light-emitting element EL1.

[0052] The metal wiring 200 can be connected to the first pixel circuit PC1. The metal wiring 200 can extend from the first pixel circuit PC1, which is disposed in the first non-display area NDA1, to the second non-display area NDA2.

[0053] The transparent wiring 210 can be connected to the first light-emitting element EL1. The transparent wiring 210 can extend from the first light-emitting element EL1 disposed in the first display area DA1 to the second non-display area NDA2. The transparent wiring 210 can be connected to the metal wiring 200 in the second non-display area NDA2.

[0054] The second light-emitting element EL2 and the second pixel circuit PC2 can be disposed in the second display area DA2. In an embodiment, each of the second light-emitting elements EL2 can emit at least one of red, green, and blue light. The second pixel circuit PC2 can overlap with and be connected to the second light-emitting element EL2 respectively. The second pixel circuit PC2 can provide driving current to the second light-emitting element EL2.

[0055] In one embodiment, the transmittance of the first display area DA1 may be greater than the transmittance of the second display area DA2. In another embodiment, for example, the first display area DA1 may transmit external light, while the second display area DA2 may not transmit external light. Therefore, the first display area DA1 may be a transmissive area, and the second display area DA2 may be a non-transmissive area.

[0056] Figure 3 It is illustrated along Figure 2 The cross-sectional view of the display device 100 taken from line II-II' in the figure.

[0057] Reference Figure 2 and Figure 3 The display device 100 may include a substrate 110, a buffer layer 120, an active pattern 130, a first gate insulating layer 140, a first gate electrode 150, a second gate insulating layer 160, a second gate electrode 170, an interlayer insulating layer 180, a first source / drain electrode 190, a metal wiring 200, a transparent wiring 210, a first via insulating layer 220, a pixel electrode 250, a pixel defining layer 260, an emission layer 270, and a counter electrode 280.

[0058] The substrate 110 may be a transparent insulating substrate. In embodiments, for example, the substrate 110 may include glass, quartz, or plastic.

[0059] A buffer layer 120 may be disposed on a substrate 110. In an embodiment, the buffer layer 120 may comprise an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0060] The active pattern 130 can be disposed on the buffer layer 120. The active pattern 130 can be disposed in the first non-display area NDA1 and the second display area DA2. In one embodiment, the active pattern 130 may include amorphous silicon or polycrystalline silicon, etc. In another embodiment, the active pattern 130 may include oxide semiconductor, etc.

[0061] A first gate insulating layer 140 may be disposed on the active pattern 130. The first gate insulating layer 140 may cover the active pattern 130 on the buffer layer 120. In an embodiment, the first gate insulating layer 140 may comprise an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0062] The first gate electrode 150 may be disposed on the first gate insulating layer 140. The first gate electrode 150 may be disposed in the first non-display area NDA1 and the second display area DA2. The first gate electrode 150 may overlap with the active pattern 130. In an embodiment, the first gate electrode 150 may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0063] The active pattern 130 and the first gate electrode 150 can form a transistor. In an embodiment, the active pattern 130 and the first gate electrode 150 can form a first transistor TR1 in a first non-display area NDA1 and a second transistor TR2 in a second display area DA2.

[0064] A second gate insulating layer 160 may be disposed on the first gate electrode 150. The second gate insulating layer 160 may cover the first gate electrode 150 on the first gate insulating layer 140. In an embodiment, the second gate insulating layer 160 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0065] The second gate electrode 170 may be disposed on the second gate insulating layer 160. The second gate electrode 170 may be disposed in the first non-display area NDA1 and the second display area DA2. The second gate electrode 170 may overlap with the first gate electrode 150. In an embodiment, the second gate electrode 170 may include a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0066] The first gate electrode 150 and the second gate electrode 170 can form a capacitor. In an embodiment, the first gate electrode 150 and the second gate electrode 170 can form a first capacitor CAP1 in a first non-display area NDA1, and a second capacitor CAP2 in a second display area DA2.

[0067] The first transistor TR1 and the first capacitor CAP1 disposed in the first non-display area NDA1 can form a first pixel circuit PC1. In other words, the first pixel circuit PC1 may include the first transistor TR1 and the first capacitor CAP1. The second transistor TR2 and the second capacitor CAP2 disposed in the second display area DA2 can form a second pixel circuit PC2. In other words, the second pixel circuit PC2 may include the second transistor TR2 and the second capacitor CAP2.

[0068] An interlayer insulating layer 180 may be disposed on the second gate electrode 170. The interlayer insulating layer 180 may cover the second gate electrode 170 on the second gate insulating layer 160. In an embodiment, the interlayer insulating layer 180 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0069] A first contact hole CH1 may be defined in the first non-display area NDA1 and the second display area DA2, within the first gate insulating layer 140, the second gate insulating layer 160, and the interlayer insulating layer 180. The first contact hole CH1 may expose the active pattern 130.

[0070] An opening OP can be defined in the first display area DA1 within the first gate insulating layer 140, the second gate insulating layer 160, and the interlayer insulating layer 180. Because the opening OP is defined, the first gate insulating layer 140, the second gate insulating layer 160, and the interlayer insulating layer 180 may not be provided in the first display area DA1. Because the opening OP is defined in the first display area DA1, the transmittance of the first display area DA1 can be greater than the transmittance of the second display area DA2.

[0071] The first source / drain electrode 190 may be disposed on the interlayer insulating layer 180. The first source / drain electrode 190 may be disposed in the first non-display area NDA1 and the second display area DA2. The first source / drain electrode 190 may be connected to the active pattern 130 through the first contact hole CH1. In an embodiment, the first source / drain electrode 190 may comprise a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0072] Metal wiring 200 may be disposed on interlayer insulating layer 180. Metal wiring 200 may be connected to first pixel circuit PC1 and may extend from first non-display area NDA1 to second non-display area NDA2. Metal wiring 200 may be connected to first source / drain electrode 190 disposed in first non-display area NDA1. In embodiments, metal wiring 200 may include metals such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0073] In one embodiment, the metal wiring 200 may be integral with the first source / drain electrode 190. In such an embodiment, the metal wiring 200 may comprise a material substantially the same as that of the first source / drain electrode 190.

[0074] The trench TCH, recessed downwards from the upper surface of the interlayer insulating layer 180, can be defined within the second non-display area NDA2 and within the interlayer insulating layer 180. The metal wiring 200 can extend from the first non-display area NDA1 into the trench TCH in the second non-display area NDA2. In other words, the metal wiring 200 can be disposed within the trench TCH in the second non-display area NDA2.

[0075] In an embodiment, the depth of the trench TCH can be less than that of the interlayer insulating layer 180 along the thickness direction (e.g., Figure 3 The thickness (in the vertical direction) of the material. In such an embodiment, the metal wiring 200 disposed in the trench TCH can be spaced apart from the second gate insulating layer 160 disposed below the interlayer insulating layer 180.

[0076] In an embodiment, the depth of the trench TCH can be less than the thickness of the metal wiring 200. In such an embodiment, the height of the upper surface of the metal wiring 200 disposed in the trench TCH from the substrate 110 can be greater than the height of the upper surface of the interlayer insulating layer 180 along the thickness direction (e.g., Figure 3 The height of the metal wiring 200 in the vertical direction from the substrate 110. In other words, the upper surface of the metal wiring 200 disposed in the trench TCH can protrude upwards from the upper surface of the interlayer insulating layer 180.

[0077] The transparent wiring 210 can extend from the first display area DA1 to the upper surface of the metal wiring 200. Therefore, the lower surface of the transparent wiring 210 can contact the upper surface of the metal wiring 200 disposed in the trench TCH, and the transparent wiring 210 can be electrically connected to the metal wiring 200. The transparent wiring 210 can be disposed in the opening OP on the buffer layer 120 in the first display area DA1, and can be disposed on the interlayer insulating layer 180 in the second non-display area NDA2.

[0078] In an embodiment, the transparent wiring 210 may include a transparent conductive oxide such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), indium gallium oxide (“IGO”), tin oxide (SnO2) or zinc oxide (ZnO).

[0079] In an embodiment, the thickness of the transparent wiring 210 can be less than the thickness of the metal wiring 200. For example, in an embodiment, the thickness of the metal wiring 200 can be approximately 7000 angstroms. Furthermore, the thickness of the transparent wiring 210 can be approximately Or smaller.

[0080] The transmittance of the transparent wiring 210 can be greater than that of the first gate electrode 150, the second gate electrode 170, the first source / drain electrode 190, and the metallic wiring 200. Because the transparent wiring 210 with relatively high transmittance is disposed in the first display area DA1, the first display area DA1 can have a higher transmittance than the second display area DA2, the first non-display area NDA1, and the second non-display area NDA2.

[0081] When the trench TCH is not confined within the second non-display area NDA2 and the interlayer insulating layer 180, a relatively large step can be provided by the metal wiring 200, and therefore, the transparent wiring 210 with a relatively small thickness can be disconnected around the end of the metal wiring 200. Specifically, the first portion of the transparent wiring 210 disposed on the interlayer insulating layer 180 and the second portion of the transparent wiring 210 disposed on the upper surface of the metal wiring 200 can be disconnected from each other by the step created by the metal wiring 200.

[0082] However, in embodiments of the present invention, the trench TCH may be defined within the second non-display area NDA2 and the interlayer insulating layer 180, and the metal wiring 200 may extend into the trench TCH to reduce the step caused by the metal wiring 200. Therefore, it is possible to prevent the transparent wiring 210 from breaking due to the step created by the metal wiring 200.

[0083] The first via insulating layer 220 may be disposed on the first source / drain electrode 190, the metallic wiring 200, and the transparent wiring 210. The first via insulating layer 220 may cover the first source / drain electrode 190, the metallic wiring 200, and the transparent wiring 210 on the interlayer insulating layer 180. In embodiments, the first via insulating layer 220 may include organic insulating materials such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, or epoxy resin.

[0084] Pixel electrode 250 may be disposed on the first via insulating layer 220. Pixel electrode 250 may be disposed in the first display area DA1 and the second display area DA2. The pixel electrode 250 disposed in the first display area DA1 can be connected to the transparent wiring 210 through a via defined in the first via insulating layer 220, and the pixel electrode 250 disposed in the second display area DA2 can be connected to the first source / drain electrode 190 through a via defined in the first via insulating layer 220. Pixel electrode 250 may include metal or transparent conductive oxide, etc. In embodiments, for example, pixel electrode 250 may include silver (Ag) or indium tin oxide (“ITO”), etc.

[0085] A pixel defining layer 260 may be disposed on the pixel electrode 250. The pixel defining layer 260 may partially cover the pixel electrode 250 on the first via insulating layer 220. In an embodiment, an opening exposing the central portion of the pixel electrode 250 may be defined in the pixel defining layer 260, and the pixel defining layer 260 may cover the peripheral portion of the pixel electrode 250. In an embodiment, the pixel defining layer 260 may include an organic insulating material such as a photoresist, polyacrylic acid resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, or epoxy resin.

[0086] The emitting layer 270 may be disposed in the opening of the pixel defining layer 260 and on the pixel electrode 250. The emitting layer 270 may include at least one of organic light-emitting materials and quantum dots.

[0087] In embodiments, the organic light-emitting material may include low-molecular-weight organic compounds or high-molecular-weight organic compounds. In embodiments, the low-molecular-weight organic compounds may include at least one of copper phthalocyanine, diphenylbenzidine (N,N'-diphenylbenzidine), and tris(8-hydroxyquinoline)aluminum. In embodiments, for example, the high-molecular-weight organic compounds may include at least one of poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylenevinylene, and polyfluorene.

[0088] In embodiments, the quantum dot may include a core comprising one of group II-VI compounds, group III-V compounds, group IV-VI compounds, group IV elements, group IV compounds, and combinations thereof. In embodiments, the quantum dot may have a core-shell structure comprising a core and a shell surrounding the core. The shell may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core, and as a charging layer for imparting electrophoretic properties to the quantum dot.

[0089] The counter electrode 280 can be disposed on the pixel defining layer 260 and the emission layer 270. The counter electrode 280 may include a metal or a transparent conductive oxide, etc. In embodiments, for example, the counter electrode 280 may include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), titanium (Ti), etc.

[0090] Pixel electrode 250, emitting layer 270, and opposing electrode 280 can form light-emitting elements. In an embodiment, pixel electrode 250, emitting layer 270, and opposing electrode 280 can form a first light-emitting element EL1 in a first display area DA1, and a second light-emitting element EL2 in a second display area DA2.

[0091] Figure 4 This is a cross-sectional view illustrating an embodiment of the display device.

[0092] Reference Figure 4 The described display device 101 can be used with reference to Figure 3 The described display device 100 is substantially the same or similar, differing only in the depth of the trench TCH. Therefore, descriptions of repeating elements will be omitted.

[0093] Reference Figure 4 In one embodiment, the depth of the trench TCH can be substantially equal to the thickness of the interlayer insulating layer 180. In such an embodiment, the metal wiring 200 disposed in the trench TCH can contact the upper surface of the second gate insulating layer 160 disposed below the interlayer insulating layer 180.

[0094] In the illustrated embodiment, because the depth of the trench TCH is substantially equal to the thickness of the interlayer insulating layer 180, the step caused by the metal wiring 200 can be further reduced. Therefore, it is possible to prevent the transparent wiring 210 from breaking due to the step created by the metal wiring 200.

[0095] Figure 5 This is a cross-sectional view illustrating an embodiment of the display device.

[0096] Reference Figure 5 The described display device 102 can be used with reference to Figure 3 The described display device 100 is substantially the same or similar, differing only in the depth of the trench TCH. Therefore, descriptions of repeating elements will be omitted.

[0097] Reference Figure 5 In one embodiment, the depth of the trench TCH can be greater than the thickness of the interlayer insulating layer 180. In such an embodiment, the trench TCH can be recessed from the upper surface of the interlayer insulating layer 180 to at least a portion of the second gate insulating layer 160 disposed below the interlayer insulating layer 180.

[0098] In one embodiment, the depth of the trench TCH can be substantially equal to the thickness of the metal wiring 200. In such an embodiment, the height of the upper surface of the metal wiring 200 disposed in the trench TCH from the substrate 110 can be substantially equal to the height of the upper surface of the interlayer insulating layer 180 from the substrate 110. In other words, the upper surface of the metal wiring 200 disposed in the trench TCH can not protrude upwards compared to the upper surface of the interlayer insulating layer 180.

[0099] In the illustrated embodiment, because the depth of the trench TCH is substantially equal to the thickness of the metal wiring 200, steps caused by the metal wiring 200 are substantially avoided. Therefore, it is possible to prevent the transparent wiring 210 from breaking due to steps created by the metal wiring 200.

[0100] Figure 6 This is a cross-sectional view illustrating an embodiment of the display device.

[0101] Reference Figure 6 The display device 103 may include a substrate 110, a buffer layer 120, an active pattern 130, a first gate insulating layer 140, a first gate electrode 150, a second gate insulating layer 160, a second gate electrode 170, an interlayer insulating layer 180, a first source / drain electrode 190, a first via insulating layer 220, a second source / drain electrode 230, a metal wiring 200, a transparent wiring 210, a second via insulating layer 240, a pixel electrode 250, a pixel defining layer 260, an emissive layer 270, and a counter electrode 280. (Refer to...) Figure 6 The described display device 103 can be used with reference to Figure 3The described display device 100 is substantially the same as or similar to the original, except that it further includes a second source / drain electrode 230 and a second through-hole insulating layer 240, as well as the positions of the metal wiring 200 and the transparent wiring 210. Therefore, descriptions of repeating elements will be omitted.

[0102] The second source / drain electrode 230 may be disposed on the first via insulating layer 220. The second source / drain electrode 230 may be disposed in the first non-display area NDA1 and the second display area DA2. The second source / drain electrode 230 may be connected to the first source / drain electrode 190 via a second contact hole CH2 defined in the first via insulating layer 220. In embodiments, the second source / drain electrode 230 may comprise a metal such as copper (Cu), molybdenum (Mo), aluminum (Al), or titanium (Ti).

[0103] Metal wiring 200 can be disposed on the first through-hole insulating layer 220. Metal wiring 200 can be connected to the second source / drain electrode 230 disposed in the first non-display area NDA1.

[0104] In one embodiment, the metal wiring 200 may be integrated with the second source / drain electrode 230. In such an embodiment, the metal wiring 200 may comprise a material substantially the same as that of the second source / drain electrode 230.

[0105] The trench TCH, recessed downwards from the upper surface of the first through-hole insulating layer 220, can be defined within the second non-display area NDA2 and the first through-hole insulating layer 220. The metal wiring 200 can extend from the first non-display area NDA1 to the second non-display area NDA2 within the trench TCH.

[0106] In one embodiment, the depth of the trench TCH can be less than the thickness of the first via insulating layer 220. In such an embodiment, the metal wiring 200 disposed in the trench TCH can be spaced apart from the interlayer insulating layer 180 disposed below the first via insulating layer 220.

[0107] In one embodiment, the depth of the trench TCH can be less than the thickness of the metal wiring 200. In such an embodiment, the height of the upper surface of the metal wiring 200 disposed in the trench TCH from the substrate 110 can be greater than the height of the upper surface of the first via insulating layer 220 from the substrate 110. In other words, the upper surface of the metal wiring 200 disposed in the trench TCH can protrude upwards beyond the upper surface of the first via insulating layer 220.

[0108] The transparent wiring 210 can extend from the first display area DA1 to the upper surface of the metal wiring 200. The transparent wiring 210 can be disposed in the first display area DA1 and the second non-display area NDA2, on the first through-hole insulating layer 220.

[0109] In an embodiment of the invention, the trench TCH may be defined within the second non-display area NDA2 and the first via insulating layer 220, and the metal wiring 200 may extend into the trench TCH to reduce the step caused by the metal wiring 200. Therefore, it is possible to prevent the transparent wiring 210 from breaking due to the step created by the metal wiring 200.

[0110] The second via insulating layer 240 can be disposed on the second source / drain electrode 230, the metal wiring 200, and the transparent wiring 210. The second via insulating layer 240 can cover the second source / drain electrode 230, the metal wiring 200, and the transparent wiring 210 on the first via insulating layer 220. In embodiments, the second via insulating layer 240 may include organic insulating materials such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, or epoxy resin.

[0111] Pixel electrode 250 can be disposed on the second via insulating layer 240. Pixel electrode 250 disposed in the first display area DA1 can be connected to transparent wiring 210 through vias defined in the second via insulating layer 240, and pixel electrode 250 disposed in the second display area DA2 can be connected to the second source / drain electrode 230 through vias defined in the second via insulating layer 240.

[0112] Figure 7 This is a cross-sectional view illustrating an embodiment of the display device.

[0113] Reference Figure 7 The described display device 104 can be used with reference to Figure 6 The described display device 103 is substantially the same as or similar to the one described above, except for the depth of the trench TCH. Therefore, descriptions of repeating elements will be omitted.

[0114] Reference Figure 7 In one embodiment, the depth of the trench TCH can be substantially equal to the thickness of the metal wiring 200. In such an embodiment, the height of the upper surface of the metal wiring 200 disposed in the trench TCH from the substrate 110 can be substantially equal to the height of the upper surface of the first via insulating layer 220 from the substrate 110. In other words, the upper surface of the metal wiring 200 disposed in the trench TCH may not protrude upwards compared to the upper surface of the first via insulating layer 220.

[0115] In the illustrated embodiment, because the depth of the trench TCH is substantially equal to the thickness of the metal wiring 200, steps caused by the metal wiring 200 are substantially avoided. Therefore, it is possible to prevent the transparent wiring 210 from breaking due to steps created by the metal wiring 200.

[0116] Figure 8 , Figure 9 , Figure 10 and Figure 11 This is a cross-sectional view illustrating an embodiment of a method for manufacturing a display device. In the embodiment, for example, Figures 8 to 11 Can be manufactured according to diagrams Figure 3 The method of the display device 100 illustrated in the figure.

[0117] Reference Figure 8 The first pixel circuit and the second pixel circuit can be formed on the substrate 110, in the first non-display area (also called the first non-pixel area) NDA1, and in the second display area (also called the second pixel area) DA2. The buffer layer 120, the active pattern 130, the first gate insulating layer 140, the first gate electrode 150, the second gate insulating layer 160, and the second gate electrode 170 can be formed sequentially on the substrate 110.

[0118] The active pattern 130 and the first gate electrode 150 can form a first transistor TR1 in the first non-display area NDA1 and a second transistor TR2 in the second display area DA2. The first gate electrode 150 and the second gate electrode 170 can form a first capacitor CAP1 in the first non-display area NDA1 and a second capacitor CAP2 in the second display area DA2. The first transistor TR1 and the first capacitor CAP1 disposed in the first non-display area NDA1 can form a first pixel circuit, and the second transistor TR2 and the second capacitor CAP2 disposed in the second display area DA2 can form a second pixel circuit.

[0119] An interlayer insulating layer 180 may be formed on a substrate 110 on which the first pixel circuit and the second pixel circuit are formed. In an embodiment, the interlayer insulating layer 180 may be formed from an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride using a vapor deposition method (such as chemical vapor deposition, physical vapor deposition, etc.).

[0120] Reference Figure 9 A first contact hole CH1, passing through the first gate insulating layer 140, the second gate insulating layer 160, and the interlayer insulating layer 180, can be defined in each of the first non-display area NDA1 and the second display area DA2. An opening OP, passing through the first gate insulating layer 140, the second gate insulating layer 160, and the interlayer insulating layer 180, can be defined in the first display area DA1. A trench TCH, recessed downward from the upper surface of the interlayer insulating layer 180, can be defined in the second non-display area NDA2. The depth of the trench TCH can be less than the depth of the first contact hole CH1 and the depth of the opening OP.

[0121] The first contact hole CH1, the opening OP, and the trench TCH can be defined substantially simultaneously by the photomask 300. In an embodiment, the photomask 300 can be a halftone mask or a slit mask.

[0122] When the photomask 300 is a halftone mask, it may include a light-transmitting portion 310, a light-blocking portion 320, and a semi-transparent portion 330. The light-transmitting portion 310 can transmit substantially all external light, and the light-blocking portion 320 can block substantially all external light. The transmittance of the semi-transparent portion 330 may be less than that of the light-transmitting portion 310, but may be greater than that of the light-blocking portion 320. The light-transmitting portion 310 may overlap with the first contact hole CH1 and the opening OP, and the semi-transparent portion 330 may overlap with the trench TCH.

[0123] When a half-width mask or a slot mask is used to define the first contact hole CH1, the opening OP, and the trench TCH, the depth of the trench TCH can be less than the depth of the first contact hole CH1 and the depth of the opening OP. Furthermore, because the trench TCH is defined together with the first contact hole CH1 and the opening OP, no additional process is required to form the trench TCH.

[0124] Reference Figure 10 The first source / drain electrode 190 and the metal wiring 200 can be disposed on the interlayer insulating layer 180. The first source / drain electrode 190 can fill the first contact hole CH1 and can contact the active pattern 130. The metal wiring 200 can be connected to the first pixel circuit and can extend from the first non-display area NDA1 to a trench TCH in the second non-display area NDA2. In an embodiment, the metal wiring 200 can be integrated with the first source / drain electrode 190.

[0125] Reference Figure 11 Transparent wiring 210 can be disposed on interlayer insulating layer 180. Transparent wiring 210 can extend from the first display area DA1 to the upper surface of metal wiring 200. Trench TCH can be defined in the second non-display area NDA2, within interlayer insulating layer 180, and metal wiring 200 can extend into trench TCH to reduce steps caused by metal wiring 200. Therefore, although transparent wiring 210 extends from the upper surface of interlayer insulating layer 180 to the upper surface of metal wiring 200, transparent wiring 210 will not be broken due to steps created by metal wiring 200.

[0126] Reference Figure 3The first through-hole insulating layer 220 can be disposed on the first source / drain electrode 190, the metal wiring 200, and the transparent wiring 210, and the first light-emitting element EL1 and the second light-emitting element EL2 can be disposed in the first display area DA1 and the second display area DA2, respectively, on the first through-hole insulating layer 220. The pixel electrode 250, the pixel defining layer 260, the emitting layer 270, and the opposing electrode 280 can be sequentially disposed on the first through-hole insulating layer 220. The pixel electrode 250, the emitting layer 270, and the opposing electrode 280 can form the first light-emitting element EL1 in the first display area DA1, and can form the second light-emitting element EL2 in the second display area DA2.

[0127] Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a cross-sectional view illustrating an embodiment of a method for manufacturing a display device. In the embodiment, for example, Figures 12 to 15 Can be manufactured according to diagrams Figure 6 The method of the display device 103 illustrated in the figure. References will be omitted. Figure 6 as well as Figures 12 to 15 The description of the elements of the method for manufacturing the display device 103, and its reference... Figure 3 as well as Figures 8 to 11 The methods for manufacturing the display device 100 described are substantially the same or similar.

[0128] Reference Figure 12 The first pixel circuit and the second pixel circuit can be disposed on the substrate 110, in the first non-display area NDA1, and in the second display area DA2, respectively. The buffer layer 120, the active pattern 130, the first gate insulating layer 140, the first gate electrode 150, the second gate insulating layer 160, the second gate electrode 170, the interlayer insulating layer 180, and the first source / drain electrode 190 can be disposed sequentially on the substrate 110.

[0129] The first through-hole insulating layer 220 can be disposed on the substrate 110 on which the first pixel circuit and the second pixel circuit are disposed. In an embodiment, the first through-hole insulating layer 220 can be formed by coating with an organic insulating material such as photoresist, polyacrylic resin, polyimide resin, polyamide resin, silicone resin, acrylic resin, epoxy resin, etc.

[0130] Reference Figure 13 The second contact hole CH2, passing through the first through-hole insulating layer 220, can be defined in each of the first non-display area NDA1 and the second display area DA2, and the trench TCH, recessed downward from the upper surface of the first through-hole insulating layer 220, can be defined in the second non-display area NDA2. The depth of the trench TCH can be less than the depth of the second contact hole CH2.

[0131] The second contact hole CH2 and the trench TCH can be defined substantially simultaneously using a photomask 400. In an embodiment, the photomask 400 can be a halftone mask or a slit mask.

[0132] When the photomask 400 is a halftone mask, it may include a light-transmitting portion 410, a light-blocking portion 420, and a semi-transparent portion 430. The light-transmitting portion 410 can transmit substantially all external light, and the light-blocking portion 420 can block substantially all external light. The transmittance of the semi-transparent portion 430 may be less than that of the light-transmitting portion 410, but may be greater than that of the light-blocking portion 420. The light-transmitting portion 410 may overlap with the second contact hole CH2, and the semi-transparent portion 430 may overlap with the trench TCH.

[0133] When the second contact hole CH2 and the trench TCH are defined using a halftone mask or a slot mask, the depth of the trench TCH can be less than the depth of the second contact hole CH2. Furthermore, because the trench TCH is defined together with the second contact hole CH2, no additional process is required to form the trench TCH.

[0134] Reference Figure 14 The second source / drain electrode 230 and the metal wiring 200 can be disposed on the first via insulating layer 220. The second source / drain electrode 230 can fill the second contact hole CH2 and can contact the first source / drain electrode 190. The metal wiring 200 can be connected to the first pixel circuit and can extend from the first non-display area NDA1 to the trench TCH in the second non-display area NDA2. In an embodiment, the metal wiring 200 can be integrated with the second source / drain electrode 230.

[0135] Reference Figure 15 Transparent wiring 210 can be disposed on the first via insulating layer 220. Transparent wiring 210 can extend from the first display area DA1 to the upper surface of the metal wiring 200. A trench TCH can be defined in the second non-display area NDA2 and the first via insulating layer 220, and the metal wiring 200 can extend into the trench TCH to reduce the step caused by the metal wiring 200. Therefore, although transparent wiring 210 extends from the upper surface of the first via insulating layer 220 to the upper surface of the metal wiring 200, transparent wiring 210 will not be broken due to the step created by the metal wiring 200.

[0136] Reference Figure 6The second via insulating layer 240 can be disposed on the second source / drain electrode 230, the metal wiring 200, and the transparent wiring 210, and the first light-emitting element EL1 and the second light-emitting element EL2 can be disposed in the first display area (also called the first pixel area) DA1 and the second display area DA2, respectively, on the second via insulating layer 240. The pixel electrode 250, the pixel defining layer 260, the emitting layer 270, and the opposing electrode 280 can be sequentially disposed on the second via insulating layer 240.

[0137] The display device in the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, portable media players (“PMPs”), personal digital assistants (“PDAs”), or MP3 players, etc.

[0138] Although the display device and the method of manufacturing the display device in the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and can be modified and changed by those skilled in the art without departing from the spirit of the art.

Claims

1. A display device, comprising: A substrate, the substrate including a first display area, a first non-display area spaced apart from the first display area, and a second non-display area disposed between the first display area and the first non-display area; A first light-emitting element is disposed in the first display area on the substrate; A first pixel circuit is disposed in the first non-display area, on the substrate, and electrically connected to the first light-emitting element; A first insulating layer is disposed on the substrate, covers the first pixel circuit, and includes a first surface facing the substrate; Metal wiring, which is disposed on the first insulating layer, connected to the first pixel circuit, extends from the first non-display area to the second non-display area, and includes a first surface facing the first insulating layer; as well as A transparent wiring is disposed on the first insulating layer, connects the first light-emitting element and the metal wiring, and extends from the first display area to a second surface of the metal wiring opposite to the first surface of the metal wiring. The trench is defined in the second non-display area, in the second surface of the first insulating layer opposite to the first surface of the first insulating layer, and The metal wiring is disposed in the trench in the second non-display area.

2. The display device according to claim 1, wherein The depth of the trench is less than the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

3. The display device according to claim 1, wherein, The depth of the trench is equal to the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

4. The display device according to claim 1, wherein, The depth of the trench is greater than the thickness of the first insulating layer in a direction perpendicular to the main plane of the substrate.

5. The display device according to claim 1, wherein, The depth of the trench is less than the thickness of the metal wiring in a direction perpendicular to the main plane of the substrate.

6. The display device according to claim 1, wherein, The depth of the trench is equal to the thickness of the metal wiring in a direction perpendicular to the main plane of the substrate.

7. The display device according to claim 1, wherein, The thickness of the transparent wiring is less than the thickness of the metal wiring in the direction perpendicular to the main plane of the substrate.

8. The display device according to claim 1, further comprising: A second insulating layer is disposed between the substrate and the first insulating layer. The trench is recessed from the second surface of the first insulating layer into at least a portion of the second insulating layer.

9. The display device according to claim 1, wherein, The first light-emitting element includes a pixel electrode, an emitting layer disposed on the pixel electrode, and a counter electrode disposed on the emitting layer. The transparent wiring is connected to the pixel electrode.

10. The display device according to claim 1, wherein, The substrate further includes a second display area surrounding at least a portion of the first display area. The display device further includes: A second light-emitting element, the second light-emitting element being disposed in the second display area and on the substrate; and The second pixel circuit overlaps with and is electrically connected to the second light-emitting element. The transmittance of the first display area is greater than that of the second display area.

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