An improved method and improved structure of a driving circuit of a multi-phase charge pump

Abstract

This invention provides an improved method for driving a multi-phase charge pump circuit. By disconnecting the short between the B and S terminals of an NMOS transistor, the B terminal is controlled to a low level, connecting it to the input terminal VBUS and the lower-level terminal of the output terminal Vout. This method protects the Fly capacitor from short-circuit overcurrent and prevents backflow of Vout, while also reducing power consumption in the Q_Block MOS transistor and system heat generation.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronic technology, and in particular relates to an improved method for a driving circuit of a multi-phase charge pump and an improved structure of the driving circuit. Background Art

[0002] The standard circuit architecture of the multi-phase charge pump driving circuit is as follows: Figure 1 As shown, a Q_Block MOS tube is needed to monitor the charge pump Fly capacitor short circuit to cause system overcurrent protection and prevent current backflow at the output end Vout. Due to the large system current, the internal resistance of the Q_Block MOS will lose energy, resulting in low system efficiency and high chip heat. Summary of the Invention

[0003] The purpose of the present invention is to provide an improved method and structure of a multi-phase charge pump drive circuit, which can achieve the functions of protecting the Fly capacitor from short-circuit overcurrent and preventing Vout backflow, while saving the power consumption of the Q_Block MOS tube and reducing system heat.

[0004] In order to achieve the above object, the technical solution of the present invention is implemented as follows:

[0005] A method for improving a multi-phase charge pump drive circuit includes disconnecting the short circuit between the B and S poles of one of the multi-phase cascaded NMOS tubes located between the input terminal VBUS and the output terminal Vout in the charge pump chip drive circuit; and controlling the B pole to a low level so that the B pole is connected to the lower end of the input terminal VBUS and the output terminal Vout.

[0006] Furthermore, the low-level control method includes: connecting the B pole to the input terminal VBUS through a diode, and connecting the B pole to the output terminal Vout through another diode; the B pole is connected to the anode of each diode.

[0007] Furthermore, the diode is a Schottky diode.

[0008] Furthermore, the low-level control method includes: setting a ping-pong circuit connecting the input terminal VBUS and the output terminal Vout, the ping-pong circuit selecting the low-level end between the input terminal VBUS and the output terminal Vout and connecting it to the B pole.

[0009] Furthermore, the ping-pong circuit is composed of a switching circuit and a comparison circuit connected to each other.

[0010] On the other hand, the present invention also proposes an improved structure of a driving circuit of a multi-phase charge pump, in which each charge pump chip is connected to multiple multi-phase cascaded NMOS tubes; the B pole and the S pole of one of the NMOS tubes located between the input terminal VBUS and the output terminal Vout are short-circuited and disconnected, and the B pole is connected to a low-level control circuit, so that the B pole is connected to the low-level end of the input terminal VBUS and the output terminal Vout.

[0011] Furthermore, the low-level control circuit includes: a cathode of a diode connected to the input terminal VBUS, a cathode of another diode connected to the output terminal Vout; and anodes of both diodes connected to the B pole.

[0012] Furthermore, the diode is a Schottky diode.

[0013] Furthermore, the low-level control circuit includes a ping-pong circuit connected to the input terminal VBUS and the output terminal Vout, and the ping-pong circuit controls and selects the low-level end between the input terminal VBUS and the output terminal Vout to be connected to the B pole.

[0014] Furthermore, the ping-pong circuit is mainly composed of a switching circuit and a comparison circuit connected to each other. The comparison circuit compares the levels of the input terminal VBUS and the output terminal Vout. The switching circuit controls the low-level end to be connected to the B pole.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The improved method and structure proposed in the present invention change the bias voltage of the body diode of the first-stage MOS in the multi-phase cascade MOS to block the backflow current, thereby realizing the function of protecting the Fly capacitor from short circuit overcurrent and preventing Vout backflow in the cascaded MOS tube;

[0017] 2. The improved method and improved structure proposed in the present invention remove the Q_Block-level MOS tube, thereby improving system efficiency, eliminating block-level power loss, and reducing system heat generation. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a diagram of a driving circuit architecture of a multi-phase charge pump in the prior art;

[0019] Figure 2 This is a schematic diagram of the body diode structure of an NMOS tube in the prior art;

[0020] Figure 3 Schematic diagram of the improved body diode structure in an embodiment of the present invention;

[0021] Figure 41 is a diagram showing an improved structure of a driving circuit of a multi-phase charge pump according to a first embodiment of the present invention;

[0022] Figure 5 1 is a diagram showing an improved structure of a driving circuit of a multi-phase charge pump according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0024] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0025] The design concept of the present invention is based on the body diode structure of the NMOS tube. The body diode structure of the NMOS tube in the prior art is as follows: Figure 2 The specific instructions are as follows:

[0026] The NMOS transistor is formed on a P-type silicon wafer substrate B with two N+ regions, namely the source region and the drain region, whose electrodes are respectively the source S and the drain D. The substrate B is also covered with a SiO2 insulating layer, and the insulating layer is covered with polysilicon as the gate G.

[0027] There are PN junctions between the two N+ regions and the P-type silicon wafer substrate B, which is equivalent to the existence of two diodes, namely body diodes;

[0028] But usually the substrate B is connected to the source S to keep the potential consistent, such as Figure 2 The B and S short-circuit structure shown in the figure is as follows: therefore, the diode between the B and S poles does not exist due to the short-circuit of B and S.

[0029] The basis of the improved method proposed by the present invention is based on the improvement of the body diode structure, such as Figure 3 As shown, the short-circuit structure between the B pole and the S pole is disconnected, so that there is still a diode between the B pole and the S pole.

[0030] Example 1:

[0031] For the multi-phase charge pump, the charge pump chip is provided with four multi-phase cascaded NMOS transistors, namely NMOS transistors Q1, Q2, Q3, and Q4; the drain of NMOS transistor Q1 is connected to the power input terminal VBUS, the S-pole of NMOS transistor Q1 is connected to the D-pole of NMOS transistor Q2, the S-pole of NMOS transistor Q2 is connected to the D-pole of NMOS transistor Q3, and the S-pole of NMOS transistor Q3 is connected to the D-pole of NMOS transistor Q4; the S-pole of NMOS transistor Q2 and the D-pole of NMOS transistor Q3 are also connected to the output terminal Vout.

[0032] like Figure 4As shown, in this embodiment, the NMOS tube Q2 as the first-stage MOS in the multi-phase cascade MOS is configured as follows: Figure 3 The short circuit between the B pole and the S pole is disconnected, and the B pole is connected to the input terminal VBUS through a Schottky diode, and the B pole is connected to the output terminal Vout through another Schottky diode; wherein the B pole is connected to the positive pole of each Schottky diode.

[0033] Based on the above design structure, the unidirectional conduction effect of the Schottky diode connects the B pole of the NMOS tube Q2 to the low-level end of the input terminal VBUS and the output terminal Vout, keeping the B pole always connected to the low-level end, so that the N+ region of the NMOS tube body is always reverse-biased with the P-type silicon wafer substrate B, thereby blocking the backflow of current from Vout (usually the battery terminal).

[0034] In addition, although the short circuit between the B pole and the S pole of the NMOS transistor Q2 is disconnected in this embodiment, if an NMOS transistor Q1 is used instead of Q2, the short circuit between the B pole and the S pole of the NMOS transistor Q1 is disconnected, and the B pole of Q1 is connected to the input terminal VBUS and the output terminal Vout through a Schottky diode, this is also possible and can also achieve the effect of this embodiment.

[0035] Example 2:

[0036] The second embodiment adopts another low-level control scheme based on the first embodiment, which is as follows:

[0037] For the multi-phase charge pump, the charge pump chip is provided with four multi-phase cascaded NMOS transistors, namely NMOS transistors Q1, Q2, Q3, and Q4; the drain of NMOS transistor Q1 is connected to the power input terminal VBUS, the S-pole of NMOS transistor Q1 is connected to the D-pole of NMOS transistor Q2, the S-pole of NMOS transistor Q2 is connected to the D-pole of NMOS transistor Q3, and the S-pole of NMOS transistor Q3 is connected to the D-pole of NMOS transistor Q4; the S-pole of NMOS transistor Q2 and the D-pole of NMOS transistor Q3 are also connected to the output terminal Vout.

[0038] like Figure 5 As shown, in this embodiment, the NMOS tube Q2 as the first-stage MOS in the multi-phase cascade MOS is configured as follows: Figure 3The short between the B and S poles is disconnected, and the B pole is connected to a ping-pong circuit. The ping-pong circuit is primarily composed of a switch circuit and a comparison circuit. The switch circuit is connected to the input terminal VBUS and the output terminal Vout, respectively. The switch circuit is connected to a comparison circuit, which is used to compare the voltage levels of the input terminal VBUS and the output terminal Vout. Based on the comparison result, the switch circuit controls the low-level terminal to be conductively connected to the B pole of the NMOS transistor Q2. The switch circuit and comparison circuit are relatively conventional circuits in the electronics field and will not be described in detail here.

[0039] Based on the above design structure, through the active selection of the comparison circuit, the B pole of the NMOS tube Q2 is connected to the low-level end of the input terminal VBUS and the output terminal Vout, keeping the B pole always connected to the low-level end, so that the N+ region of the NMOS tube body is always reverse-biased with the P-type silicon wafer substrate B, thereby blocking the backflow of current from Vout (usually the battery terminal).

[0040] In addition, although the short circuit between the B pole and the S pole of the NMOS transistor Q2 is disconnected in this embodiment, if the NMOS transistor Q1 is used instead of Q2, the short circuit between the B pole and the S pole of the NMOS transistor Q1 is disconnected, and the B pole of Q1 is connected to the ping-pong circuit, this is also possible and can also achieve the effect of this embodiment.

[0041] The above embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for improving a driving circuit of a multi-phase charge pump, characterized in that: The short circuit between the B and S poles of one of the NMOS tubes in the multi-phase cascade connection, where the substrate B and the source S are connected between the input terminal VBUS and the output terminal Vout, is disconnected, so that a diode still exists between the B and S poles; and the B pole is controlled to be low-level so that the B pole is connected to the lower end of the input terminal VBUS and the output terminal Vout; The low-level control method includes: connecting the B pole to the input terminal VBUS through a diode, and connecting the B pole to the output terminal Vout through another diode; the B pole is connected to the anode of each diode; or: The low-level control method includes: setting a ping-pong circuit connected to the input terminal VBUS and the output terminal Vout, wherein the ping-pong circuit selects a low-level end between the input terminal VBUS and the output terminal Vout and connects the low-level end to the B pole.

2. The method for improving the driving circuit of a multi-phase charge pump according to claim 1, wherein: The diode is a Schottky diode.

3. The method for improving the driving circuit of a multi-phase charge pump according to claim 1, wherein: The ping-pong circuit is composed of a switch circuit and a comparison circuit connected to each other.

4. An improved structure of a multi-phase charge pump driving circuit, characterized in that: Each charge pump chip in the multi-phase charge pump is connected to a plurality of multi-phase cascaded NMOS transistors; the B pole and the S pole of one of the NMOS transistors connected to the substrate B and the source S between the input terminal VBUS and the output terminal Vout are short-circuited and disconnected, and the B pole is connected to a low-level control circuit, so that the B pole is connected to the low-level end of the input terminal VBUS and the output terminal Vout; The low-level control circuit includes: a cathode of a diode connected to the input terminal VBUS, a cathode of another diode connected to the output terminal Vout; and anodes of the two diodes are connected to the B pole; or: The low-level control circuit includes a ping-pong circuit connected to the input terminal VBUS and the output terminal Vout, and the ping-pong circuit controls and selects the low-level end between the input terminal VBUS and the output terminal Vout to be connected to the B pole.

5. The improved structure of the driving circuit of the multi-phase charge pump according to claim 4, characterized in that: The diode is a Schottky diode.

6. The improved structure of the driving circuit of the multi-phase charge pump according to claim 4, characterized in that: The ping-pong circuit is mainly composed of a switching circuit and a comparison circuit connected to each other. The comparison circuit compares the levels of the input terminal VBUS and the output terminal Vout. The switching circuit controls the low-level end to be connected to the B pole.

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