A system for passive implementation of data encoding and storage in data communication

Abstract

The application discloses a system for realizing data coding and storage in passive data communication, which comprises MxN row control units, M column control units, one NMOS tube and M+1 pull-down resistors. One row control unit is composed of a diode and a switch; one column control unit is composed of a diode and a PMOS tube. The application adopts passive devices, and can realize the required data coding and storage under the condition of no stable power supply, and can normally output data under the condition of high voltage such as 3.3V-30V. Meanwhile, the passive devices are used, and no current is needed to maintain the circuit working when the circuit is not working, so that 0 power consumption is realized.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, specifically a passive system for data encoding and storage in data communication. Background Technology

[0002] With the development of various electronic devices, identification coding and data storage in electronic devices are becoming increasingly important. Currently, under stable power supply, data encoding and storage circuits based on voltages below 5V are very common and widespread; and the control of signals above 5V using devices at or below 5V is also very common.

[0003] However, there is no mature method for encoding and storing high-voltage or 5V and below data when there is no stable power supply. If a method is to obtain a stable power supply using voltage regulation circuit modules or energy storage technology when there is no stable power supply, there are limitations on the time from no power supply to obtaining a stable power supply. Summary of the Invention

[0004] The purpose of this invention is to provide a passive system for data encoding and storage in data communication, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A passive system for data encoding and storage in data communication includes M x N row control units, M column control units, one NMOS transistor, and M+1 pull-down resistors. Each row control unit consists of a diode and a switch; each column control unit consists of a diode and a PMOS transistor. The device comprises diodes D101 and D102, MOSFETs Q101 and Q102, resistors R101 and R102, characterized in that the anode of diode D101 is connected to the anodes of diodes D102 to D10M and control signal L1; the anode of diode D201 is connected to the anodes of diodes D202 to D20M and control signal L2; the anode of diode D301 is connected to the anodes of diodes D302 to D30M and control signal L3; the anode of diode DN01 is connected to the anodes of diodes DN02 to DN0M and control signal LN; the cathode of diode D101 is connected to the cathodes of diodes D201 to DN01, the gate of MOSFET Q101, and resistor R101; and the cathode of diode D102 is connected to the anodes of diodes D202 to D10M. The cathode of N02, the gate of MOSFET Q102, and resistor R102 are connected. The cathode of diode D10M is connected to the cathodes of diodes D20M to DN0M, the gate of MOSFET Q10M, and resistor R10M. The source of MOSFET Q101 is connected to the source of MOSFET Q102, the source of MOSFET Q10M, resistor R201, and the gate of MOSFET Q200. The drain of MOSFET Q101 is connected to the cathode of diode D01. The anode of diode D01 is connected to signal C1. The drain of MOSFET Q102 is connected to the cathode of diode D02. The anode of diode D02 is connected to signal C2. The drain of MOSFET Q10M is connected to the cathode of diode D0M. The anode of diode D0M is connected to signal CM. The drain of MOSFET Q200 is connected to signal Data.

[0007] As a further technical solution of the present invention, a switch SW is provided between the cathode of diodes D101~D10M, diodes D201~D20M, diodes D301~D30M, and diodes DN01~DN0M and the gate of the corresponding MOS transistor.

[0008] As a further technical solution of the present invention, MOS transistors Q101, Q102 to Q10M are all PMOS transistors, and MOS transistor Q200 is an NMOS transistor.

[0009] As a further technical solution of the present invention, the diodes D101 to D10M are all switching diodes.

[0010] As a further technical solution of the present invention, the diodes D201 to D20M are all switching diodes.

[0011] As a further technical solution of the present invention, the diodes D301 to D30M are all switching diodes.

[0012] As a further technical solution of the present invention, the diodes DN01 to DN0M are all switching diodes.

[0013] As a further technical solution of the present invention, the diodes D01 to D0M are all switching diodes.

[0014] Compared with the prior art, the beneficial effects of the present invention are:

[0015] This invention employs passive components, enabling the necessary data encoding and storage even without a stable power supply, and supports normal data output under high voltage conditions such as 3.3V to 30V. Furthermore, because passive components are used, no current is required to maintain circuit operation when not in use, thus achieving true zero power consumption. Attached Figure Description

[0016] Figure 1 A circuit diagram for MxN bit data encoding;

[0017] Figure 2 This is a circuit diagram for data encoding "FFF".

[0018] Figure 3 This is a circuit diagram for encoding data as “A6D”.

[0019] Figure 4 This is a typical working circuit diagram.

[0020] Figure 5 This is the access waveform diagram for the data encoding circuit corresponding to "A6D". Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] Please see Figure 1-5 Example 1: Figure 1The present invention discloses a passive system for data encoding and storage in data communication, comprising M x N row control units, M column control units, one NMOS transistor, and M+1 pull-down resistors. Each row control unit consists of a diode and a switch; each column control unit consists of a diode and a PMOS transistor. The device comprises diodes D101 and D102, MOSFETs Q101 and Q102, resistors R101 and R102, characterized in that the anode of diode D101 is connected to the anodes of diodes D102 to D10M and control signal L1; the anode of diode D201 is connected to the anodes of diodes D202 to D20M and control signal L2; the anode of diode D301 is connected to the anodes of diodes D302 to D30M and control signal L3; the anode of diode DN01 is connected to the anodes of diodes DN02 to DN0M and control signal LN; the cathode of diode D101 is connected to the cathodes of diodes D201 to DN01, the gate of MOSFET Q101, and resistor R101; and the cathode of diode D102 is connected to the anodes of diodes D202 to D10M. The cathode of N02, the gate of MOSFET Q102, and resistor R102 are connected. The cathode of diode D10M is connected to the cathodes of diodes D20M to DN0M, the gate of MOSFET Q10M, and resistor R10M. The source of MOSFET Q101 is connected to the source of MOSFET Q102, the source of MOSFET Q10M, resistor R201, and the gate of MOSFET Q200. The drain of MOSFET Q101 is connected to the cathode of diode D01. The anode of diode D01 is connected to signal C1. The drain of MOSFET Q102 is connected to the cathode of diode D02. The anode of diode D02 is connected to signal C2. The drain of MOSFET Q10M is connected to the cathode of diode D0M. The anode of diode D0M is connected to signal CM. The drain of MOSFET Q200 is connected to signal Data.

[0023] This invention employs a row-column structure, utilizing the unidirectional and switching characteristics of diodes, switches, PMOS transistors, and NMOS transistors. For an MxN data encoding circuit, data encoding and storage are achieved through a row control array composed of MxN diode and switch pairs, a column control array composed of M diode and PMOS transistor pairs, and NMOS transistors.

[0024] A complete 3x4 data encoding circuit with all outputs being "1", such as Figure 2 As shown.

[0025] Figure 2 In the middle, the horizontal control array is an array of 3x4 diode and switch pairs, with one diode paired with one switch. The function of the diode is to conduct in one direction, so as to avoid mutual interference between the horizontal control signals Lx, and to ensure that the voltage signal is conducted from the horizontal control signal Lx to the intermediate node LCx, and to prevent the reverse conduction of LCx to other horizontal control signals.

[0026] The intermediate nodes LCx are connected to the control terminal G of PMOS transistors Q101 / Q102 / Q103 respectively. Node LC1 can be unidirectionally turned on by diodes and switches through the four row control signals L1 / L2 / L3 / L4 to receive a high-level signal. Nodes LC2 and LC3 are the same.

[0027] The column control array consists of an array of three diodes and PMOS transistors, with one diode paired with one PMOS transistor. Here, the diodes also serve a unidirectional conduction function to prevent the row control signals Cx from interfering with each other, ensuring that the voltage signal is conducted from the column control signal Cx to the NMOS transistor control terminal node, and preventing reverse voltage conduction.

[0028] Figure 2 In this circuit, if any one of the L1 / L2 / L3 / L4 signals is high, then LC1 / LC2 / LC3 are all high. At this time, regardless of whether the C1 / C2 / C3 signals are high, the voltage at the control terminal G of the NMOS transistor is pulled down to "0V" by the pull-down resistor R201, and the NMOS transistor is off. The voltage at the Data terminal is determined by the external input; if the external input is high, it is a high level "1"; if the external input is 0V, it is a 0V level. The data encoding of this circuit is an all-"1" output, and according to the order of the intermediate nodes LC1, LC2, LC3 (i.e., the order of the row control signals L1, L2, L3, L4), its data encoding is FFF.

[0029] Example 2, based on Example 1, such as Figure 3 As shown, a switch SW is provided between the cathode of diodes D101, D102, D103, D201, D202, D203, D301, D302, D303, D401, D402, and D403 and the corresponding MOSFET.

[0030] Figure 3The circuit in the middle is the "A6D" encoding circuit. The LC1 node implements the "A" value; that is, when L1 / L2 / L3 / L4 are applied high, "1010" is achieved at the LC1 terminal. Because the switch between L1 and LC1 is closed, unidirectional conduction at high levels is possible. The switch between L2 and LC1 is open, so only when L2 is high is the LC1 node pulled down to 0V by the pull-down resistor R101. L3 / L4 are similar to L1 / L2. When a high level is applied to C1, the switching on and off of PMOS transistor Q101 is determined by the voltage at node LC1. When L1 / L3 is high, LC1 is high, PMOS transistor Q101 is off, and the voltage at the control terminal G of the NMOS transistor is pulled down to "0V" by the pull-down resistor R201, so the NMOS transistor is off. At this time, the voltage at the Data terminal is determined by the external input; that is, if the external input is high, it is a high level "1". When L2 / L4 is high, since there is no diode path, LC1 is low, PMOS transistor Q101 is on, and the voltage at the control terminal G of the NMOS transistor remains high, so the NMOS transistor is on. At this time, regardless of the external input voltage, the voltage at the Data terminal is pulled down to "0V" by the NMOS transistor, that is, the output is "0".

[0031] Similarly, in the LC2 and C2 control paths, the encoding of "0110" (i.e., "6") is implemented; in the LC3 and C3 control paths, the encoding of "1101" (i.e., "D") is implemented.

[0032] Figure 4 This is a typical circuit diagram for reading the data encoding. When it is necessary to read the HVMEM data encoding, the working voltage is applied to Vwr, and the Vdata voltage is read at the Vrd terminal to determine the level of the data bits specified by C1~C3 and L1~L4 for HVMEM.

[0033] Figure 5 This is the access waveform of the data encoding circuit corresponding to "A6D".

[0034] Figure 5 In the waveform, you can see that on Vdata, there is “A6D” data waveform data based on the control signals of L1~L4 and C1~C3.

[0035] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0036] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A system for passive implementation of data encoding and storage in data communication, comprising MxN row control units, M column control units, one NMOS transistor and M+1 pull-down resistors, one row control unit consisting of a diode and a switch; one column control unit consisting of a diode and a PMOS transistor, comprising diode D101, diode D102, MOS transistor Q101, MOS transistor Q102, resistor R101 and resistor R102, characterized in that, An anode of the diode D101 is connected to anodes of diodes D102-D10M and a control signal L1, an anode of the diode D201 is connected to anodes of diodes D202-D20M and a control signal L2, an anode of the diode D301 is connected to anodes of diodes D302-D30M and a control signal L3, an anode of the diode DN01 is connected to anodes of diodes DN02-DN0M and a control signal LN, a cathode of the diode D101 is connected to cathodes of diodes D201-DN01, a gate of a MOS Q101 and a resistor R101, a cathode of the diode D102 is connected to cathodes of diodes D202-DN02, a gate of a MOS Q102 and a resistor R102, a cathode of the diode D10M is connected to cathodes of diodes D20M-DN0M, a gate of a MOS Q10M and a resistor R10M, a source of the MOS Q101 is connected to a source of the MOS Q102, a source of the MOS Q10M, a resistor R201 and a gate of a MOS Q200, a drain of the MOS Q101 is connected to a cathode of the diode D01, an anode of the diode D01 is connected to a signal C1, a drain of the MOS Q102 is connected to a cathode of the diode D02, an anode of the diode D02 is connected to a signal C2, a drain of the MOS Q10M is connected to a cathode of the diode D0M, an anode of the diode D0M is connected to a signal CM, a drain of the MOS Q200 is connected to a signal Data. Switches SW are arranged between cathodes of the diodes D101-D10M, the diodes D201-D20M, the diodes D301-D30M, the diodes DN01-DN0M and gates of corresponding MOS.

2. The system for encoding and storing data in data communication according to claim 1, wherein, The MOS Q101, the MOS Q102-Q10M are PMOS, and the MOS Q200 is NMOS.

3. The system for encoding and storing data in data communication according to claim 1, wherein, The diodes D101-D10M, the diodes D201-D20M, the diodes D301-D30M, the diodes DN01-DN0M are switching diodes.

4. The system for encoding and storing data in data communication according to claim 1, wherein, The diodes D01, the diodes D02, the diodes D0M are switching diodes.

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