Device link management

Abstract

Apparatuses, systems, and techniques for optimizing device communication are disclosed. In at least one embodiment, one or more neural networks are used to determine optimal power and frequency states for communication links between processing devices.

Description

[0001] Cross Reference to Related Applications

[0002] This application is a PCT application which claims priority to U.S. Patent Application No. 16 / 570,586, filed September 13, 2019, entitled “DEVICE LINK MANAGEMENT,” the entire disclosure of which is incorporated by reference herein for all purposes. TECHNICAL FIELD

[0003] At least one embodiment relates to processing resources for executing computer-readable instructions. For example, at least one embodiment relates to managing communication links between processors or computing devices in accordance with various novel techniques described herein. BACKGROUND

[0004] For large or complex computing tasks, multiple processors are often used, each processor processing a portion of a given task. In many systems, communication links between devices and other components will operate at full power, which will result in excess power consumption when there is no data transfer over these links. Further, these systems allow for adjusting bandwidth by changing the number of links used, but this adjustment does not control the data transfer rate, so a relatively consistent data transfer rate is used, which is suboptimal for various processing tasks. BRIEF DESCRIPTION OF DRAWINGS

[0005] Various embodiments according to the present disclosure will be described with reference to the drawings, wherein:

[0006] Figure 1A AND 1B A device connection is shown that is available according to at least one embodiment;

[0007] Figure 2 Components for device communication are shown according to at least one embodiment;

[0008] Figure 3 A process for managing the operational state of a communication link is shown according to at least one embodiment;

[0009] Figure 4 A computer system is shown according to at least one embodiment;

[0010] Figure 5A Inference and / or training logic is shown in accordance with at least one embodiment;

[0011] Figure 5B Inference and / or training logic is shown in accordance with at least one embodiment;

[0012] Figure 6An exemplary data center system is shown in accordance with at least one embodiment;

[0013] Figure 7 A computer system is shown in accordance with at least one embodiment;

[0014] Figure 8 A computer system is shown in accordance with at least one embodiment;

[0015] Figure 9 A computer system is shown in accordance with at least one embodiment;

[0016] Figure 10 A computer system is shown in accordance with at least one embodiment;

[0017] Figure 11A A computer system is shown in accordance with at least one embodiment;

[0018] Figure 11B A computer system is shown in accordance with at least one embodiment;

[0019] Figure 11C A computer system is shown in accordance with at least one embodiment;

[0020] Figure 11D A computer system is shown in accordance with at least one embodiment;

[0021] Figure 11E and Figure 11F A shared programming model is shown in accordance with at least one embodiment;

[0022] Figure 12 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0023] Figures 13A-13B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0024] Figures 14A-14B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0025] Figure 15 A computer system is shown in accordance with at least one embodiment;

[0026] Figure 16A A parallel processor is shown in accordance with at least one embodiment;

[0027] Figure 16B A partition unit is shown in accordance with at least one embodiment;

[0028] Figure 16C A processing cluster is shown in accordance with at least one embodiment;

[0029] Figure 16D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0030] Figure 17 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0031] Figure 18 A graphics processor according to at least one embodiment is shown;

[0032] Figure 19 shows a processor microarchitecture according to at least one embodiment;

[0033] Figure 20 A deep learning application processor according to at least one embodiment is shown;

[0034] Figure 21 An exemplary neuromorphic processor is shown in accordance with at least one embodiment;

[0035] Figure 22 and 23 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0036] Figure 24 illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0037] Figures 25A-25B illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0038] Figure 26 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0039] Figure 27 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0040] Figure 28 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment; and

[0041] Figure 29 A streaming multiprocessor in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0042] In at least one embodiment, Figure 1AAs shown in configuration 100, the computing device includes multiple devices 108, 110, 112, 114 connected through communication links 118 for communication through two switches 104, 106. In at least one embodiment, when these devices are fully connected, the device controller 102 can communicate with these devices 108, 110, 112, 114 through either of the switches 104, 106 using the communication links 116, 118 shown. In at least one embodiment, the controller 102 can also communicate with the devices 108, 110, 112, 114 through a set of reverse channel communication links 152, as Figure 1B shown in configuration 150. In at least one embodiment, each of these communication links 116, 118, 152 (or channels) will have multiple power states and operating frequencies. In at least one embodiment, these power states and operating frequencies will affect aspects such as bandwidth achieved, latency, and / or power consumption.

[0043] In at least one embodiment, each device 108, 110, 112, 114 can be a processor, such as a central processing unit (CPU) or a graphics processing unit (GPU). In at least one embodiment, these devices can execute instructions for one or more applications. In at least one embodiment, each of these devices includes a set of subcomponents as shown in configuration 200. In at least one embodiment, for ease of illustration, Figure 2 Figure 2 A single switch, device, and controller are shown, but multiple switches and devices can be connected in the manner discussed in Figure 1A and Figure 1B and carry reference numbers between figures to show this functionality. In at least one embodiment, one controller, or each controller, can control a controller hierarchy of a subset of communication links, can manage more than four devices, where a controller hub can communicate global information and make different inter-node decisions.

[0044] ​In at least one embodiment, device 108 includes a transceiver that functions as a primary communication interface to enable sending and / or receiving data to and from switch 104 and sending and / or receiving commands from controller 102. In at least one embodiment, device 108 also includes a device performance metric collector 224. In at least one embodiment, metric collector 224 is an IP block or IP core with a buffer that can collect key performance metrics representative of device activity and can store these metrics to at least one repository 226. In at least one embodiment, key performance metrics on a GPU device include GPU instruction throughput, GPU frequency, GPU memory bandwidth (BW), streaming multiprocessor (SM) utilization, cache hit rate, and power values. In at least one embodiment, metric collector 224 can interface with power estimators and performance monitors on-die or within a device. In at least one embodiment, a device can send metrics or statistics to a connected switch, such as switch 104, which in turn can forward to controller 102 to make decisions related to the device. In at least one embodiment, these decisions can include operational adjustment decisions, such as turbo boost decisions and dynamic voltage and frequency scaling (DVFS) decisions. In at least one embodiment, performance manager 222 can function as a local controller that can perform operations such as adjusting frequency and voltage, and can also respond to commands sent by controller 102 to improve performance. In at least one embodiment, device 108 includes a transceiver 220, a metric collector 224 or IP block with a buffer to collect performance metrics, and a performance manager 222. In at least one embodiment, there can be a default DVFS algorithm at system boot or reboot of device 108 that controller 102 will be aware of. In at least one embodiment, metrics will be collected and analyzed over time, and controller 102 can send appropriate commands to modify device performance. In at least one embodiment, a device can include other types of devices connected over a communication link, and is not limited to the specific examples provided herein.

[0045] In at least one embodiment, switch 104 can store data representative of a history of traffic transferred between pairs of devices, such as pairs of GPUs. In at least one embodiment, history data can include information such as number of bytes, frequency of transfer, and one or more data switch patterns. In at least one embodiment, switch 104 can also receive and store device performance metrics. In at least one embodiment, switch 104 has two main sub-blocks, including a transceiver 210 that functions as a primary communication interface to send and receive data to and from controller 102 and devices 108, as well as other switches and devices.

[0046] In at least one embodiment, the switch 104 includes a metrics table 212 for storing device performance metrics and inter-device communication history as well as information about the recent power states of the related devices and switches.

[0047] In at least one embodiment, the switch 104 periodically forwards its tables to the controller 102, which can use this information to make adjustment decisions for the related connected devices.

[0048] In at least one embodiment, the controller 102 can periodically collect key performance metrics of the devices, such as device 108, and collect communication metrics of the switches, such as switch 104. In at least one embodiment, this information can be used to train a model to generate inferences about adjustments to make with respect to the operation of any two pairs of communication links between devices, such as the frequency of operation and power state. In at least one embodiment, the controller 102 contains at least three sub-blocks, including a transceiver 206 that serves as the primary communication interface for sending and receiving data and commands with respect to the connected switches and devices. In at least one embodiment, the controller 102 includes a history database 204 for storing historical performance data, which can also include P-stats tables, device performance metrics statistics, and communication history. In at least one embodiment, the controller 102 also includes a performance optimizer 202 that can review current and historical data to make decisions about adjustments to performance, which can involve turbo boosting or DVFS, for example. In at least one embodiment, the optimizer 202 can also implement or request retraining or further training of the model if the performance optimizer 202 determines that the currently trained model is not accurate enough in its inferences.

[0049] In at least one embodiment, each switch can store historical data related to the traffic transmitted between pairs of devices, such as the number of bytes, frequency of transmission, and data switching patterns. In at least one embodiment, the linked devices can also store historical data about the frequency of operation, voltage, and power values. In at least one embodiment, this historical data is periodically shared by the back channel 152 to the hardware controller 102, which can use this information to make decisions about the frequency of operation and power state of the communication links between devices.

[0050] In at least one embodiment, such a method can be used to attempt to optimize performance of these devices and links between these devices over time. In at least one embodiment, this includes adapting power states and operating frequencies of these links and devices in order to maximize overall performance. In at least one embodiment, for general purpose applications, performance can be measured by instruction throughput. In at least one embodiment, for a class of applications that can involve deep learning or neural network type workloads, controller 102 can monitor durations and intervals between successive transactions that utilize certain links. In at least one embodiment, for deep learning type workloads, devices can exchange weights and gradients of neural networks at normal epochs. In at least one embodiment, an amount of computation done between any two epochs can be constant. In at least one embodiment, an amount of data transferred between any two devices (including model weights and gradients that update those weights) can also be constant at epoch times. In at least one embodiment, monitoring times between different epochs can be used to represent overall performance gains or losses of this system. In at least one embodiment, software can also be allowed to pass hints or expected workload information. In at least one embodiment, runtimes and compilers can do high level analysis and can provide a set of APIs that enable these runtimes and compilers to pass information about expected communication link efficiency or other such things. In at least one embodiment, controller 102 can record these hints from various devices or sources and can make global optimal decisions. In at least one embodiment, a distinction between hints and human control is that software does not make any explicit power throttling decisions, but rather increases a controller knowledge base to make better decisions in hardware.

[0051] In at least one embodiment, controller 102 can use performance or power sensitivity with respect to different settings of devices and communication links, which can help decide power state and / or operating frequency of communication links between two or more devices (e.g., GPUs). In at least one embodiment, different algorithms can be used that help achieve other goals. In at least one embodiment, performance optimizer 202 can perform optimizations such as turbo boosting and DVFS adjustment. In at least one embodiment, for turbo boosting, it can be inferred that, when communicating, a device running at a higher frequency is more likely to benefit from higher data transfer rates, and vice versa. In at least one embodiment, a turbo boosting algorithm can determine turbo boosted links between highly active devices, and throttle remaining links. In at least one embodiment, this approach can allow devices to benefit from higher transfer rates, while saving power for other devices that can not benefit, or at least not need, higher transfer rates. In at least one embodiment, for a turbo boosting approach, device performance metrics can be used as input, and it can be determined whether a given device (e.g., GPU) is highly active by analyzing instruction throughput for that device. In at least one embodiment, data including link metrics can be analyzed, and it can be determined whether certain devices are communicating frequently. In at least one embodiment, devices and links determined to be highly active can be selected for turbo boosting. In at least one embodiment, if all devices of a given controller have similar activity levels, which can occur in various applications, then DVFS can be performed instead of turbo boosting. In at least one embodiment, two or more algorithms can be used to try to determine appropriate or optimal DVFS settings. In at least one embodiment, adjustments to DVFS settings can help adjust power and speed settings on devices in order to optimize resource allocation for individual tasks and maximize power savings when those resources are not needed. In at least one embodiment, a binary search algorithm can be used when controller 102 performs a binary search of possible power states. In at least one embodiment, this algorithm can find an optimal setting in log(n) time in the worst case, where n is the number of configurations before an optimal configuration is selected. In at least one embodiment, controller 102 does not need any input for this algorithm. In at least one embodiment, a binary search can set a frequency point and measure results by seeing whether device instruction throughput changes. In at least one embodiment, this search will occur until device instruction throughput stabilizes within a specified tolerance or range.

[0052] In at least one embodiment, a neural network can be used to infer optimal DVFS values. In at least one embodiment, a neural network can take device statistics, device-to-device communication history, and performance metrics as inputs and infer appropriate DVFS or p-states for associated devices and links. In at least one embodiment, if output of this trained neural network does not result in performance improvement, as can be measured using instruction throughput or duration between epochs, then this neural network can benefit from being retrained and recalibrated. In at least one embodiment, to balance training overhead and accuracy, after training N samples and then inferring MxN time samples, these neural networks can be saved in memory of associated controllers.

[0053] In at least one embodiment, before performing DVFS for devices and links, a neural network for predicting DVFS needs to be trained. In at least one embodiment, data and GPU frequencies for associated links can be used to train a neural network to predict results of link power and frequency states. In at least one embodiment, to pre-train a model with inputs and results, a binary search can be used while modifying for storage device and link performance metrics and recording results of binary search. In at least one embodiment, this can be performed on hundreds of DGX machines to process large number of workloads. In at least one embodiment, this data can then be used to train a model that can be formed from a baseline. In at least one embodiment, a baseline model can be deployed and used for inference to set DVFS. In at least one embodiment, if a decrease in GPU performance, as measured by instruction throughput, is detected due to DVFS settings, then it indicates that the model needs refinement. In at least one embodiment, another set of binary searches can be performed and device and link metrics can be stored as during pre-training. In at least one embodiment, additional input and result data can be used to further train and improve the model. In at least one embodiment, once the model becomes stable, DVFS settings do not cause performance degradation, as measured by device instruction throughput.

[0054] In at least one embodiment, in multi-node connections, information of local nodes and global nodes can be utilized to make fast decisions and fast reaction times on hardware. In at least one embodiment, large multi-mode GPU machines can benefit from this approach, where relative to included switches, such as NVIDIA® switches or Lower total operational power consumption can be obtained. In at least one embodiment, more active GPUs in such devices can be dynamically turbo boosted in order to obtain improved overall performance. In at least one embodiment, these approaches can be applied to deployments that use these types of links to connect nodes, but through Ethernet or IB standard based systems. In at least one embodiment, these approaches can be extended to large nodes used in industries and applications related to high performance computing (HPC), where power budgets can be computed for thousands of nodes, and a few hundred watts of power saved per node can translate to large scale savings.

[0055] In at least one embodiment, a workload can be a distributed workload distributed across multiple devices (e.g., GPUs) in a system. In at least one embodiment, there will be communication between these GPUs to perform or process this workload. In at least one embodiment, such a workload can be related to training of a neural network, where this workload can include computing or updating weights of a network. In at least one embodiment, each GPU will go through a series of processing phases and data transfer phases. In at least one embodiment, during a processing phase, a given GPU will not be communicating data over a connected link. In at least one embodiment, a controller can attempt to adjust power state of those links without data communication over those links. In at least one embodiment, a controller can also attempt to have those links operate at an optimal or maximum speed or target speed when data transfer or communication is to occur over those links. In at least one embodiment, for a deep learning workload, various GPUs can perform computational operations related to computing weights, and then these GPUs will need to exchange data and weights generated for respective portions of this computation. In at least one embodiment, after exchanging weights and data, these GPUs can perform a next batch of computations for network training. In at least one embodiment, a frequency of communication can depend on a problem being attempted to be solved, or overall operations or computations to be performed. In at least one embodiment, a GPU can be in an idle state until it receives data from another GPU that needs to process a next iteration. In at least one embodiment, latency of communication can thus reduce efficiency of these GPUs. In at least one embodiment, a communication link such as an NVLink is powered to a maximum value at all times in anticipation of data transfer. In at least one embodiment, turbo boost lift can be used to improve latency, where power state management is used to improve power efficiency. In at least one embodiment, a data center can include thousands of machines, each requiring thousands of watts of power, with a switch contributing about 1 kilowatt of power for each machine. In at least one embodiment, even if a portion of these links can be throttled, then power savings and operational costs will be significantly reduced. In at least one embodiment, a hardware controller based system can attempt to automatically detect in hardware when turbo boost should be applied and when a lower power should be activated. In at least one embodiment, a hardware controller can analyze available data to make such a decision. In at least one embodiment, a hardware controller to determine that a device needs to operate at a lower latency can provide a link turbo boost lift to improve performance. In at least one embodiment, a hardware controller to identify that a link is not active or is less active can cause a link to operate at a lower frequency state or a lower DVFS so as to reduce operating voltage to save power. In at least one embodiment, such an approach helps to have links that need performance operate at a higher potential, while idle links operate at a lower frequency point.

[0056] In at least one embodiment, statistics representing monitored behavior of a system can be generated. In at least one embodiment, these statistics are generated using various monitors built into the system, such as into specific devices like GPUs, which can include performance counters, frequency monitors, voltage monitors, compute intensity monitors, and data transfer rate monitors. In at least one embodiment, data from these monitors can be analyzed at runtime of an application in order to monitor communications occurring between related devices. In at least one embodiment, this data can be stored as historical data as discussed above, which can be analyzed to determine how to optimize a related system, such as changing a frequency of a link based in part on what the connected devices are doing or how they are operating at a particular time. In at least one embodiment, data collected can include a number of bytes transferred and a frequency of those transfers. In at least one embodiment, it can be determined that a given link is transferring small messages at a high frequency, while another link is only transferring large messages but relatively infrequently. In at least one embodiment, a hardware controller can analyze historical data to determine that a given pair of devices is very active and they are transferring data at a very fast rate or frequency, and can determine that a link between these two devices should be turbocharged. In at least one embodiment, if there are two devices that are not particularly active or are below a determined activity threshold, and those devices are communicating relatively infrequently, a hardware controller can determine to potentially downshift a link between those devices. In at least one embodiment, a hardware controller can store information about activity levels in monitored devices and activity in respective links, and use this data to make optimization decisions.

[0057] In at least one embodiment, one or more interfaces (e.g., application programming interfaces (APIs)) can be provided to enable software or applications to provide hints about activity levels. In at least one embodiment, applications can utilize these interfaces to provide information for optimizing a related workload. In at least one embodiment, an application can indicate a frequency or operating state for a related link to run. However, in at least one embodiment, decisions about operation can still be made on hardware, but can take into account software input by or operations performed by a related device.

[0058] In at least one embodiment, there can be multiple operating points for turbo boost operation. In at least one embodiment, turbo boost can be turned on or off. In at least one embodiment, when there are multiple operating points, turbo boost can also be set to a particular amount of turbo boost, whether adjusted to one of a set of boost values or dynamically adjusted over a range of boost values. In at least one embodiment, a link can be turbo boosted to a highest frequency, up to a maximum thermal allowed point. In at least one embodiment, a link can be able to be boosted by 30-40%, which can depend in part on a baseline setting. In at least one embodiment, turbo boost can only apply for a relatively short period of time, and can not be applied throughout an entire operation or computation. In at least one embodiment, turbo boost decisions are made in a hardware controller, but actual turbo boost hardware will be located at a transceiver of a particular link. In at least one embodiment, a hardware controller will send instructions to a relevant device or switch to increase or decrease an operating frequency of a link. In at least one embodiment, a hardware controller can send commands to a switch and a device for a link when the switch is connected to the device through the particular link to adjust operation. In at least one embodiment, a hardware controller monitors and sends commands to devices and switches on a single machine, which can help avoid devices from becoming a bottleneck for other devices in a network or data center.

[0059] In at least one embodiment, any of a variety of different algorithms or methods can be used to adjust an operating frequency. In at least one embodiment, a neural network can be trained to adjust an operating frequency in order to improve its performance and power efficiency under different operating conditions. In at least one embodiment, such a network can be trained using data related to monitored frequencies, data transfer rates, and device power states. In at least one embodiment, a trained network can infer an optimal frequency that is allowed by the hardware that also does not negatively impact performance. In at least one embodiment, a deep learning model can be trained for a particular machine or type of machine, or a deep learning model can be trained for a network of such machines.

[0060] In at least one embodiment, as Figure 3As shown, the process 300 for link management can be utilized. In at least one embodiment, an application to be executed across a set of processing devices on a system can be determined 302. In at least one embodiment, other tasks to be executed across a set of processing devices can also be considered, and can require partial execution by different processors, with results communicated between them. In at least one embodiment, the processing devices are graphics processing units (GPUs) connected by a communication link pair and one or more switches with attributes managed by a hardware controller. In at least one embodiment, performance data for these monitored devices, switches, and / or links is obtained 304. In at least one embodiment, the monitored data can be collected and stored locally, and periodically transmitted to the hardware controller for analysis. In at least one embodiment, data for individual links or link pairs between devices can be analyzed 306. In at least one embodiment, for a given link, it can be determined whether data is infrequently transmitted 308 across the link, at least with small enough packet sizes so that a high frequency connection is not required. In at least one embodiment, a determination of infrequent data can direct the hardware controller to operate the link or link pair in a low frequency state 310. In at least one embodiment, there can be multiple frequency states, and lower frequency states can be sequentially utilized until an optimal frequency point is reached.

[0061] In at least one embodiment, if there is no infrequent data transmission, or if the size of the data transmitted is itself not suitable for lower frequency operation, it can be determined whether there is a high demand on that link 312, such as when one or both of the connected devices is operating at full capacity or at a high load.

[0062] In at least one embodiment, a determination of demand and frequency can be determined together. In at least one embodiment, a determination by a hardware controller that demand on a link is too much or above a normal operating threshold or range can cause a link or pair of links to operate in a default operating state 314, such as in a default frequency state and a default power state. In at least one embodiment, there can be multiple frequency states or power states, and the default can vary based on type of device or application. In at least one embodiment, a determination of high demand can cause turbocharging to be applied to a given link 316, or pair or group of links of a device. In at least one embodiment, turbocharging can only be applied if available, as turbocharging is only applied for a limited amount of time in certain systems, then another amount of time is needed before it can be applied again. In at least one embodiment, turbocharging of one or more links can require temporarily lowering frequency of other related links to ensure maximum frequency capacity is not exceeded. In at least one embodiment, if a determination is made that more links are to be analyzed 318, then the process can continue. In at least one embodiment, once all links have been updated, and a current set of processing tasks is complete, another determination can be made 320 as to whether an application task has been completed. In at least one embodiment, if the task is not complete, then links can be analyzed and updated for a next round of processing. In at least one embodiment, if the task has been completed, then a hardware controller can determine to return some or all of these links to a default state 322. In at least one embodiment, this can include at least turning off turbocharging for any links, and can include increasing power or frequency state of links that can need a subsequent task or application of higher performance.

[0063] Figure 4 A computer system 400 according to at least one embodiment is shown. In at least one embodiment, computer system 400 is configured to implement various processes and methods described throughout this disclosure. In at least one embodiment, parallel processing units 414 can communicate through interconnect 418 and at least one switch 420 to implement portions of tasks as described above.

[0064] In at least one embodiment, computer system 400 includes, without limitation, at least one central processing unit (“CPU”) 402 that is connected to a communication bus 410 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), PCIe (“Peripheral Component Interconnect express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 400 includes, without limitation, a main memory 404 and control logic (e.g., as hardware, software, or a combination thereof) and data are stored in main memory 404, which can take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 422 provides an interface to other computing devices and networks for receiving data from, and transmitting data to, other systems from computer system 400.

[0065] In at least one embodiment, computer system 400 includes, without limitation, input device(s) 408, parallel processing system 412, and display device(s) 406 that can be implemented using traditional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technologies in at least one embodiment. In at least one embodiment, user input is received from input device(s) 408, such as a keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each of the foregoing modules can be located on a single semiconductor platform.

[0066] Inference and / or Training Logic

[0067] Figure 5A Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6.

[0068] In at least one embodiment, inference and / or training logic 515 can include, without limitation, code and / or data storage 501 for storing and / or outputting weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network being trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 515 can include or be coupled to code and / or data storage 501 for storing graphics code or other software for controlling timing and / or order, where weight and / or other parameter information is to be loaded to configure logic including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs)). In at least one embodiment, code, such as graphics code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network that this code corresponds to. In at least one embodiment, code and / or data storage 501 stores weight parameters and / or input / output data for each layer of a neural network being trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters when training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 501 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory.

[0069] In at least one embodiment, any portion of code and / or data storage 501 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 501 can be cache memory, dynamic random addressable memory (“DRAM”), static random addressable memory (“SRAM”), non-volatile memory (e.g., Flash), or other storage. In at least one embodiment, whether code and / or code and / or data storage 501 is internal or external to a processor, e.g., or includes DRAM, SRAM, Flash, or some other storage type, can depend on available storage on-chip versus off-chip, latency requirements of training and / or inferencing functions being performed, batch size of data being used in inferencing and / or training of a neural network, or some combination of these factors.

[0070] In at least one embodiment, inference and / or training logic 515 can include, without limitation, code and / or data storage 505 for storing and / or outputting weights and / or input / output data corresponding to neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during backward propagation of weight parameters and / or input / output data during training and / or inference using aspects of one or more embodiments, code and / or data storage 505 stores weight parameters and / or input / output data for each layer of a neural network being trained or used with one or more embodiments. In at least one embodiment, training logic 515 can include or be coupled to code and / or data storage 505 for storing graphics codes or other software to control timing and / or order, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating point units (collectively, arithmetic logic unit(s) (ALUs)). In at least one embodiment, code, such as graphics code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which code corresponds. In at least one embodiment, any portion of code and / or data storage 505 can be included with other on-chip or off-chip data storage, including a processor’s L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 505 can be on-chip or off-chip of one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 505 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, a determination of whether code and / or data storage 505 is internal or external to a processor, e.g., made up of DRAM, SRAM, Flash memory, or some other storage type, can depend on available on-chip versus off-chip storage, latency requirements of training and / or inference functions being performed, batch size of data used in a neural network’s deduction and / or training, or some combination of these factors.

[0071] In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 can be separate storage structures. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 can be the same storage structure. In at least one embodiment, code and / or data storage 501 and code and / or data storage 505 can be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 501 and code and / or data storage 505 can be included with other on-chip or off-chip data storage, including a processor’s L1, L2, or L3 cache or system memory.

[0072] In at least one embodiment, inference and / or training logic 515 can include, without limitation, one or more arithmetic logic units (“ALUs”) 510, including integer and / or floating point units, to perform logical and / or mathematical operations whose results can produce activations (e.g., output values from layers or neurons within a neural network) stored in activation storage 520 that are a function of input / output and / or weight parameter data stored in code and / or data storage 501 and / or code and / or data storage 505, based at least in part on or directed by training and / or inference code (e.g., graphics code). In at least one embodiment, in response to executing instructions or other code, activations stored in activation storage 520 result from linear algebraic and / or matrix-based mathematical operations performed by one or more ALUs 510, where weight values stored in code and / or data storage 505 and / or code and / or data storage 501 are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which can be stored in code and / or data storage 505 or code and / or data storage 501 or other on-chip or off-chip storage.

[0073] In at least one embodiment, one or more ALUs 510 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 510 can be external to a processor or other hardware logic device or circuit (e.g., a co-processor). In at least one embodiment, ALUs 510 can be included within execution units of a processor or otherwise included within a bank of ALUs accessible by execution units of a processor, either within the same processor or distributed between different types of processors (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 501, code and / or data storage 505, and activation storage 520 can be on the same processor or other hardware logic device or circuit, while in another embodiment, they can be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 520 can be included with other on-chip or off-chip data storage, including a processor’s LI, L2, or L3 cache or system memory. Moreover, inference and / or training code can be stored with other code accessible by a processor or other hardware logic or circuit, and can be fetched and / or processed using fetch, decode, schedule, execute, exit, and / or other logic circuits of a processor.

[0074] In at least one embodiment, activation storage 520 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 520 may be fully or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 520 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors. In at least one embodiment, Figure 5A The inference and / or training logic 515 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 5A The inference and / or training logic 515 shown in FIG may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0075] Figure 5B Inference and / or training logic 515 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 515 may include, but is not limited to, hardware logic where computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 5B The inference and / or training logic 515 shown in FIG can be used in conjunction with an application specific integrated circuit (ASIC), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 5BThe inference and / or training logic 515 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 515 includes, but is not limited to, code and / or data storage 501 and code and / or data storage device 505, which can be used to store code (e.g., graphics code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 5B In at least one embodiment shown, code and / or data storage 501 and code and / or data storage 505 are each associated with dedicated computing resources, such as computing hardware 502 and computing hardware 506, respectively. In at least one embodiment, computing hardware 502 and computing hardware 506 each include one or more ALUs that perform mathematical functions, such as linear algebraic functions, on information stored in code and / or data storage 501 and code and / or data storage 505, with the results of the mathematical functions being stored in activation storage 520.

[0076] In at least one embodiment, each of code and / or data storage 501 and 505 and corresponding computing hardware 502 and 506 corresponds to a different layer of a neural network, such that activations generated from one "storage / compute pair 501 / 502" of code and / or data storage 501 and computing hardware 502 are provided as inputs to a "storage / compute pair 505 / 506" of code and / or data storage 505 and computing hardware 506, reflecting the conceptual organization of the neural network. In at least one embodiment, each of storage / compute pairs 501 / 502 and 505 / 506 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 515, either after or in parallel with storage / compute pairs 501 / 502 and 505 / 506.

[0077] Data Center

[0078] Figure 6 An example data center 600 is shown in which at least one embodiment may be used. In at least one embodiment, data center 600 includes a data center infrastructure layer 610, a framework layer 620, a software layer 630, and an application layer 640.

[0079] In at least one embodiment, Figure 6As shown, the data center infrastructure layer 610 can include a resource orchestrator 612, grouped computing resources 614, and node computing resources (“node C.R.s”) 616(1)-616(N), where “N” represents any whole, non-zero number. In at least one embodiment, node C.R.s 616(1)-616(N) can include, but are not limited to, any number of central processing units (“CPUs” or “processors”), including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc., memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s of node C.R.s 616(1)-616(N) can be a server having one or more of the above computing resources.

[0080] In at least one embodiment, grouped computing resources 614 can include individual groups of node C.R.s housed within one or more racks (not shown), or housed within a number of racks (also not shown) within various geographic locations. Individual groups of node C.R.s within grouped computing resources 614 can include groups of computing, network, memory, or storage resources that can be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors can be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks can also include any number of power modules, cooling modules, and network switches, in any combination.

[0081] In at least one embodiment, resource orchestrator 612 can configure or otherwise control one or more node C.R.s 616(1)-616(N) and / or grouped computing resources 614. In at least one embodiment, resource orchestrator 612 can include a software design infrastructure (“SDI”) management entity for data center 600. In at least one embodiment, resource orchestrator can include hardware, software, or some combination thereof.

[0082] In at least one embodiment, as Figure 6As shown, the framework layer 620 includes a job scheduler 622, a configuration manager 624, a resource manager 626, and a distributed file system 628. In at least one embodiment, the framework layer 620 may include a framework that supports software 632 of the software layer 630 and / or one or more applications 642 of the application layer 640. In at least one embodiment, the software 632 or the application 642 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 620 may be, but is not limited to, a free and open source software web application framework, such as Apache Spark, which may utilize the distributed file system 628 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 632 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 600. In at least one embodiment, the configuration manager 624 may be capable of configuring different layers, such as the software layer 630 and the framework layer 620 including Spark and a distributed file system 628 for supporting large-scale data processing. In at least one embodiment, the resource manager 626 may be capable of managing the cluster or group computing resources mapped to or allocated to support the distributed file system 628 and the job scheduler 622. In at least one embodiment, the cluster or group computing resources may include the group computing resources 614 on the data center infrastructure layer 610. In at least one embodiment, the resource manager 626 may coordinate with the resource coordinator 612 to manage these mapped or allocated computing resources.

[0083] In at least one embodiment, the software 632 included in the software layer 630 may include software used by at least a portion of the node CRs 616(1)-616(N), the grouped computing resources 614, and / or the distributed file system 628 of the framework layer 620. The one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0084] In at least one embodiment, one or more applications 642 included in application layer 640 can include one or more types of applications used by at least portions of node C.R.s 616(1)-616(N), grouped computing resources 614, and / or distributed file system 628 of framework layer 620. One or more types of applications can include, but are not limited to, any number and / or type of genomics applications, cognitive computing and machine learning applications including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0085] In at least one embodiment, any of configuration manager 624, resource manager 626, and resource orchestrator 612 can implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions can mitigate data center operators of data center 600 making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of a data center.

[0086] In at least one embodiment, data center 600 can include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information in accordance with one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 600. In at least one embodiment, using weight parameters computed by one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks can be used to infer or predict information using resources described above with respect to data center 600.

[0087] In at least one embodiment, a data center can use CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inference using resources described above. Furthermore, one or more software and / or hardware resources described above can be configured as a service to allow users to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0088] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. Figure 5A and / or Figure 5BProvides details about the reasoning and / or training logic 515. In at least one embodiment, the reasoning and / or training logic 515 may be implemented in the system Figure 6 for use in inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0089] In at least one embodiment, such a component can be used to manage a communication link connecting processing devices. In at least one embodiment, this can include determining a frequency state and a power state of a communication link between processors.

[0090] Computer system

[0091] Figure 7 A is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, computer system 700 may include, but is not limited to, components, such as processor 702, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, computer system 700 may include a processor, such as the Intel Corporation of Santa Clara, California, available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 700 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0092] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications can include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area

[0093] In at least one embodiment, computer system 700 can include, but is not limited to, processor 702 that can include, but is not limited to, one or more execution units 708 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 700 is a single processor desktop or server system, but in another embodiment, computer system 700 can be a multiprocessor system. In at least one embodiment, processor 702 can include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor implementing a combo of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, processor 702 can be coupled to a processor bus 710 that can transmit data signals between processor 702 and other components in computer system 700.

[0094] In at least one embodiment, processor 702 can include, but is not limited to, level 1 ("Ll") internal cache memory ("cache") 704. In at least one embodiment, processor 702 can have a single -level internal cache or multi-level internal cache. In at least one embodiment, cache memory can reside in the processor 702's external. Other embodiments can include a combination of internal and external caches based on specific implementation and requirements. In at least one embodiment, register file 706 can store different types of data within various registers including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0095] In at least one embodiment, execution unit 708 includes, without limitation, logic to perform integer and floating point operations, including bit- wide operations. In at least one embodiment, processor 702 can also include microcode (“ucode”) read-only memory (“ROM”), which stores microcode for certain macroinstructions. In at least one embodiment, execution unit 708 can also include logic to handle a packed data instruction set 709. In at least one embodiment, by including packed data instruction set 709 in a general-purpose processor 702, along with associated circuitry for handling packed data instructions, many multimedia applications that would typically require a graphics processing unit (GPU) to process can instead be performed by general-purpose processor 702. In one or more embodiments, by using the full width of a processor’s data bus and intelligent memory addressing

[0096] In at least one embodiment, execution unit 708 can also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuits. In at least one embodiment, computer system 700 can include, without limitation, memory 720. In at least one embodiment, memory 720 can be implemented using a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, flash memory device, or other memory device. In at least one embodiment, memory 720 can store data 721 and / or instructions 719 that can be executed by processor 702, as represented by data signals.

[0097] In at least one embodiment, a system logic chip can be coupled to processor bus 710 and memory 720. In at least one embodiment, system logic chip can include, without limitation, a memory controller hub (“MCH”) 716 and processor 702 can communicate with MCH 716 via processor bus 710. In at least one embodiment, MCH 716 can provide a high bandwidth memory path 718 to memory 720 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, MCH 716 can direct data signals between processor 702, memory 720, and other components in computer system 700 and can bridge data signals between processor bus 710, memory 720, and system I / O 722. In at least one embodiment, system logic chip can provide a graphics port

[0098] In at least one embodiment, computer system 700 can use system I / O 722 as a proprietary hub interface bus to couple MCH 716 to I / O controller hub (“ICH”) 730. In at least one embodiment, ICH 730 can provide a direct connection to some I / O devices and can include, without limitation, a low-pin count (LPC) bus

[0099] In at least one embodiment, Figure 7 A illustrates a system including interconnected hardware devices or “chips,” while in other embodiments, Figure 7 A can illustrate an exemplary system on a chip (“SoC”). In at least one embodiment, devices can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 700 are interconnected using a compute express link (CXL) interconnect.

[0100] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and 5B. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and 5B. In at least one embodiment, inference and / or training logic 515 can be used in a system that uses neural network training operations, neural network functions and / or architectures, or neural network use cases described herein to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. Figure 7

[0101] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0102] Figure 8 is a block diagram illustrating an electronic device 800 for utilizing processor 810, in accordance with at least one embodiment. In at least one embodiment, electronic device 800 can be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0103] In at least one embodiment, system 800 can include, without limitation, processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 810 is coupled using a bus or interface, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus. Figure 8 In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus. Figure 8 In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus. Figure 8 In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus. Figure 8 In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus.

[0104] In at least one embodiment, system 800 can include, without limitation, a processor 810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices using a Compute Express Link (CXL) bus. Figure 8 ​The display 824, touch screen 825, touch pad 830, near field communication unit ("NFC") 845, sensor hub 840, thermal sensor 846, express chip set ("EC") 835, trusted platform module ("TPM") 838, BIOS / firmware / flash ("BIOS, FW Flash") 822, DSP 860, drive 820 (e.g., solid state disk ("SSD") or hard disk drive ("HDD")), wireless local area network unit ("WLAN") 850, Bluetooth unit 852, wireless wide area network unit ("WWAN") 856, global positioning system ("GPS") 855, camera ("USB 3.0 camera") 854 (e.g., USB 3.0 camera), and / or low power double data rate ("LPDDR") memory unit ("LPDDR3") 815 implemented in, for example, LPDDR3 standard, can each be implemented in any suitable manner.

[0105] In at least one embodiment, other components can be communicatively coupled to processor 810 by components described above. In at least one embodiment, accelerometer 841, ambient light sensor ("ALS") 842, compass 843, and gyroscope 844 can be communicatively coupled to sensor hub 840. In at least one embodiment, thermal sensor 839, fan 837, keyboard 846, and touch pad 830 can be communicatively coupled to EC 835. In at least one embodiment, speaker 863, earpiece 864, and microphone ("mic") 865 can be communicatively coupled to audio unit ("audio codec and class D amplifier") 862, which in turn can be communicatively coupled to DSP 860. In at least one embodiment, audio unit 864 can include, for example and without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, SIM card ("SIM") 857 can be communicatively coupled to WWAN unit 856. In at least one embodiment, components such as WLAN unit 850 and Bluetooth unit 852, and WWAN unit 856 can be implemented as a next generation form factor ("NGFF").

[0106] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and / or 5B. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and / or 5B. In at least one embodiment, inference and / or training logic 515 can be used in system Figure 8 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0107] In at least one embodiment, such a component can be used to manage a communication link connecting processing devices. In at least one embodiment, this can include determining a frequency state and a power state of a communication link between processors.

[0108] Figure 9 A computer system 900 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 900 is configured to implement the various processes and methods described throughout this disclosure.

[0109] In at least one embodiment, the computer system 900 includes, but is not limited to, at least one central processing unit ("CPU") 902 connected to a communication bus 910 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 900 includes, but is not limited to, a main memory 904 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in the main memory 904 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 922 provides an interface to other computing devices and networks for receiving data from the computer system 900 and transmitting data to other systems.

[0110] In at least one embodiment, computer system 900 includes, but is not limited to, input device 908, parallel processing system 912, and display device 906, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 908 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the above modules can be located on a single semiconductor platform to form a processing system.

[0111] The reasoning and / or training logic 515 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 5A and / or Figure 5B Provides details about the reasoning and / or training logic 515. In at least one embodiment, the reasoning and / or training logic 515 may be implemented in the system Figure 9 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0112] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0113] Figure 10 A computer system 1000 according to at least one embodiment is shown. In at least one embodiment, computer system 1000 includes, without limitation, a computer 1010 and a USB stick 1020. In at least one embodiment, computer 1010 can include, without limitation, any number and type of processor (not shown) and memory (not shown). In at least one embodiment, computer 1010 includes, without limitation, a server, a cloud instance, a laptop computer, and a desktop computer.

[0114] In at least one embodiment, USB stick 1020 includes, without limitation, a processing unit 1030, a USB interface 1040, and USB interface logic 1050. In at least one embodiment, processing unit 1030 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing core 1030 can include, without limitation, any number and type of processing core (not shown). In at least one embodiment, processing core 1030 includes an application specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, processing core 1030 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, processing unit 1030 is a visual processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0115] In at least one embodiment, USB interface 1040 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1040 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1040 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1050 can include any number and type of logic that enables processing unit 1030 to interface with a device (e.g., computer 1010) via USB connector 1040.

[0116] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, inference and / or training logic 515 can be used in system FIG. 5A and / or system FIG. 5B, among other possibilities. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 can be used in system FIG. 5A and / or system FIG. 5B, among other possibilities.Figure 10 Inference and / or prediction operations for the techniques described herein can be done using, at least in part, weight parameters computed based on neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0117] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states for communication links between processors.

[0118] Figure 11A An exemplary architecture is shown in which a plurality of GPUs 1110-1113 are communicatively coupled to a plurality of multi-core processors 1105-1106 over high-speed links 1140-1143 (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high-speed links 1140-1143 support a communication throughput of 4GB / s, 30GB / s, 80GB / s or higher. Various interconnect protocols can be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0.

[0119] Further, in one embodiment, two or more of GPUs 1110-1113 are interconnected over high-speed links 1129-1130, which can be implemented using same or different protocol / links than used for high-speed links 1140-1143. Similarly, two or more of multi-core processors 1105-1106 can be connected over a high-speed link 1128, which can be an SMP bus running at 20GB / s, 30GB / s, 120GB / s or higher. Alternatively, two or more of multi-core processors 1105-1106 can be interconnected via a high-speed network, instead of Figure 11A All communication between various system components shown in FIG. 11.

[0120] In one embodiment, each multi-core processor 1105-1106 is communicatively coupled to processor memories 1101-1102 via memory interconnects 1126-1127, respectively, and each GPU 1110-1113 is communicatively coupled to GPU memories 1120-1123 by GPU memory interconnects 1150-1153, respectively. Memory interconnects 1126-1127 and 1150-1153 can utilize the same or different memory access technologies. By way of non-limiting example, processor memories 1101-1102 and GPU memories 1120-1123 can be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, certain portions of processor memories 1101-1102 can be volatile memory while another portion can be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0121] As described below, although various processors 1105-1106 and GPUs 1110-1113 can be physically coupled to particular memories 1101-1102, 1120-1123, respectively, a unified memory architecture can be implemented in which a virtual system address space (also referred to as an “effective address” space) is distributed across the various physical memories. For example, processor memories 1101-1102 can each include 64 GB of system memory address space, and GPU memories 1120-1123 can each include 32 GB of system memory address space (resulting in a total of 256 GB of addressable memory size in this example).

[0122] Figure 11B Additional details for interconnect between multi-core processor 1107 and graphics acceleration module 1146 are shown according to one example embodiment. Graphics acceleration module 1146 can include one or more GPU chips integrated on a line card that is coupled via a high-speed link 1140 to processor 1107. Alternatively, graphics acceleration module 1146 can be integrated on the same package or chip as processor 1107.

[0123] In at least one embodiment, processor 1107 is shown including multiple cores 1160A-1160D each with a translation lookaside buffer 1161 A-1161 D and one or more caches 1162A-1162D. In at least one embodiment, cores 1160A-1160D can include various other components not shown for purposes of this illustration, for executing instructions and processing data. Caches 1162A-1162D can include level one (LI) and level two (L2) caches. Additionally, one or more shared caches 1156 can be included in caches 1162A-1162D and shared by groups of cores 1160A-1160D. For example, one embodiment of processor 1107 includes 24 cores each with its own LI cache, twelve shared L2 caches, and twelve shared L3 caches. In that embodiment, two adjacent cores share one or more L2 and L3 caches. Processor 1107 and graphics acceleration module 1146 are connected with system memory 1114, which can include processor memory 1101-1102 in Figure 11A

[0124] Consistency for data and instructions stored in individual caches 1162A-1162D, 1156, and system memory 1114 is maintained by inter-core communication over coherency bus 1164. For example, each cache can have cache coherency logic / circuitry associated therewith to communicate over coherency bus 1164 in response to detecting a read or write to a particular cache line. In one implementation, a cache snoop protocol is implemented over coherency bus 1164 to snoop cache accesses.

[0125] In one embodiment, agent circuit 1125 communicatively couples graphics acceleration module 1146 to coherency bus 1164, allowing graphics acceleration module 1146 to participate in a cache coherence protocol as a peer to cores 1160A-1160D. In particular, interface 1135 provides connectivity to agent circuit 1125 over high-speed link 1140 (e.g., a PCIe bus, NVlink, etc.) and interface 1137 connects graphics acceleration module 1146 to link 1140.

[0126] ​In one implementation, accelerator integration circuit 1136 provides cache management, memory access, context management, and interrupt management services on behalf of graphics processing engines 1131, 1132, N of graphics processing module 1146. In at least one embodiment, graphics processing engines 1131, 1132, N can each comprise a separate graphics processing unit (GPU). Alternatively, graphics processing engines 1131, 1132, N can comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1146 can be a GPU with a plurality of graphics processing engines 1131-1132, N or graphics processing engines 1131-1132, N can be individual GPUs integrated on a common package, line card, or chip.

[0127] In one embodiment, accelerator integration circuit 1136 includes a memory management unit (MMU) 1139 to translate virtual addresses into physical addresses, as is well known in the art. In at least one embodiment, MMU 1139 includes memory protection mechanisms provided by hardware-based memory management techniques. In at least one embodiment, MMU 1139 includes a translation lookaside buffer (TLB) to improve translation speed between instructions.

[0128] A set of registers 1145 store context data for threads executed by the graphics processing engines 1131-1132, N, and context management circuit 1148 manages thread contexts. For example, the context management circuit 1148 can perform save and restore operations to save and restore the context for individual threads during context switches (e.g., where a first thread is saved and a second thread is stored so that it can be executed by the graphics processing engines). For example, the context management circuit 1148, upon context switch, can store current register values to a designated area in memory (e.g., identified by a context pointer). The register values can then be restored when the context is returned to. In one embodiment, the interrupt management circuit 1147 receives and processes interrupts received from system devices.

[0129] In one implementation, the MMU 1139 translates virtual / effective addresses from the graphics processing engines 1131-1132, N to real / physical addresses in system memory 1114. One embodiment of the accelerator integration circuit 1136 supports multiple (e.g., 4, 8, 16) graphics processor modules 1146 and / or other accelerator devices. The graphics processor modules 1146 can be dedicated to a single application or shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which resources of the graphics processing engines 1131-1132, N are shared between multiple applications or virtual machines (VMs). In at least one embodiment, resources can be subdivided into “slices” that are assigned to different VMs and / or applications based on processing requirements and priority level associated with VMs and / or applications.

[0130] In at least one embodiment, the accelerator integration circuit 1136 performs as a bridge to the system for the graphics processor module 1146, and provides address translation and memory management services to the graphics processor 1131-1132, N. In addition, the accelerator integration circuit 1136 can provide virtualization facilities to allow a host processor to manage a virtualized

[0131] Because the hardware resources of the graphics processing engines 1131-1132, N are explicitly mapped to the real address space seen by the host processor 1107, any host processor can directly address these resources using effective address values. In at least one embodiment, a function of the accelerator integration circuit 1136 is to physically separate the graphics processing engines 1131-1132, N so that they appear as independent units to the system.

[0132] In at least one embodiment, one or more graphics memory 1133-1134, M is coupled to each graphics processing engines 1131-1132, N, respectively. Graphics memory 1133-1134, M stores instructions and data for processing by each of graphics processing engines 1131-1132, N. Graphics memory 1133-1134, M can be a volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be a non-volatile memory, such as 3D XPoint or Nano-Ram.

[0133] In one embodiment, to reduce data traffic on link 1140, bias techniques are used to ensure that data stored in graphics memory 1133-1134, M is that which is most frequently used by graphics processing engines 1131-1132, N and that which is least used by cores 1160A-1160D, preferably. Similarly, bias mechanisms attempt to keep data needed by cores (and preferably not graphics processing engines 1131-1132, N) in caches 1162A-1162D, 1156 and system memory 1114 of the cores.

[0134] Figure 11C Another exemplary embodiment is shown in which accelerator integration circuit 1136 is integrated within processor 1107. In at least this embodiment, graphics processing engines 1131-1132, N communicate directly over high-speed link 1140 to accelerator integration circuit 1136 via interface 1137 and interface 1135 (which can also utilize any form of bus or interface protocol). Accelerator integration circuit 1136 can perform same operations as described with regard to Figure 11B described operations. But due to its close proximity to coherence bus 1164 and caches 1162A-1162D, 1156, can have higher throughput. At least one embodiment supports different programming models including a dedicated process programming model (no graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include programming models controlled by accelerator integration circuit 1136 and programming models controlled by graphics acceleration module 1146.

[0135] In at least one embodiment, graphics processing engines 1131-1132, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1131-1132, N, providing virtualization within a VM / partition.

[0136] In at least one embodiment, graphics processing engines 1131-1132, N can be shared by multiple VM / application partitions. In at least one embodiment, a shared model can use a hypervisor to virtualize graphics processing engines 1131-1132, N to allow access by each operating system. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1131-1132, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1131-1132, N to provide access to each process or application.

[0137] In at least one embodiment, graphics acceleration module 1146 or individual graphics processing engines 1131-1132, N use a process handle to select a process element. In at least one embodiment, process elements are stored in system memory 1114 and can be addressed using effective to real address translation techniques described herein. In at least one embodiment, process handle can be an implementation-specific value provided to a host process when it registers its context with graphics processing engines 1131-1132, N (i.e., calls system software to add a process element to a process element linked list). In at least one embodiment, lower 16 bits of process handle can be an offset into process element linked list for process element.

[0138] Figure 11D An exemplary accelerator integration slice 1190 is shown. As used here, a “slice” comprises a specified portion of processing resources of accelerator integration circuit 1136. Application is an effective address space 1182 in system memory 1114 that stores process elements 1183. In one embodiment, process elements 1183 are stored in response to GPU invocations 1181 from applications 1180 executing on processor 1107. Process elements 1183 contain process state for respective applications 1180. A work descriptor (WD) 1184 contained in process element 1183 can be a single job requested by an application or can contain a pointer to a queue of jobs. In at least one embodiment, WD 1184 is a pointer to a job request queue in an application’s address space 1182.

[0139] Graphics acceleration module 1146 and / or individual graphics processing engines 1131-1132, N can be shared by all or a subset of processes in a system. In at least one embodiment, can include infrastructure for setting up process state and sending WDs 1184 to graphics acceleration module 1146 to start jobs in a virtualized environment.

[0140] In at least one embodiment, a dedicated process programming model is implementation specific. In this model, a single process owns a graphics acceleration module 1146 or individual graphics processing engines 1131-1132, N. Because the graphics acceleration module 1146 is owned by a single process, a hypervisor initializes the accelerator integration circuit for the owned partition, and an operating system initializes the accelerator integration circuit 1136 for the owned process when the graphics acceleration module 1146 is assigned.

[0141] In operation, a WD fetch unit 1191 in an accelerator integration slice 1190 fetches a next WD 1184, which includes an indication of work to be completed by one or more graphics processing engines of a graphics acceleration module 1146. Data from the WD 1184 can be stored in registers 1145 and used by MMU 1139, interrupt management circuit 1147, and / or context management circuit 1148, as shown. For example, one embodiment of MMU 1139 includes segment / page walk circuitry to access segment / page tables 1186 within an OS virtual address space 1185. Interrupt management circuit 1147 can handle interrupt events 1192 received from a graphics acceleration module 1146. Effective addresses 1193 generated by graphics processing engines 1131-1132, N are translated to real addresses by MMU 1139 when performing graphics operations.

[0142] In one embodiment, registers 1145 are replicated for each graphics processing engine 1131-1132, N and / or graphics acceleration module 1146, and a same set of said registers 1145 can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integration slice 1190. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0143] Table 1 - Hypervisor-Initialized Registers

[0144]

[0145] Exemplary registers that can be initialized by an operating system are shown in Table 2.

[0146] Table 2 - Operating System-Initialized Registers

[0147] 1 Process and thread identification 2 Effective address (EA) context save / restore pointer 3 Virtual address (VA) accelerator utilization record pointer 4 Virtual address (VA) storage segment table pointer 5 Authority mask 6 Work descriptor

[0148] In at least one embodiment, each WD 1184 is specific to a particular graphics acceleration module 1146 and / or graphics processing engines 1131-1132, N. It contains all information needed for a graphics processing engines 1131-1132, N to complete work, or it can be a pointer to a memory location where an application has set up a command queue of work to be completed.

[0149] Figure 11E Additional details are shown for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space 1198 in which a list of process elements 1199 is stored. The hypervisor real address space 1198 is accessible via a hypervisor 1196 that virtualizes the graphics acceleration module engine for the operating system 1195.

[0150] In at least one embodiment, a shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in a system to use a graphics acceleration module 1146. There are two programming models in which a graphics acceleration module 1146 is shared by multiple processes and partitions, time-sliced sharing and graphics-directed sharing.

[0151] In this model, the system hypervisor 1196 owns the graphics acceleration module 1146 and makes its functionality available to all operating systems 1195. For the graphics acceleration module 1146 to support virtualization by the system hypervisor 1196, the graphics acceleration module 1146 can adhere to the following regulations, 1) an application's job request must be autonomous (i.e., state does not need to be maintained between jobs), or the graphics acceleration module 1146 must provide a context save and restore mechanism, 2) the graphics acceleration module 1146 guarantees that an application's job request completes within a specified amount of time, including any translation faults, or the graphics acceleration module 1146 provides the ability to preempt job processing, 3) fairness between the graphics acceleration module 1146 processes must be ensured when operating in a directed shared programming model.

[0152] In at least one embodiment, application 1180 is required to use a graphics acceleration module 1146 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1195 system call. In at least one embodiment, the graphics acceleration module 1146 type describes a target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for graphics acceleration module 1146 and can take the form of a graphics acceleration module 1146 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure describing work to be done by graphics acceleration module 1146. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to how an application program sets the AMR. If the accelerator integration circuit 1136 and graphics acceleration module 1146 implementation does not support a user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. The hypervisor 1196 can selectively apply the current authority mask override register (AMOR) value before placing the AMR in the process element 1183. In at least one embodiment, the CSRP is one of registers 1145 that contains a valid address of an area in application’s effective address space 1182 for graphics acceleration module 1146 to save and restore context state. This pointer is optional if there is no need to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0153] Upon receiving the system call, operating system 1195 can verify that application 1180 is registered and has been granted authority to use graphics acceleration module 1146. Operating system 1195 then uses the information shown in Table 3 to call hypervisor 1196, in at least one embodiment.

[0154] Table 3 - Operating system to hypervisor call parameters

[0155] 1 Work descriptor (WD) 2 Authority mask register (AMR) value (possibly masked) 3 Effective address (EA) context save / restore area pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 Logical interrupt service number (LISN)

[0156] Until receiving the hypervisor call, hypervisor 1196 verifies that operating system 1195 is registered and has been granted authority to use graphics acceleration module 1146. Hypervisor 1196 then places process element 1183 in a process element linked list of the corresponding graphics acceleration module 1146 type. Process element can include the information shown in Table 4.

[0157] Table 4 - Process Element Information

[0158] 1 Work descriptor (WD) 2 Authority mask register (AMR) value (possibly masked) 3 Effective address (EA) context save / restore area pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual address (VA) accelerator utilization record pointer (AURP) 6 Virtual address of storage segment table pointer (SSTP) 7 Logical interrupt service number (LISN) 8 Interrupt vector table derived from hypervisor invocation parameters 9 State register (SR) value 10 Logical partition ID (LPID) 11 Real address (RA) hypervisor accelerator utilization record pointer 12 Storage descriptor register (SDR)

[0159] In at least one embodiment, hypervisor initializes a plurality of accelerator integration slices 1190 registers 1145.

[0160] As Figure 11F shown in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memory 1101-1102 and GPU memory 1120-1123. In this implementation, operations performed on GPUs 1110-1113 utilize the same virtual / effective memory address space to access processor memory 1101-1102 and vice versa, simplifying programmability. In one embodiment, a first portion of virtual / effective address space is allocated to processor memory 1101, a second portion to a second processor memory 1102, a third portion to GPU memory 1120, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as effective address space) is thus distributed among processor memory 1101-1102 and GPU memory 1120-1123, allowing any processor or GPU to access a memory with a virtual address that maps to that memory.

[0161] In one embodiment, bias / coherence management circuitry 1194A-1194E within one or more MMUs 1139A-1139E ensures cache coherency between one or more host processors (e.g., 1105) and caches of GPUs 1110-1113, and implements bias techniques that indicate a physical memory in which certain types of data should be stored. While multiple instances of bias / coherence management circuitry 1194A-1194E are shown in Figure 11F FIG. 11B, bias / coherence circuitry can be implemented within MMU(s) of one or more host processors 1105 and / or within accelerator integration circuit 1136.

[0162] One embodiment allows GPU-attached memory 1120-1123 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without suffering the performance penalties associated with full system cache coherency. In at least one embodiment, the ability to access GPU-attached memory 1120-1123 as system memory without the heavy cache coherency overhead provides a favorable operating environment for GPU offload. This arrangement allows software of host processor 1105 to set operands and access computation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU-attached memory 1120-1123 without cache coherency overhead can be critical to the execution time of offloaded computations. For example, in cases with a large amount of streaming write memory traffic, cache coherency overhead can significantly reduce the effective write bandwidth seen by GPU 1110. In at least one embodiment, the efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation can all play a role in determining the effectiveness of GPU offload.

[0163] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (i.e., controlled at the granularity of a memory page) that includes a per-GPU-attached memory page 1 or 2 bits. In at least one embodiment, with or without a bias cache in GPUs 1110-1113 (e.g., to cache frequently / recently used entries of the bias table), the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1120-1123. Alternatively, the entire bias table can be maintained within the GPU.

[0164] In at least one embodiment, prior to actually accessing GPU memory, the bias table entry associated with each access to GPU-attached memory 1120-1123 is accessed, resulting in the following operations. First, local requests from GPUs 1110-1113 that find their pages in GPU bias are forwarded directly to corresponding GPU memory 1120-1123. Local requests from GPUs that find their pages in host bias are forwarded to processor 1105 (e.g., over high-speed link described above). In one embodiment, requests from processor 1105 that find requested pages in host processor bias complete requests similar to normal memory reads. Alternatively, requests that point to GPU-biased pages can be forwarded to GPUs 1110-1113. In at least one embodiment, if a page is not currently in use by a GPU, the GPU can then migrate the page to host processor bias. In at least one embodiment, the bias state of a page can be changed through software-based mechanisms, hardware-assisted software-based mechanisms, or in limited cases, purely hardware-based mechanisms.

[0165] One mechanism for changing bias state employs an API call (e.g., OpenCL) that in turn invokes a device driver of a GPU, which in turn sends a message (or causes a command descriptor to be enqueued) to the GPU, directing the GPU to change the bias state, and in certain migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1105 bias to GPU bias, but not for the reverse.

[0166] In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1105. To access these pages, processor 1105 can request access from GPU 1110, which can or can not grant access immediately. Thus, to reduce communication between processor 1105 and GPU 1110, it is beneficial to ensure that GPU-biased pages are pages that are needed by the GPU but not by host processor 1105, and vice versa.

[0167] Inference and / or training logic 515 are used to perform one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and 5B. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and 5B.

[0168] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0169] Figure 12 Exemplary integrated circuits and associated graphics processors in accordance with various embodiments described herein are shown, which can be fabricated using one or more IP cores. In addition to the illustrated, other logic and circuitry can be included in the at least one embodiment, including additional graphics processors / cores, peripheral interface controllers or general purpose processor cores.

[0170] Figure 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that can be fabricated using one or more IP cores, in accordance with at least one embodiment. In at least one embodiment, the integrated circuit 1200 includes one or more application processor(s) 1205 (e.g., CPUs), at least one graphics processor 1210, and can additionally include an image processor 1215 and / or a video processor 1220, any of which can be a modular IP core. In at least one embodiment, the integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I2S / I2C controller 1240. In at least one embodiment, the integrated circuit 1200 can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. In at least one embodiment, storage can be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. In at least one embodiment, memory interface can be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1270. 2 S / I 2 Ccontroller 1240. In at least one embodiment, the integrated circuit 1200 can include a display device 1245 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1250 and a mobile industry processor interface (MIPI) display interface 1255. In at least one embodiment, storage can be provided by a flash memory subsystem 1260 including flash memory and a flash memory controller. In at least one embodiment, memory interface can be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1270.

[0171] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. In at least one embodiment, inference and / or training logic 515 can be used in integrated circuit 1200 to infer or predict operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0172] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0173] Figures 13A-13BExemplary integrated circuits and associated graphics processors according to various embodiments described herein can be fabricated using one or more IP cores. In addition to the illustrated IP cores, other logic and circuits can be included in the integrated circuits in at least one embodiment, including e.g., additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0174] Figures 13A-13B is a block diagram illustrating an exemplary graphics processor used within SoCs according to embodiments described herein. Figure 13A An exemplary graphics processor 1310 of a system on a chip integrated circuit according to at least one embodiment is shown, which can be fabricated using one or more IP cores. Figure 13B Another exemplary graphics processor 1340 of a system on a chip integrated circuit according to at least one embodiment is shown, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 13A The graphics processor 1310 of is a low power graphics processor core. In at least one embodiment, Figure 13B The graphics processor 1340 of is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1310, 1340 can be Figure 12 a variant of the graphics processor 1210 of

[0175] In at least one embodiment, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processor(s) 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D, through 1315N-1, and 1315N). In at least one embodiment, the graphics processor 1310 can execute different shader programs via separate logic for vertex processing, hence the vertex processor 1305, and for fragment or pixel processing, hence one or more fragment processor(s) 1315A-1315N. In at least one embodiment, vertex processor 1305 executes operations to be performed for vertex shader programs, such as vertex processing operations and lighting operations. In at least one embodiment, one or more fragment processor(s) 1315A-1315N

[0176] In at least one embodiment, graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, one or more caches 1325A-1325B, and one or more circuit interconnects 1330A-1330B. In at least one embodiment, one or more MMUs 1320A-1320B provide virtual-to-physical address mapping for graphics processor 1310, including for vertex processor 1305 and / or fragment processors 1315A-1315N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In at least one embodiment, one or more MMUs 1320A-1320B may synchronize with other MMUs within the system, including with other MMUs. Figure 12 One or more MMUs associated with one or more application processors 1205, graphics processor 1215, and / or video processor 1220 enable each processor 1205-1220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1330A-1330B enable graphics processor 1310 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0177] In at least one embodiment, graphics processor 1340 includes Figure 13A 13. The graphics processor 1310 includes one or more MMUs 1320A-1320B, one or more caches 1325A-1325B, and one or more circuit interconnects 1330A-1330B. In at least one embodiment, the graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F through 1355N-1 and 1355N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1340 includes an inter-core task manager 1345 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1355A-1355N and a tiling unit 1358 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0178] The reasoning and / or training logic 515 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 5A and / or Figure 5B Provides details about the inference and / or training logic 515. In at least one embodiment, the inference and / or training logic 515 may be implemented in an integrated circuit. Figure 13A and / or Figure 13B for performing inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function or architecture, or a neural network use case described herein.

[0179] In at least one embodiment, such a component can be used to manage a communication link connecting processing devices. In at least one embodiment, this can include determining a frequency state and a power state of a communication link between processors.

[0180] Figures 14A-14B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 14A Shows that can be included in Figure 12 Graphics core 1400 within graphics processor 1210 of FIG. 1 and, in at least one embodiment, may be such as Figure 13B Unified shader cores 1355A-1355N are shown. Figure 14B A highly parallel, general-purpose graphics processing unit 1430 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0181] In at least one embodiment, graphics core 1400 includes a shared instruction cache 1402, texture units 1418, and cache / shared memory 1417, which are common to execution resources within graphics core 1400. In at least one embodiment, graphics core 1400 may include multiple slices 1401A-1401N, or partitions of each core, and the graphics processor may include multiple instances of graphics core 1400. Slices 1401A-1401N may include support logic including local instruction caches 1404A-1404N, thread schedulers 1406A-1406N, thread dispatchers 1408A-1408N, and a set of registers 1410A-1410N. In at least one embodiment, slices 1401A-1401N may include a set of additional function units (AFUs 1412A-1412N), floating point units (FPUs 1414A-1414N), integer arithmetic logic units (ALUs 1416A-1416N), address calculation units (ACUs 1413A-1413N), double-precision floating point units (DPFPUs 1415A-1415N), and matrix processing units (MPUs 1417A-1417N).

[0182] In at least one embodiment, FPUs 1414A-1414N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs 1415A-1415N perform double-precision (64-bit) floating point operations. In at least one embodiment, ALUs 1416A-1416N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured to operate in mixed precision. In at least one embodiment, MPUs 1417A-1417N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs 1417A-1417N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated General Matrix to Matrix Multiplication (GEMM).

[0183] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5A and / or 5B. In examples in which inference and / or training logic 515 are used for inferencing only, inference and / or training logic 515 can be referred to as inference logic 515. Figure 5A And / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5A and / or 5B. In examples in which inference and / or training logic 515 are used for inferencing only, inference and / or training logic 515 can be referred to as inference logic 515.

[0184] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0185] Figure 14BA general purpose processing unit (GPGPU) 1430 is shown in at least one embodiment, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1430 can be directly linked to other instances of GPGPU 1430 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1430 includes a host interface 1432 to enable connection to a host processor. In at least one embodiment, host interface 1432 is a PCI Express interface. In at least one embodiment, host interface 1432 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1430 receives commands from the host processor and uses a global scheduler 1434 to assign execution threads associated with those commands to a group of compute clusters 1436A-1436H. In at least one embodiment, compute clusters 1436A-1436H share cache memory 1438. In at least one embodiment, cache memory 1438 may serve as a higher level of cache for cache memory within compute clusters 1436A-1436H.

[0186] In at least one embodiment, GPGPU 1430 includes memory 1444A-1444B coupled to compute clusters 1436A-1436H via a set of memory controllers 1442A-1442B. In at least one embodiment, memory 1444A-1444B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0187] In at least one embodiment, computing clusters 1436A-1436H each include a set of graphics cores, e.g. Figure 14A The graphics core 1400 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1436A-1436H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0188] In at least one embodiment, multiple instances of GPGPU 1430 can be configured to function as a compute cluster. In at least one embodiment, communication for synchronization and data exchange for compute clusters 1436A-1436H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1430 communicate through host interface 1432. In at least one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples the GPGPU 1430 with a GPU link 1440 enabling a direct connection to other instances of GPGPU 1430. In at least one embodiment, GPU link 1440 couples to a specialized GPU-to-GPU bridge enabling communication and synchronization between multiple instances of GPGP 1430. In at least one embodiment, GPU link 1440 couples with a high-speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1430 are located in separate data processing systems and communicate over a network device accessible through host interface 1432. In at least one embodiment, GPU link 1440 can be configured to enable connection to a host processor in addition to or as an alternative to host interface 1432.

[0189] In at least one embodiment, GPGPU 1430 can be configured to train neural networks. In at least one embodiment, GPGPU 1430 can be used within an inferencing platform. In at least one embodiment, where GPGPU 1430 is used for inferencing, GPGPU 1430 can include fewer compute clusters 1436A-1436H relative to when GPGPU is used to train neural networks. In at least one embodiment, memory technology associated with memory 1444A-1444B can vary between inferencing and training configurations, with higher bandwidth memory technology dedicated to training configurations. In at least one embodiment, inferencing configurations of GPGPU can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions that can be used during inferencing operations of deployed neural networks.

[0190] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and 5B. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 can be used in GPGPU 1430 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0191] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0192] Figure 15 A block diagram illustrating computer system 1500 according to at least one embodiment is shown. In at least one embodiment, computer system 1500 includes a processing subsystem 1501 with one or more processors 1502 and a system memory 1504 communicating via an interconnection path 1505 that can include a memory hub 1505. In at least one embodiment, memory hub 1505 can be a separate component coupled with one or more processors 1502 via communication links 1506 to perform memory access operations; alternatively, memory hub 1505 can be integrated into one or more processors 1502, communication links 1506 can be communication buses or communication links inside one or more processors 1502. In at least one embodiment, memory hub 1505 couples with system memory 1504, one or more input / output (I / O) subsystems 1511 with one or more I / O

[0193] In at least one embodiment, processing subsystem 1501 includes one or more parallel processor(s) 1512 coupled to memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, communication link 1513 can use any one of a number of standard communication links, such as, but not limited to, a PCI Express, or can be a vendor specific communications interface or communications structure. In at least one embodiment, one or more parallel processor(s) 1512 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processor(s) 1512 form a graphics processing subsystem that can output pixels to one or more display device(s) 1510A coupled via I / O Hub 1507. In at least one embodiment, one or more parallel processor(s) 1512 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 1510B.

[0194] In at least one embodiment, system storage 1514 can connect to I / O hub 1507 to provide storage mechanisms for computing system 1500. In at least one embodiment, I / O switches 1516 can be used to provide an interface mechanism to enable connections between I / O hub 1507 and other components, such as network adapters 1518 and / or wireless network adapters 1519 that can be integrated into a platform, as well as various other devices that can be added via one or more add-in devices 1520. In at least one embodiment, network adapters 1518 can be Ethernet adapters or another wired network adapters. In at least one embodiment, wireless network adapters 1519 can include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices that include one or more radio(s).

[0195] In at least one embodiment, computing system 1500 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which can also be connected to I / O hub 1507. In at least one embodiment, interconnection of the components of computing system 1500 can be achieved by using any suitable protocols, including PCI- based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and / or protocols, such as NV-Link high-speed interconnect, or interconnect protocols. Figure 15

[0196] In at least one embodiment, parallel processor(s) 1512 include circuitry optimized for graphics and video processing, including for example video output circuitry, and are configured for use in a gaming console, a personal computer, or other system. In at least one embodiment, parallel processor(s) 1512 incorporate circuitry optimized for general use computational processing, which can comprise parallel processor(s) 1512 configured for use in a server or like system. In at least one embodiment, one or more parallel processor(s) 1512 can be integrated on a graphics add-on board that can further communicate with processors 1502 over a high-speed link 1515, which can be a proprietary interconnect such as NV-Link, or other interconnect.

[0197] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Inferences can be made by inference and / or training logic 515 using one or more trained models. In at least one embodiment, one or more of the trained models used by inference and / or training logic 515 can be pre-trained using a small amount of labeled data and then fine-tuned using a larger amount of unlabeled data. In at least one embodiment, inference and / or training logic 515 can be used for any application that can benefit from artificial intelligence and / or machine learning.​Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 can be used in system 1500 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein. Figure 15

[0198] In at least one embodiment, such components can be used to manage communication links that connect processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0199] Processor

[0200] Figure 16A A parallel processor 1600, according to at least one embodiment, is shown. In at least one embodiment, various components of parallel processor 1600 can be implemented using one or more integrated circuits, which can be programmable integrated circuits, application specific integrated circuits, or field programmable gate arrays. In at least one embodiment, parallel processor 1600 is a variant of the Figure 15 Variants of one or more parallel processors 1512 are shown.

[0201] In at least one embodiment, parallel processor 1600 includes a parallel processing unit 1602. In at least one embodiment, parallel processing unit 1602 includes an I / O unit 1604 that enables communication with other devices, including other instances of parallel processing unit 1602. In at least one embodiment, I / O unit 1604 can be directly connected to other devices. In at least one embodiment, I / O unit 1604 connects with other devices via use of a hub or switch interface, such as memory hub 1505. In at least one embodiment, connections between memory hub 1505 and I / O unit 1604 form a communication link 1513. In at least one embodiment, I / O unit 1604 connects with a host interface 1606 and a memory crossbar switch 1616, where host interface 1606 receives commands directed to processing operations and memory crossbar switch 1616 receives commands directed to memory operations.

[0202] ​In at least one embodiment, when host interface 1606 receives a command buffer via I / O unit 1604, host interface 1606 can direct a work operation to execute those commands to front end 1608. In at least one embodiment, front end 1608 is coupled with scheduler 1610, which is configured to assign commands or other work items to processing cluster array 1612. In at least one embodiment, scheduler 1610 ensures that processing cluster array 1612 is properly configured and in an active state before assigning tasks to processing cluster array 1612. In at least one embodiment, scheduler 1610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, microcontroller- implemented scheduler 1610 is configurable to perform complex scheduling and work distribution operations with coarse and fine grain precision, enabling fast preemption and context switching for threads executing on processing array 1612. In at least one embodiment, host software can prove a workload for scheduling on processing array 1612 through one of multiple graphics processing paths. In at least one embodiment, workload can then be automatically distributed by scheduler 1610 logic within a microcontroller including scheduler 1610 on processing array 1612.

[0203] In at least one embodiment, processing cluster array 1612 can include up to “N” processing clusters (e.g., cluster 1614A, cluster 1614B, through cluster 1614N). In at least one embodiment, each cluster 1614A-1614N of processing cluster array 1612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 1610 can use various scheduling and / or work distribution algorithms to assign work to clusters 1614A-1614N of processing cluster array 1612, which can vary depending on workload of each type of program or computation. In at least one embodiment, scheduling can be handled by scheduler 1610 dynamically, or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array 1612. In at least one embodiment, different clusters 1614A-1614N of processing cluster array 1612 can be allocated for processing different types of programs or for performing different types of computations.

[0204] In at least one embodiment, processing cluster array 1612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1612 is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array 1612 can include logic to perform processing tasks including filtering of video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0205] In at least one embodiment, processing cluster array 1612 is configured to perform parallel graph processing operations. In at least one embodiment, processing cluster array 1612 can include additional logic to support performance of such graph processing operations, including but not limited to texture mapping logic to perform texture operations, and tessellation logic, and other vertex processing logic. In at least one embodiment, processing cluster array 1612 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel (or fragment) shaders. In at least one embodiment, parallel processor 1602 can transfer data to be processed from system memory via I / O unit 1604. In at least one embodiment, data being transferred can be stored to on-chip memory (e.g., parallel processor memory 1622) during processing for access by the processing cores. In at least one embodiment, results from the processing can be written to memory when processing is completed or a processing step is completed.

[0206] In at least one embodiment, when parallel processor 1602 is used to perform graphics processing, scheduler 1610 can be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations across multiple clusters 1614A-1614N of processing cluster array 1612. In at least one embodiment, portions of processing cluster array 1612 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations, to produce a rendered image for display on a display device. In at least one embodiment, intermediate data produced by one or more of clusters 1614A-1614N can be stored in buffers to allow transmission of the intermediate data between clusters 1614A-1614N for further processing.

[0207] In at least one embodiment, processing cluster array 1612 can receive processing tasks to be executed via scheduler 1610, which receives commands defining the processing tasks from front end 1608. In at least one embodiment, a processing task can include an index of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler 1610 can be configured to fetch the index corresponding to a task, or can receive the index from front end 1608. In at least one embodiment, front end 1608 can be configured to ensure that processing cluster array 1612 is configured in an effective state before launching a workload specified by an incoming command buffer (e.g., a batch- buffer, a push buffer, etc.).

[0208] In at least one embodiment, each of one or more instances of parallel processing unit 1602 can be coupled to a parallel processor memory 1622. In at least one embodiment, parallel processor memory 1622 can be accessed by parallel processing unit 1602, either by one or more instances of parallel processing unit 1602, or by the memory interconnect 1616. In at least one embodiment, parallel processor memory 1622 can be accessed by the memory interconnect 1616, which can be a high-speed, cross-pipeline memory interconnect that provides memory requests from the I / O unit 1604, and the processing cluster array 1612 to the memory units 1624A-1624N of parallel processor memory 1622. In at least one embodiment, the memory interconnect 1616 can provide parallel memory requests and memory responses using a parallel processor memory request and response scheme.

[0209] In at least one embodiment, memory units 1624A-1624N can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM). In at least one embodiment, memory units 1624A-1624N can also include 3D stacked memory including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across memory units 1624A-1624N allowing partition units 1620A-1620N to write portions of each rendering target in parallel to effectively use available bandwidth of parallel processor memory 1622. In at least one embodiment, local instances of parallel processor memory 1622 can be excluded from a unified memory design that utilizes system memory in combination with local cache memory.

[0210] In at least one embodiment, any of clusters 1614A-1614N of processing cluster array 1612 can process data to be written into any of memory locations 1624A-1624N within parallel processor memory 1622. In at least one embodiment, memory crossbar 1616 can be configured to transmit outputs of each cluster 1614A-1614N to any partition unit 1620A-1620N or another cluster 1614A-1614N, which can perform further processing operations on the outputs. In at least one embodiment, each cluster 1614A-1614N can communicate with memory interface 1618 through memory crossbar 1616 to read from or write to various external memory devices. In at least one embodiment, memory crossbar 1616 has a connection to memory interface 1618 to communicate with I / O unit 1604, and a local instance of connection to parallel processor memory 1622, to enable processing clusters 1614A-1614N within different processing clusters 1614A-1614N to communicate with system memory or other memories not local to the parallel processing units 1602. In at least one embodiment, memory crossbar 1616 can use virtual channels to separate traffic streams between clusters 1614A-1614N and partition units 1620A-1620N.

[0211] In at least one embodiment, multiple instances of parallel processing unit 1602 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1602 can be configured to operate together as a single parallel processing unit 1602, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences.

[0212] Figure 16B is a block diagram of a partition unit 1620, in accordance with at least one embodiment. In at least one embodiment, partition unit 1620 is a Figure 16Aone of partition units 1620A-1620N of FIG. 16. In at least one embodiment, partition unit 1620 includes an L2 cache 1621, a frame buffer interface 1625, and a raster operations unit (“ROP”) 1626. L2 cache 1621 is a read / write cache that is configured to perform load and store operations received from memory crossbar 1616 and ROP 1626. In at least one embodiment, L2 cache 1621 outputs read misses and urgent write-back requests to frame buffer interface 1625 for processing. In at least one embodiment, updates can also be sent to frame buffer via frame buffer interface 1625 for processing. In at least one embodiment, frame buffer interface 1625 interacts with one of memory units 1624A-1624N (e.g., within parallel processor memory 1622) in parallel processor memory. Figure 16A

[0213] In at least one embodiment, ROP 1626 is a processing unit that performs raster operations including, for example, fill, line, ellipse, triangle, and / or the like. In at least one embodiment, ROP 1626 is configured to execute shaders consumed by graphics processing pipeline 1600. In at least one embodiment, ROP 1626 includes support for integer and floating point data formats including single and double-precision floating point data formats. In at least one embodiment, ROP 1626 also includes support for video graphics

[0214] In at least one embodiment, ROP 1626 is included within each processing cluster (e.g., clusters 1614A-1614N of FIG. 16) instead of in partition unit 1620. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 1616 instead of pixel fragment data. In at least one embodiment, processed graphics data can be displayed on display device(s) 2210 which is / are routed through a display controller 2212 in FIG. 22. In at least one embodiment, processed graphics data can be displayed on display device(s) 2210 which is / are routed through a display controller 2212 in FIG. 22. Figure 16A Figure 22 Figure 16A

[0215] Figure 16C is a block diagram of a processing cluster 1614 within a parallel processing unit according to at least one embodiment. In at least one embodiment, processing cluster is a Figure 16A ​​​​one of the processing clusters 1614A-1614N. In at least one embodiment, one or more processing clusters 1614 can be configured to execute many threads in parallel, where a “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, Single Instruction Multiple Data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads with without providing multiple independent instruction units to apply the instructions to separate sets of data. In at least one embodiment, Single Instruction Multiple Thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0216] In at least one embodiment, operation of processing cluster 1614 can be controlled by a pipeline manager 1632 that allocates processing tasks to SIMT parallel processor cores. In at least one embodiment, pipeline manager 1632 receives instructions from scheduler 1610, and manages execution of those instructions via graphics multiprocessor 1634 and / or texture unit 1636. In at least one embodiment, graphics multiprocessor 1634 is an exemplary instance of a SIMT parallel processor core. However, in at least one embodiment, various types of SIMT parallel processor cores of differing architecture can be included within processing cluster 1614. In at least one embodiment, one or more instances of graphics multiprocessor 1634 can be included within a processing cluster 1614. In at least one embodiment, graphics multiprocessor 1634 can process data, and a data crossbar 1640 can be used to distribute processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, pipeline manager 1632 can facilitate distribution by specifying destinations for processed data as a function of its origin. Figure 16A

[0217] In at least one embodiment, each graphics multiprocessor 1634 within processing cluster 1614 can include an identical set of functional execution logic (e.g., arithmetic logic, load store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, shift operations, and a multitude of algebraic functions. In at least one embodiment, same functional -unit hardware can be leveraged to perform different operations using different data types. Any combination of hardware units can be present. For example, graphics multiprocessor 1634 can include single precision floating point

[0218] ​In at least one embodiment, instructions delivered to processing cluster 1614 constitute a thread for execution. In at least one embodiment, a group of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1634. In at least one embodiment, a thread group can include fewer threads than are present in a plurality of processing engines. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines present in graphics multiprocessor 1634, one or more of the processing engines can be idle during the period that a thread group is processing threads. In at least one embodiment, a thread group can also include more threads than are present in a plurality of processing engines. In at least one embodiment, when a thread group includes more threads than the number of processing engines present in graphics multiprocessor 1634, multiple threads in a thread group can be executed across the same processing engine in different clock cycles.

[0219] In at least one embodiment, graphics multiprocessor 1634 includes internal cache memory, to perform load and store operations. In at least one embodiment, graphics multiprocessor 1634 can bypass internal cache and use cache memory within processing cluster 1614 (e.g., Ll cache 1648). In at least one embodiment, each graphics multiprocessor 1634 can also have access to L2 Cache within a partition unit (e.g., partition units 1620A-1620N) that is shared among all processing clusters 1614 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1634 can also have access to off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processor 1602 can be used as global memory. In at least one embodiment, processing cluster 1614 includes multiple instances of graphics multiprocessor 1634, which can share common instructions and data stored in Ll cache 1648. Figure 16A

[0220] In at least one embodiment, each processing cluster 1614 can include a memory management unit (MMU) 1645 to map virtual addresses into physical addresses, as is known in the art. In at least one embodiment, one or more instances of MMU 1645 can reside in Figure 16A ​In at least one embodiment, MMU 1645 includes a set of page table entries (PTEs) used to map virtual addresses into physical addresses for task computation and optionally into cache line indices for tasks. In at least one embodiment, MMU 1645 can include an address translation lookaside buffer (TLB) or can reside in a graphics multiprocessor 1634 or Ll cache or processing cluster 1614. In at least one embodiment, processing physical addresses enables data access locality to be determined for efficient request interleaving between partition units.

[0221] In at least one embodiment, processing clusters 1614 can be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture Ll cache (not shown) or from an Ll cache within graphics multiprocessor 1634 as needed, and texture data is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 1634 outputs processed tasks to data crossbar 1640 to provide processed tasks to another processing cluster 1614 for further processing or to store processed task data in an L2 cache, local parallel processor memory, or system memory via memory crossbar 1616. In at least one embodiment, a ROP 1642 (Raster Operations unit) is configured to receive data from graphics multiprocessor 1634, direct data to front-end processor as described herein that can be positioned, e.g., with partition units (e.g., partition units 1620A-1620N) described herein, in at least one embodiment. In at least one embodiment, ROP 1642 can perform optimizations for color blending, organize pixel color data, and perform address translation. Figure 16A

[0222] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. Figure 5A Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6.

[0223] ​​In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0224] Figure 16D A graphics processing unit 1634 according to at least one embodiment is shown. In at least one embodiment, graphics processing unit 1634 is coupled with a pipeline manager 1632 of processing cluster 1614. In at least one embodiment, graphics processing unit 1634 has a thread execution pipeline that includes, without limitation, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more general-purpose GPU (GPGPU) cores 1662, and one or more load / store units 1666. One or more GPGPU cores 1662 and one or more load / store units 1666 are coupled with cache memory 1672 and shared memory 1670 via a memory and cache interconnect 1668.

[0225] In at least one embodiment, instruction cache 1652 receives a stream of instructions to execute from pipeline manager 1632. In at least one embodiment, instructions are cached in instruction cache 1652 and dispatched for execution by instruction unit 1654. In one embodiment, instruction unit 1654 can dispatch instructions to the threads of a thread group (e.g., a thread warp) with each thread in the thread group allocated a different execution unit within GPGPU cores 1662. In at least one embodiment, instructions can access any of a number of different address spaces, including a local, shared, or global address space, by specifying an address in a unified address space. In at least one embodiment, address mapping unit 1656 can be used to convert an address in the unified address space into a different address that can be accessed by load / store unit 1666.

[0226] In at least one embodiment, register file 1658 provides a set of registers for functional units of graphics processing unit 1634. In at least one embodiment, register file 1658 provides temporary storage for operands of the data paths connected to the functional units (e.g., GPGPU cores 1662, load / store unit 1666) of graphics processing unit 1634. In at least one embodiment, register file 1658 is partitioned between each of the functional units such that there is a dedicated portion of the register file 1658 for each functional unit. In at least one embodiment, register file 1658 is partitioned between different thread blocks being executed by graphics processing unit 1634.

[0227] In at least one embodiment, GPGPU cores 1662 can each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) that are capable of performing instructions defined by an extension of the SIMD instruction set implemented in GPGPU cores 1662. In at least one embodiment, first portions of GPGPU cores 1662 include single precision FPU’s and integer ALUs, while second portions of GPGPU cores 1662 include double precision FPU’s.

[0228] In at least one embodiment, GPGPU cores 1662 include SIMD logic capable of performing a single -instruction multiple-data (SIMD) operation on multiple groups of data objects. In at least one embodiment, GPGPU cores 1662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores 1662 can be generated by a shader compiler during compilation of compute program written using a high level programming language such as, for example, C or C++.

[0229] In at least one embodiment, memory and cache interconnect 1668 is an interconnect network that connects each functional unit of graphics multiprocessor 1634 to register file 1658 and shared memory 1670. In at least one embodiment, memory and cache interconnect 1668 is a crossbar interconnect that allows load / store units 1666 to implement load and store operations between shared memory 1670 and register file 1658. In at least one embodiment, register file 1658 can operate at same frequency as GPGPU cores 1662, such that latency for data transfers between GPGPU cores 1662 and register file 1658 is very low. In at least one embodiment, shared memory 1670 can be used to enable communication between threads executing on functional units within graphics multiprocessor 1634. In at least one embodiment, cache memory 1672 can be used to cache texture data communicated between texture unit 1636 and functional units. In at least one embodiment, shared memory 1670 can also be used as a program managed cache. In at least one embodiment, in addition to auto cached data stored in cache memory 1672, threads executing on GPGPU cores 1662 can also store data in shared memory in a programmed manner.

[0230] In at least one embodiment, parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU can be communicatively coupled to host processor / cores by a bus or other interconnect (e.g., a high speed

[0231] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5 and 6. Figure 5A and / or Figure 5BDetails regarding inference and / or training logic 515 are provided. In at least one embodiment, inference and / or training logic 515 can be used in graphics multiprocessor 1634 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0232] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0233] Figure 17 A multi-GPU computing system 1700 is shown, in accordance with at least one embodiment. In at least one embodiment, multi-GPU computing system 1700 can include a processor 1702 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1706A-D via a host interface switch 1704. In at least one embodiment, host interface switch 1704 is a PCI Express switch device that couples processor 1702 to a PCI Express bus over which processor 1702 can communicate with GPGPUs 1706A-D. GPGPUs 1706A-D can be interconnected via a set of high-speed P2P GPU-to-GPU links 1716. In at least one embodiment, GPU-to-GPU links 1716 connect to each of GPGPUs 1706A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 1716 enable direct communication between each GPGPU 1706A-D without having to communicate through host interface bus 1704 to which processor 1702 is connected. In at least one embodiment, host interface bus 1704 remains available for system memory access or communication with other instances of multi-GPU computing system 1700, e.g., via one or more network devices, in case GPU-to-GPU traffic is directed to P2P GPU links 1716. While, in at least one embodiment, GPGPUs 1706A-D are connected to processor 1702 via host interface switch 1704, in at least one embodiment, processor 1702 includes direct support for P2P GPU links 1716 and can be directly connected to GPGPUs 1706A-D.

[0234] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Inference and / or training logic 515, among other examples, can be used to implement neural network functions and / or architectures described herein. Figure 5A and / or Figure 5BDetails regarding the inference and / or training logic 515 are provided. In at least one embodiment, the inference and / or training logic 515 can be used in multi-GPU computing system 1700 for performing inference or prediction operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0235] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0236] Figure 18 is a block diagram of a graphics processor 1800 in accordance with at least one embodiment. In at least one embodiment, graphics processor 1800 includes ring interconnect 1802, front-end pipeline 1804, media engine 1837, and graphics cores 1880A-1880N. In at least one embodiment, ring interconnect 1802 couples graphics processor 1800 to other processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1800 is one of many processors integrated within a multi-core processing system.

[0237] In at least one embodiment, graphics processor 1800 receives batches of commands via ring interconnect 1802. In at least one embodiment, incoming commands are interpreted by a command streamer 1803 in pipeline front-end 1804. In at least one embodiment, graphics processor 1800 includes scalable execution logic to perform 3D geometry processing and media processing via the graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, command streamer 1803 supplies commands to geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, command streamer 1803 supplies commands to video front end 1834, which couples with media engine 1837. In at least one embodiment, media engine 1837 includes a video quality engine (VQE) 1830 for video and image post-processing, and a multi-format encode / decode (MFX) 1833 engine to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline 1836 and media engine 1837 each generate execution threads for the thread execution resources provided by at least one graphics core 1880A.

[0238] In at least one embodiment, graphics processor 1800 includes a scalable thread execution resource including a plurality of module cores 1880A-1880N (sometimes referred to as core slices), each including multiple sub-cores 1850A-1850N, 1860A-1860N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor 1800 can have any number of graphics cores 1880A-1880N. In at least one embodiment, graphics processor 1800 includes graphics core 1880A having at least a first sub-core 1850A and a second sub-core 1860A. In at least one embodiment, graphics processor 1800 is a low power processor with a single sub-core (e.g., 1850A). In at least one embodiment, graphics processor 1800 includes multiple graphics cores 1880A-1880N each including a set of first sub-cores 1850A-1850N and a set of second sub-cores 1860A-1860N. In at least one embodiment, each sub-core in first sub-cores 1850A-1850N includes at least a first set of execution units 1852A-1852N and media / texture samplers 1854A-1854N. In at least one embodiment, each sub-core in second sub-cores 1860A-1860N includes at least a second set of execution units 1862A-1862N and samplers 1864A-1864N. In at least one embodiment, each sub-core 1850A-1850N, 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic.

[0239] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5A and / or 5B. In at least one embodiment, inference and / or training logic 515 can be used in graphics processor 1800 for inferencing or predicting operations, based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below. In at least one embodiment, inference and / or training logic 515 can be used in graphics processor 1800 for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0240] In at least one embodiment, such components can be used to manage communication links that connect processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0241] Figure 19is a block diagram illustrating a microarchitecture for a processor 1900 according to at least one embodiment, which can include logic circuits to execute instructions. In at least one embodiment, processor 1900 can execute instructions including x86 instructions, ARM instructions, specialized instructions for application specific integrated circuits (ASICs), and the like. In at least one embodiment, processor 1900 can include registers to store packed data, such as 64-bit wide MMX® registers enabled by Intel® MMX Technology in microprocessors by Intel Corporation, Santa Clara, CA, as well as SIMD TM registers available for integer and floating point number formats can operate with packed data elements accompanying Single Instruction, Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers related to SSE2, SSE3, SSE4, AVX, or higher (generically referred to as “SSEx”) technology can hold such packed data operands. In at least one embodiment, processor 1900 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0242] In at least one embodiment, processor 1900 includes an in-order front-end (“front-end”) 1901 to fetch instructions to be executed and to prepare instructions for execution by other pipelines. In at least one embodiment, front-end 1901 can include several units. In at least one embodiment, instruction prefetcher 1923 fetches instructions from memory and provides pre-fetched instructions to an instruction decoder 1928 which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder 1928 decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro-op” or “microops”) that the machine can execute. In at least one embodiment, instruction decoder 1928 parses the instruction into an operation code that it can use to identify an operation to be performed and corresponding data and control fields that convey operands and other necessary information for the operation. In at least one embodiment, a trace cache 1930 can assemble decoded micro-instructions into program ordered sequences or traces in a microinstruction queue 1934 for execution. In at least one embodiment, when trace cache 1930 encounters a complex instruction, a microcode ROM 1932 provides the micro-instructions needed to complete the operation.

[0243] In at least one embodiment, some instructions can be converted into a single micro- operation, while others can require several micro-operations to complete. In at least one embodiment, if more than four micro-instructions are needed to complete a single instruction, then instruction decoder 1928 can access microcode ROM 1932 to perform that instruction. In at least one embodiment, instructions can be decoded into a small number of micro-instructions to handle at instruction decoder 1928. In at least one embodiment, if multiple micro-instructions are needed to complete an operation, then an instruction can be stored in microcode ROM 1932. In at least one embodiment, a trace cache 1930 references an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading a microcode sequence from microcode ROM 1932 to complete one or more instructions, in accordance with at least one embodiment. In at least one embodiment, after microcode ROM 1932 completes sequencing of micro-operations for an instruction, a front end 1901 of a machine can resume fetching micro-operations from trace cache 1930.

[0244] In at least one embodiment, out-of-order execution engine (“out-of-order engine”) 1903 can prepare instructions for execution. In at least one embodiment, out-of-order execution logic has multiple buffers to smooth and reorder instruction flow to optimize performance as instructions are pipelined down and dispatched for execution. In at least one embodiment, out-of-order execution engine 1903 includes, without limitation, an allocator / register renamer 1940, a memory micro instruction queue 1942, an integer / float micro instruction queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow / general floating point scheduler (“slow / general FP scheduler”) 1904, and a simple floating point scheduler (“simple FP scheduler”) 1906. In at least one embodiment, fast scheduler 1902, slow / general floating point scheduler 1904, and simple floating point scheduler 1906 are also collectively referred to as “micro instruction schedulers 1902, 1904, 1906.” In at least one embodiment, allocator / register renamer 1940 allocates machine buffers and resources needed by each micro instruction to execute in sequence. In at least one embodiment, allocator / register renamer 1940 renames logical registers to entries in a register file. In at least one embodiment, allocator / register renamer 1940 also allocates entries for each micro instruction in one of two micro instruction queues, memory micro instruction queue 1942 for memory operations and integer / float micro instruction queue 1944 for non-memory operations, in front of memory scheduler 1946 and micro instruction schedulers 1902, 1904, 1906. In at least one embodiment, micro instruction schedulers 1902, 1904, 1906 determine when micro instructions are ready to execute based on readiness of their dependent input register operand sources and availability of execution resource micro instructions needed to complete. In at least one embodiment, fast scheduler 1902 can schedule on every half of a main clock cycle, while slow / general floating point scheduler 1904 and simple floating point scheduler 1906 can schedule once per main processor clock cycle. In at least one embodiment, micro instruction schedulers 1902, 1904, 1906 arbitrate for a dispatch port to dispatch micro instructions for execution.

[0245] In at least one embodiment, execution block 1911 includes, without limitation, integer register file / bypass network 1908, floating point register file / bypass network (“FP register file / bypass network”) 1910, address generation units (“AGUs”) 1912 and 1914, fast arithmetic logic units (“fast ALUs”) 1916 and 1918, slow arithmetic logic unit (“slow ALU”) 1920, floating point ALU (“FP”) 1922, and floating point move unit (“FP move”) 1924. In at least one embodiment, integer register file / bypass network 1908 and floating point register file / bypass network 1910 are also referred to herein as “register files 1908, 1910.” In at least one embodiment, AGUs 1912 and 1914, fast ALUs 1916 and 1918, slow ALU 1920, floating point ALU 1922, and floating point move unit 1924 are also referred to herein as “execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924.” In at least one embodiment, execution block 1911 can include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units (in any combination).

[0246] In at least one embodiment, register files 1908, 1910 can be arranged between micro-instruction schedulers 1902, 1904, 1906 and execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, integer register file / bypass network 1908 performs integer operations. In at least one embodiment, floating point register file / bypass network 1910 performs floating point operations. In at least one embodiment, each of register files 1908, 1910 can include, without limitation, a bypass network that can bypass or forward a just-completed result that has not yet been written into a register file to a new dependee. In at least one embodiment, register files 1908, 1910 can communicate data with each other. In at least one embodiment, integer register file / bypass network 1908 can include, without limitation, two separate register files, one for lower 32 bits of data and a second for upper 32 bits of data. In at least one embodiment, floating point register file / bypass network 1910 can include, without limitation, 128 bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0247] In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924 can execute instructions. In at least one embodiment, register files 1908, 1910 store integer and floating point data operand values upon which microinstructions require execution. In at least one embodiment, processor 1900 can include, without limitation, any number and combination of execution units 1912, 1914, 1916, 1918, 1920, 1922, 1924. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU 1922 can include, without limitation, a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. In at least one embodiment, instructions for dealing with floating point values can be handled with floating point hardware. In at least one embodiment, ALU operations can be passed to fast ALUs 1916, 1918. In at least one embodiment, fast ALUs 1916, 1918 can execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALU 1920 as slow ALU 1920 can include, without limitation, integer execution hardware for long latency type of operations such as multiplies, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be executed by AGUs 1912, 1914. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can execute integer operations on 64 bit data operands. In at least one embodiment, fast ALU 1916, fast ALU 1918, and slow ALU 1920 can be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU 1922 and floating point move unit 1924 can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

[0248] In at least one embodiment, micro-instruction scheduler 1902, 1904, 1906 schedules dependent operations prior to completion of parent load execution. In at least one embodiment, because micro-instructions can be speculatively scheduled and executed in processor 1900, processor 1900 can also include logic to handle memory misses. In at least one embodiment, if a data load in a data cache misses, there can be dependent operations running in a pipeline that cause the scheduler to temporarily have incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations can need to be replayed and independent operations can be allowed to complete. In at least one embodiment, a scheduler and replay mechanism of at least one embodiment of a processor can also be designed to capture instruction sequences for text string compare operations.

[0249] In at least one embodiment, the term “register” can refer to an on-board processor storage location that can be used as part of an instruction that identifies an operand. In at least one embodiment, a register can be one that can be used from outside of a processor (from a programmer’s perspective). In at least one embodiment, a register can not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein can be implemented by circuitry within a processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packing data.

[0250] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5I and / or 5J. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5I and / or 5J. In at least one embodiment, portions or all of inference and / or training logic 515 can be incorporated in execution block 1911 and other memory or registers shown or not shown. For example, in at least one embodiment, training and / or inferencing techniques described herein can use one or more ALUs shown in execution block 1911. Further, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure ALUs of execution block 1911 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0251] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0252] Figure 20 A deep learning application processor 2000, in accordance with at least one embodiment, is shown. In at least one embodiment, deep learning application processor 2000 uses instructions that, if executed by deep learning application processor 2000, cause deep learning application processor 2000 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor 2000 is an application specific integrated circuit (ASIC). In at least one embodiment, application processor 2000 performs matrix multiplication operations or is “hardwired” into hardware as a result of executing one or more instructions or both. In at least one embodiment, deep learning application processor 2000 includes, without limitation, processing clusters 2010(1)-2010(12), inter-chip links (“ICLs”) 2020(1)-2020(12), inter-chip controllers (“ICCs”) 2030(1)-2030(2), memory controllers (“Mem Ctrlrs”) 2042(1)-2042(4), high bandwidth memory physical layers (“HBM PHYs”) 2044(1)-2044(4), management controller central processing units (“Mgmt Ctrlr CPUs”) 2050, serial peripheral interfaces, internal integrated circuits, and general purpose input / output blocks (“SPI, I2C, GPIO”), peripheral component interconnect express controllers and direct memory access blocks (“PCIe Controllers and DMA”) 2070, and a peripheral component interconnect express x 16 port (“PCI Express x 16”) 2080.

[0253] In at least one embodiment, processing clusters 2010 can perform deep learning operations, including inference or prediction operations based on weight parameters calculated based on one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2010 can include, without limitation, any number and type of processor. In at least one embodiment, deep learning application processor 2000 can include any number and type of processing clusters 2000. In at least one embodiment, inter-chip links 2020 are bidirectional. In at least one embodiment, inter-chip links 2020 and inter-chip controllers 2030 enable multiple deep learning application processors 2000 to exchange information, including activation information resulting from execution of one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor 2000 can include any number (including zero) and type of ICL 2020 and ICC 2030.

[0254] In at least one embodiment, HBMs 22040 provide a total of 32 GB of memory. HBM 22040(i) is associated with both memory controller 2042(i) and HBM PHY 2044(i). In at least one embodiment, any number of HBMs 22040 can provide any type and total amount of high bandwidth memory, and can be associated with any number (including zero) and type of memory controller 2042 and HBM PHY 2044. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2060, and DMA 2070 and / or PCIe 2080 can be replaced with any number and type of block to implement any number and type of communication standard in any technically feasible fashion.

[0255] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5i and / or 5j. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided. In at least one embodiment, deep learning application processor 2000 is used to train a machine learning model (e.g., neural network) to predict or infer information provided to deep learning application processor 2000. In at least one embodiment, deep learning application processor 2000 is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep learning application processor 2000. In at least one embodiment, processor 2000 can be used to perform one or more neural network use cases described herein.

[0256] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0257] Figure 21 is a block diagram of a neuromorphic processor 2100, in accordance with at least one embodiment. In at least one embodiment, neuromorphic processor 2100 can receive one or more inputs from a source external to neuromorphic processor 2100. In at least one embodiment, these inputs can be transmitted to one or more neurons 2102 within neuromorphic processor 2100. In at least one embodiment, neurons 2102 and components thereof can be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor 2100 can include, without limitation, thousands or millions of instances of neurons 2102, although any suitable number of neurons 2102 can be used. In at least one embodiment, each instance of neurons 2102 can include neuron inputs 2104 and neuron outputs 2106. In at least one embodiment, neurons 2102 can generate outputs that can be transmitted to inputs of other instances of neurons 2102. In at least one embodiment, neuron inputs 2104 and neuron outputs 2106 can be interconnected via synapses 2108.

[0258] In at least one embodiment, neurons 2102 and synapses 2108 can be interconnected such that neuromorphic processor 2100 operates to process or analyze information received by neuromorphic processor 2100. In at least one embodiment, a neuron 2102 can send out an output spike (or “spike” or “peak”) when input received through neuron input 2104 exceeds a threshold value. In at least one embodiment, neuron 2102 can sum or integrate signals received at neuron input 2104. For example, in at least one embodiment, neuron 2102 can be implemented as a leaky integrate-and-fire neuron, where neuron 2102 can produce an output (or “spike”) using a transfer function such as a sigmoid or threshold function if a sum (referred to as “membrane potential”) exceeds a threshold value. In at least one embodiment, a leaky integrate-and-fire neuron can sum signals received at neuron input 2104 into a membrane potential, and can apply a program decay factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron can spike if multiple input signals are received at neuron input 2104 fast enough to exceed a threshold value (i.e., before the membrane potential decays too low to spike). In at least one embodiment, neuron 2102 can be implemented using circuitry or logic that receives input, integrates input into a membrane potential, and decays the membrane potential. In at least one embodiment, input can be averaged, or any other suitable transfer function can be used. Furthermore, in at least one embodiment, neuron 2102 can include, without limitation, comparator circuitry or logic that produces an output spike at neuron output 2106 when a result of applying a transfer function to neuron input 2104 exceeds a threshold value. In at least one embodiment, once neuron 2102 spikes, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2102 can resume normal operation after a suitable period of time (or refractory period).

[0259] In at least one embodiment, neurons 2102 can be interconnected by synapses 2108. In at least one embodiment, synapses 2108 can operate to transmit a signal from an output of a first neuron 2102 to an input of a second neuron 2102. In at least one embodiment, a neuron 2102 can transmit information over more than one instance of a synapse 2108. In at least one embodiment, one or more instances of neuron output 2106 can be connected through an instance of synapse 2108 to an instance of neuron input 2104 in the same neuron 2102. In at least one embodiment, an instance of a neuron 2102 that produces an output to be transmitted over an instance of a synapse 2108 can be referred to as a “presynaptic neuron” with respect to that instance of synapse 2108. In at least one embodiment, an instance of a neuron 2102 that receives input transmitted over an instance of a synapse 2108 can be referred to as a “postsynaptic neuron” with respect to that instance of synapse 2108. In at least one embodiment, with respect to various instances of synapse 2108, because an instance of a neuron 2102 can receive input from one or more instances of synapse 2108 and can also transmit output through one or more instances of synapse 2108, a single instance of a neuron 2102 can be both a “presynaptic neuron” and a “postsynaptic neuron”.

[0260] In at least one embodiment, neurons 2102 can be organized into one or more layers. Each instance of neuron 2102 can have one neuron output 2106 that can fan out to one or more neuron inputs 2104 through one or more synapses 2108. In at least one embodiment, neuron outputs 2106 of neurons 2102 in a first layer 2110 can be connected to neuron inputs 2104 of neurons 2102 in a second layer 2112. In at least one embodiment, layer 2110 can be referred to as a “feedforward layer”. In at least one embodiment, each instance of neuron 2102 in an instance of first layer 2110 can fan out to each instance of neuron 2102 in a second layer 2112. In at least one embodiment, first layer 2110 can be referred to as a “fully connected feedforward layer”. In at least one embodiment, each instance of neuron 2102 in each instance of second layer 2112 fans out to fewer than all instances of neuron 2102 in a third layer 2114. In at least one embodiment, second layer 2112 can be referred to as a “sparsely connected feedforward layer”. In at least one embodiment, neurons 2102 in second layer 2112 can fan out to neurons 2102 in multiple other layers, including to neurons 2102 in (the same) second layer 2112. In at least one embodiment, second layer 2112 can be referred to as a “cycle layer”. In at least one embodiment, neuromorphic processor 2100 can include any suitable combination of cycle layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0261] In at least one embodiment, neuromorphic processor 2100 can include, without limitation, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect synapses 2108 to neurons 2102. In at least one embodiment, neuromorphic processor 2100 can include, without limitation, circuitry or logic that, depending on a neural network topology and neuron fan-in / fan-out, allows synapses to be allocated to different neurons 2102 as needed. For example, in at least one embodiment, synapses 2108 can be connected to neurons 2102 using an interconnect structure such as a network-on-chip or through dedicated connections. In at least one embodiment, synapse interconnects and components thereof can be implemented using circuitry or logic.

[0262] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0263] Figure 22A processing system is shown in accordance with at least one embodiment. In at least one embodiment, system 2200 includes one or more processor(s) 2202 and one or more graphics processor(s) 2208, and can be a single processor desktop system, a multiprocessor workstation system, or a server system having many processor(s) 2202 or processor core(s) 2207. In at least one embodiment, system 2200 is a processing platform incorporated within a system on a chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0264] In at least one embodiment, system 2200 can include or be coupled to a graphics processing unit(s) 2208 (GPU(s) 2208) or graphics processing unit(s) on a processor(s) 2202 (processor(s) 2202 GPUs). In at least one embodiment, system 2200 is a gaming console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system 2200 is a mobile phone, a smart phone, a tablet device, or a mobile internet device. In at least one embodiment, processing system 2200 can also include or be coupled to a wearable device, such as a smart watch wearable device, smart glass device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2200 is a television or set-top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[0265] In at least one embodiment, one or more processor(s) 2202 each include one or more processor cores 2207 to process instructions which, when executed, implement the operations for system and user software. In at least one embodiment, each of the one or more processor cores 2207 is configured to process a specific instruction set 2209. In at least one embodiment, instruction set 2209 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via a very long instruction word (VLIW). In at least one embodiment, processor core 2207 can each process a different instruction set 2209, which can include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core 2207 can include other processing devices, such as a digital signal processor (DSP).

[0266] In at least one embodiment, processor 2202 includes cache memory 2204. In at least one embodiment, processor 2202 can have a single level of internal cache or multiple levels of internal caches. In at least one embodiment, cache memory is shared among multiple components of processor 2202. In at least one embodiment, processor 2202 also uses an external cache (e.g., a level three (L3) cache, or last level cache (LLC)) (not shown), which can be shared between processor cores 2207 using known cache coherency techniques. In at least one embodiment, additionally included in processor 2202 are register files 2206, which processor can include different types of registers to store different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). In at least one embodiment, register files 2206 can include general registers or other registers.

[0267] In at least one embodiment, one or more processors 2202 are coupled with one or more interface buses 2210 for communicating information to and from other components in system 2200, for example, address, data, or control signals. In at least one embodiment, interface bus 2210 can be implemented, in one embodiment, as a version of a processor bus such as a direct media interface (DMI) bus. In at least one embodiment, interface 2210 is not limited to DMI bus, and can include one or more peripheral component interconnect buses (e.g., a PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, processor 2202 includes an integrated memory controller 2216 and platform controller hub 2230. In at least one embodiment, memory controller 2216 facilitates communication between memory devices and other components of processing system 2200, while platform controller hub (PCH) 2230 provides connections to input / output (I / O) devices via a local I / O bus.

[0268] In at least one embodiment, memory device 2220 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, or a phase change memory device, among others. In at least one embodiment, memory device 2220 can be a system memory of processing system 2200, to store data 2222 and instructions 2221 for use when one or more processors 2202 executes an application or process. In at least one embodiment, memory controller 2216 also couples with an optional external graphics processor 2212, which can communicate with one or more graphics processors 2208 in processors 2202 to perform graphics and media operations.

[0269] In at least one embodiment, platform controller hub 2230 enables peripherals coupled to bridge 2250 to interact with the processor 2202. In at least one embodiment, I / O peripherals include, but are not limited to, an audio controller 2246, a network controller 2234, a firmware interface 2228, a wireless transceiver 2226, a touch sensor 2225, a data storage device 2224 (e.g., solid-state drive (SSD), floppy drive, optical drive, etc.), a graphics processor 2212, a high-definition multimedia

[0270] In at least one embodiment, memory controller 2216 and instances of platform controller hub 2230 can be integrated into a discrete external graphics processor, such as external graphics processor 2212. In at least one embodiment, platform controller hub 2230 and / or memory controller 2216 can be external to one or more processor(s) 2202. For example, in at least one embodiment, system 2200 can include an external memory controller 2216 and platform controller hub 2230, which can be configured as a memory controller hub and peripheral controller hub within a system chipset that is separate from processor(s) 2202.

[0271] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 and 6. Figure 5A and / or Figure 5BDetails regarding the inference and / or training logic 515 are provided. In at least one embodiment, some or all of inference and / or training logic 515 can be incorporated with graphics processor 2200. For example, in at least one embodiment, the training and / or inference techniques described herein can use one or more ALUs embodied in graphics processor 2212. Moreover, in at least one embodiment, the inference and / or training operations described herein can be accomplished with logic other than that shown. Figure 5A or Figure 5B In at least one embodiment, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not) that configure ALUs of graphics processor 2200 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0272] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0273] Figure 23 is a block diagram of a processor 2300 having one or more processor cores 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308, according to at least one embodiment. In at least one embodiment, processor 2300 can include additional cores, up to and including an additional core 2302N represented by a dashed lined in at least one embodiment. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core can also access one or more shared cache units 2306.

[0274] In at least one embodiment, internal cache units 2304A-2304N and shared cache unit 2306 represent a cache memory hierarchy within processor 2300. In at least one embodiment, cache memory units 2304A-2304N can include at least one level of instruction and data caches per processor core and one or more shared level caches, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other level cache, where the highest level of cache prior to main memory is classified as an LLC. In at least one embodiment, cache coherence logic maintains coherence between various cache units 2306 and 2304A-2304N.

[0275] In at least one embodiment, processor 2300 also includes a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, system agent core 2310 provides management functionality for various processor components. In at least one embodiment, system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown), including support for data bus protocols such as DDR DRAM.

[0276] In at least one embodiment, one or more processor cores 2302A-2302N include support to run in multiple threads simultaneously. In at least one embodiment, system agent core 2310 includes components for coordination and operation of cores 2302A-2302N during multi-threaded processing. In at least one embodiment, system agent core 2310 can additionally include a power control unit (PCU), including logic and components to govern one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0277] In at least one embodiment, processor 2300 also includes graphics processor 2308, which is used to perform graphics and compute processing tasks. In at least one embodiment, graphics processor 2308 couples with shared cache unit 2306 and system agent core 2310, including one or more integrated memory controllers 2314. In at least one embodiment, system agent core 2310 also includes a display controller 2311 to drive one or more coupled displays to display graphics processor output. In at least one embodiment, display controller 2311 can also be a separate module coupled with graphics processor 2308 via at least one interconnect, or can be integrated within graphics processor 2308.

[0278] In at least one embodiment, ring based interconnect unit 2312 is used to couple the internal components of the processor 2300. In at least one embodiment, an alternative interconnect unit can be used, such as a point-to-point interconnect, a switched interconnect, or other technology. In at least one embodiment, graphics processor 2308 couples with ring interconnect 2312 via I / O link 2313.

[0279] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2318 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared last-level cache.

[0280] In at least one embodiment, the processor cores 2302A-2302N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2302A-2302N execute a common instruction set, while one or more other processor cores 2302A-2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2300 can be implemented on one or more chips or as a SoC integrated circuit.

[0281] The reasoning and / or training logic 515 is used to perform reasoning and / or training operations associated with one or more embodiments. Figure 5A and / or Figure 5B Detail is provided regarding the inference and / or training logic 515. In at least one embodiment, some or all of the inference and / or training logic 515 may be incorporated into the processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may utilize one or more ALUs embodied in Figure 23 In addition, in at least one embodiment, the inference and / or training operations described herein may use a graphics processor 2212, graphics cores 2302A-2302N, or other components in the graphics processor 2212. Figure 5A or Figure 5B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2300 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0282] In at least one embodiment, such a component can be used to manage a communication link connecting processing devices. In at least one embodiment, this can include determining a frequency state and a power state of a communication link between processors.

[0283] Figure 24 is a block diagram of hardware logic of a graphics processor core 2400 in accordance with at least one embodiment described herein. In at least one embodiment, graphics processor core 2400 is included within a graphics core array. In at least one embodiment, graphics processor core 2400 (sometimes called a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2400 is an example of one graphics core slice, and a graphics processor described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2400 can include fixed function block 2430, also known as a sub slice, coupled with multiple sub-cores 2401A-2401F that include modules of general-purpose and fixed function logic.

[0284] In at least one embodiment, fixed function block 2430 includes geometry / fixed function pipeline 2436, for example, that can be shared by all of the sub-cores in graphics processor 2400 in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry and fixed function pipeline 2436 includes a 3D fixed function pipeline, a video front-end unit, a thread generator and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0285] In at least one embodiment, fixed function block 2430 also includes a graphics SoC interface 2437, a graphics microcontroller 2438, and a media pipeline 2439. In at least one embodiment, graphics SoC interface 2437 provides an interface between graphics core 2400 and other processor cores within a system on a chip. In at least one embodiment, graphics microcontroller 2438 is a programmable sub-processor that is configurable to manage various functions of graphics processor 2400, including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline 2439 includes logic to facilitate decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2439 implements media operations via requests to compute or sample logic within sub-cores 2401-2401F.

[0286] In at least one embodiment, SoC interface 2437 enables graphics core 2400 to communicate with general application processor cores (e.g., CPUs) and / or other components within an SoC, including memory hierarchy elements such as shared last level cache, system RAM, and / or embedded on-chip or package DRAM. In at least one embodiment, SoC interface 2437 can also enable communication with fixed function devices (e.g., camera imaging pipeline) within an SoC, and to use and / or implement global memory atoms that can be shared between graphics core 2400 and a CPU within the SoC. In at least one embodiment, SoC interface 2437 can also implement power management controls for graphics core 2400 and enable an interface between a clock domain of graphics core 2400 with other clock domains within the SoC. In at least one embodiment, SoC interface 2437 enables receiving command buffers from command streamer and global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched for media operations to a media pipeline 2439, or to a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline 2436, geometry and fixed function pipeline 2414) when graphics processing operations are to be performed.

[0287] In at least one embodiment, graphics microcontroller 2438 can be configured to perform various scheduling and management tasks for graphics core 2400. In at least one embodiment, graphics microcontroller 2438 can perform graphics and / or compute workload scheduling on various graphics processing engines within execution unit (EU) arrays 2402A-2402F, 2404A-2404F in sub-cores 2401A-2401F. In at least one embodiment, host software executing on CPU cores of an SoC including graphics core 2400 can submit workloads for one of multiple graphics processor paths, which invoke scheduling operations on appropriate graphics engines. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and informing host software when a workload is complete. In at least one embodiment, graphics microcontroller 2438 can also facilitate low power or idle state

[0288] In at least one embodiment, graphics core 2400 can have up to N more or less modular cores than shown in FIG. 24A. For each set of N cores, graphics core 2400 can also include shared function logic 2410, shared and / or cache memory 2412, geometry / fixed function pipeline 2414, and additional fixed function logic 2416 to accelerate various graphics and compute operations. In at least one embodiment, shared function logic 2410 can include logic units (e.g., samplers, math, and / or inter-thread communication logic) that are shared by each N core within graphics core 2400. In at least one embodiment, shared and / or cache memory 2412 can be a last level cache memory for N cores 2401A-2401F within graphics core 2400, and can also be used as shared memory that can be accessed by multiple cores. In at least one embodiment, geometry / fixed function pipeline 2414 can be included instead of geometry / fixed function pipeline 2436 within fixed function block 2430, and can include the same or similar logic units.

[0289] In at least one embodiment, graphics core 2400 includes additional fixed function logic 2416 that can include various fixed function acceleration logic used by graphics core 2400. In at least one embodiment, additional fixed function logic 2416 includes an additional geometry pipeline used in position only shading. In position only shading, there are at least two geometry pipelines, while in a full geometry pipeline and cull pipeline within geometry / fixed function pipeline 2416, 2436, which is an additional geometry pipeline that can be included in additional fixed function logic 2416. In at least one embodiment, the cull pipeline is a trimmed down version of the full geometry pipeline. In at least one embodiment, the full pipeline and the cull pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position only shading can hide long cull runs of triangles that are discarded, which can complete shading earlier in some cases. For example, in at least one embodiment, cull pipeline logic in additional fixed function logic 2416 can execute position shaders in parallel with a main application, and often generate critical results faster than the full pipeline because the cull pipeline takes and shades position attributes of vertices without performing rasterization and rendering pixels to a frame buffer. In at least one embodiment, the cull pipeline can use generated critical results to compute visibility information for all triangles, regardless of whether those triangles are culled or not. In at least one embodiment, the full pipeline, which can be referred to as a replay pipeline in this case, can consume the visibility information to skip culled triangles to only shade visible triangles that are ultimately passed to a rasterization stage.

[0290] In at least one embodiment, additional fixed function logic 2416 can also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or inferencing.

[0291] In at least one embodiment, within each graphics sub-core 2401A-2401F includes a set of execution resources, which can be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader program. In at least one embodiment, graphics sub-cores 2401A-2401F include multiple arrays of execution units 2402A-2402F, 2404A-2404F, thread dispatch and inter-thread communication (TD / IC) logic 2403A-2403F, 3D (e.g., texture) samplers 2405A-2405F, media samplers 2406A-2406F, shader processors 2407A-2407F, and shared local memory (SLM) 2408A-2408F. Arrays of execution units 2402A-2402F, 2404A-2404F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer / fixed-point logic operations including graphics, media, and compute operations in response to shader programs. In at least one embodiment, TD / IC logic 2403A-2403F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate

[0292] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, inferencing and / or training operations include machine learning for implementing neural networks to execute adaptive audio coding operations described herein. Figure 5A and / or Figure 5BDetails regarding the inference and / or training logic 515 are provided. In at least one embodiment, portions of inference and / or training logic 515 can be incorporated into graphics processor 2410. For example, in at least one embodiment, training and / or inference techniques described herein can be implemented using one or more ALUs embodied in graphics processor 2212, graphics microcontroller 2438, geometry & fixed function pipeline 2414 and 2436, or other logic in Figure 23 Figure 5A Figure 5B In at least one embodiment, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not) that configure ALUs of graphics processor 2400 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0293] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0294] Figures 25A-25B Thread execution logic 2500 including an array of processing elements that include graphics processor cores is shown in accordance with at least one embodiment. Figure 25A At least one embodiment is shown in which thread execution logic 2500 is used. Figure 25B Exemplary internal details of an execution unit are shown in accordance with at least one embodiment.

[0295] As Figure 25A ​​As shown in FIG, in at least one embodiment, thread execution logic 2500 includes a shader processor 2502, a thread dispatcher 2504, an instruction cache 2506, a scalable execution unit array including a plurality of execution units 2508A-2508N, a sampler 2510, a data cache 2512, and a data port 2514. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2508A, 2508B, 2508C, 2508D through 2508N-1 and 2508N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected via an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 2500 includes one or more connections to memory (such as system memory or cache memory) through instruction cache 2506, data port 2514, sampler 2510, and one or more of execution units 2508A-2508N. In at least one embodiment, each execution unit (e.g., 2507A) is an independent programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2508A-2508N is scalable to include any number of individual execution units.

[0296] In at least one embodiment, execution units 2508A-2508N are primarily used to execute shader programs. In at least one embodiment, shader processor 2502 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2504. In at least one embodiment, thread dispatcher 2504 includes logic for arbitrating thread initialization events from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 2508A-2508N. For example, in at least one embodiment, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2504 can also handle runtime thread generation requests from executing shader programs.

[0297] In at least one embodiment, execution units 2508A-2508N support a instruction set that includes native support for many standard 3D graphics shader instructions, such that a graphics processor can be executed with a minimum of translations from assembly language. In at least one embodiment, execution units 2508A-2508N include vertex and geometry processing (e.g., vertex

[0298] In at least one embodiment, each of execution units 2508A-2508N operate on arrays of data elements. In at least one embodiment, the number of data elements is the “execution size,” or the number of channels for instructions. In at least one embodiment, an execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. In at least one embodiment, a channel may not be physically implemented; it can be a simulated unit to provide functionality when multiple instruction passes are taken.

[0299] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, SIMD instructions support multiple, parallel data elements of e.g., 64, 128, 256, 512, or other vector widths. In at least one embodiment, integer instructions are available in 8, 16, 32, and 64-bit data sizes. In at least one embodiment, floating-point instructions are available in 16, 32, 64, and 128-bit data sizes. In at least one embodiment, instruction set includes instructions to convert between these vector widths.

[0300] In at least one embodiment, one or more execution units can be combined in a fused execution unit 2509A-2509N having thread control logic (2507A-2507N) for fused EU. In at least one embodiment, multiple EU can be combined into a group of EUs. In at least one embodiment, number of EUs in a fused EU group can be configured to execute separate SIMD hardware threads, and number of EUs in a fused EU group can vary according to various embodiments. In at least one embodiment, each EU can execute a variety of SIMD widths including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2509A-2509N includes at least two execution units. For example, in at least one embodiment, fused execution unit 2509A includes first EU 2508A, second EU 2508B, and thread control logic 2507A common to both first EU 2508A and second EU 2508B. In at least one embodiment, thread control logic 2507A controls threads executing on fused graphics execution unit 2509A, allowing each EU within fused execution unit 2509A-2509N to execute using a common instruction pointer register.

[0301] In at least one embodiment, one or more internal instruction caches (e.g., 2506) are included in thread execution logic 2500 to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g., 2512) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2510 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 2510 includes specialized texture or media sampling functionality to process texture or media

[0302] During execution, in at least one embodiment, graphics and media pipelines send thread initiation requests to thread execution logic 2500 through thread spawn and dispatch logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2502 is invoked to further compute output information and cause resulting values to be written to an output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, pixel or fragment shaders compute values of various vertex attributes to be interpolated across a rasterized object. In at least one embodiment, pixel processor logic within shader processor 2502 then executes a pixel or fragment shader program provided by an application program interface (API). In at least one embodiment, to execute a shader program, shader processor 2502 dispatches threads to execution units (e.g., 2508A) via thread dispatcher 2504. In at least one embodiment, shader processor 2502 uses texture sampling logic in sampler 2510 to access texture data stored in a texture map in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data compute pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0303] In at least one embodiment, data port 2514 provides a memory access mechanism for thread execution logic 2500 to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, data port 2514 includes or couples to one or more cache memories (e.g., data cache 2512) to cache data for memory access via a data port.

[0304] As Figure 25BAs shown, in at least one embodiment, graphics processing unit 2508 can include an instruction fetch unit 2537, a general register file array (GRF) 2524, an architectural register file array (ARF) 2526, a thread arbiter 2522, an issue unit 2530, a branch unit 2532, a set of SIMD floating point units (FPUs) 2531, and in at least one embodiment, a set of dedicated integer SIMD ALUs 2535. GRF 2524 and ARF 2526 include a set of general purpose register files and architectural register files associated with each simultaneous hardware thread that can be active in graphics processing unit 2508. In at least one embodiment, each thread architectural state is maintained in ARF 2526, while data used during thread execution is stored in GRF 2524. In at least one embodiment, each thread’s execution state, including each thread’s instruction pointer, can be saved in thread-specific registers in ARF 2526.

[0305] In at least one embodiment, graphics processing unit 2508 has an architecture that is a combination of simultaneous multi-threading (SMT) and fine-grained interleaved multi-threading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and a number of registers per execution unit, where execution unit resources are logically allocated for execution of multiple simultaneous threads.

[0306] In at least one embodiment, graphics processing unit 2508 can co-issue multiple instructions, each of which can be different instructions. In at least one embodiment, thread arbiter 2522 of graphics processing unit thread 2508 can dispatch an instruction to one of issue unit 2530, branch unit 2542, or SIMD FPU 2534 for execution. In at least one embodiment, each execution thread can have access to 128 general purpose registers in GRF 2524, where each register can store 32 bytes, which can be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread can have access to 4 KB in GRF 2524, although embodiments are not limited thereto, and in other embodiments can provide more or less register resources. In at least one embodiment, although the number of threads per execution unit can also vary according to embodiments, up to seven threads can be executed simultaneously. In at least one embodiment in which seven threads have access to 4 KB, GRF 2524 can store a total of 28 KB. In at least one embodiment, flexible addressing modes can allow registers to be addressed together to effectively establish wider registers or rectangular block data structures that represent strides.

[0307] In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via a “send” instruction executed by message passing send unit 2530. In at least one embodiment, dispatching branch instructions to a dedicated branch unit 2532 facilitates SIMD divergence and eventual convergence.

[0308] In at least one embodiment, graphics execution unit 2508 includes one or more SIMD floating point units (FPU) 2534 to perform floating point operations. In at least one embodiment, one or more FPU 2534 also support integer computing. In at least one embodiment, one or more FPU 2534 can SIMD execute up to M 32-bit floating point (or integer) operations, or up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one FPU provides extended math capability to support high throughput of math functions and double precision 64-bit floating point. In at least one embodiment, there is also a set of 8-bit integer SIMD ALUs 2535 and can be specifically optimized to perform operations related to machine learning calculations.

[0309] In at least one embodiment, an array of multiple instances of graphics execution unit 2508 can be instantiated in a graphics sub-core group (e.g., a sub-slice). In at least one embodiment, execution unit 2508 can execute instructions across multiple execution lanes. In at least one embodiment, each thread executing on graphics execution unit 2508 executes on a different lane.

[0310] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5I and / or 5J. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGS. 5I and / or 5J. In at least one embodiment, portions or all of inference and / or training logic 515 can be incorporated in thread execution logic 2500. Moreover, in at least one embodiment, logic other than that shown in FIGS. 5I and / or 5J can be used to perform the inferencing and / or training operations described herein. Figure 5A or Figure 5B In at least one embodiment, weight parameters can be stored in on-chip or off-chip memory and / or registers (shown or not) that configure ALUs of execution logic 2500 to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques introduced herein.

[0311] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0312] Figure 26 A parallel processing unit (“PPU”) 2600, in accordance with at least one embodiment, is shown. In at least one embodiment, PPU 2600 is configured with machine-readable code that, if executed by PPU 2600, causes PPU 2600 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, PPU 2600 is a multi-threaded processor implemented on one or more integrated circuit devices and utilizes multi-threading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) that are executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of an instruction set configured to be executed by PPU 2600. In at least one embodiment, PPU 2600 is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as a liquid crystal display (“LCD”) device. In at least one embodiment, PPU 2600 is used to perform computations such as linear algebraic operations and machine learning operations. Figure 26 Example parallel processors are shown for illustrative purposes only and are to be construed as non-limiting examples of processor architectures contemplated within the scope of this disclosure, and any suitable processor can be employed in addition to and / or in place of.

[0313] In at least one embodiment, one or more PPUs 2600 are configured to accelerate high performance computing (“HPC”), data center, and machine learning applications. In at least one embodiment, PPU 2600 is configured to accelerate deep learning systems and applications including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision voice, image, and text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather prediction, big data analytics, astronomy, molecular dynamics simulations, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, among others.

[0314] In at least one embodiment, PPU 2600 includes, without limitation, input / output (“I / O”) units 2606, front-end units 2610, scheduler units 2612, work distribution units 2614, hub 2616, crossbar (“Xbar”) 2620, one or more general processing clusters (“GPCs”) 2618, and one or more partition units (“memory partition units”) 2622. In at least one embodiment, PPU 2600 connects with one or more host processors or other PPUs 2600 via one or more high-performance GPU interconnects (“GPU interconnects”) 2608. In at least one embodiment, PPU 2600 connects with host processors or other peripherals via an

[0315] In at least one embodiment, high-speed GPU interconnect 2608 can refer to a link-based parallel computer bus that systems use to scale, and includes one or more PPUs 2600 in conjunction with one or more central processing units (“CPUs”), supports cache coherence between PPUs 2600 and CPUs, and CPU mastering. In at least one embodiment, high-speed GPU interconnect 2608 transfers data and / or commands between hub 2616 and other units of PPU 2600, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components not explicitly shown in FIG. 2. Figure 26 In at least one embodiment, high-speed GPU interconnect 2608 transfers data and / or commands between hub 2616 and other units of PPU 2600, such as one or more copy engines, video encoders, video decoders, power management units, and / or other components not explicitly shown in FIG. 2.

[0316] In at least one embodiment, I / O units 2606 are configured to facilitate communication between PPU 2600 and one or more other processors (not shown) of a system in which PPU 2600 is employed. In at least one embodiment, I / O units 2606 are configured to facilitate communication between PPU 2600 and Figure 26The I / O unit 2606 sends and receives communications (e.g., commands, data) to and from the system bus 2602 (e.g., over a wire, wirelessly). In at least one embodiment, the I / O unit 2606 communicates directly with the host processor(s) via the system bus 2602 or through one or more intermediate devices such as a memory bridge. In at least one embodiment, the I / O unit 2606 can communicate with one or more other processors (e.g., one or more PPUs 2600) via the system bus 2602. In at least one embodiment, the I / O unit 2606 implements a Peripheral Component Interconnect Express (“PCIe”) interface for communications over a PCIe bus. In at least one embodiment, the I / O unit 2606 implements interfaces for communicating with external devices.

[0317] In at least one embodiment, the I / O unit 2606 decodes packets received via the system bus 2602. In at least one embodiment, at least some packets represent commands configured to cause the PPU 2600 to perform various operations. In at least one embodiment, the I / O unit 2606 sends decoded commands to various other units of the PPU 2600 as specified by the commands. In at least one embodiment, commands are sent to the front-end unit 2610 and / or to the hub 2616 or other units of the PPU 2600 such as one or more copy engines, video encoders, video decoders, power management units, etc. Figure 26 In at least one embodiment, the I / O unit 2606 is not explicitly shown in FIG. 26. In at least one embodiment, the I / O unit 2606 is configured to route communications between various logical units of the PPU 2600.

[0318] In at least one embodiment, a program executed by the host processor encodes a command stream in a buffer that provides a workload to the PPU 2600 for processing. In at least one embodiment, a workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is a region in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2600 - the host interface unit can be configured to access memory requests transmitted via the I / O unit 2606 over the system bus 2602 to connect to the buffer in system memory. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer to the beginning of the command stream to the PPU 2600, causing the front-end unit 2610 to receive the one or more command stream pointers and manage the one or more command streams, reading commands from the command stream and forwarding the commands to various units of the PPU 2600.

[0319] In at least one embodiment, front-end unit 2610 is coupled to a scheduler unit 2612 which configures various GPCs 2618 to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit 2612 is configured to track state information related to various tasks managed by scheduler unit 2612, where state information can indicate which task is assigned to which GPC 2618, whether task is active or inactive, priority of task associated with it, and so forth. In at least one embodiment, scheduler unit 2612 manages multiple tasks that are executed on one or more GPCs 2618.

[0320] In at least one embodiment, scheduler unit 2612 is coupled to a work distribution unit 2614, which is configured to dispatch tasks for execution on GPCs 2618. In at least one embodiment, work distribution unit 2614 tracks a number of tasks received for execution by scheduler unit 2612 and work distribution unit 2614 manages a pending task queue and an active task queue for each GPC 2618. In at least one embodiment, the pending task queue includes a number of slots (e.g., 32 slots) that hold tasks assigned to be processed by a particular GPC 2618; the active task queue can include a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPC 2618, such that as one task is completed by GPC 2618, that task is evicted from GPC 2618’s active task queue and another task is selected from the pending task queue for processing on GPC 2618. In at least one embodiment, if an active task is idle, for example, while waiting for a data dependency to resolve, the active task is evicted from GPC 2618 and returned to the pending task queue while another task is selected from the pending task queue and scheduled for execution on GPC 2618.

[0321] In at least one embodiment, work distribution unit 2614 communicates with one or more GPCs 2618 via XBar 2620. In at least one embodiment, XBar 2620 is an interconnect network that couples many units of PPU 2600 to other units of PPU 2600 and can be configured to couple work distribution unit 2614 to a particular GPC 2618. In at least one embodiment, other units of one or more PPUs 2600 can also be connected to XBar 2620 via hub 2616.

[0322] In at least one embodiment, tasks are managed by a scheduler unit 2612 and dispatched to one of GPCs 2618 by a work distribution unit 2614. GPCs 2618 are configured to process tasks and generate results. In at least one embodiment, results can be consumed by other tasks within GPC 2618, routed to different GPCs 2618 over XBar 2620, or stored in memory 2604. In at least one embodiment, results can be written to memory 2604 by a partition unit 2622, which implements a memory interface for reading and writing data to memory 2604. In at least one embodiment, results can be transmitted over a high-speed GPU interconnect 2608 to another PPU 2604 or CPU. In at least one embodiment, PPU 2600 includes, without limitation, U partition units 2622 equal to a number of separate and distinct memory devices 2604 coupled to PPU 2600, as described below in more detail in conjunction with FIG. 26B. Figure 28 In more detail.

[0323] In at least one embodiment, a host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on a host processor to schedule operations to be performed on PPU 2600. In one embodiment, multiple compute applications are executed simultaneously by PPU 2600 and PPU 2600 provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in the form of API calls) that cause a driver core to generate one or more tasks for execution by PPU 2600 and driver core outputs tasks to one or more streams processed by PPU 2600. In at least one embodiment, each task includes one or more groups of related threads, which can be referred to as warps. In at least one embodiment, a warp includes a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads that include instructions for performing a task and exchanging data via shared memory, in conjunction with Figure 28 Threads and cooperating threads are described in more detail in accordance with at least one embodiment.

[0324] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Inferences and / or determinations described herein can be made based on one or more probabilities. Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Figure 5A and / or Figure 5BProvides details regarding inference and / or training logic 515. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 2600. In at least one embodiment, the PPU 2600 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 2600. In at least one embodiment, the PPU 2600 can be used to perform one or more of the neural network use cases described herein.

[0325] In at least one embodiment, such a component can be used to manage a communication link connecting processing devices. In at least one embodiment, this can include determining a frequency state and a power state of a communication link between processors.

[0326] Figure 27 A general processing cluster ("GPC") 2700 is shown in accordance with at least one embodiment. In at least one embodiment, GPC 2700 is Figure 26 2618. In at least one embodiment, each GPC 2700 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2700 includes, but is not limited to, a pipeline manager 2702, a pre-raster operations unit ("PROP") 2704, a raster engine 2708, a work distribution crossbar switch ("WDX") 2716, a memory management unit ("MMU") 2718, one or more data processing clusters ("DPCs") 2706, and any suitable combination of components.

[0327] In at least one embodiment, operation of GPC 2700 is controlled by a pipeline manager 2702. In at least one embodiment, pipeline manager 2702 manages configuration of one or more DPCs 2706 to process tasks distributed to GPC 2700. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to implement at least part of a graphics rendering pipeline. In at least one embodiment, DPC 2706 is configured to execute vertex shader programs on programmable streaming multi-processors (“SMs”) 2714. In at least one embodiment, pipeline manager 2702 is configured to route packets received from a work distribution unit to appropriate logical units within GPC 2700, and in at least one embodiment, can route some packets to fixed function hardware units in PROP 2704 and / or raster engine 2708, while routing other packets to DPCs 2706 for processing by workgroups of RAs 2712 or SMs 2714. In at least one embodiment, pipeline manager 2702 configures at least one of DPCs 2706 to implement a neural network model and / or compute pipeline.

[0328] In at least one embodiment, PROP unit 2704 is configured to route data generated by raster engine 2708 and DPCs 2706 to a raster operations (“ROP”) unit in a partition unit 2622, in at least one embodiment, in accordance with techniques described above in reference to FIG. 26. Figure 26 In more detail, in at least one embodiment, PROP unit 2704 is configured to perform optimizations for color blending, organize pixel data, perform address translations, and so forth. In at least one embodiment, raster engine 2708 includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, and in at least one embodiment, includes, without limitation, a setup engine, a coarse raster engine, a cull engine, a clip engine, a fine raster engine, a tile aggregation engine, and any suitable combinations thereof. In at least one embodiment, the setup engine receives transformed vertices and generates a plane equation associated with a geometric primitive defined by the vertices; the plane equation is communicated to the coarse raster engine to generate coverage information (e.g., x, y coverage masks for tiles) of the primitive; output of the coarse raster engine is communicated to the cull engine where fragments associated with primitives that fail a z-test are culled, and to the clip engine where fragments that are outside a viewing frustum are clipped. In at least one embodiment, clipped and culled fragments are passed to the fine raster engine to generate attributes of pixel fragments based on the plane equation generated by the setup engine. In at least one embodiment, output of raster engine 2708 includes fragments that are to be processed by any suitable entity, such as by a fragment shader implemented within DPC 2706.

[0329] In at least one embodiment, each DPC 2706 included in a GPC 2700 includes, but is not limited to, an M-pipeline controller ("MPC") 2710; a primitive engine 2712; one or more SMs 2714; and any suitable combination thereof. In at least one embodiment, the MPC 2710 controls the operation of the DPC 2706, routing packets received from the pipeline manager 2702 to appropriate units within the DPC 2706. In at least one embodiment, packets associated with vertices are routed to the primitive engine 2712, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to the SM 2714.

[0330] In at least one embodiment, SM 2714 includes, but is not limited to, a programmable streaming processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2714 is multithreaded and configured to simultaneously execute multiple threads (e.g., 32 threads) from a particular thread group, and implements a single instruction, multiple data ("SIMD") architecture, in which each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instructions. In at least one embodiment, SM 2714 implements a single instruction, multiple thread ("SIMT") architecture, in which each thread in a group of threads is configured to process a different set of data based on the same instructions, but in which individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby enabling concurrency between warps and serial execution within a warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within a warp and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instruction can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 2714 is described in more detail below.

[0331] In at least one embodiment, the MMU 2718 provides a communication channel between the GPC 2700 and the memory partition unit (e.g., Figure 26 The MMU 2718 provides an interface between the memory and the partition unit 2622, and provides virtual to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2718 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0332] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5L and 5M. Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5L and 5M. In at least one embodiment, deep learning application processor is used to train machine learning models, such as neural networks, to predict or infer information provided to GPC 2700. In at least one embodiment, GPC 2700 is used to infer or predict information based on a machine learning model (e.g., neural network) that has been trained by another processor or system or GPC 2700. In at least one embodiment, GPC 2700 can be used to perform one or more neural network use cases described herein.

[0333] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0334] Figure 28 A memory partition unit 2800 of a parallel processing unit (“PPU”) is shown in accordance with at least one embodiment. In at least one embodiment, memory partition unit 2800 includes, without limitation, a raster operations (“ROP”) unit 2802; a level two (“L2”) cache 2804; a memory interface 2806; and any suitable combination thereof. In at least one embodiment, memory interface 2806 is coupled to a memory. In at least one embodiment, memory interface 2806 can implement a 32-, 64-, 128-, 1024-bit data bus, or similar implementation for high-speed data transfer. In at least one embodiment, PPU includes U memory interfaces 2806, one for each pair of partition units 2800, with each pair of partition units 2800 connected to a corresponding memory device. For example, in at least one embodiment, PPU can be connected to up to Y memory devices, such as a high bandwidth memory stack or graphics double data rate version 5 synchronous dynamic random access memory (“GDDR5 SDRAM”).

[0335] In at least one embodiment, memory interface 2806 implements a High Bandwidth Memory Second Generation (“HBM2”) memory interface, and Y is equal to half of U. In at least one embodiment, HBM2 memory stacks are located on same physical package as PPU, which can provide substantial power savings and area compared to a traditional GDDR5 SDRAM system. In at least one embodiment, each HBM2 stack includes, without limitation, four memory dies, and Y is equal to 4, each HBM2 stack includes two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, memory supports Single Error Correction Double Error Detection (“SECDED”) error correction code (“ECC”) to protect data. In at least one embodiment, ECC can provide higher reliability for compute applications that are sensitive to data corruption.

[0336] In at least one embodiment, PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit 2800 supports a unified memory to provide a single unified virtual address space for central processing unit (“CPU”) and PPU memory, enabling data sharing between functional units located on other processors. In at least one embodiment, frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to physical memory of PPU that accesses pages more frequently. In at least one embodiment, high-speed GPU interconnect 2608 supports address translation services, which allow PPU to directly access CPU pages and provide full access to CPU memory by PPU.

[0337] In at least one embodiment, a copy engine transfers data between multiple PPU or between a PPU and a CPU. In at least one embodiment, copy engine can generate a page fault for an address that is not mapped into a page table, and memory partition unit 2800 then services the page fault by mapping an address into a page table before copy engine performs a transfer. In at least one embodiment, a fixed (i.e., non-paged) amount of memory is operated for multiple copy engines between multiple processors, which substantially reduces amount of available memory. In at least one embodiment, in case of a hardware page fault, an address can be passed to copy engine without considering whether a memory page is resident, and copy process is transparent.

[0338] According to at least one embodiment, data from Figure 26Data from memory 2604 or other system memory is retrieved by the memory partition unit 2800 and stored in the L2 cache 2804, which is located on-chip and shared between the various GPCs. In at least one embodiment, each memory partition unit 2800 includes, but is not limited to, at least a portion of the L2 cache associated with the corresponding memory device. In at least one embodiment, lower-level caches are implemented in various units within the GPC. In at least one embodiment, each SM 2714 may implement a level 1 ("L1") cache, where the L1 cache is private memory dedicated to a particular SM 2714, and data is retrieved from the L2 cache 2804 and stored in each L1 cache for processing within the functional units of the SM 2714. In at least one embodiment, the L2 cache 2804 is coupled to the memory interface 2806 and the XBar 2620.

[0339] In at least one embodiment, ROP unit 2802 performs graphics raster operations related to pixel color, such as color compression, pixel blending, and the like. In at least one embodiment, ROP unit 2802 performs depth testing in conjunction with raster engine 2708, receiving the depth of a sample location associated with a pixel fragment from the culling engine of raster engine 2708. In at least one embodiment, the depth is tested against the corresponding depth in the depth buffer associated with the sample location of the fragment. In at least one embodiment, if the fragment passes the depth test for the sample location, ROP unit 2802 updates the depth buffer and sends the result of the depth test to raster engine 2708. It will be appreciated that the number of partition units 2800 can differ from the number of GPCs, and therefore, in at least one embodiment, each ROP unit 2802 can be coupled to each of the GPCs. In at least one embodiment, ROP unit 2802 tracks packets received from different GPCs and determines whether the results generated by ROP unit 2802 should be routed through XBar 2620.

[0340] Figure 29 Streaming Multiprocessor ("SM") 2900 is shown in accordance with at least one embodiment. In at least one embodiment, SM 2900 is Figure 27SM 2714. In at least one embodiment, SM 2900 includes, without limitation, an instruction cache 2902; one or more scheduler units 2904; a register file 2908; one or more processing cores (“cores”) 2910; one or more special-function units (“SFUs”) 2912; one or more load / store units (“LSUs”) 2914; an interconnect network 2916; shared memory / level-one (“LI”) cache 2918; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on general processing clusters (“GPCs”) of parallel processing units (“PPUs”) and each task is assigned a specific data processing cluster (“DPC”) within a GPC and, if task is associated with a shader program, to one of SMs 2900. In at least one embodiment, scheduler units 2904 receive tasks from work distribution unit and manage dispatch of instructions to one or more thread blocks for execution on SM 2900. In at least one embodiment, scheduler units 2904 schedule thread blocks to be executed to be dispatched as thread warps of parallel threads, with each thread block allocated at least one thread warp. In at least one embodiment, each thread warp executes a thread. In at least one embodiment, scheduler units 2904 manage a plurality of different thread blocks, allocating thread warps of an instruction to different thread blocks, and then dispatching instructions from a plurality of different cooperating groups to various functional units (e.g., processing cores 2910, SFUs 2912, and LSUs 2914) during each clock cycle.

[0341] In at least one embodiment, a cooperative group can refer to a programming model for organizing groups of communication threads that allows developers to express the granularity at which threads are communicating, enabling richer, more efficient parallel decomposition. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, an application of a conventional programming model provides a single, simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, a programmer can define thread groups at less than a thread block granularity and synchronize within defined groups to achieve higher performance, design flexibility, and software reuse in the form of collective group-wide function interfaces. In at least one embodiment, a cooperative group enables a programmer to explicitly define thread groups at sub-block (i.e., down to a single thread) and multi-block granularity and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, this programming model supports clean composition across software boundaries, such that library and utility functions can safely synchronize in their local environment without having to make assumptions about convergence. In at least one embodiment, a cooperative group primitive enables new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization across a grid of thread blocks.

[0342] In at least one embodiment, a dispatch unit 2906 is configured to send instructions to one or more of the functional units, and a scheduler unit 2904 includes, without limitation, two dispatch units 2906 that enable two different instructions from a common warp to be dispatched in each clock cycle. In at least one embodiment, each scheduler unit 2904 includes a single dispatch unit 2906 or an additional dispatch unit 2906.

[0343] In at least one embodiment, each SM 2900 includes, without limitation, a register file 2908 that provides a set of registers for functional units of the SM 2900. In at least one embodiment, register file 2908 is split between functional units as is needed to facilitate effective code fetch and register communication. In at least one embodiment, register file 2908 is partitioned between different thread blocks executed by the SM 2900, and register file 2908 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM 2900 includes, without limitation, a plurality L of processing cores 2910, where L is a positive integer. In at least one embodiment, SM 2900 comprises, without limitation, a large number (e.g., 128 or more) of distinct processing cores 2910. In at least one embodiment, each processing core 2910 includes, without limitation, a fully-pipelined, single-precision, double-precision, and / or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores 2910 include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores.

[0344] In at least one embodiment, one or more tensor cores are included in processing cores 2910. In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for use in neural network training and inferencing. In at least one embodiment, each tensor core operates on 4x4 matrices and performs matrix multiplication and accumulation operations D = A x B + C, where A, B, C, and D are 4x4 matrices.

[0345] In at least one embodiment, matrix multiplication inputs A and B are 16-bit floating point matrices, and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, a tensor core performs 32-bit floating point accumulation operations on 16-bit floating point input data. In at least one embodiment, 16-bit floating point multiplication uses 64 operations and results in a full precision product, which is then accumulated with other intermediate products using 32-bit floating point addition for 4x4x4 matrix multiplication. In at least one embodiment, tensor cores are used to perform larger two-dimensional or higher dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API such as CUDA 9 C++ API exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at CUDA level, a warp level interface assumes a 16x16 size matrix across all 32 warp threads.

[0346] In at least one embodiment, each SM 2900 includes, without limitation, M SFUs 2912 to perform special functions (e.g., certain math functions, exponentials, logarithms, etc.). In at least one embodiment, SFUs 2912 include, without limitation, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs 2912 include, without limitation, texture units configured to perform texture mapping operations. In at least one embodiment, texture units are configured to load a texture map (e.g., a 2D array of texture pixels) from memory and sample the texture map to produce sampled texture values for use by a shader program executed by SM 2900. In at least one embodiment, texture maps are stored in shared memory / L1 cache 2918. In at least one embodiment, texture units use mip-maps (e.g., different levels of detail for a texture map) to perform texture operations such as filtering operations according to at least one embodiment. In at least one embodiment, each SM 2900 includes, without limitation, two texture units.

[0347] In at least one embodiment, each SM 2900 includes, without limitation, N LSUs 2914 that implement load and store operations between shared memory / L1 cache 2918 and register file 2908. In at least one embodiment, each SM 2900 includes, without limitation, interconnect network 2916 that connects each of the functional units to register file 2908, and LSU 2914 to register file 2908 and shared memory / L1 cache 2918. In at least one embodiment, interconnect network 2916 is a cross-bar switch that can be configured to connect any function unit to any register file, as well as connect LSUs 2914 to registers files 2908 and memory locations in shared memory / L1 cache 2918.

[0348] In at least one embodiment, shared memory / L1 cache 2918 is an array of on-chip memory that, in at least one embodiment, allows SM 2900 to store data used by a thread before the data is consumed by the thread. In at least one embodiment, shared memory / L1 cache 2918 includes, without limitation, 128 KB of storage space to a path from SM 2900 to partition units. In at least one embodiment, shared memory / L1 cache 2918 is used for cache reads and writes, in at least one embodiment. In at least one embodiment, one or more of shared memory / L1 cache 2918, L2 cache, and memory are backing stores.

[0349] In at least one embodiment, combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses. In at least one embodiment, capacity is used by programs that do not use shared memory or used as a cache, e.g., if shared memory is configured to use half of capacity, and textures and load / store operations can use remaining capacity. According to at least one embodiment, integration within shared memory / L1 cache 2918 enables shared memory / L1 cache 2918 to be used as a high-throughput pipeline for streaming data while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared to graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, creating a more straightforward programming model. In at least one embodiment, in a general purpose parallel computation configuration, work distribution unit allocates and distributes blocks of threads directly to DPCs. In at least one embodiment, threads in a block execute the same program, use a unique thread ID in a computation to ensure that each thread generates a unique result, use SM 2900 to execute the program and perform the computation, use shared memory / L1 cache 2918 to communicate between threads, and use LSUs 2914 to read and write to global memory through shared memory / L1 cache 2918 and memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM 2900 writes to scheduler unit 2904 commands that can be used to launch new work on DPCs.

[0350] In at least one embodiment, PPU is included in a desktop computer, laptop computer, tablet computer, server computer, supercomputer, smart- phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), digital camera, vehicle, head mounted display, hand-held electronic device, etc. or is coupled to such devices. In at least one embodiment, PPU is implemented on a single semiconductor

[0351] In at least one embodiment, PPU can be included on a graphics card that includes one or more memory devices. In at least one embodiment, graphics card can be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU can be an integrated graphics processing unit (“iGPU”) included in a chipset of a motherboard.

[0352] Inference and / or training logic 515 are used to perform inferencing and / or training operations associated with one or more embodiments. Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and / or 5B. In various embodiments, elements of inference and / or training logic 515 can be used with or Figure 5A and / or Figure 5B Details regarding inference and / or training logic 515 are provided below in conjunction with FIGs. 5 A and / or 5B. In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to SM 2900. In at least one embodiment, SM 2900 is used to infer or predict information based on a machine learning model (e.g., neural network) that has been trained by another processor or system or by SM 2900. In at least one embodiment, SM 2900 can be used to perform one or more neural network use cases described herein.

[0353] In at least one embodiment, such components can be used to manage communication links connecting processing devices. In at least one embodiment, this can include determining frequency states and power states of communication links between processors.

[0354] In at least one embodiment, a single semiconductor platform can refer to a sole unitary integrated circuit or chipset that can contain one or more processing units (e.g., CPUs, GPU, digital signal processors (DSPs), etc.). In at least one embodiment, multiple semiconductor platforms can be used to implement a single computing device, e.g., the platforms can be symmetric multi-processing (SMP) platforms. In at least one embodiment, a single semiconductor platform can be used to implement a plurality of computing devices, e.g., the platform can be a single processing unit used to implement multiple computing devices.

[0355] In at least one embodiment, computer programs in the form of executable code or computer control logic algorithms in the form of machine-readable executable code are stored in main memory 904 and / or secondary storage. In at least one embodiment, if executed by one or more processors, the computer programs enable system 900 to perform various functions. In at least one embodiment, memory 904, storage, and / or any other storage is a possible example of computer-readable media. In at least one embodiment, secondary storage can refer to any suitable storage device or system for storing data, e.g., hard disk drives and / or removable storage drives, representing a floppy disk drive, a magnetic tape drive, an optical disk drive, a digital versatile disk (“DVD”) drive, a recording device, a universal serial bus (“USB”) flash memory, etc. In at least one embodiment, the architecture and / or functionality of various previous figures are implemented in the environment of CPU 902; parallel processing system 912; an integrated circuit that can have at least portions of the capabilities of both CPU 902; parallel processing system 912; a chipset (e.g., a group of integrated circuits designed to work together as a unit and sold as a unit, etc.); and any appropriate combination thereof.

[0356] In at least one embodiment, the architecture and / or functionality of the various previous figures is implemented in the environment of a general purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, an application-specific system, etc. In at least one embodiment, computer system 900 can take any of a myriad of forms in a desktop, laptop, tablet, server, supercomputer, smartphone (e.g., wireless, hand-held device), personal digital assistant (“PDA”), digital camera, vehicle, head mounted display, hand-held electronic device, mobile telephone device, television, workstation, game console, embedded system, and / or any other type of logic.

[0357] In at least one embodiment, parallel processing system 912 includes, without limitation, a plurality of parallel processing units (“PPUs”) 914 and associated memory 916. In at least one embodiment, PPUs 914 are connected to a host processor or other peripheral device via an interconnect 918 and switch 920 or multiplexer. In at least one embodiment, parallel processing system 912 allocates computational tasks to PPUs 914 that can be parallelized, e.g., as part of a distribution of computational tasks across a plurality of graphics processing unit (“GPU”) thread blocks. In at least one embodiment, memory is shared and accessed among some or all of PPUs 914 (e.g., for read and / or write access), although such shared memory can incur a performance penalty relative to using local memory and registers resident on PPUs 914. In at least one embodiment, operations of PPUs 914 are synchronized by use of commands such as __syncthreads(), where all threads in a block (e.g., executing across multiple PPUs 914) reach a certain code execution point before proceeding.

[0358] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in the appended claims.

[0359] Unless otherwise indicated or contradicted by context, the use of the terms "a" and "one" and "the" and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated or contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (meaning "including, but not limited to") unless otherwise noted or contradicted by context. The term "connected" (when used without modification) is to be construed as partly or wholly encompassed, attached to, or joined together, even if there are some intervening items. Unless otherwise indicated herein, a reference to a range of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, and each separate value is incorporated in the specification as if it were individually recited herein. Unless otherwise indicated or contradicted by context, the use of the term "set" (e.g., "set of items") or "subset" is to be construed as a non-empty set of one or more members. Also, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily denote a proper subset of the corresponding set, but rather the subset and the corresponding set can be equal.

[0360] Unless explicitly indicated otherwise or contradicted by context, conjunction language such as phrases in the form "at least one of A, B, and C" or "at least one of A, B, and C" is to be construed in context as generally used to mean that the item, clause, etc. can be A or B or C, or any non-empty subset of the set of A and B and C. For example, in the illustrative example of a set having three members, the conjunction phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunction language is not generally intended to imply that certain embodiments require the existence of at least one of A, at least one of B, and at least one of C. Additionally, unless otherwise indicated or contradicted by context, the term "plurality" denotes a plural state (e.g., "a plurality of items" denotes multiple items). The plurality is at least two items, but can be more if explicitly indicated or indicated by context. Furthermore, unless otherwise indicated or clear from context, the phrase "based on" means "based at least in part on" rather than "based only on."

[0361] The operations of a process described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process, such as those described herein (or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with executable instructions to perform the operations of the process, and the process is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) that is collectively executed by, for example, a hardware or combination of hardware and / or software. In at least one embodiment, the code is stored on a computer-readable storage medium, such as a computer program stored on a computer-readable storage medium, which includes instructions that are executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues). In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media (or other memory for storing executable instructions) having stored thereon executable instructions that, as a result of being executed by one or more processors of a computer system (i.e., as a result of being executed), cause the computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes multiple non-transitory computer-readable storage media, and one or more of the individual non-transitory storage media of the multiple non-transitory computer-readable storage media lack all of the code, with the multiple non-transitory computer-readable storage media collectively storing the entire code. In at least one embodiment, executable instructions are executed to cause different instructions to be executed by different processors, e.g., a non-transitory computer-readable storage medium stores instructions and a main central processing unit (“CPU”) executes some instructions, while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of the instructions.

[0362] Accordingly, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform operations of processes described herein, and such a computer system is configured with applicable hardware and / or software to enable implementation of the operations. Moreover, a computer system implementing at least one embodiment of the present disclosure is a single device, and in another embodiment is a distributed computer system including multiple devices operating in different manners such that the distributed computer system performs operations described herein and such that a single device does not perform all of the operations.

[0363] The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0364] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0365] In the description and claims, the terms "coupled" and "connected," along with derivatives thereof, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" or "coupled" can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0366] Unless specifically stated otherwise, it can be appreciated that throughout the specification terms such as "processing," "computing," "calculating," "determining," or the like, refer to the action and / or processes of a computer or computing system, or similar electronic

[0367] In a similar manner, the term "processor" can refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" can be a CPU or GPU. A "computing platform" can include one or more processors. As used herein, a "software" process can include, for example, software and / or hardware entities such as tasks, threads, and intelligent agents that perform work over time. Likewise, each process can refer to multiple processes to sequentially or concurrently execute instructions, either continuously or intermittently. The terms "system" and "method" can be used interchangeably herein so long as a system can embody one or more methods and a method can be considered a system.

[0368] In this document, reference may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, a computer system, or a computer-implemented machine. Obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways, such as by receiving data as parameters of a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transmitting data from a providing entity to an acquiring entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, the process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transmitting data as input or output parameters of a function call, an application programming interface, or an interprocess communication mechanism.

[0369] Although the above discussion sets forth example implementations of the described technology, other architectures may be used to implement the described functionality and are intended to fall within the scope of this disclosure. In addition, although specific responsibilities are defined above for discussion purposes, the various functions and responsibilities may be allocated and divided in different ways depending on the circumstances.

[0370] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A system comprising: At least three processors, wherein the at least three processors are configured to use one or more neural networks to predict traffic on one or more interconnects and cause bandwidth of the one or more interconnects to be adjusted based at least in part on previous traffic associated with the one or more interconnects. 2 . The system of claim 1 , wherein the at least three processors comprise a graphics processing unit (GPU).

3. The system of claim 1 , wherein the bandwidth of the one or more interconnects is further adjusted by the at least three processors based at least in part on a performance metric, the performance metric comprising instruction throughput, transfer frequency, byte throughput, data switching pattern, operating frequency, operating voltage, memory bandwidth, streaming multiprocessor (SM) utilization, cache hit rate, or power value.

4. The system of claim 1 , wherein the one or more neural networks are trained using graphics processing unit frequency information. 5 . The system of claim 1 , wherein the adjusting comprises one or more adjustments to an operating frequency of one or more graphics processing units and temporarily applying turbo boost or selecting a different frequency state.

6. The system of claim 1 , wherein the adjustments include one or more dynamic voltage and frequency scaling (DVFS) adjustments determined using a binary algorithm or one or more other neural networks.

7. A method comprising: One or more neural networks are used to predict traffic on one or more interconnects and to cause bandwidth of the one or more interconnects to be adjusted based at least in part on previous traffic associated with the one or more interconnects.

8. The method of claim 7, wherein the method comprises using at least three processors, the at least three processors comprising a Graphics Processing Unit (GPU).

9. The method according to claim 8, further comprising: Information regarding expected performance of the one or more processors is received through an application interface.

10. The method of claim 7, wherein the bandwidth of the one or more interconnects is further adjusted by the at least three processors based at least in part on a performance metric, the performance metric comprising instruction throughput, transfer frequency, byte throughput, data switching pattern, operating frequency, operating voltage, memory bandwidth, streaming multiprocessor (SM) utilization, cache hit rate, or power value.

11. The method according to claim 7, further comprising: Adjust the operating frequency of one or more processors by temporarily applying turbo boost or selecting a different frequency state.

12. The method of claim 7, wherein adjusting comprises one or more dynamic voltage and frequency scaling (DVFS) adjustments determined using a binary algorithm or one or more other neural networks.

13. A non-transitory machine-readable storage medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: One or more neural networks are used to predict traffic on one or more interconnects and to cause bandwidth of the one or more interconnects to be adjusted based at least in part on previous traffic associated with the one or more interconnects.

14. The non-transitory machine-readable storage medium of claim 13, wherein the one or more processors comprise a graphics processing unit (GPU).

15. The non-transitory machine-readable storage medium of claim 13, further comprising: Information regarding expected performance of the one or more processors is received through an application interface.

16. The non-transitory machine-readable storage medium of claim 13, wherein adjusting comprises adjusting the one or more performance metrics, the one or more performance metrics comprising instruction throughput, transfer frequency, byte throughput, data switching pattern, operating frequency, operating voltage, memory bandwidth, streaming multiprocessor (SM) utilization, cache hit rate, or power value.

17. The non-transitory machine-readable storage medium of claim 13, wherein the instructions, when executed, further cause the one or more processors to: The operating frequency of one or more graphics processing units is adjusted by temporarily applying turbo boost or selecting a different frequency state.

18. The non-transitory machine-readable storage medium of claim 13, wherein the adjustments include one or more dynamic voltage and frequency scaling (DVFS) adjustments determined using a binary algorithm or one or more other neural networks.

19. A processor comprising: One or more circuits for using one or more neural networks to predict traffic on one or more interconnects and causing bandwidth of the one or more interconnects to be adjusted based at least in part on previous traffic associated with the one or more interconnects.

20. The processor of claim 19, wherein the processor comprises a graphics processing unit (GPU).

21. The processor of claim 19, further comprising one or more ALUs for receiving as input information regarding expected performance for use in determining the adjustments to be made to the operating frequency of the one or more processors.

22. The processor of claim 19, wherein adjusting comprises adjusting the one or more performance metrics, the one or more performance metrics comprising instruction throughput, transfer frequency, byte throughput, data switching pattern, operating frequency, operating voltage, memory bandwidth, streaming multiprocessor (SM) utilization, cache hit rate, or power value.

23. The processor of claim 19, wherein adjusting comprises applying turbo boost, selecting a different frequency state, or adjusting one or more dynamic voltage and frequency scaling (DVFS) values.

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