Artificial intelligence accelerator and data processing method thereof

Abstract

The application provides an artificial intelligence accelerator and a data processing method thereof, the accelerator comprising: a storage unit for storing a target learning rate, the target learning rate being parameter information of target neural network model training; the computing capacitor circuit is used for reading the target learning rate from the storage unit, receiving an externally input target residual value and a target input value, and outputting a target analog voltage based on the target learning rate, the target residual value and the target input value; an analog-to-digital conversion unit is used for receiving the target analog voltage output by the computing capacitor circuit and converting the target analog voltage into a target digital voltage for network weight parameter updating of the target neural network model training. The artificial intelligence accelerator of the application realizes that the artificial intelligence accelerator supports low-power consumption training calculation function, avoids reasoning calculation errors caused by sensor aging, and ensures the accuracy of reasoning calculation.

Description

Technical Field

[0001] This invention relates to the field of information processing technology, and in particular to an artificial intelligence accelerator and its data processing method. Background Technology

[0002] Currently, classic artificial intelligence applications are achieved by utilizing sensors and AI accelerators.

[0003] However, in practical applications, sensors are prone to aging, and existing AI accelerators lack training computation capabilities. Therefore, over time, this will inevitably lead to a mismatch between the AI ​​accelerator and the sensor, resulting in inference errors. To avoid these technical shortcomings, AI accelerators need to also support training computation capabilities.

[0004] Therefore, how to better realize AI accelerators that support training computation has become an urgent problem to be solved in the industry. Summary of the Invention

[0005] This invention provides an artificial intelligence accelerator and its data processing method, which can better realize the artificial intelligence accelerator that supports training computing functions.

[0006] This invention provides an artificial intelligence accelerator, comprising:

[0007] A storage unit is used to store the target learning rate, which is the parameter information for training the target neural network model;

[0008] The computational capacitor circuit is used to read the target learning rate from the storage unit and receive the target residual value and target input value from external input.

[0009] Based on the target learning rate, the target residual value, and the target input value, a target simulated voltage is output, wherein the target residual value is determined based on the residual information of the current layer during the backpropagation process of the target neural network model training, the target input value is determined based on the input information of the forward propagation process of the target neural network model training, and the target simulated voltage is a voltage analog quantity of the weight change information during the training of the target neural network model;

[0010] An analog-to-digital converter is used to receive the target analog voltage output by the computational capacitor circuit and convert the target analog voltage into a target digital voltage for the target neural network model training to update network weight parameters.

[0011] According to an embodiment of the present invention, an artificial intelligence accelerator is provided, wherein the computational capacitor circuit is further used for:

[0012] The target learning rate, the target residual value, and the target input value are multiplied by analog signals to calculate the target analog voltage.

[0013] According to an embodiment of the present invention, an artificial intelligence accelerator is provided, wherein the computational capacitor circuit is further used for:

[0014] The target analog product is obtained by multiplying the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value.

[0015] The target simulated voltage is obtained by multiplying the target simulated product with the preset unit voltage.

[0016] According to an embodiment of the present invention, an artificial intelligence accelerator is provided, wherein the storage unit includes an 8-tube static random access memory (SRAM).

[0017] According to an embodiment of the present invention, an artificial intelligence accelerator is provided in which the analog signal multiplication calculation is implemented through charge sharing.

[0018] This invention also provides a data processing method for an artificial intelligence accelerator as described in any of the above embodiments, comprising:

[0019] The computational capacitor circuit reads the target learning rate from the storage unit and receives the target residual value and target input value from external input.

[0020] The computational capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value. The target learning rate is the parameter information for training the target neural network model. The target residual value is determined based on the residual information of the current layer during the backpropagation process of training the target neural network model. The target input value is determined based on the input information during the forward propagation process of training the target neural network model. The target analog voltage is the voltage analog quantity of the weight change information during training the target neural network model.

[0021] The analog-to-digital conversion unit receives the target analog voltage output by the computational capacitor circuit and converts the target analog voltage into a target digital voltage for the target neural network model training to update network weight parameters.

[0022] According to an embodiment of the present invention, a data processing method is provided, wherein the calculation capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value, comprising:

[0023] The computational capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value, and outputs the target analog voltage.

[0024] According to an embodiment of the present invention, a data processing method is provided in which the calculation capacitor circuit performs analog signal multiplication calculation on the target learning rate, the target residual value, and the target input value, and outputs the target analog voltage, including:

[0025] The computational capacitor circuit calculates the product of the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value to obtain the target analog product;

[0026] The calculation capacitor circuit calculates the product of the target analog product and the preset unit voltage to obtain the target analog voltage.

[0027] According to an embodiment of the present invention, a data processing method is provided in which the calculation capacitor circuit performs analog signal multiplication calculation on the target learning rate, the target residual value, and the target input value, and outputs the target analog voltage, including:

[0028] The computational capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value based on charge sharing, and outputs the target analog voltage.

[0029] This invention provides an artificial intelligence accelerator and its data processing method. The accelerator stores the training parameters of the target neural network model, i.e., the target learning rate, in a storage unit. A computational capacitor circuit can read the target learning rate from the storage unit. The computational capacitor circuit receives the target residual value and the target input value from external input, and then calculates the target learning rate, target residual value, and target input value, as well as the target analog voltage. The analog voltage is then converted into a digital signal representing the weight changes during the training of the target neural network model through an analog-to-digital converter. This enables the artificial intelligence accelerator to support low-power training computation, and can be applied to in-memory computing architectures. Furthermore, when sensors age, activating the training computation function of the artificial intelligence accelerator allows for re-matching between the accelerator and the aging sensor, avoiding inference computation errors caused by sensor aging in existing technologies and ensuring the accuracy of inference computation. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the structure of the artificial intelligence accelerator provided in an embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram of the training data stream of the artificial intelligence accelerator provided in an embodiment of the present invention;

[0033] Figure 3 This is a circuit diagram of the storage unit in the artificial intelligence accelerator provided in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the computational capacitor circuit in the artificial intelligence accelerator provided in this embodiment of the invention;

[0035] Figure 5 This is a waveform timing diagram of the artificial intelligence accelerator performing training calculations according to an embodiment of the present invention;

[0036] Figure 6 This is a flowchart illustrating the data processing method provided in an embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0038] The following is combined with Figures 1-6 This invention describes an artificial intelligence accelerator and its data processing method.

[0039] It should be noted that the inference computing function supported by the in-memory computing AI accelerator is not complete. Therefore, this invention provides an AI accelerator and its data processing method to solve the above-mentioned technical defects.

[0040] Figure 1 This is a schematic diagram of the structure of the artificial intelligence accelerator provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the artificial intelligence accelerator includes: a storage unit 101, a computing capacitor circuit 102, and an analog-to-digital conversion unit 103.

[0041] Storage unit 101 is used to store the target learning rate, which is the parameter information for training the target neural network model;

[0042] Specifically, the target neural network described in the embodiments of the present invention can be a backpropagation (BP) neural network or a convolutional neural network (CNN) in deep learning, etc., and is not specifically limited in the embodiments of the present invention.

[0043] The target learning rate described in this embodiment of the invention is the parameter information for training the target neural network model. It can be a value randomly generated by the system or a value manually set by the user. Generally, the value range is 0 to 1.

[0044] In embodiments of the present invention, the storage unit has a read-write separation function, which can achieve better read-write performance.

[0045] The calculation capacitor circuit 102 is used to read the target learning rate from the storage unit 101 and receive the target residual value and target input value from external input;

[0046] Based on the target learning rate, the target residual value, and the target input value, a target simulated voltage is output, wherein the target residual value is determined based on the residual information of the current layer during the backpropagation process of the target neural network model training, the target input value is determined based on the input information of the forward propagation process of the target neural network model training, and the target simulated voltage is a voltage analog quantity of the weight change information during the training of the target neural network model;

[0047] Specifically, in an embodiment of the present invention, the calculation capacitor circuit 102 is connected to the storage unit 101. Therefore, after the storage unit 101 receives the target learning rate written externally and stores the target learning rate, the calculation capacitor circuit 102 can read the target learning rate from the storage unit 101.

[0048] The target input value described in this embodiment of the invention is determined based on the input information of the feature map during the forward propagation process of the target neural network model training, that is, the input value of the training sample information during the forward propagation process, which is an externally input digital signal.

[0049] The target residual value described in this embodiment of the invention is determined based on the residual information of the current layer during the backpropagation process of the target neural network model training. Specifically, it is the output value obtained during the forward propagation process. The output value and the actual value are substituted into the loss function of the target neural network to calculate the residual information, which is also an externally input digital signal.

[0050] The target simulated voltage described in this embodiment of the invention is a voltage analog quantity representing the weight change information during the training of the target neural network model. Specifically, it can be used to update the network weight parameters during the training of the target neural network model.

[0051] In an embodiment of the present invention, based on the BP algorithm, the weight change information of the target neural network model training can be determined according to the target learning rate, the target residual value, and the target input value.

[0052] Furthermore, the calculation capacitor circuit reads the target learning rate from the storage unit and receives the target residual value and target input value from the external input. It converts the target learning rate, target residual value, and target input value into corresponding analog signals, and then performs training calculations on the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the model signal corresponding to the target input value, and outputs the target analog voltage.

[0053] The analog-to-digital conversion unit 103 is used to receive the target analog voltage output by the computing capacitor circuit 102 and convert the target analog voltage into a target digital voltage for the target neural network model training to update the network weight parameters.

[0054] Specifically, in an embodiment of the present invention, the analog-to-digital conversion unit 103 is an analog-to-digital conversion circuit, which is connected to the computing capacitor circuit 102 and is used to receive the target analog voltage output by the computing capacitor circuit 102 and convert the target analog voltage into a target digital voltage.

[0055] In an embodiment of the present invention, the target digital voltage is a digital signal of the weight change amount during the training of the target neural network model. It can be understood that after the analog-to-digital conversion unit converts the target analog voltage into the target digital voltage, the target digital voltage can be used by external software to perform network weight parameter update calculations during the training process of the target neural network model, thereby realizing the function of supporting training calculation.

[0056] Preferably, Figure 2 This is a schematic diagram of the training data stream of the artificial intelligence accelerator provided in an embodiment of the present invention, such as... Figure 2 As shown in the embodiment of the invention, the target learning rate can be represented by η, which is a 4-bit digital signal stored in the memory unit; the target input value can be represented by IN, which is the input information of the forward propagation process, a 2-bit digital signal, and belongs to the off-chip input; the target residual value can be represented by σ, which is the residual information of the current layer during the backward propagation process, a 1-bit digital signal, and belongs to the off-chip input. The three digital signals are input to the computational capacitor circuit, which converts the three digital signals into analog signals for analog multiplication calculation, outputting the target analog voltage, thus obtaining a 6-bit analog signal.

[0057] Furthermore, the 6-bit analog signal is input into the analog-to-digital converter (ADC), and the ADC outputs the target digital voltage, thus obtaining a 6-bit digital signal.

[0058] In other embodiments of the present invention, the target learning rate may also be a digital signal such as 3-bit or 5-bit. Correspondingly, the number of bits of the target input value and the target residual value may also be other values, which are not specifically limited in the embodiments of this application.

[0059] Therefore, the artificial intelligence accelerator in this embodiment of the invention can support the calculation of weight information changes during neural network model training, and can be applied to in-memory computing architecture, enabling the in-memory computing chip to support on-chip training functionality.

[0060] In an embodiment of the present invention, applied to a real-world artificial intelligence application scenario, when sensor aging is detected, the training and computation function of the artificial intelligence accelerator can be activated. By analyzing the results of the training and computation, the artificial intelligence accelerator can be re-matched with the aging sensor, thus avoiding inference and computation errors caused by sensor aging in the prior art.

[0061] The artificial intelligence accelerator provided in this invention stores the parameter information of the target neural network model training, i.e., the target learning rate, in a storage unit. A computational capacitor circuit can read the target learning rate from the storage unit. The computational capacitor circuit receives the target residual value and the target input value from the external input, and then calculates the target learning rate, the target residual value, and the target input value, as well as the target analog voltage. The analog voltage is then converted into a digital signal that represents the weight change information of the target neural network model training through an analog-to-digital conversion unit. This enables the artificial intelligence accelerator to support low-power training computation functions and can be applied to in-memory computing architectures. At the same time, when the sensor ages, by activating the training computation function of the artificial intelligence accelerator, the artificial intelligence accelerator can be re-matched with the aging sensor, avoiding inference computation errors caused by sensor aging in the prior art and ensuring the accuracy of inference computation.

[0062] Optionally, the storage unit includes an 8-tube static random access memory (SRAM).

[0063] Specifically, in embodiments of the present invention, the storage unit may include an 8-transistor (8T) static random-access memory (SRAM). To facilitate the calculation of the capacitor circuit, the 8T SRAM consists of 4 NMOS transistors and 4 PMOS transistors. When the Q terminal is 0, a 1 is read at the RBL terminal. Compared to the traditional structure of 6 NMOS transistors and 2 PMOS transistors, the 8T SRAM in the present invention does not require pre-charging of the RBL terminal each time it reads stored data, making the entire structure more power-efficient and having lower power consumption.

[0064] Figure 3 This is a circuit diagram of the storage unit in the artificial intelligence accelerator provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the storage unit in this embodiment of the invention can be an 8-transistor PMOS read-write separated SRAM. The externally written data is stored at the Q or QB terminal, WL is the word line, BL and BLB are the bit lines, RBL is used to input the 4-bit target learning rate, and RWL is used to input the 1-bit target residual value.

[0065] In an embodiment of the present invention, when the Q terminal is stored as 0, it indicates that the target learning rate η is 1; when the RWL input is 0, it indicates that the target residual value σ is 1.

[0066] The artificial intelligence accelerator of this invention can use an 8T SRAM storage unit, which includes 4 NMOS and 4 PMOS. When reading stored data each time, there is no need to precharge the RBL terminal, making the entire circuit more energy-efficient and enabling the artificial intelligence accelerator to have lower power consumption and higher energy efficiency.

[0067] Optionally, the capacitor calculation circuit is further used for:

[0068] The target learning rate, the target residual value, and the target input value are multiplied by analog signals to calculate the target analog voltage.

[0069] Specifically, the analog signal multiplication calculation described in this embodiment of the invention refers to performing analog multiplication operations on three digital signals: the target learning rate, the target residual value, and the target input value.

[0070] Figure 4 This is a schematic diagram of the computational capacitor circuit in the artificial intelligence accelerator provided in an embodiment of the present invention, as shown below. Figure 4As shown, it is a multiply circuit (MC) circuit, in which 4 drivers drive 4 capacitors. Assume that the capacitance values ​​of the 4 capacitors are 1C, 2C, 4C and 8C respectively. Among them, 8T#0, 8T#1, 8T#2 and 8T#3 are used to store the first RBL[0], the second RBL[1], the third RBL[2] and the fourth RBL[3] of the 4-bit target learning rate respectively; 3 switches SW0, SW1 and SW2 and capacitors 30C and 7.5C are used to represent the 2-bit target input value IN. The RESET switch is used to reset the analog output of the circuit.

[0071] Table 1 is the input-output truth table of the artificial intelligence accelerator for training calculation provided in the embodiment of the present invention. As shown in Table 1, the input information includes three inputs, namely the target learning rate η, the target residual value σ, and the target input value IN. The target learning rate η is represented by a signal stored in SRAM, the target residual value σ is represented by an RWL signal, and the target input value IN is represented by an SW signal. The output information is an output MC_OUT signal.

[0072] Table 1

[0073]

[0074] Specifically, in the embodiments of the present invention, the RWL signal corresponding to the target residual value σ is a 1-bit digital signal that is active low. That is, when the RWL input is 0, it means that σ is 1; when the RWL input is 1, it means that σ is 0.

[0075] In an embodiment of the present invention, the RBL signal corresponding to the target learning rate η is a 4-bit digital signal, which is active high. RBL[0] is the least significant bit and RBL[3] is the most significant bit. Among them, RBL[0] = 1, RBL[1] = 0, RBL[2] = 0, RBL[3] = 0, indicating that the true value of η is 1; RBL[0] = 0, RBL[1] = 1, RBL[2] = 0, RBL[3] = 0, indicating that the true value of η is 2; ..., RBL[0] = 1, RBL[1] = 1, RBL[2] = 1, RBL[3] = 1, indicating that the true value of η is 15.

[0076] In the embodiments of the present invention, the SW signal corresponding to the target input value IN is a 2-bit digital signal, represented by SW[2:0]. Where SW[0] = 1, SW[1] = 0, SW[2] = 0, indicating IN is 0; SW[0] = 0, SW[1] = 1, SW[2] = 0, indicating the true value of IN is 1; SW[0] = 0, SW[1] = 0, SW[2] = 1, indicating the true value of IN is 2; SW[0] = 0, SW[1] = 0, SW[2] = 0, indicating the true value of IN is 3. The output information MC_OUT is equal to the true value corresponding to η × IN × σ.

[0077] Furthermore, the calculation capacitor circuit performs analog signal multiplication calculations on the target learning rate, target residual value, and target input value, and outputs the corresponding target analog voltage based on the above input-output truth table.

[0078] The artificial intelligence accelerator of this invention performs analog signal multiplication calculations on the target learning rate, target residual value, and target input value through a computational capacitor circuit, and outputs a target analog voltage. This enables the calculation of weight information changes to support the training of neural network models and can be applied to in-memory computing architectures, which is beneficial for enabling in-memory computing chips to support on-chip training functions.

[0079] Optionally, the capacitor calculation circuit is further used for:

[0080] The target analog product is obtained by multiplying the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value.

[0081] The target simulated voltage is obtained by multiplying the target simulated product with the preset unit voltage.

[0082] Specifically, the target analog product described in the embodiments of the present invention refers to the result of the analog signal product operation of the target learning rate, the target residual value, and the target input value.

[0083] The preset unit voltage described in this embodiment of the invention is determined based on the structure of the calculation capacitor circuit. Its specific value can be determined by the product of the analog signals of the maximum value of the target learning rate, the maximum value of the target residual value, and the maximum value of the target input value, and the preset working voltage.

[0084] The preset operating voltage described in this embodiment of the invention is the operating voltage of the calculated capacitor circuit, denoted by VDD. In this embodiment of the invention, the preset operating voltage can be 0.9V. It is understood that the preset operating voltage can be determined according to different integrated circuit processes, and is not specifically limited in this embodiment of the invention.

[0085] Furthermore, in an embodiment of the present invention, the formula for calculating the target analog voltage is:

[0086]

[0087] MC_OUT_max=η_max×IN_max×σ_max;

[0088] Where MC_OUT represents the target analog voltage, η represents the target learning rate, IN represents the target input value, and σ represents the target residual value. This represents the preset unit voltage, MC_OUT_max represents the maximum value of the analog multiplication of η×IN×σ, and VDD represents the preset operating voltage.

[0089] In the embodiments of the present invention, based on Table 1, it can be seen that MC_OUT_max can be 45, VDD is 0.9V, and the preset unit voltage is 0.9 / 45, which is 0.02V.

[0090] Figure 5 This is a waveform timing diagram of the artificial intelligence accelerator performing training calculations according to an embodiment of the present invention, such as... Figure 5 As shown, VSS represents the circuit's common ground voltage. The training calculation is divided into two stages. The first stage is the reset stage, where RESET and RBL_RESET are high, occurring during the high-level phase of the clock signal. Figure 4 The RBL, MC_OUT, 30C, and 7.5C of the capacitor calculation circuit shown are reset to 0 level. At this time, both the upper and lower plates of the capacitor are at low level.

[0091] The second stage is the calculation stage. The RWL signal is active low. It is determined based on the current layer residual information of the back propagation process of the target neural network model training, i.e., the target residual value. When RWL is low, the 8-tube SRAM will charge and discharge the RBL terminal according to the target learning rate η. SW[0], SW[1], and SW[2] are opened or closed according to the target input value IN. The SW signal can be set to 0 to indicate that the switch is open and 1 to indicate that the switch is closed. Finally, MC_OUT will couple out an analog voltage value equal to η×IN×σ.

[0092] like Figure 5As shown, for example, after the capacitor calculation circuit passes through the reset stage where RESET and RBL_RESET are high, RESET and RBL_RESET are low, and RWL is low, which means that the RWL input is 0 and the target residual value σ is 1. Similarly, it can be seen that RBL[0] = 0, RBL[1] = 0, RBL[2] = 0, RBL[3] = 1, which means that the true value of η is 8. SW[0] = 0, SW[1] = 0, SW[2] = 1, which means that the true value of IN is 2. Therefore, the true value of the target analog voltage is η × IN × σ = 16. Based on the above calculation formula for the target analog voltage, the target analog voltage can be calculated to be 0.32V.

[0093] Similarly, after the circuit goes through the reset phase where RESET and RBL_RESET are high, RESET and RBL_RESET are low, RWL is low, the target residual value σ is 1, RBL[0] = 1, RBL[1] = 0, RBL[2] = 0, RBL[3] = 1, indicating that the true value of η is 9, SW[0] = 0, SW[1] = 1, SW[2] = 0, indicating that the true value of IN is 1. Therefore, the true value of the target analog voltage is η × IN × σ = 9. Based on the above calculation formula for the target analog voltage, the target analog voltage can be calculated to be 0.18V.

[0094] Table 2 is a comparison table of energy consumption between the artificial intelligence accelerator provided in the embodiments of the present invention and the digital multiplier in the prior art under the same process and computing scale. As shown in Table 2, when performing the same 4-bit x 2-bit x 1-bit operation calculation under the same 28nm process, the artificial intelligence accelerator in the present invention can achieve lower power consumption and higher energy efficiency.

[0095] Table 2

[0096]

[0097] The artificial intelligence accelerator of this invention can achieve offline low-power training by performing analog signal multiplication calculations on the target learning rate, target residual value and target input value through the computing capacitor circuit. Compared with existing digital multipliers, it has lower power consumption and higher energy efficiency.

[0098] Optionally, the analog signal multiplication calculation is implemented through charge sharing.

[0099] Specifically, in the embodiments of the present invention, the analog signal multiplication calculation of the calculation capacitor circuit can be implemented by charge sharing. The output voltage is changed by changing the size of the connected capacitor, thereby completing the analog signal multiplication operation.

[0100] The artificial intelligence accelerator of this invention realizes analog signal multiplication operation of the computing capacitor circuit through charge sharing, which is beneficial to improving the efficiency of analog signal operation.

[0101] The data processing method provided by the present invention is described below. The data processing method described below is applied to the artificial intelligence accelerator described above.

[0102] Figure 6 This is a flowchart illustrating the data processing method provided in an embodiment of the present invention, as shown below. Figure 6 As shown, this method is applied to the aforementioned artificial intelligence accelerator, and the method includes:

[0103] Step 601: The calculation capacitor circuit reads the target learning rate from the storage unit and receives the target residual value and target input value from the external input.

[0104] Step 602: The calculation capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value. The target learning rate is the parameter information used to train the target neural network model. The target residual value is determined based on the residual information of the current layer during the backpropagation process of the target neural network model training. The target input value is determined based on the input information during the forward propagation process of the target neural network model training. The target analog voltage is the analog voltage quantity representing the weight change information during the training of the target neural network model.

[0105] Step 603: The analog-to-digital conversion unit receives the target analog voltage output by the computational capacitor circuit and converts the target analog voltage into a target digital voltage for the target neural network model training to update network weight parameters.

[0106] Optionally, the calculation capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value, including:

[0107] The computational capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value, and outputs the target analog voltage.

[0108] Optionally, the calculation capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value to output the target analog voltage, including:

[0109] The computational capacitor circuit calculates the product of the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value to obtain the target analog product;

[0110] The calculation capacitor circuit calculates the product of the target analog product and the preset unit voltage to obtain the target analog voltage.

[0111] Optionally, the calculation capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value to output the target analog voltage, including:

[0112] The computational capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value based on charge sharing, and outputs the target analog voltage.

[0113] The data processing method described in this embodiment of the invention can be applied to the above-mentioned embodiments of the artificial intelligence accelerator, and its principle and technical effect are similar, so it will not be repeated here.

[0114] The data processing method for the aforementioned artificial intelligence accelerator provided by this invention stores the parameter information of the target neural network model training, i.e., the target learning rate, in a storage unit. A computational capacitor circuit can read the target learning rate from the storage unit. The computational capacitor circuit receives the target residual value and the target input value from the external input, and then calculates the target learning rate, the target residual value, and the target input value, as well as the target analog voltage. The analog voltage is then converted into a digital signal representing the weight change information of the target neural network model training by an analog-to-digital conversion unit. This enables the artificial intelligence accelerator to support low-power training computation functions and can be applied to in-memory computing architectures. At the same time, when the sensor ages, by activating the training computation function of the artificial intelligence accelerator, the artificial intelligence accelerator can be re-matched with the aging sensor, avoiding inference computation errors caused by sensor aging in the prior art and ensuring the accuracy of inference computation.

[0115] In another aspect, this application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described artificial intelligence accelerator embodiments and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0116] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0117] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An artificial intelligence accelerator, characterized in that, include: A storage unit is used to store the target learning rate, which is the parameter information for training the target neural network model; A calculation capacitor circuit is used to read the target learning rate from the storage cell and receive the target residual value and the target input value from external input; Based on the target learning rate, the target residual value, and the target input value, a target simulated voltage is output, wherein the target residual value is determined based on the residual information of the current layer during the backpropagation process of the target neural network model training, the target input value is determined based on the input information of the forward propagation process of the target neural network model training, and the target simulated voltage is a voltage analog quantity of the weight change information during the training of the target neural network model; An analog-to-digital converter is used to receive the target analog voltage output by the computing capacitor circuit and convert the target analog voltage into a target digital voltage for the target neural network model training to update network weight parameters. The capacitor calculation circuit is further used for: The target learning rate, the target residual value, and the target input value are multiplied by analog signals to calculate the target analog voltage. The analog signal multiplication calculation is achieved through charge sharing.

2. The artificial intelligence accelerator according to claim 1, characterized in that, The capacitor calculation circuit is further used for: The target analog product is obtained by multiplying the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value. The target simulated voltage is obtained by multiplying the target simulated product with the preset unit voltage. The formula for calculating the target simulated voltage is as follows: MC_OUT_max=η_max×IN_max×σ_max; Where MC_OUT represents the target analog voltage, η represents the target learning rate, IN represents the target input value, and σ represents the target residual value. This indicates the preset unit voltage; MC_OUT_max indicates the maximum value of the analog multiplication of η×IN×σ; and VDD indicates the preset operating voltage. The storage unit includes an 8-tube static random access memory (SRAM). The capacitance calculation circuit includes: A first capacitor with a capacitance of 1C is connected to the first terminal of a first driver, and the input terminal of the first driver is connected to a first 8-transistor SRAM. A second capacitor with a capacitance of 2C is connected to the output terminal of a second driver, and the input terminal of the second driver is connected to a second 8-transistor SRAM. A third capacitor with a capacitance of 4C is provided. The first terminal of the third capacitor is connected to the output terminal of the third driver, and the input terminal of the third driver is connected to the third 8-transistor SRAM. A fourth capacitor with a capacitance of 8C is provided. The first terminal of the fourth capacitor is connected to the output terminal of the fourth driver, and the input terminal of the fourth driver is connected to the fourth 8-transistor SRAM. A fifth capacitor with a capacitance of 30C, one end of which is connected via a first switch (SW1) to the second terminal of the first capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor; A sixth capacitor with a capacitance of 7.5C, one end of which is connected via a second switch (SW2) to the second terminal of the first capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor; The third switch (SW0) is connected to the second terminal of the first capacitor, the second terminal of the second capacitor, the second terminal of the third capacitor, and the second terminal of the fourth capacitor.

3. A data processing method applied to an artificial intelligence accelerator as described in claim 1, characterized in that, include: The computational capacitor circuit reads the target learning rate from the storage unit and receives the target residual value and target input value from external input. The computational capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value. The target learning rate is the parameter information for training the target neural network model. The target residual value is determined based on the residual information of the current layer during the backpropagation process of training the target neural network model. The target input value is determined based on the input information during the forward propagation process of training the target neural network model. The target analog voltage is the voltage analog quantity of the weight change information during training the target neural network model. The analog-to-digital conversion unit receives the target analog voltage output by the computational capacitor circuit and converts the target analog voltage into a target digital voltage for the target neural network model training to update network weight parameters; The calculation capacitor circuit outputs a target analog voltage based on the target learning rate, the target residual value, and the target input value, including: The target learning rate, the target residual value, and the target input value are multiplied by analog signals to output the target analog voltage; the analog signal multiplication is achieved through charge sharing.

4. The data processing method according to claim 3, characterized in that, The computational capacitor circuit performs analog signal multiplication calculations on the target learning rate, the target residual value, and the target input value, and outputs the target analog voltage, including: The computational capacitor circuit calculates the product of the analog signal corresponding to the target learning rate, the analog signal corresponding to the target residual value, and the analog signal corresponding to the target input value to obtain the target analog product; The calculation capacitor circuit calculates the product of the target analog product and the preset unit voltage to obtain the target analog voltage.

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