A puf circuit for secure authentication of power data mobile clients

Abstract

The application discloses a kind of PUF circuits for electric power data mobile client security authentication, including n 2-input Xor gate, m and a D flip-flop;Oscillation signal is divided into two ways, one way is directly introduced back to the first 2-input Xor gate, another way is introduced into the data input end of D flip-flop;D flip-flop exports corresponding feedback signal under the action of one frequency lower than oscillation frequency clock signal;The feedback signal of D flip-flop output is loaded to the other input end of corresponding m first Xor gate after being with the m bit first excitation in the n bit excitation of external input;Wherein, the number of 1 in the m bit first excitation in the n bit excitation of external input is even;Another n-m bit second excitation in the n bit excitation of external input is input to the other input end of the remaining n-m second Xor gate.The application can greatly improve the security of mobile client.

Description

Technical Field

[0001] This invention relates to a PUF circuit for secure authentication of mobile clients for power data, belonging to the field of security authentication technology. Background Technology

[0002] With advancements in modeling attack techniques, hardware security issues for mobile clients have garnered increasing attention. Traditional software encryption methods are vulnerable to physical attacks, such as channel-to-channel attacks. Therefore, Physically Unclonable Functions (PUFs), as a low-power, lightweight hardware security encryption primitive, have gained favor among researchers.

[0003] For example, Chinese Patent CN201710315266.9, published on September 8, 2017, proposes a low-overhead RO PUF circuit structure based on FPGA. This invention utilizes the structural feature of a dual-output LUT in an FPGA, which consists of two single-output LUTs. The designed dual-output RO PUF circuit saves nearly half the LUT resources compared to traditional RO PUF circuits. As another example, Chinese Patent CN109167664A, published on January 8, 2019, proposes a reconfigurable ring oscillator PUF circuit based on an XOR gate, which features simple implementation, high reliability, stability, and randomness, low resource consumption, and multiple excitation response pairs.

[0004] However, even with the aforementioned technical solutions, attackers, once they know the circuit structure, can still pose a security threat to mobile clients through effective modeling. Summary of the Invention

[0005] Objective: To overcome the shortcomings of existing technologies, this invention provides a PUF circuit for secure authentication of mobile clients for power data. Even if an attacker reads the circuit structure, they cannot threaten the security of the mobile client, thus improving the security of the mobile client.

[0006] Technical solution: To solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0007] A PUF circuit for secure authentication of mobile clients for power data, the PUF circuit comprising n 2-input XOR gates, m AND gates and a D flip-flop; n and m are positive integers greater than 2, and n is greater than m;

[0008] The n 2-input XOR gates are cascaded sequentially, with the output of each 2-input XOR gate connected to one of the inputs of the next stage 2-input XOR gate. An oscillation signal is output at the output of the last stage 2-input XOR gate. The n 2-input XOR gates are divided into m first XOR gates and nm second XOR gates. The 2-input XOR gates connected to the AND gate belong to the first XOR gates.

[0009] The oscillation signal is divided into two paths: one path is directly fed back to the first-stage 2-input XOR gate, and the other path is introduced into the data input terminal of the D flip-flop. The D flip-flop outputs a corresponding feedback signal under the action of a clock signal with a frequency lower than that of the oscillation signal. The output terminal of the D flip-flop is connected to one of the input terminals of m AND gates, the other input terminal of the m AND gates is connected to an external excitation source, and the output terminal of the m AND gates is connected to one of the m first XOR gates. The feedback signal output by the D flip-flop is ANDed with one of the m first excitations CI [m-1 : 0] in the n-bit external excitation and then loaded onto the other input terminal of the corresponding m first XOR gate as the control signal of the corresponding first XOR gate. The number of 1s in the m first excitations CI [m-1 : 0] in the n-bit external excitation is even.

[0010] The additional nm bits of the second excitation CⅡ [n-1 : m] in the n-bit external input excitation are input to the other input of the remaining nm second XOR gates as the control signal of the respective second XOR gate.

[0011] To optimize the above technical solution, the specific measures also include:

[0012] Furthermore, an explicit lookup table is used to implement a 2-input XOR gate.

[0013] Furthermore, the clock signal frequency of the D flip-flop is below the 100 MHz level.

[0014] Furthermore, consider one input B of each 2-input XOR gate as an input variable and the other input A as a control signal. When A is 0, the output Q is the same as input B, and the logic function of the 2-input XOR gate is equivalent to a buffer, providing device delay; when A is 1, the output Q is opposite to input B, and the 2-input XOR gate is equivalent to an inverter, also providing device delay.

[0015] Based on the aforementioned PUF circuit, this invention also mentions a method for operating a PUF circuit for security authentication of power data mobile clients, the method comprising the following steps:

[0016] Input a clock signal to the D flip-flop, sample the output oscillation signal, and make the D flip-flop output a cyclic random sequence signal as a feedback signal;

[0017] An n-bit external stimulus is input, where the m-bit first stimulus CI [m-1 : 0] is ANDed with the cyclic random sequence signal output by the D flip-flop and then loaded into the corresponding m first XOR gates as the control signal of the first XOR gate. The remaining nm-bit second stimulus CⅡ [n-1 : m] is input into the remaining nm second XOR gates as the control signal of the second XOR gate, and the oscillation signal is continuously output.

[0018] Beneficial effects: The present invention provides a PUF circuit for security authentication of mobile clients for power data. The present invention expands the influence of process error on the output oscillation frequency, increases the distinguishability between different chips, and increases the difficulty for attackers to obtain circuit information. Moreover, even if attackers obtain the specific information of the circuit, they cannot directly and accurately read the oscillation frequency of XFRO. The average uniqueness of XFRO PUF can reach 49.49%, which greatly increases the security of mobile clients. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the PUF circuit for security authentication of power data mobile clients according to the present invention.

[0020] Figure 2 This is a schematic diagram illustrating the configurable principle of the XOR gate in this invention.

[0021] Figure 3 This is an example diagram of low-frequency signal sampling of high-frequency signals according to the present invention.

[0022] Figure 4 This is the equivalent circuit diagram modeled under the condition that the specific internal wiring of the present invention is unknown.

[0023] Figure 5 This describes the anti-attack effect of the XCRO PUF of the present invention.

[0024] Figure 6 This is a unique schematic diagram of the XFRO PUF of the present invention. Detailed Implementation

[0025] The present invention will be further described below with reference to specific embodiments.

[0026] The invention will now be described in further detail with reference to the accompanying drawings.

[0027] It should be noted that the terms such as "upper", "lower", "left", "right", "front", and "back" used in the invention are only for clarity of description and are not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0028] I. Explanation of the Principle of XFRO PUF

[0029] Figure 1 This is a schematic diagram of the PUF circuit for security authentication of mobile clients for power data according to the present invention. See also... Figure 1 The PUF circuit includes n 2-input XOR gates, m AND gates, and a D flip-flop; n and m are positive integers greater than 2, and n is greater than m.

[0030] n 2-input XOR gates are cascaded in sequence, with the output of each 2-input XOR gate connected to one of the inputs of the next stage 2-input XOR gate. The output of the last stage 2-input XOR gate is an oscillating signal. The n 2-input XOR gates are divided into m first XOR gates and nm second XOR gates. The first stage 2-input XOR gates belong to the first XOR gates.

[0031] The oscillation signal is split into two paths: one path is directly fed back to the first-stage 2-input XOR gate, and the other path is introduced into the data input terminal of the D flip-flop. The D flip-flop outputs a corresponding feedback signal under the action of a clock signal with a frequency lower than the XFRO oscillation frequency. The output terminal of the D flip-flop is connected to one of the input terminals of m AND gates, the other input terminal of the m AND gates is connected to an external excitation source, and the output terminal of the m AND gates is connected to one of the m first XOR gates. The feedback signal output by the D flip-flop is ANDed with one of the m first excitations CI [m-1 : 0] in the n-bit external excitation and then loaded onto the other input terminal of the corresponding m first XOR gate as the control signal of the corresponding first XOR gate. The number of 1s in the m first excitations CI [m-1 : 0] in the n-bit external excitation is even.

[0032] The additional nm bits of the second excitation CⅡ [n-1 : m] in the n-bit external input excitation are input to the other input of the remaining nm second XOR gates as the control signal of the respective second XOR gate.

[0033] The XFRO PUF circuit proposed in this embodiment possesses excellent resistance to machine learning attacks. The specific circuit structure of this XFRO unit is as follows: Figure 1As shown, the components constituting the oscillation loop are the same as those in the XOR-based reconfigurable PUF, consisting of n 2-input XOR gates. The output of each XOR gate is connected to one of the inputs of the next-stage XOR gate, ultimately outputting an oscillation signal at the output of the last XOR gate. Unlike the XOR-based reconfigurable PUF circuit, the output oscillation signal, in addition to being fed back to the first-stage XOR gate, is also fed back to the other input of several XOR gates via a special path. In this special path, the oscillation signal is first introduced to the data input of a D flip-flop. The clock input of the D flip-flop is a clock signal with a frequency lower than the XFRO oscillation frequency. The output signal, after being ANDed with m bits CI [m-1 : 0] of the external input stimulus, is loaded onto the other input of the corresponding m XOR gates. The remaining portion of the stimulus CⅡ [n-1 : m] is input to the inputs of the remaining XOR gates.

[0034] In the XFRO cell, the XOR gate provides configurable logic and device delays for the entire loop. The configurability principle of the XOR gate is as follows: Figure 2 As shown, if we consider one input B of the XOR gate as an input variable and the other input A as a control signal, then the output Q can be considered a function of B controlled by A. When A is 0, the value of the output Q is always the same as the input B. In this case, the logic function of the XOR gate is equivalent to a buffer, only providing device delay for the XFRO loop. When A is 1, the value of the output Q is always opposite to the input B. In this case, the XOR gate is equivalent to an inverter, and also provides device delay for the XFRO loop. In FPGAs, XOR gates are usually implemented using LUTs. Due to the characteristics of LUTs, different input values ​​will lead to different transmission paths for the output signal in the LUT. Therefore, A controls both the logic function of the XOR gate and the device delay it provides. Figure 1 In the structure, the configuration of the m XOR gates is controlled by the AND operation of the excitation and feedback signals. This means that when the input excitation is 1, the operation of the XOR gate is determined by the sampled feedback signal, while when the input excitation is 0, the logic function of the XOR gate is locked as a buffer. The configuration of the remaining XOR gates is directly controlled by the external input excitation. The purpose is to ensure that, with proper configuration of these XOR gates, the number of XOR gates with the logic function of inverters in the entire loop is always odd, so that the XFRO can always meet the oscillation condition. It should be noted that the number of 1s in the excitation CI [m-1 : 0] must be even to ensure that the XFRO does not stop oscillating during the operation of the PUF.

[0035] In Figure 3, the D flip-flop uses a low-frequency signal fs to sample a high-frequency oscillating signal to obtain an unpredictable cyclic random sequence. Figure 3 shows an example of the output result of sampling a high-frequency signal with a low-frequency signal. In the figure, Clk1 is the sampled signal with a period of 5ns, and Clk2 is the sampling clock with a period of 7ns. The sampled output is an infinitely looping sequence. The right side of the figure shows the timing diagram of all signals. In this example, the output sequence is {11010 ..}, and the cycle period is the least common factor of the periods of Clk1 and Clk2, which is 35ns. If this sequence is used to control the configuration of XOR gates, then within these 35ns, the first, second, and fourth 7ns XOR gates are configured as inverters, and the third and fifth 7ns XOR gates are configured as buffers. The same loop will continue in subsequent cycles until the next reconfiguration.

[0036] In an XFRO cell, fs is the externally input clock signal, and the sampled signal is the oscillation signal generated by the XFRO itself. Typically, the oscillation frequency of 8-16 stage ROs implemented in an FPGA is in the hundreds of megahertz range, so the fs frequency only needs to be below the hundreds of megahertz level, offering a wide selection range. A change in either fs or the oscillation frequency will alter the cyclic sequence output by the D flip-flops, which controls the configuration of the XOR gate, thus changing the XFRO output frequency. The influence of fs on the output frequency allows it to be used as the excitation for the PUF when needed, significantly increasing the number of CRPs that can be generated. Due to unavoidable delay differences in the chip caused by process variations, the oscillation frequencies of different XFROs will inevitably differ. Therefore, the influence of the oscillation frequency on the XOR gate configuration will amplify the differences in the internal configuration of different XFROs, even if their structure, implementation, and external input signals are identical.

[0037] In summary, the configuration of an XFRO cell is influenced by both the excitation and its own inherent characteristics, which is its most distinctive feature compared to other reconfigurable operational units (ROs). This characteristic means that even if an attacker knows the XFRO PUF circuit structure, they cannot know the cycle of the configuration modes during operation, or the number of times each configuration mode occurs within that cycle. Under these conditions, even if a delay model is built based on the circuit diagram, the sheer number of possible states necessitates a massive CRP dataset, and a long training time is required to achieve a sufficient prediction rate. Therefore, the only effective way to attack an XFRO PUF is likely to be to obtain the random sequence generated by the D flip-flops. However, the output of the D flip-flops is only used to configure the XOR gate throughout the circuit, and there is no way to directly read the output of the D flip-flops. Therefore, attackers can only employ physical methods, such as side-channel attacks, which will inevitably be a very costly endeavor. In summary, modeling XFRO PUF is very difficult. Unlike other reconfigurable RO PUF structures that can establish accurate delay models, it is almost impossible to establish an accurate delay model for XFRO PUF. Therefore, machine learning attacks are unlikely to achieve the same level of success as attacks on other reconfigurable RO PUF structures in the past, providing a good solution to the problem of insufficient security of RO PUF.

[0038] II. FPGA Implementation and Functional Verification of XFRO PUF

[0039] To verify whether the actual functionality of the proposed XFRO PUF structure matches the theoretical analysis described above, this embodiment implements 100 16-level XFRO cells and 60 XFRO PUF instances on a Xilinx ARTIX-7 BASYS3 FPGA development board. The oscillation frequencies of all 100 implemented XFRO cells were measured, and a large amount of CRP data was collected. The obtained oscillation frequencies are used in this embodiment to verify the actual impact of the design principles analyzed above on the frequency. The CRP data will be used later to evaluate the various performance characteristics of the PUF.

[0040] Because the XFRO cell structure is relatively simple, the XOR gates, AND gates, and D flip-flops used can all be implemented in the LUT. Therefore, implementing the XFRO PUF on the FPGA only requires following the standard design flow. The only point of concern is the arrangement of the XOR and AND gates to prevent asymmetry in wiring from affecting the PUF's performance. In this embodiment, the first and last XOR gates in the implemented 16-level XFRO cell are directly configured by the excitation CI, and the remaining XOR gates are configured by the AND signal obtained by the excitation CI and the feedback signal. That is, the implemented XFRO cell contains 16 XOR gates, 14 AND gates, and 1 D flip-flop, requiring at least 4 CLBs to implement. The arrangement of these logic gates is as follows: the 16 XOR gates are arranged sequentially, grouped into sets of 4, and implemented in one SLICE of each of the 4 adjacent CLBs, while the corresponding AND gate is placed in the other SLICE.

[0041] To facilitate the experiment, the excitation CI was initially set to 0 or 1, ensuring that only one of the first and last XOR gates was configured as an inverter. To ensure the XFRO consistently met the oscillation condition, the number of 1s in the excitation CI had to be even. Therefore, the excitation used for functional verification was "4000, 4030, 403C, 43F0, 40FF, 4FFC, 7FFC, 7FFF" (arranged in ascending order of the number of 1s). The frequency of the XFRO unit was tested under the following three experimental conditions to compare and verify different conclusions.

[0042] • Without changing the input sampling clock fs, input different excitations in the same XFRO unit to verify whether the feedback signal can affect the oscillation frequency;

[0043] • Without changing the input sampling clock fs, input the same excitation into different XFRO cells to verify whether there is sufficient differentiation between the oscillation frequencies of different XFROs;

[0044] • By inputting different sampling clocks fs, the same excitation is input into the same XFRO cell to verify whether the sampling clock can affect the oscillation frequency.

[0045] Table 1 lists the oscillation frequencies of five different XFROs tested under eight different excitations under the same sampling clock condition. Looking at the oscillation frequency of each XFRO individually, it can be seen that the frequency of each XFRO changes to varying degrees with the change of excitation, proving that the feedback signal can indeed affect the oscillation frequency. A longitudinal comparison of the oscillation frequencies of different XFROs under the same excitation reveals that, except when the excitation is 4000 (where no XOR gate is configured by the feedback signal), the oscillation frequencies of all XFROs are relatively similar. At other times, the frequency differences between each XFRO increase, and in most cases, the trend of oscillation frequency change is the same. In other words, while the differentiation between XFRO cells increases, the stability of the response is not significantly sacrificed.

[0046] Table 1. Oscillation frequency (MHz) of XFRO unit under the same sampling clock fs condition.

[0047]

[0048] Table 2 Oscillation frequency (MHz) of the same XFRO cell under different sampling clock fs conditions

[0049]

[0050] Table 2 lists the oscillation frequencies of XFRO1 when the frequency of fs is 100, 75, and 50 MHz, respectively. After changing fs, the oscillation frequency corresponding to different excitations will also change, and there is no particular pattern to this change. Therefore, it can be considered that the delay characteristics of XFRO after changing fs are completely different from those before the change, and it can be regarded as a new XFRO.

[0051] The above comparative analysis of oscillation frequencies proves that the actual function of XFRO conforms to the principle analysis above, and XFRO can be used to generate the response of PUF.

[0052] After a black-box attack, assuming the attacker has already obtained... Figure 1The circuit structure of the XFRO PUF is shown in Figure 4. However, without knowing the specific internal connections, an attacker cannot determine whether each excitation directly controls the configuration of the XOR gate or performs an AND operation with the feedback signal, thus making it impossible to establish the relationship between the excitation and the XFRO delay. Therefore, the circuit needs to be equivalent to the equivalent circuit in Figure 4 (the circuit in the dashed box only represents the function and does not actually exist). In the figure, MUX represents that each XOR gate can be configured either directly by the excitation or by the feedback signal. The box contains a random 0 or 1, which remains unchanged after being determined. This equivalent circuit simulates the reality that for an n-level XFRO unit, there are 2^n different implementations. During the design phase, it can be any one of these, but as long as it is implemented on the hardware platform, this...

[0053] The XFRO unit can only be fixed in this one form and cannot be changed. That is, the vector {S0, S1, ..., Sn−1} in the equivalent circuit diagram is fixed to a certain combination. However, this vector does not represent readable values ​​such as voltage and current in the actual circuit, but rather the combination pattern of several components. Unless the circuit structure can be read, it is impossible to know its specific information.

[0054] Under the conditions shown in Figure 4, the process of establishing the delay model of the circuit is as follows:

[0055] As explained in the previous section, the function of a D flip-flop is to generate an unpredictable, infinitely looping random sequence, assuming it to be {R0R1 ... RX−1 ...}, where X is the length of this random sequence, a random value determined by the circuit. The product of X and the sampling clock period is the cycle period of the XFRO cell configuration. Let the delay of the XOR gate configured as an inverter be denoted as D(I), and the delay of the device configured as a buffer be denoted as D(B). Then, in the x-th clock cycle of each configuration cycle, the delay of the n-stage XFRO is as follows: Figure 5 As shown.

[0056] from Figure 5 (a) Figure 5 (c) and Figure 5 As shown in the attack results graph of LR in (e), regardless of how many CRPs are trained, the final prediction rate remains around 50%, which is no different from the result of random guessing. This is because LR is only efficient when attacking linear models, such as APUF and other reconfigurable ROPUFs, where it can achieve a prediction rate of 100%. However, the delay model of XFROPUF is the accumulation of multiple unknowns with an indefinite number of terms, which is obviously nonlinear. Therefore, LR is almost ineffective when attacking XFROPUF. Figure 5 (b) Figure 5 (d) and Figure 5 As shown in the attack results diagram of ANN in (f), the ANN algorithm is still effective in dealing with non-linear delay models such as XFRO PUF. However, even after training with 20,000 CRPs, the highest prediction rate achieved is only 68% when attacking level 8 XFRO PUF. Such a prediction rate is insufficient to determine whether XFRO PUF can be breached. Moreover, in real-world scenarios, the prediction rate obtained using a training set that mixes effective and ineffective CRPs is even lower, reaching a maximum of only 63%.

[0057] After failing to attack the aforementioned model, the attacker will undoubtedly continue to seek specific information about the circuit to build a more accurate model. Regardless of the method used to obtain the circuit information, without the ability to directly and accurately read the oscillation frequency of the XFRO, machine learning methods will still be necessary for the attack. Let's assume the attacker already knows exactly all the connections in the XFRO cell, that is, they know which XOR gates are directly configured by activating CI, and which XOR gates are jointly configured by activating CI and the feedback signal. The following will illustrate this... Figure 1 Taking the circuit structure in the figure as an example, we can illustrate the process of establishing the delay model under this condition. In the figure, the first m XOR gates are directly configured by the excitation CI [m-1 : 0], and the last n XOR gates are jointly configured by the excitation CⅡ [n-1 : 0] and the feedback signal.

[0058] The uniqueness and reliability calculation results of FRO PUF are as follows: Figure 6 As shown, the average uniqueness of XFRO PUF is 49.49%, which is very close to the ideal value. This may be due to the fact that the configuration of some XOR gates in XFRO is determined by their own delay characteristics, which amplifies the impact of process error on the output oscillation frequency and increases the distinguishability between different chips.

[0059] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A PUF circuit for security authentication of mobile clients for power data, characterized in that, The PUF circuit includes n 2-input XOR gates, m AND gates, and one D flip-flop; n and m are positive integers greater than 2, and n is greater than m; The n 2-input XOR gates are cascaded sequentially, with the output of each 2-input XOR gate connected to one of the inputs of the next stage 2-input XOR gate. An oscillating signal is output at the output of the last stage 2-input XOR gate. The n 2-input XOR gates are divided into m first XOR gates and nm second XOR gates. The 2-input XOR gates connected to the AND gate belong to the first XOR gates. The oscillation signal is divided into two paths: one path is directly fed back to the first-stage 2-input XOR gate, and the other path is introduced into the data input terminal of the D flip-flop. The D flip-flop outputs a corresponding feedback signal under the action of a clock signal with a frequency lower than that of the oscillation signal. The output terminal of the D flip-flop is connected to one of the input terminals of m AND gates, the other input terminal of the m AND gates is connected to an external excitation source, and the output terminal of the m AND gates is connected to one of the m first XOR gates. The feedback signal output by the D flip-flop is ANDed with one of the m first excitations CI [m-1 : 0] in the n-bit external excitation and then loaded onto the other input terminal of the corresponding m first XOR gate as the control signal of the corresponding first XOR gate. The number of 1s in the m first excitations CI [m-1 : 0] in the n-bit external excitation is even. The additional nm bits of the second excitation CⅡ [n-1 : m] in the n-bit external input excitation are input to the other input of the remaining nm second XOR gates as the control signal of the respective second XOR gate; The operation method of the PUF circuit includes the following steps: Input a clock signal to the D flip-flop, sample the output oscillation signal, and make the D flip-flop output a cyclic random sequence signal as a feedback signal; An n-bit external stimulus is input, where the m-bit first stimulus CI [m-1 : 0] is ANDed with the cyclic random sequence signal output by the D flip-flop and then loaded into the corresponding m first XOR gates as the control signal of the first XOR gate. The remaining nm-bit second stimulus CⅡ [n-1 : m] is input into the remaining nm second XOR gates as the control signal of the second XOR gate, and the oscillation signal is continuously output.

2. The PUF circuit for security authentication of power data mobile clients according to claim 1, characterized in that, A 2-input XOR gate is implemented using an explicit lookup table.

3. The PUF circuit for security authentication of power data mobile clients according to claim 1, characterized in that, The clock signal frequency of a D flip-flop is below the 100 MHz level.

4. The PUF circuit for security authentication of power data mobile clients according to claim 1, characterized in that, Consider one input B of each 2-input XOR gate as an input variable and the other input A as a control signal. When A is 0, the output Q is the same as the input B. In this case, the logic function of the 2-input XOR gate is equivalent to a buffer, providing device delay. When A is 1, the output Q is opposite to the input B. In this case, the 2-input XOR gate is equivalent to an inverter, while also providing device delay.

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