Semiconductor device

Abstract

Provided is a semiconductor device capable of achieving an improvement in heat dissipation characteristics of a transistor. An adhesion layer containing at least one metal region in plan view is provided over a surface layer portion of a substrate composed of a semiconductor. A semiconductor element is provided over the adhesion layer. The semiconductor element includes a first transistor provided over a first metal region that is one of the metal regions of the adhesion layer. The first transistor includes a collector layer electrically connected to the first metal region, a base layer provided thereover, and an emitter layer provided thereover. A first emitter electrode is provided over the emitter layer of the first transistor. A first conductor protrusion is provided over the first emitter electrode. The thermal conductivity of the semiconductor material of the surface layer portion of the substrate is higher than that of any of the collector layer, the base layer, and the emitter layer of the first transistor.

Description

Technical Field

[0001] This invention relates to semiconductor devices. Background Technology

[0002] High-frequency signal amplification circuits use heterojunction bipolar transistors (HBTs). To achieve high output in the amplification circuit, it is desirable to improve the heat dissipation characteristics of the HBT. Patent Document 1 discloses an HBT with improved heat dissipation characteristics. The HBT disclosed in Patent Document 1 has a base layer and an emitter layer stacked on top of a collector layer, and a collector electrode is disposed below the collector layer. The collector electrode is bonded to a heat dissipation substrate, thereby conducting heat generated in the HBT to the heat dissipation substrate and dissipating heat from the heat dissipation substrate to the outside.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2016-219682

[0004] To further improve the output of amplifier circuits, it is necessary to further improve the heat dissipation characteristics of transistors such as HBTs. Summary of the Invention

[0005] The object of the present invention is to provide a semiconductor device that can achieve an improvement in the heat dissipation characteristics of transistors.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0007] A substrate, including a surface layer made of semiconductor material;

[0008] An adhesive layer, disposed on the surface portion of the substrate, includes at least one metallic region when viewed from above; and

[0009] At least one semiconductor element is disposed on the adhesive layer described above.

[0010] The aforementioned semiconductor element includes a first transistor disposed on a first metal region that serves as a metal region of the aforementioned adhesive layer.

[0011] The first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer.

[0012] It also has:

[0013] The first emitter electrode is disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; and

[0014] A first conductor protrusion is disposed on and electrically connected to the first emitter electrode, and protrudes in a direction away from the substrate.

[0015] The thermal conductivity of the semiconductor material on the surface of the substrate is higher than that of any one of the collector layer, base layer, and emitter layer of the first transistor.

[0016] The heat generated by the first transistor is conducted through the first emitter electrode and the first conductor protrusion to the component connected to the first conductor protrusion. Furthermore, the heat generated by the first transistor is conducted to the substrate via the adhesive layer. Thus, the heat generated by the first transistor is conducted in two directions, thereby improving the heat dissipation characteristics of the first transistor. Attached Figure Description

[0017] Figure 1 This is a schematic top view of the semiconductor device of the first embodiment.

[0018] Figure 2 yes Figure 1 A sectional view on the dashed-dot line 2-2.

[0019] Figures 3A to 3F The accompanying drawing is a schematic cross-sectional view of a stage in the manufacturing process of a semiconductor device.

[0020] Figures 4A to 4C The accompanying drawing is a schematic cross-sectional view of a stage in the manufacturing process of a semiconductor device. Figure 4D It is a schematic cross-sectional view of a completed semiconductor device.

[0021] Figure 5A This is a schematic top view of the semiconductor device of the first embodiment. Figure 5B This is a schematic top view of a comparative example semiconductor device.

[0022] Figure 6 This is a schematic top view of a semiconductor device according to a variation of the first embodiment.

[0023] Figure 7 This is a schematic top view of the semiconductor device of the second embodiment.

[0024] Figure 8 yes Figure 7 A sectional view on the dashed line 8-8.

[0025] Figure 9 This is a cross-sectional view of the semiconductor device according to the third embodiment.

[0026] Figure 10 This is a cross-sectional view of the semiconductor device according to the fourth embodiment.

[0027] Figure 11A This is an equivalent circuit diagram illustrating an example of an electronic circuit using the semiconductor device of the fourth embodiment. Figure 11B It is used to implement Figure 11A A partial cross-sectional view of the semiconductor device of the electronic circuit shown.

[0028] Figure 12 This is a cross-sectional view of the semiconductor device of the fifth embodiment.

[0029] Figure 13 This is a cross-sectional view of the semiconductor device according to the sixth embodiment.

[0030] Figure 14 This is a cross-sectional view of the semiconductor device of the seventh embodiment.

[0031] Figure 15 This is a cross-sectional view of the semiconductor device of the eighth embodiment.

[0032] Figure 16 This is a cross-sectional view of a semiconductor device according to a variation of the eighth embodiment.

[0033] Figure 17 This is a cross-sectional view of a semiconductor device, which is another variation of the eighth embodiment.

[0034] Explanation of reference numerals in the attached figures

[0035] 20…substrate, 21…adhesive layer, 21A…first metal region, 21B…second metal region, 21C…third metal region, 21D…fourth metal region, 21E…fifth metal region, 21F…sixth metal region, 21Z…insulating region, 22…multilayer wiring structure, 23…insulating layer, 25…wiring, 26…via, 27…substrate-side transistor, 28…semiconductor device, 40…substrate semiconductor layer, 40A…first conductive region, 40B…second conductive region, 40C…third conductive region, 40D…fourth conductive region Electrical region, 40E…fifth conductive region, 40F…sixth conductive region, 40G…seventh conductive region, 40K…opening, 40Z…component separation region, 41…first transistor, 41B…base layer, 41C…collector layer, 41E…emitter layer, 42B…first base electrode, 42BA…main part, 42BB…contact part, 42C…first collector electrode, 42CC…metal pattern, 42E…first emitter electrode, 45…base ballast resistor, 46…base bias circuit, 51…second transistor, 51B…base… 51C…Collector layer, 51E…Emitter layer, 52B…Second base electrode, 52E…Second emitter electrode, 61…Third transistor, 61B…Base layer, 61C…Collector layer, 61E…Emitter layer, 62B…Third base electrode, 62C…Third collector electrode, 62E…Third emitter electrode, 71…Diode, 71L…Lower layer of diode, 71U…Upper layer of diode, 72U…Upper electrode, 72L…Lower electrode, 75…Wireline, 76…Pad, 77…Metal component, 80…Interlayer Insulating film, 81C… First collector wiring, 81E… First emitter wiring, 82C… First collector pad, 82E… First emitter pad, 82W… Interconnection wiring, 83C… Conductor protrusion for collector, 83E… First conductor protrusion, 84… Solder, 86… Interlayer insulating film, 87… Protective film, 87A… Opening, 91E… Second emitter wiring, 92E… Second emitter pad, 93E… Second conductor protrusion, 200… Mother substrate, 201… Release layer, 202… Component forming layer, 204… Connector support. Detailed Implementation

[0036] [First Embodiment]

[0037] Reference Figures 1 to 5B The accompanying drawings illustrate the semiconductor device of the first embodiment.

[0038] Figure 1This is a schematic top view of the semiconductor device according to the first embodiment. An adhesive layer including a first metal region 21A is disposed on a substrate. A first conductive region 40A of the substrate semiconductor layer is configured to almost overlap with the first metal region 21A. A plurality of semiconductor elements are disposed on the first conductive region 40A. A plurality of first transistors 41 are disposed as a plurality of semiconductor elements.

[0039] Each first transistor 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E. The collector layer 41C and the base layer 41B almost overlap when viewed from above. The emitter layer 41E is smaller than the base layer 41B when viewed from above and is contained within the base layer 41B.

[0040] The first emitter electrode 42E is configured to almost overlap with the emitter layer 41E when viewed from above. The first emitter electrode 42E has a direction (in view from above) Figure 1 The first emitter electrode 42E has a relatively long shape (in the left-right direction). Its shape when viewed from above is, for example, rectangular. When viewed from above, the U-shaped first base electrode 42B is positioned spaced apart from the two long sides and one short side of the first emitter electrode 42E. Figure 1 In the image, additional shading lines are added to the first emitter electrode 42E and the first base electrode 42B. A plurality of first transistors 41 are arranged side-by-side in the width direction orthogonal to the long side direction of the first emitter electrode 42E.

[0041] Figure 2 yes Figure 1 A cross-sectional view along the dashed line 2-2. An adhesive layer 21 is disposed on the substrate 20. The adhesive layer 21 includes at least one first metal region 21A. Figure 2 A cross-section of a first metal region 21A of the adhesive layer 21 is shown. The substrate 20 includes a surface layer made of semiconductor. As the substrate 20, for example, a silicon substrate, a silicon-on-insulator (SOI) substrate, etc., can be used.

[0042] A substrate semiconductor layer 40, made of semiconductor material, is bonded onto the adhesive layer 21. The substrate semiconductor layer 40 includes a first conductive region 40A that is imparted with conductivity, and an insulating element separation region. Figure 2 A cross-section of the first conductive region 40A is shown. A plurality of first transistors 41 are disposed on the first conductive region 40A.

[0043] Each first transistor 41 includes a collector layer 41C, a base layer 41B, and an emitter layer 41E, sequentially stacked from the substrate 20 side. The first transistor 41 is, for example, a heterojunction bipolar transistor. As an example, the first conductive region 40A of the substrate semiconductor layer 40 and the collector layer 41C are formed of n-type GaAs, and the base layer 41B is formed of p-type GaAs. The emitter layer 41E includes, for example, a bilayer of an n-type InGaP layer and an n-type GaAs layer thereon. Alternatively, other compound semiconductors, such as InP, GaN, SiGe, and SiC, can be used to form these semiconductor layers.

[0044] The collector layer 41C is electrically connected to the first metal region 21A via the first conductive region 40A. The first metal region 21A functions as the collector electrode of the first transistor 41. The emitter layer 41E is disposed over a portion of the base layer 41B. Alternatively, the emitter layer 41E may be disposed over the entire region of the base layer 41B, and an emitter mesa may be disposed over a portion of the emitter layer 41E. In this configuration, the region overlapping with the emitter mesa when viewed from above effectively functions as the emitter layer.

[0045] A first base electrode 42B is disposed on the base layer 41B, and a first emitter electrode 42E is disposed on the emitter layer 41E. The first base electrode 42B is electrically connected to the base layer 41B, and the first emitter electrode 42E is electrically connected to the emitter layer 41E.

[0046] A first emitter wiring 81E is disposed on the first emitter electrode 42E via an interlayer insulating film 80. The first emitter wiring 81E connects multiple first emitter electrodes 42E to each other through openings in the interlayer insulating film 80. Furthermore, the collector layers 41C of multiple first transistors 41 are also interconnected through a first conductive region 40A and a first metal region 21A. That is, multiple first transistors 41 are connected in parallel.

[0047] A first emitter pad 82E and a first conductor protrusion 83E are disposed on the first emitter wiring 81E. Solder 84 is placed on the first conductor protrusion 83E. The structure of the first conductor protrusion 83E, formed of Cu, on which solder 84 is placed, can be described as a "Cu pillar bump". Alternatively, a protrusion with a structure that does not place solder on it, such as an Au bump, can also be used as the first conductor protrusion 83E. Such a protrusion can also be described as a "pillar". In addition, a protrusion with a structure in which a conductor pillar is erected on the pad can also be used as the first conductor protrusion 83E. Such a conductor protrusion can also be described as a "pile". Alternatively, a ball bump that causes the solder to reflow into a spherical shape can also be used as the first conductor protrusion 83E. In addition to these various structures of protrusions, various structures including conductors protruding from the substrate can also be used as conductor protrusions.

[0048] Next, refer to Figures 3A to 4D The accompanying drawings illustrate a method for manufacturing a semiconductor device according to a first embodiment. Figures 3A to 4C The accompanying drawing is a schematic cross-sectional view of a stage in the manufacturing process of a semiconductor device. Figure 4D It is a schematic cross-sectional view of a completed semiconductor device.

[0049] like Figure 3A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 containing... Figure 2 The diagram shows a component structure including a substrate semiconductor layer 40, a plurality of first transistors 41, a first emitter electrode 42E, a first base electrode 42B, an interlayer insulating film 80, and a first emitter wiring 81E. These component structures are formed using conventional semiconductor processes. Figure 3A The device structure formed in the device formation layer 202 is omitted from the description. At this stage, a device structure equivalent to multiple semiconductor devices is formed in the device formation layer 202, but it is not separated into individual semiconductor devices. Furthermore, the first emitter pad 82E, the first conductor protrusion 83E, and the solder 84 are not formed. Figure 2 ).

[0050] Next, as Figure 3B As shown, a resist pattern (not shown) is used as an etching mask to pattern the device formation layer 202 and the release layer 201. In this stage, the device formation layer 202 is separated into individual semiconductor devices.

[0051] Next, as Figure 3C As shown, a connecting support 204 is attached to the separated component forming layer 202. Thus, multiple component forming layers 202 are interconnected via the connecting support 204. Alternatively, it is also possible to leave... Figure 3BThe patterning process is used as a resist pattern for etching mask, so that the resist pattern is sandwiched between the component forming layer 202 and the connecting support 204.

[0052] Next, as Figure 3D As shown, the release layer 201 is selectively etched relative to the mother substrate 200 and the device forming layer 202. As a result, the device forming layer 202 and the bonding support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from both the mother substrate 200 and the device forming layer 202 is used as the release layer 201.

[0053] like Figure 3E As shown, an adhesive layer 21 is formed on the upper surface of the substrate 20. The adhesive layer 21 includes a plurality of first metal regions 21A distributed in-plane and insulating regions 21Z disposed in the regions where the first metal regions 21A are not disposed. For example, the adhesive layer 21 can be formed by a damascene process.

[0054] like Figure 3F As shown, the element forming layer 202 is bonded to the adhesive layer 21. The bonding between the element forming layer 202 and the adhesive layer 21 is based on van der Waals bonds or hydrogen bonds. Alternatively, the element forming layer 202 and the adhesive layer 21 can also be bonded by electrostatic forces, covalent bonds, eutectic alloy bonds, etc. For example, when the first metal region 21A is formed of Au, the two can also be bonded by pressing the element forming layer 202 tightly against the Au film.

[0055] Next, as Figure 4A As shown, the connecting support 204 is peeled off from the component forming layer 202. After peeling off the connecting support 204, as... Figure 4B As shown, an interlayer insulating film 86 and a redistribution layer are formed on the adhesive layer 21 and the component forming layer 202. The redistribution layer includes a first emitter wiring 81E. Figure 2 The first emitter pad 82E on the top of the component forming layer 202, the interconnect wiring 82W connecting the circuit contained in the component forming layer 202 to a metal area of ​​the adhesive layer 21, etc.

[0056] Next, as Figure 4C As shown, a protective film 87 is formed on the redistribution layer, and a plurality of openings 87A are formed in the protective film 87. The plurality of openings 87A, when viewed from above, are respectively contained within a plurality of first emitter pads 82E. First conductor protrusions 83E are formed within the openings 87A and on the protective film 87. The first conductor protrusions 83E protrude in a direction away from the substrate 20. Then, solder 84 is placed on the top surface of the first conductor protrusions 83E for reflow processing.

[0057] Finally, as Figure 4D As shown, the substrate 20 is cut. This yields a monolithic semiconductor device 28 comprising the substrate 20, an adhesive layer 21, a component forming layer 202, a first emitter pad 82E, a first conductor protrusion 83E, interconnecting wiring 82W, etc. In the monolithic semiconductor device 28, the substrate 20 is larger than the component forming layer 202 when viewed from above. The monolithic semiconductor device 28 is flip-chip mounted on a module substrate, etc.

[0058] Next, the superior effects of the first embodiment will be explained.

[0059] In the first embodiment, in the first transistor 41 ( Figure 2 The heat generated is conducted to the substrate 20 through the base semiconductor layer 40 and the adhesive layer 21, and then to the solder 84 through the first emitter electrode 42E, the first emitter wiring 81E, the first emitter pad 82E, and the first conductor protrusion 83E. The heat conducted to the solder 84 is then conducted to the module substrate on which the semiconductor device is mounted. The heat conducted to the substrate 20 diffuses within the substrate 20 and is then dissipated to the outside. Similarly, the heat conducted to the module substrate is also dissipated to the outside from the module substrate.

[0060] In this way, the heat generated by the first transistor 41 is conducted and dissipated in both downward (towards the substrate 20 side) and upward (towards the first conductor protrusion 83E side). Therefore, compared to the case where heat is conducted in only one direction, the heat dissipation characteristics of the first transistor 41 can be improved. Due to the improved heat dissipation characteristics of the first transistor 41, multiple first transistors 41 can be arranged more closely. As a result, miniaturization of the semiconductor device is possible.

[0061] To ensure sufficient heat dissipation within the substrate 20, it is preferable to use a material with a thermal conductivity higher than that of any one of the collector layer 41C, base layer 41B, and emitter layer 41E of the first transistor 41 as the semiconductor material for the surface layer of the substrate 20. Examples of such semiconductor materials include silicon. Furthermore, to efficiently dissipate heat from the substrate 20 to the outside, it is preferable that the substrate 20 is larger than the base semiconductor layer 40 when viewed from above.

[0062] Next, refer to Figure 5A as well as Figure 5B The superior effects of the first embodiment will be explained while comparing it with the comparative example.

[0063] Figure 5A This is a schematic top view of the semiconductor device of the first embodiment, and... Figure 1 The schematic top view shown is the same. Figure 5B This is a schematic top view of a comparative example semiconductor device.

[0064] In the comparative example semiconductor device, an adhesive layer 21 containing the first metal region 21A is not disposed. Figure 2 A first collector electrode 42C is disposed between two adjacent first transistors 41. The first collector electrode 42C is disposed on the substrate semiconductor layer 40. Figure 2 The first conductive region 40A of the first transistor 41 is connected to the collector layer 41C of the first transistor 41 via the first conductive region 40A. Figure 2 Electrical connection. In contrast, in the first embodiment, the first metal region 21A of the adhesive layer 21 ( Figure 2 It functions as a collector electrode.

[0065] In the first embodiment, it is not necessary to ensure the configuration of the first collector electrode 42C when viewed from above. Figure 5B The space allows for the miniaturization of semiconductor devices.

[0066] exist Figure 5B In the comparative example shown, the distance from the edge of the emitter layer 41E to the first collector electrode 42C is not equal to the distance from the inner part of the emitter layer 41E to the first collector electrode 42C; the distance deviates depending on the in-plane position. In contrast, in the first embodiment, the distance in the thickness direction between the emitter layer 41E and the first metal region 21A, which functions as the collector electrode, is constant regardless of the in-plane position. Therefore, uniform operation can be performed within the plane of the emitter layer 41E.

[0067] Next, refer to Figure 6 A variation of the first embodiment will be described.

[0068] Figure 6 This is a schematic top view of a semiconductor device, a variation of the first embodiment. Figure 1 In this configuration, each first transistor 41 includes an emitter layer 41E, and each first transistor 41 is configured with a first emitter electrode 42E. In contrast, in... Figure 6 In the variant shown, a first transistor 41 includes two emitter layers 41E, and two first emitter electrodes 42E are configured for each first transistor 41. The two first emitter electrodes 42E are arranged in a direction orthogonal to the long side direction of the first emitter electrodes 42E.

[0069] Viewed from above, a main portion 42BA of a first base electrode 42B is disposed between the two first emitter electrodes 42E. A contact portion 42BB extending in the width direction of the first emitter electrode 42E is provided at one end of the main portion 42BA of the first base electrode 42B. The first base electrode 42B is connected to the upper base wiring (not shown) at the contact portion 42BB.

[0070] In this variant, similar to the first embodiment, it is possible to improve the heat dissipation characteristics of the first transistor 41, and as a further effect, it is possible to miniaturize the semiconductor device.

[0071] Next, other variations of the first embodiment will be described.

[0072] In the first embodiment, the first conductive region 40A is surrounded by an insulated element separation region. Figure 1 However, it is also possible to omit the component separation region and instead allow the substrate semiconductor layer 40 ( Figure 2 The entire area of ​​the first conductive region 40A is defined as the first conductive region 40A. Although a plurality of first transistors 41 are configured in the first embodiment, only one first transistor 41 may be configured. Furthermore, although in the first embodiment, as... Figure 2 As shown, a base semiconductor layer 40 is disposed between the adhesive layer 21 and the first transistor 41, but the base semiconductor layer 40 may be omitted. In this case, the collector layer 41C of the first transistor 41 is directly bonded to the first metal region 21A of the adhesive layer 21. In addition, the interlayer insulating film 80 is also directly bonded to the adhesive layer 21.

[0073] [Second Embodiment]

[0074] Next, refer to Figure 7 as well as Figure 8 The semiconductor device of the second embodiment will be described below. Hereinafter, the device will be compared with the one described above. Figures 1 to 4D The semiconductor device of the first embodiment, as illustrated in the accompanying drawings, has the same configuration, which is omitted from the description.

[0075] Figure 7 This is a schematic top view of the semiconductor device of the second embodiment. Figure 8 yes Figure 7 A sectional view along the dashed line 8-8. Figure 7 In the first embodiment, additional shading lines are added to the first emitter electrode 42E and the first base electrode 42B. Figure 1 , Figure 2 In the first embodiment, a collector layer 41C and a base layer 41B are separated for each first transistor 41. In contrast, in the second embodiment, the collector layer 41C and the base layer 41B are continuous across a plurality of first transistors 41. Furthermore, in the second embodiment, an emitter layer 41E, and the base layer 41B and collector layer 41C directly below it are defined as a first transistor 41.

[0076] A main portion 42BA of a first base electrode 42B is disposed between two adjacent first emitter electrodes 42E. A contact portion 42BB extending in the width direction of the first emitter electrode 42E is provided at one end of the main portion 42BA of the first base electrode 42B. One first base electrode 42B is shared by two first transistors 41 connected to the two first emitter electrodes 42E on either side of it. Multiple first base electrodes 42B are connected to a base bias circuit 46 via base ballast resistors 45.

[0077] Next, the superior effects of the second embodiment will be explained.

[0078] In the first embodiment, two first base electrodes 42B are disposed between two adjacent first emitter electrodes 42E. In contrast, in the second embodiment, one first base electrode 42B is disposed between two adjacent first emitter electrodes 42E. Therefore, miniaturization of the semiconductor device can be achieved compared to the first embodiment. Furthermore, with the same size and number of first transistors 41, the area of ​​the collector-base junction interface of the semiconductor device in the second embodiment is smaller than the combined area of ​​the collector-base junction interfaces of the semiconductor device in the first embodiment. Therefore, the excellent effect of reducing the parasitic capacitance between the base and collector can be obtained.

[0079] Next, a variation of the second embodiment will be described.

[0080] In the second embodiment, multiple first base electrodes 42B, respectively disposed between two adjacent first emitter electrodes 42E, are separated from each other, and each of the multiple first base electrodes 42B is connected to a base ballast resistor 45. If a deviation occurs in the collector current among the multiple first transistors 41, a particular first transistor 41 with a relatively large collector current may experience thermal runaway. The base ballast resistor 45 has the function of averaging the deviation in collector current and suppressing thermal runaway. Depending on the operating conditions of the first transistor 41, there are situations where the first transistor 41 is less likely to reach thermal runaway. In such cases, the multiple first base electrodes 42B can also be made continuous, with a single base ballast resistor 45 connected to each of the multiple first base electrodes 42B.

[0081] [Third Embodiment]

[0082] Next, refer to Figure 9 The semiconductor device of the third embodiment will be described below. Hereinafter, the device will be compared with the one described above. Figures 1 to 4D The semiconductor device of the first embodiment, as illustrated in the accompanying drawings, has the same configuration, which is omitted from the description.

[0083] Figure 9 This is a cross-sectional view of the semiconductor device of the third embodiment. The semiconductor device of the first embodiment ( Figure 1 , Figure 2 The first embodiment has multiple first transistors 41 as semiconductor elements. In contrast, for the semiconductor device of the third embodiment, the multiple semiconductor elements disposed on the substrate 20 include second transistors 51 in addition to the first transistors 41.

[0084] The adhesive layer 21 includes a second metal region 21B in addition to the first metal region 21A, serving as a metal region. The first metal region 21A and the second metal region 21B are separated from each other by the insulating region 21Z included in the adhesive layer 21. The substrate semiconductor layer 40 includes a second conductive region 40B in addition to the first conductive region 40A, serving as a conductive region. The first conductive region 40A and the second conductive region 40B are separated from each other by the element separation region 40Z included in the substrate semiconductor layer 40. In top view, the first conductive region 40A and the first metal region 21A have overlapping regions. Similarly, the second conductive region 40B and the second metal region 21B also have overlapping regions. Furthermore, in order to electrically insulate the region formed by the first conductive region 40A and the first metal region 21A, and the region formed by the second conductive region 40B and the second metal region 21B from each other, at least a portion of the element separation region 40Z and the insulating region 21Z overlap each other in top view.

[0085] The second transistor 51 is disposed on the second conductive region 40B. The second transistor 51 is also identical to the first transistor 41, including a collector layer 51C, a base layer 51B, and an emitter layer 51E. The second metal region 21B functions as the collector electrode of the second transistor 51. A second base electrode 52B is connected to the base layer 51B, and a second emitter electrode 52E is connected to the emitter layer 51E.

[0086] Above the second emitter electrode 52E, a second emitter wiring 91E, a second emitter pad 92E, and a second conductor protrusion 93E are disposed. Solder 84 is placed on the second conductor protrusion 93E. The second emitter pad 92E, like the first emitter pad 82E, is contained within the redistribution layer. Figure 4B An interlayer insulating film 86 is disposed between the first emitter wiring 81E and the second emitter wiring 91E and the rewiring layer. The first emitter pad 82E and the second emitter pad 92E are covered by a protective film 87 except for the areas connected to the first conductor protrusion 83E and the second conductor protrusion 93E.

[0087] Next, the superior effects of the third embodiment will be explained.

[0088] In the third embodiment, a first transistor 41 and a second transistor 51, which are electrically separated, are formed on a common substrate 20. Therefore, two amplifier circuits can be included in a single semiconductor device. For example, the second transistor 51 can be used to form a pre-amplifier circuit, and the first transistor 41 can be used to form a post-amplifier circuit, thus realizing a two-stage amplifier circuit. Furthermore, similar to the first embodiment, improved heat dissipation characteristics can be achieved in the third embodiment.

[0089] [Fourth Embodiment]

[0090] Next, refer to Figure 10 , Figure 11A ,as well as Figure 11B The semiconductor device of the fourth embodiment will now be described. Hereinafter, the device will be compared with that described above. Figures 1 to 4D The semiconductor device of the first embodiment, as illustrated in the accompanying drawings, has the same configuration, which is omitted from the description.

[0091] Figure 10 This is a cross-sectional view of the semiconductor device according to the fourth embodiment. In the semiconductor device of the fourth embodiment, in addition to the first transistor 41, the plurality of semiconductor elements disposed on the substrate 20 also include a third transistor 61 and a diode 71.

[0092] In addition to the first metal region 21A, the adhesive layer 21 also includes a third metal region 21C and a fourth metal region 21D, serving as metal regions. The first metal region 21A, the third metal region 21C, and the fourth metal region 21D are separated from each other by an insulating region 21Z. In addition to the first conductive region 40A, the substrate semiconductor layer 40 also includes a third conductive region 40C and a fourth conductive region 40D. The first conductive region 40A, the third conductive region 40C, and the fourth conductive region 40D are separated from each other by an element separation region 40Z. When viewed from above, the first metal region 21A, the third metal region 21C, and the fourth metal region 21D overlap with the first conductive region 40A, the third conductive region 40C, and the fourth conductive region 40D by at least a portion of each other. In addition, in order to make the three regions consisting of the first conductive region 40A and the first metal region 21A, the region consisting of the second conductive region 40B and the second metal region 21B, and the region consisting of the third conductive region 40C and the third metal region 21C electrically insulated from each other, the insulating region 21Z and at least a portion of the component separation region 40Z overlap each other when viewed from above.

[0093] The third transistor 61 is disposed on the third conductive region 40C. The third transistor 61 is the same as the first transistor 41, including a collector layer 61C, a base layer 61B, and an emitter layer 61E. A third base electrode 62B is connected to the base layer 61B, and a third emitter electrode 62E is connected to the emitter layer 61E.

[0094] In top view, a third collector electrode 62C is disposed inside the third conductive region 40C and the third metal region 21C, and outside the third transistor 61. The third collector electrode 62C is electrically connected to the collector layer 61C of the third transistor 61 via the third conductive region 40C and the third metal region 21C. No conductor protrusions for the third transistor 61 are provided. Furthermore, the third collector electrode 62C only needs to be disposed inside the third conductive region 40C in top view, and does not necessarily need to be disposed inside the third metal region 21C. In addition, if a configuration is adopted in which the third metal region 21C and the third conductive region 40C are directly connected to other electronic components, the third collector electrode 62C may be omitted. For example, the collector layer 61C of the third transistor 61 may be connected to other electronic components disposed on the substrate 20 or other electronic components disposed on the substrate semiconductor layer 40 via the third metal region 21C and the third conductive region 40C.

[0095] Diode 71 is disposed above the fourth conductive region 40D. Diode 71 includes a lower layer 71L of a first conductivity type (e.g., n-type) connected to the fourth conductive region 40D, and an upper layer 71U of a second conductivity type (e.g., p-type) disposed thereon. The lower layer 71L, together with the collector layer 41C of the first transistor 41 and the collector layer 61C of the third transistor 61, is formed by patterning a common semiconductor layer. Similarly, the upper layer 71U, together with the base layer 41B of the first transistor 41 and the base layer 61B of the third transistor 61, is formed by patterning a common semiconductor layer.

[0096] In top view, a lower electrode 72L is disposed inside the fourth conductive region 40D and the fourth metal region 21D, and outside the diode 71. The lower electrode 72L is electrically connected to the lower layer 71L via the fourth conductive region 40D and the fourth metal region 21D. Furthermore, the lower electrode 72L only needs to be disposed inside the fourth conductive region 40D in top view; it does not necessarily need to be disposed inside the fourth metal region 21D. An upper electrode 72U is disposed on the upper layer 71U. The upper electrode 72U is electrically connected to the upper layer 71U. Furthermore, in the case where the fourth metal region 21D and the fourth conductive region 40D are directly connected to other electronic components, the lower electrode 72L can be omitted. For example, the lower layer 71L of the diode 71 can be connected to other electronic components disposed on the substrate 20 and other electronic components disposed on the substrate semiconductor layer 40 via the fourth metal region 21D and the fourth conductive region 40D.

[0097] Next, the superior effects of the fourth embodiment will be explained.

[0098] Similar to the first embodiment, the fourth embodiment also achieves improved heat dissipation characteristics of the first transistor 41. Furthermore, in addition to the first transistor 41, which functions as a collector electrode in the first metal region 21A disposed below the substrate semiconductor layer 40, the semiconductor device of the fourth embodiment also includes a third transistor 61 with a third collector electrode 62C disposed above the substrate semiconductor layer 40. Therefore, the design freedom of the wiring connected to the collector of the transistor is increased, resulting in superior advantages such as easier circuit design.

[0099] Next, refer to Figure 11A as well as Figure 11B An example of an electronic circuit using the semiconductor device of the fourth embodiment will be described.

[0100] Figure 11A This is an equivalent circuit diagram illustrating an example of an electronic circuit using the semiconductor device of the fourth embodiment. A power stage amplifier circuit is constructed using the first transistor 41. A power supply voltage is applied to the collector of the first transistor 41 from the power supply terminal Vcc through the choke coil Lc.

[0101] The base bias circuit of the first transistor 41 includes a third transistor 61. The emitter of the third transistor 61 is connected to the base of the first transistor 41 via a base ballast resistor Rb. The collector and base of the third transistor 61 are connected to the bias power supply port Vbatt and the bias control port Vbias, respectively. According to the control current supplied to the bias control port Vbias, a base bias voltage is supplied to the first transistor 41 from the bias power supply port Vbatt through the third transistor 61 and the base ballast resistor Rb.

[0102] A high-frequency signal is input from the input port RFin through the input capacitor Cin to the base of the first transistor 41. The emitter of the first transistor 41 is grounded, and its collector is connected to the output port RFout.

[0103] The collector of the first transistor 41 is grounded via a plurality of diodes 71 connected in series. The plurality of diodes 71 are connected with a positive polarity from the collector of the first transistor 41 toward the ground potential, and function as clamping diodes.

[0104] Figure 11B It is used to implement Figure 11A A partial cross-sectional view of the semiconductor device in the illustrated electronic circuit. The following section discusses... Figure 10The differences in the structure shown will be explained. The adhesive layer 21 includes a fifth metal region 21E, and the substrate semiconductor layer 40 includes a fifth conductive region 40E. A pad 76 is disposed on the fifth conductive region 40E. The fifth metal region 21E and the fifth conductive region 40E overlap when viewed from above. The pad 76 is electrically connected to the fifth metal region 21E via the fifth conductive region 40E.

[0105] In addition to the first emitter wiring 81E, wiring 75 is disposed on the interlayer insulating film 80. Wiring 75 is connected to the upper electrode 72U and the pad 76 through an opening in the interlayer insulating film 80. A multilayer wiring structure 22 is disposed between the substrate 20 and the adhesive layer 21. The multilayer wiring structure 22 includes wiring 25 and a plurality of vias 26. The upper electrode 72U of the diode 71 is electrically connected to the first metal region 21A, which functions as the collector electrode of the first transistor 41, via wiring 75, pad 76, fifth conductive region 40E, fifth metal region 21E, and wiring 25 and vias 26 in the multilayer wiring structure 22. Alternatively, the upper electrode 72U can be connected to the first metal region 21A by extending the fifth metal region 21E through the adhesive layer 21, bypassing the third transistor 61. With this configuration, the multilayer wiring structure 22 can be omitted.

[0106] exist Figure 11B The diagram shows an example of a wiring layer comprising a first emitter wiring 81E disposed between the interlayer insulating film 80 and the first emitter pad 82E, but multiple wiring layers may also be disposed between the interlayer insulating film 80 and the first emitter pad 82E. The base ballast resistor Rb and the input capacitor Cin are formed on the substrate semiconductor layer 40, for example, before the interlayer insulating film 80 is formed.

[0107] The third collector electrode 62C of the third transistor 61 is connected to a collector conductor protrusion (not shown) disposed on the protective film 87. The bias power supply port Vbatt of the module substrate... Figure 11A A bias power supply is supplied to the collector of the third transistor 61 via a collector conductor protrusion and a third collector electrode 62C. The third collector electrode 62C is disposed on the substrate semiconductor layer 40, so compared with the case where the collector electrode of the third transistor 61 is disposed below the substrate semiconductor layer 40, the connection structure between the third collector electrode 62C and the collector conductor protrusion for connection to the bias power supply port Vbatt can be simplified.

[0108] Next, a variation of the fourth embodiment will be described. In the fourth embodiment, wiring 25 and vias 26 are arranged within the multilayer wiring structure 22, but passive components composed of metal patterns may also be arranged in addition. For example, an inductor may be formed by a spiral or serpentine metal pattern. Alternatively, a capacitor may be formed by metal patterns arranged above and below via an interlayer insulating film.

[0109] [Fifth Embodiment]

[0110] Next, refer to Figure 12 The semiconductor device of the fifth embodiment will be described below. Hereinafter, the device will be compared with the one described above. Figures 1 to 4D The semiconductor device of the first embodiment, as illustrated in the accompanying drawings, has the same configuration, which is omitted from the description.

[0111] Figure 12 This is a cross-sectional view of the semiconductor device according to the fifth embodiment. In the fifth embodiment, the adhesive layer 21 includes a sixth metal region 21F as a metal region in addition to the first metal region 21A. The substrate semiconductor layer 40 includes a sixth conductive region 40F and a seventh conductive region 40G as conductive regions in addition to the first conductive region 40A. The sixth conductive region 40F and the seventh conductive region 40G overlap with a portion of the sixth metal region 21F when viewed from above, and the two are electrically connected to each other via the sixth metal region 21F.

[0112] A diode 71 is disposed above the sixth conductive region 40F. The diode 71 has the same characteristics as the diode 71 in the semiconductor device of the fourth embodiment. Figure 10 The same structure. A metal component 77, such as a wiring component, is disposed on the seventh conductive region 40G. The metal component 77 is electrically connected to the sixth metal region 21F through an opening 40K provided in the substrate semiconductor layer 40. The metal component 77 is electrically connected to the diode 71 through the sixth metal region 21F and the sixth conductive region 40F. During the manufacturing process... Figure 3A The stage shown forms an opening of 40K. In Figure 3D As shown, with the stripping layer 201 removed, the metal component 77 inside the opening 40K is exposed.

[0113] Next, the superior effects of the fifth embodiment will be explained. Similar to the first embodiment, the fifth embodiment achieves improved heat dissipation characteristics of the first transistor 41. Furthermore, in the fifth embodiment, the diode 71 and the metal component 77 are interconnected via a sixth metal region 21F contained in the adhesive layer 21. By utilizing the metal region contained in the adhesive layer 21 as wiring, the flexibility of wiring design can be increased. Additionally, since the metal component 77 is connected to the sixth metal region 21F through an opening 40K provided in the substrate semiconductor layer 40, lower resistance can be achieved compared to a configuration where electrical connections are made through conductive regions contained in the substrate semiconductor layer 40.

[0114] Next, a variation of the fifth embodiment will be described.

[0115] In the fifth embodiment, the metal component 77 on the substrate semiconductor layer 40 is connected to the diode 71 via the sixth metal region 21F of the adhesive layer 21. However, the metal component 77 can also be connected to other semiconductor elements via the sixth metal region 21F. Furthermore, in the fifth embodiment, the metal component 77 is disposed on the seventh conductive region 40G included in the substrate semiconductor layer 40. However, the metal component 77 can also be disposed on the component separation region 40Z. In this case, it is sufficient to provide an opening 40K in the component separation region 40Z.

[0116] [Sixth Embodiment]

[0117] Next, refer to Figure 13 The semiconductor device of the sixth embodiment will be described. Hereinafter, the device will be compared with that described above. Figures 10-11B The semiconductor device of the fourth embodiment, which is illustrated in the accompanying drawings, has the same configuration, and the description is omitted.

[0118] Figure 13 This is a cross-sectional view of the semiconductor device according to the sixth embodiment. In the fourth embodiment ( Figure 10 In the first embodiment, the third conductive region 40C and the fourth conductive region 40D of the substrate semiconductor layer 40 are disposed on the third metal region 21C and the fourth metal region 21D of the adhesive layer 21, respectively. In contrast, in the sixth embodiment, the third conductive region 40C and the fourth conductive region 40D of the substrate semiconductor layer 40 are disposed on the insulating region 21Z of the adhesive layer 21.

[0119] In the sixth embodiment, the third collector electrode 62C is connected to the collector layer 61C of the third transistor 61 only through the third conductive region 40C of the substrate semiconductor layer 40. Similarly, the lower electrode 72L is connected to the lower layer 71L of the diode 71 only through the fourth conductive region 40D of the substrate semiconductor layer 40.

[0120] A multilayer wiring structure 22 is disposed between the substrate 20 and the adhesive layer 21. The multilayer wiring structure 22 includes a plurality of wirings 25 and a plurality of through holes 26.

[0121] Next, the superior effects of the sixth embodiment will be explained.

[0122] Similar to the first embodiment, the sixth embodiment also achieves improved heat dissipation characteristics of the first transistor 41. Furthermore, in the sixth embodiment, the insulating region 21Z lies directly beneath the third conductive region 40C and the fourth conductive region 40D of the substrate semiconductor layer 40. Therefore, the wiring 25 of the uppermost wiring layer within the multilayer wiring structure 22 can be positioned in the region overlapping with the third conductive region 40C and the fourth conductive region 40D when viewed from above. Thus, the excellent effect of increased freedom in the arrangement of the wiring 25 within the multilayer wiring structure 22 is achieved.

[0123] [Seventh Embodiment]

[0124] Next, refer to Figure 14 The semiconductor device of the seventh embodiment will be described. Hereinafter, the device will be compared with that described above. Figures 1 to 4D The semiconductor device of the first embodiment, as illustrated in the accompanying drawings, has the same configuration, which is omitted from the description.

[0125] Figure 14 This is a cross-sectional view of the semiconductor device according to the seventh embodiment. In the first embodiment ( Figure 2 In the first embodiment, the substrate 20 is in contact with the adhesive layer 21. In contrast, in the seventh embodiment, an insulating layer 23 is disposed between the substrate 20 and the adhesive layer 21. The insulating layer 23 is made of inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.

[0126] Next, the superior effects of the seventh embodiment will be explained.

[0127] Similar to the first embodiment, the heat dissipation characteristics of the first transistor 41 can be improved in the seventh embodiment. Furthermore, in the seventh embodiment, the insulation between the semiconductor element, such as the first transistor 41, disposed on the substrate semiconductor layer 40 and the substrate 20 can be improved.

[0128] [Eighth Embodiment]

[0129] Next, refer to Figure 15 The semiconductor device of the eighth embodiment will be described. Hereinafter, the device will be compared with that described above. Figure 10 The semiconductor device of the fourth embodiment described herein has the same configuration, which is omitted from the description.

[0130] Figure 15This is a cross-sectional view of the semiconductor device according to the eighth embodiment. In the eighth embodiment, a multilayer wiring structure 22 is disposed between the substrate 20 and the adhesive layer 21. The multilayer wiring structure 22 includes a plurality of wirings 25 and a plurality of vias 26. A substrate-side transistor 27 is formed on the surface portion of the substrate 20. The substrate-side transistor 27 is, for example, a silicon-based MOS transistor or a silicon-based bipolar transistor.

[0131] The first metal region 21A included in the adhesive layer 21 is connected to at least one wiring 25 and via 26 within the multilayer wiring structure 22. Furthermore, the substrate-side transistor 27 is also electrically connected to at least one wiring 25 and via 26 within the multilayer wiring structure 22. For example, a metal region included in the adhesive layer 21 is connected to the substrate-side transistor 27 via wiring 25 and via 26 within the multilayer wiring structure 22. Alternatively, metal regions other than the first metal region 21A included in the adhesive layer 21 can be connected to wiring and vias within the multilayer wiring structure 22.

[0132] Next, the superior effects of the eighth embodiment will be explained.

[0133] Similar to the first embodiment, the heat dissipation characteristics of the first transistor 41 can be improved in the eighth embodiment. Furthermore, in the eighth embodiment, the electronic circuit composed of the substrate-side transistor 27 formed on the surface layer of the substrate 20 and the electronic circuit composed of semiconductor elements such as the first transistor 41 disposed on the substrate semiconductor layer 40 are electrically connected via the multilayer wiring structure 22. Therefore, compound semiconductor-based semiconductor elements and silicon semiconductor elements can be connected within the semiconductor device without passing through a module substrate or the like. This enables the miniaturization of the semiconductor module containing the semiconductor device.

[0134] Next, a variation of the eighth embodiment will be described. In the eighth embodiment, the wiring 25 and vias 26 within the multilayer wiring structure 22 are electrically connected to the substrate-side transistor 27 disposed below the adhesive layer 21 and the first transistor 41 disposed above the adhesive layer 21. As a variation, the wiring 25 and vias 26 within the multilayer wiring structure 22 can also be electrically connected to the substrate-side transistor 27 below the adhesive layer 21, but not to the components above the adhesive layer 21. According to this configuration, when connecting the substrate-side transistor 27 to the components above the adhesive layer 21, for example, the two can be electrically connected via conductor protrusions and wiring on the module substrate side, or via interconnecting wiring 82W without going through the module substrate. Figure 4D The two can be electrically connected. As another variation, the wiring 25 and through-hole 26 in the multilayer wiring structure 22 can be electrically connected to the components on the adhesive layer 21, but not electrically connected to the components on the substrate 20 below the multilayer wiring structure 22.

[0135] Alternatively, in the eighth embodiment, the first metal region 21A, which is electrically connected to the first transistor 41, may be electrically connected to the via 26 and wiring 25 in the multilayer wiring structure 22, but the first metal region 21A may not be connected to the via 26 and wiring 25 in the multilayer wiring structure 22.

[0136] Next, refer to Figure 16 as well as Figure 17 A modified example is described, in which the first metal region 21A is not connected to the through-hole 26 and wiring 25 in the multilayer wiring structure 22.

[0137] Figure 16 This is a cross-sectional view of a semiconductor device according to a variation of the eighth embodiment. The first metal region 21A is not connected to the wiring within the multilayer wiring structure 22. The first metal region 21A and the first conductive region 40A extend inwards, and a metal pattern 42CC is disposed on the extended portion of the first conductive region 40A. The metal pattern 42CC is covered by an interlayer insulating film 80. A first collector wiring 81C is disposed on the interlayer insulating film 80. The first collector wiring 81C is connected to the metal pattern 42CC through an opening in the interlayer insulating film 80.

[0138] A first collector pad 82C and a collector conductor protrusion 83C are disposed on the first collector wiring 81C. The configuration of the first collector pad 82C and the collector conductor protrusion 83C is the same as that of the first emitter pad 82E and the first conductor protrusion 83E. Solder 84 is placed on the collector conductor protrusion 83. Figure 16 In the variant shown, the collector of the first transistor 41 is connected to the electronic circuitry on the module substrate via a collector conductor protrusion 83C.

[0139] exist Figure 16 In the modified example shown, the first conductive region 40A is continuous from the region where the first transistor 41 is disposed to the region where the collector conductor protrusion 83C is disposed, but the first conductive region 40A may not necessarily be continuous. Even if the first conductive region 40A is not continuous, the collector of the first transistor 41 and the collector conductor protrusion 83C are electrically connected via the first metal region 21A.

[0140] Metal pattern 42CC, for example, in Figure 5A In the top view shown, it can be configured to run parallel to a column consisting of multiple first transistors 41. By configuring it in this way, it can be... Figure 5B The comparative example shown can shorten the length of the column composed of multiple first transistors 41.

[0141] Figure 17 This is a cross-sectional view of a semiconductor device according to another variation of the eighth embodiment. In this variation, the first metal region 21A is not connected to the wiring within the multilayer wiring structure 22. Figure 16 In the modified example shown, the collector conductor protrusion 83C is disposed on the element forming layer 202 when viewed from top. Figure 4D However, in this modified example, the collector conductor protrusion 83C is disposed on the inner side of the element forming layer 202 when viewed from above. Figure 4D The outside of ).

[0142] The first metal region 21A extends to the element forming layer 202 when viewed from above. Figure 4D The outer side of the substrate semiconductor layer 40 is the outer side of the substrate semiconductor layer 40. An interlayer insulating film 86 is disposed on the adhesive layer 21 on the outer side of the substrate semiconductor layer 40. A first collector pad 82C is disposed on the interlayer insulating film 86 on the outer side of the substrate semiconductor layer 40. The first collector pad 82C is connected to the first metal region 21A through an opening provided in the interlayer insulating film 86. A protective film 87 is disposed on the first collector pad 82C. A collector conductor protrusion 83C is disposed on the protective film 87. The collector conductor protrusion 83C is connected to the first collector pad 82C through an opening provided in the protective film 87. Solder 84 is placed on the collector conductor protrusion 83C.

[0143] The first collector electrode pad 82C, for example, in... Figure 5A In the top view shown, it can be configured to run parallel to a column consisting of multiple first transistors 41. By configuring it in this way, it can be... Figure 5B The comparative example shown can shorten the length of the column composed of multiple first transistors 41.

[0144] As in this variant, the collector electrode connected to the collector of the first transistor 41 can also be disposed in the area where the substrate semiconductor layer 40 is not disposed when viewed from above.

[0145] exist Figure 16 as well as Figure 17 In a variation of the eighth embodiment shown, a current path connected in parallel with the first metal region 21A can also be formed through wiring and vias within the multilayer wiring structure 22. This reduces the resistance between the collector of the first transistor 41 and the collector conductor protrusion 83C.

[0146] The above embodiments are illustrative examples, and of course, different substitutions or combinations of the components shown in the embodiments are possible. The same effects resulting from the same configuration in multiple embodiments are not mentioned sequentially for each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, those skilled in the art will recognize that various changes, improvements, combinations, etc., can be made.

Claims

1. A semiconductor device, wherein, have: A substrate, including a surface layer made of semiconductor material; An adhesive layer is disposed on the surface portion of the substrate and includes at least one metal region when viewed from above. as well as At least one semiconductor element is disposed on the adhesive layer described above. The aforementioned semiconductor element includes a first transistor disposed on a first metal region that serves as a metal region of the aforementioned adhesive layer. The first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also has: The first emitter electrode is disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; and A first conductor protrusion is disposed on and electrically connected to the first emitter electrode, and protrudes in a direction away from the substrate. The thermal conductivity of the semiconductor material on the surface of the substrate is higher than that of any one of the collector layer, base layer, and emitter layer of the first transistor. The aforementioned semiconductor element further includes a third transistor disposed on a third metal region that serves as a metal region of the aforementioned adhesive layer. The third transistor includes a collector layer electrically connected to the third metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also includes a third emitter electrode, which is disposed on the emitter layer of the third transistor and electrically connected to the emitter layer of the third transistor. No conductor protrusion is provided for connection to the third emitter electrode mentioned above.

2. The semiconductor device according to claim 1, wherein, The device is configured with a plurality of the aforementioned first transistors, and each of the aforementioned first transistors is configured with the aforementioned first emitter electrode. It also includes a first emitter wiring, which is disposed between the plurality of first emitter electrodes and the first conductor protrusion, and connects the plurality of first emitter electrodes to each other. The aforementioned first conductor protrusion is electrically connected to the aforementioned first emitter wiring.

3. The semiconductor device according to claim 2, wherein, The collector layer and base layer of the plurality of the aforementioned first transistors are respectively distributed continuously across the plurality of the aforementioned first transistors.

4. The semiconductor device according to claim 1, wherein, The aforementioned semiconductor element further includes a second transistor disposed on a second metal region that serves as a metal region of the aforementioned adhesive layer. The second transistor includes a collector layer electrically connected to the second metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also has: The second emitter electrode is disposed on the emitter layer of the second transistor and electrically connected to the emitter layer of the second transistor; and The second conductor protrusion is disposed on the second emitter electrode and electrically connected to the second emitter electrode, and protrudes in a direction away from the substrate.

5. The semiconductor device according to claim 1, wherein, It also includes a third collector electrode, which, when viewed from above, is disposed inside the third metal region and outside the third transistor, and is electrically connected to the third metal region.

6. The semiconductor device according to claim 1, wherein, The aforementioned semiconductor element further includes a diode disposed on a fourth metal region, which serves as a metal region of the aforementioned adhesive layer. The diode comprises a lower layer composed of a semiconductor of a first conductivity type disposed above the fourth metal region, and an upper layer composed of a semiconductor of a second conductivity type opposite to the first conductivity type disposed above the lower layer. It also has an upper electrode, which is disposed on the upper layer and electrically connected to the upper layer.

7. The semiconductor device according to claim 6, wherein, It also has a lower electrode, which, when viewed from above, is disposed inside the fourth metal region and outside the diode, and is electrically connected to the fourth metal region.

8. The semiconductor device according to claim 1, wherein, It also includes a substrate semiconductor layer disposed between the adhesive layer and the semiconductor element. The aforementioned substrate semiconductor layer includes conductive regions that overlap with the metal regions of the aforementioned adhesive layer when viewed from above. The conductive region of the aforementioned substrate semiconductor layer will be electrically connected to the metal region of the aforementioned adhesive layer, which overlaps with itself when viewed from above, and to the aforementioned semiconductor element on the aforementioned substrate semiconductor layer.

9. The semiconductor device according to any one of claims 1 to 8, wherein, It also includes an insulating layer disposed between the surface portion of the substrate and the adhesive layer.

10. The semiconductor device according to any one of claims 1 to 8, wherein, It also has a multilayer wiring structure disposed between the surface layer of the substrate and the adhesive layer.

11. The semiconductor device according to claim 10, wherein, The aforementioned multilayer wiring structure includes multiple wirings and multiple through-holes, and the metal region of the aforementioned adhesive layer is electrically connected to at least one wiring included in the aforementioned multilayer wiring structure.

12. The semiconductor device according to claim 11, wherein, It also includes at least one substrate-side transistor formed on the surface portion of the substrate. The aforementioned substrate-side transistors are connected to the wiring contained in the aforementioned multilayer wiring structure.

13. The semiconductor device according to claim 1, wherein, The surface layer of the aforementioned substrate is formed of silicon. The collector layer, base layer, and emitter layer of the aforementioned first transistor are formed of compound semiconductor.

14. A semiconductor device, wherein, have: A substrate, including a surface layer made of semiconductor material; An adhesive layer is disposed on the surface portion of the substrate and includes at least one metal region when viewed from above. as well as At least one semiconductor element is disposed on the adhesive layer described above. The aforementioned semiconductor element includes a first transistor disposed on a first metal region that serves as a metal region of the aforementioned adhesive layer. The first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also has: The first emitter electrode is disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; and A first conductor protrusion is disposed on and electrically connected to the first emitter electrode, and protrudes in a direction away from the substrate. The thermal conductivity of the semiconductor material on the surface of the substrate is higher than that of any one of the collector layer, base layer, and emitter layer of the first transistor. It also includes a substrate semiconductor layer disposed between the adhesive layer and the semiconductor element. The aforementioned substrate semiconductor layer, when viewed from above, includes multiple conductive regions and component separation regions outside the conductive regions. The collector layer of the first transistor is electrically connected to the metal region of the adhesive layer via the conductive region of the substrate semiconductor layer. The aforementioned adhesive layer includes an insulating region located on the outside of the metal region when viewed from above. The aforementioned substrate semiconductor layer further includes a third conductive region disposed on the insulating region of the aforementioned adhesive layer. The aforementioned semiconductor device further includes a third transistor disposed on the aforementioned third conductive region. The third transistor includes a collector layer electrically connected to the third conductive region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also has: The third emitter electrode is disposed on the emitter layer of the third transistor and electrically connected to the emitter layer of the third transistor; and The third collector electrode, when viewed from above, is disposed inside the third conductive region and outside the third transistor, and is electrically connected to the third conductive region.

15. The semiconductor device according to claim 14, wherein, It also includes an insulating layer disposed between the surface portion of the substrate and the adhesive layer.

16. The semiconductor device according to claim 14, wherein, It also has a multilayer wiring structure disposed between the surface layer of the substrate and the adhesive layer.

17. The semiconductor device according to claim 16, wherein, The aforementioned multilayer wiring structure includes multiple wirings and multiple through-holes, and the metal region of the aforementioned adhesive layer is electrically connected to at least one wiring included in the aforementioned multilayer wiring structure.

18. The semiconductor device according to claim 17, wherein, It also includes at least one substrate-side transistor formed on the surface portion of the substrate. The aforementioned substrate-side transistors are connected to the wiring contained in the aforementioned multilayer wiring structure.

19. The semiconductor device according to claim 14, wherein, The surface layer of the aforementioned substrate is formed of silicon. The collector layer, base layer, and emitter layer of the aforementioned first transistor are formed of compound semiconductor.

20. A semiconductor device, wherein, have: A substrate, including a surface layer made of semiconductor material; An adhesive layer is disposed on the surface portion of the substrate and includes at least one metal region when viewed from above. as well as At least one semiconductor element is disposed on the adhesive layer described above. The aforementioned semiconductor element includes a first transistor disposed on a first metal region that serves as a metal region of the aforementioned adhesive layer. The first transistor includes a collector layer electrically connected to the first metal region, a base layer disposed on the collector layer, and an emitter layer disposed on the base layer. It also has: The first emitter electrode is disposed on the emitter layer of the first transistor and electrically connected to the emitter layer; and A first conductor protrusion is disposed on and electrically connected to the first emitter electrode, and protrudes in a direction away from the substrate. The thermal conductivity of the semiconductor material on the surface of the substrate is higher than that of any one of the collector layer, base layer, and emitter layer of the first transistor. It also includes a substrate semiconductor layer disposed between the adhesive layer and the semiconductor element. The aforementioned substrate semiconductor layer, when viewed from above, includes multiple conductive regions and component separation regions outside the conductive regions. The collector layer of the first transistor is electrically connected to the metal region of the adhesive layer via the conductive region of the substrate semiconductor layer. The aforementioned adhesive layer includes an insulating region located on the outside of the metal region when viewed from above. The aforementioned substrate semiconductor layer further includes a fourth conductive region disposed on the insulating region of the aforementioned adhesive layer. The aforementioned semiconductor device further includes a diode disposed on the aforementioned fourth conductive region. The diode described above includes a lower layer composed of a semiconductor of a first conductivity type disposed above the fourth conductive region, and an upper layer disposed above the lower layer and composed of a semiconductor of a second conductivity type opposite to the first conductivity type. It also has: The upper electrode is disposed on the upper layer and electrically connected to the upper layer; and The lower electrode, when viewed from above, is disposed inside the fourth conductive region and outside the diode, and is electrically connected to the fourth conductive region.

21. The semiconductor device according to claim 20, wherein, It also includes an insulating layer disposed between the surface portion of the substrate and the adhesive layer.

22. The semiconductor device of claim 20, wherein, It also has a multilayer wiring structure disposed between the surface layer of the substrate and the adhesive layer.

23. The semiconductor device according to claim 22, wherein, The aforementioned multilayer wiring structure includes multiple wirings and multiple through-holes, and the metal region of the aforementioned adhesive layer is electrically connected to at least one wiring included in the aforementioned multilayer wiring structure.

24. The semiconductor device according to claim 23, wherein, It also includes at least one substrate-side transistor formed on the surface portion of the substrate. The aforementioned substrate-side transistors are connected to the wiring contained in the aforementioned multilayer wiring structure.

25. The semiconductor device according to claim 20, wherein, The surface layer of the aforementioned substrate is formed of silicon. The collector layer, base layer, and emitter layer of the aforementioned first transistor are formed of compound semiconductor.

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