Method and apparatus for detecting semiconductor structure, semiconductor structure and memory
By setting up various test structures to detect the capacitance difference of FinFETs, the problem of inaccurate detection of parasitic capacitance in FinFETs in existing technologies is solved, enabling accurate calculation and performance analysis of parasitic capacitance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-01-10
- Publication Date
- 2026-05-29
Smart Images
Figure CN114388477B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method, apparatus, semiconductor structure and memory for detecting semiconductor structures. Background Technology
[0002] Currently, the parasitic capacitance of transistors is detected by setting up multiple test structures for the transistor. Different test structures have a different number of source-drain contacts connected to the source and drain regions, and the parasitic capacitance of the transistor is calculated by measuring the capacitance of different test structures. However, if the source and drain regions (including the source and drain regions) of the transistor (such as a FinFET) are small, and there is only one source-drain contact connected to the source and drain regions (i.e., one source contact connected to the source region and one drain contact connected to the drain region), then the above method cannot accurately detect the parasitic capacitance of the transistor. Summary of the Invention
[0003] This invention provides a method, apparatus, semiconductor structure, and memory for detecting semiconductor structures, which can improve the accuracy of detecting the parasitic capacitance of a target transistor.
[0004] This invention provides a method for detecting a semiconductor structure, the semiconductor structure including a first test structure and a second test structure of a target transistor; the first test structure includes a first well region, a first source-drain region located in the first well region, a first gate structure located on the first well region, a first source-drain contact located on and connected to the first source-drain region, and a source-drain connection layer located on and connected to the first source-drain contact, wherein the first well region and the first source-drain region have the same conductivity type; the second test structure includes a second well region, a second source-drain region located in the second well region, and a second gate structure located on the second well region, wherein the second well region and the second source-drain region have the same conductivity type.
[0005] The method includes:
[0006] Detect the first capacitance between the first well region and the first gate structure in the first test structure;
[0007] Detect the second capacitance between the second well region and the second gate structure in the second test structure;
[0008] Calculate the total parasitic capacitance of the target transistor based on the first capacitance and the second capacitance.
[0009] Further, the step of calculating the parasitic capacitance of the target transistor based on the first capacitance and the second capacitance includes:
[0010] Calculate the first difference between the first capacitor and the second capacitor, and use the first difference as the total parasitic capacitance of the target transistor.
[0011] Furthermore, the semiconductor structure also includes a third test structure for the target transistor, the third test structure including a third well region, a third source-drain region located in the third well region, a third gate structure located on the third well region, and a second source-drain contact located on and connected to the third source-drain region, wherein the third well region and the third source-drain region have the same conductivity type.
[0012] The method further includes:
[0013] Detect the third capacitance between the third well region and the third gate structure in the third test structure;
[0014] Calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor;
[0015] The contact parasitic capacitance of the target transistor is calculated based on the second capacitor and the third capacitor.
[0016] Further, the step of calculating the parasitic capacitance of the connection layer of the target transistor based on the first capacitance and the third capacitance includes:
[0017] Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
[0018] Further, the step of calculating the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor includes:
[0019] Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
[0020] Furthermore, the semiconductor structure also includes the target transistor, which includes a target well region, a target source / drain region located in the target well region, a target gate structure located on the target well region, a target source / drain contact located on and connected to the target source / drain region, and a target source / drain connection layer located on and connected to the target source / drain contact; the target well region and the target source / drain region have different conductivity types;
[0021] The method further includes:
[0022] Short-circuit the target source-drain regions in the target transistor;
[0023] Detect the fourth capacitance between the target source / drain region and the target gate structure;
[0024] Calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and use the fifth difference as the actual capacitance of the target transistor.
[0025] This invention also provides a semiconductor structure, including a first test structure and a second test structure for a target transistor;
[0026] The first test structure includes:
[0027] First well region;
[0028] The first source-drain region is located in the first well region, and the first well region and the first source-drain region have the same conductivity type.
[0029] A first gate structure located on the first well region;
[0030] A first source-drain contact located on and connected to the first source-drain region; and,
[0031] A source-drain connection layer located on and connected to the first source-drain contact;
[0032] The second test structure includes:
[0033] Second trap region;
[0034] The second source / drain region is located within the second well region, and the second well region has the same conductivity type as the second source / drain region; and,
[0035] The second gate structure is located on the second well region.
[0036] Furthermore, the semiconductor structure also includes a third test structure for the target transistor;
[0037] The third test structure includes:
[0038] Third trap region;
[0039] The third source / drain region is located in the third well region, and the third well region has the same conductivity type as the third source / drain region;
[0040] The third gate structure located on the third well region; and,
[0041] The second source-drain contact is located on and connected to the third source-drain region.
[0042] Furthermore, the semiconductor structure also includes the target transistor;
[0043] The target transistor includes:
[0044] Target trap area;
[0045] The target source / drain region is located in the target well region, and the target well region has a different conductivity type from the target source / drain region.
[0046] The target gate structure located on the target well region;
[0047] A target source / drain contact located on and connected to the target source / drain region; and,
[0048] The target source-drain connection layer is located on and connected to the target source-drain contact.
[0049] Furthermore, the target transistor is a fin field-effect transistor.
[0050] This invention also provides a semiconductor structure detection device, the semiconductor structure including a first test structure and a second test structure of a target transistor; the first test structure includes a first well region, a first source-drain region located in the first well region, a first gate structure located on the first well region, a first source-drain contact located on and connected to the first source-drain region, and a source-drain connection layer located on and connected to the first source-drain contact, wherein the first well region and the first source-drain region have the same conductivity type; the second test structure includes a second well region, a second source-drain region located in the second well region, and a second gate structure located on the second well region, wherein the second well region and the second source-drain region have the same conductivity type;
[0051] The device includes:
[0052] The first detection module is used to detect the first capacitance between the first well region and the first gate structure in the first test structure.
[0053] The second detection module is used to detect the second capacitance between the second well region and the second gate structure in the second test structure; and...
[0054] A first calculation module is used to calculate the total parasitic capacitance of the target transistor based on the first capacitor and the second capacitor.
[0055] Furthermore, the first calculation module is specifically used for:
[0056] Calculate the first difference between the first capacitor and the second capacitor, and use the first difference as the total parasitic capacitance of the target transistor.
[0057] Furthermore, the semiconductor structure also includes a third test structure for the target transistor, the third test structure including a third well region, a third source-drain region located in the third well region, a third gate structure located on the third well region, and a second source-drain contact located on and connected to the third source-drain region, wherein the third well region and the third source-drain region have the same conductivity type.
[0058] The device further includes:
[0059] The third detection module is used to detect the third capacitance between the third well region and the third gate structure in the third test structure.
[0060] The second calculation module is used to calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor; and,
[0061] The third calculation module is used to calculate the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor.
[0062] Furthermore, the second calculation module is specifically used for:
[0063] Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
[0064] Furthermore, the third calculation module is specifically used for:
[0065] Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
[0066] Furthermore, the semiconductor structure also includes the target transistor, which includes a target well region, a target source / drain region located in the target well region, a target gate structure located on the target well region, a target source / drain contact located on and connected to the target source / drain region, and a target source / drain connection layer located on and connected to the target source / drain contact; the target well region and the target source / drain region have different conductivity types;
[0067] The device further includes:
[0068] A shorting module is used to short-circuit the target source-drain region in the target transistor.
[0069] The fourth detection module is used to detect the fourth capacitance between the target source / drain region and the target gate structure; and,
[0070] The fourth calculation module is used to calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and to use the fifth difference as the actual capacitance of the target transistor.
[0071] This invention also provides a memory, including a memory array structure and a peripheral structure connected to the memory array structure;
[0072] The peripheral structure includes the aforementioned semiconductor structure.
[0073] The beneficial effects of this invention are as follows: By setting a first test structure and a second test structure for the target transistor, the first test structure has source-drain contacts and a source-drain connection layer, and the well region of the first test structure has the same conductivity type as the source-drain region. The second test structure does not have source-drain contacts and a source-drain connection layer, and the well region of the second test structure has the same conductivity type as the source-drain region. This allows for the detection of the first capacitance between the well region and the gate structure in the first test structure, the detection of the second capacitance between the well region and the gate structure in the second test structure, and the calculation of the total parasitic capacitance of the target transistor based on the first and second capacitances. This effectively improves the accuracy of parasitic capacitance detection for the target transistor and helps in subsequent performance analysis of the target transistor. Attached Figure Description
[0074] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0075] Figure 1a This is a schematic diagram of a target transistor in a semiconductor structure provided in an embodiment of the present invention;
[0076] Figure 1b This is a schematic diagram of a first test structure in a semiconductor structure provided in an embodiment of the present invention;
[0077] Figure 1c This is a schematic diagram of a third test structure in a semiconductor structure provided in an embodiment of the present invention;
[0078] Figure 1d This is a schematic diagram of a second test structure in a semiconductor structure provided in an embodiment of the present invention;
[0079] Figure 2 A schematic flowchart of a semiconductor structure detection method provided in an embodiment of the present invention;
[0080] Figure 3This is a schematic diagram of a semiconductor structure detection device provided in an embodiment of the present invention;
[0081] Figure 4 This is a schematic diagram of a memory structure provided in an embodiment of the present invention. Detailed Implementation
[0082] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, the invention can be embodied in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.
[0083] In the description of this invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.
[0084] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.
[0086] See Figures 1a to 1d This is a schematic diagram of a semiconductor structure provided in an embodiment of the present invention. The semiconductor structure may include a first test structure and a second test structure for the target transistor, such as... Figure 1b and Figure 1d As shown, Figure 1b This is a schematic diagram of the first test structure 10b for the target transistor. Figure 1d This is a schematic diagram of the second test structure 10d for the target transistor. The semiconductor structure may also include a third test structure for the target transistor, such as... Figure 1c As shown, Figure 1c This is a schematic diagram of the third test structure 10c for the target transistor. The semiconductor structure may also include the target transistor, such as... Figure 1a As shown, Figure 1a This is a schematic diagram of the target transistor 10a.
[0087] The semiconductor structure can be applied in a memory, which includes a memory array structure and peripheral structures connected to the memory array structure. The target transistor 10a can be a transistor in the peripheral structure, and the first test structure 10b, the second test structure 10d, and the third test structure 10c can refer to test structures used to detect parasitic capacitance in the target transistor 10a.
[0088] Specifically, such as Figure 1a As shown, the target transistor 10a may include a substrate 1, which may be a silicon substrate, a germanium substrate, or a semiconductor substrate containing other elements. The substrate 1 may be doped with trace amounts of trivalent elements, such as boron, indium, gallium, and aluminum, to form a P-type semiconductor substrate; or it may be doped with trace amounts of pentavalent elements, such as phosphorus, antimony, and arsenic, to form an N-type semiconductor substrate. In this embodiment, the substrate 1 may be a P-type semiconductor substrate.
[0089] The target transistor 10a may further include a target well region 11a, which is located in the substrate 1 and disposed near the upper surface of the substrate 1. Through ion implantation, the target well region 11a can be formed into a P-type well region or an N-type well region. In this embodiment, the target well region 11a can be a P-type well region (PW).
[0090] The target transistor 10a may further include a target source / drain region 12a and a target gate structure 13a. The target source / drain region 12a is located within the target well region 11a, and may include a target source region S1 and a target drain region D1 spaced apart. The target source region S1 and the target drain region D1 have the same conductivity type, meaning they are doped with the same type of ions. The target source / drain region 12a has a different conductivity type than the target well region 11a, meaning they are doped with different types of ions. In this embodiment, the target well region 11a may be doped with P-type ions, and the target source / drain region 12a may be doped with N-type ions. The target gate structure 13a is located on the target well region 11a between the target source region S1 and the target drain region D1. Specifically, the gate structure 13a includes a target gate oxide layer (not shown in the figure) located on the target well region 11a between the target source region S1 and the target drain region D1, and a target gate layer (not shown in the figure) located on the target gate oxide layer. The target gate oxide layer includes, but is not limited to, oxides such as silicon oxide, and the target gate layer includes, but is not limited to, polysilicon.
[0091] In some embodiments, the target transistor 10a may be a fin field-effect transistor, and the target well region 11a includes a fin protruding from the surface of the substrate 1. The fin has an isolation layer 14 on its periphery, and the isolation layer 14 is disposed near the bottom of the sidewall of the fin. The target source-drain region 12a is located in the fin, and the gate structure 13a is located on the fin and extends along the opposite sidewalls of the fin to the isolation layer 14.
[0092] The target transistor 10a may further include a target source-drain contact 15a and a target gate contact 16a. The target source-drain contact 15a is located on and connected to the target source-drain region 12a. Specifically, the target source-drain contact 15a may include a target source contact 151a located on and connected to the target source region S1, and a target drain contact 152a located on and connected to the target drain region D1. In this embodiment, the target source-drain region 12a may be small, such that the target source-drain region 12a has only one target source-drain contact 15a (including one target source contact 151a and one target drain contact 152a). The target gate contact 16a is located on and connected to the target gate structure 13a. Specifically, the target gate contact 16a is connected to the target gate layer in the target gate structure 13a. The target source-drain contact 15a and the target gate contact 16a include, but are not limited to, tungsten, cobalt, copper, and aluminum.
[0093] The orthographic projection of the target source-drain contact 15a onto the first plane partially overlaps with the orthographic projection of the target gate structure 13a onto the first plane, resulting in a contact parasitic capacitance C between the target source-drain contact 15a and the target gate structure 13a. g2c The first plane is the plane containing the side surface of the target gate structure 13a (i.e., the surface of the target gate structure 13a near the target source-drain contact 15a).
[0094] The target transistor 10a may further include a target source-drain connection layer 17a and a target gate connection layer 18a disposed on the same layer. The target source-drain connection layer 17a is located on and connected to the target source-drain contact 15a. Specifically, the target source-drain connection layer 17a includes a target source connection layer 171a located on and connected to the target source contact 151a, and a target drain connection layer 172a located on and connected to the target drain contact 152a. The target gate connection layer 18a is located on and connected to the target gate contact 16a. The target source-drain connection layer 17a and the target gate connection layer 18a include, but are not limited to, tungsten, cobalt, copper, and aluminum.
[0095] The orthographic projection of the target source-drain connection layer 17a onto the second plane may partially overlap with the orthographic projection of the target gate structure 13a onto the second plane, resulting in a parasitic capacitance C between the target source-drain connection layer 17a and the target gate structure 13a. g2m The second plane is the plane containing the upper surface of the target gate structure 13a (i.e., the surface of the target gate structure 13a near the target source-drain connection layer 17a).
[0096] like Figure 1b As shown, the first test structure 10b of the target transistor 10a is a test structure based on the structure of the target transistor 10a. The first test structure 10b may include a first well region 11b located in the substrate 1, and the first well region 11b is disposed close to the upper surface of the substrate 1. Through ion implantation, the first well region 11b can be formed into a P-type well region or an N-type well region, but the conductivity type of the first well region 11b is different from that of the target well region 11a. When the target well region 11a is a P-type well region, the first well region 11b is an N-type well region (NW).
[0097] The first test structure 10b may further include a first source-drain region 12b and a first gate structure 13b. The first source-drain region 12b is located in the first well region 11b, and the first source-drain region 12b may include a first source region S2 and a first drain region D2 spaced apart. The first source region S2 and the first drain region D2 have the same conductivity type. The first source-drain region 12b has the same conductivity type as the first well region 11b, so that the first source region S2 and the first drain region D2 can be short-circuited. In this embodiment, both the first source-drain region 12b and the first well region 11b may be doped with N-type ions. The first gate structure 13b is located on the first well region 11b, and the first gate structure 13b includes a first gate oxide layer (not shown in the figure) located on the first well region 11b, and a first gate layer (not shown in the figure) located on the first gate oxide layer.
[0098] The first source-drain region 12b has the same structure as the target source-drain region 12a, and the first gate structure 13b has the same structure as the target gate structure 13a. That is, the first source-drain region 12b and the target source-drain region 12a have the same size, shape and doped ions, and the first gate structure 13b and the target gate structure 13a have the same size, shape and material. Moreover, the positional relationship between the first source-drain region 12b and the first gate structure 13b is the same as the positional relationship between the target source-drain region 12a and the target gate structure 13a.
[0099] The first test structure 10b may further include a first source-drain contact 15b and a first gate contact 16b. The first source-drain contact 15b is located on and connected to the first source-drain region 12b. Specifically, the first source-drain contact 15b may include a first source contact 151b located on and connected to the first source region S2, and a first drain contact 152b located on and connected to the first drain region D2. The first gate contact 16b is located on and connected to the first gate structure 13b. Specifically, the first gate contact 16b is connected to the first gate layer in the first gate structure 13b.
[0100] The first source-drain contact 15b has the same structure as the target source-drain contact 15a, meaning that the size, shape, number, and material of the first source-drain contact 15b and the target source-drain contact 15a are exactly the same. Furthermore, the positional relationship between the first source-drain contact 15b and the first gate structure 13b is the same as the positional relationship between the target source-drain contact 15a and the target gate structure 13a. Therefore, a contact parasitic capacitance C also exists between the first source-drain contact 15b and the first gate structure 13b. g2c And the parasitic capacitance C of this contact g2c The contact parasitic capacitance C between the target source-drain contact 15a and the target gate structure 13a g2c They are the same size.
[0101] The first test structure 10b may further include a source-drain connection layer 17b and a first gate connection layer 18b disposed on the same layer. The source-drain connection layer 17b is located on and connected to the first source-drain contact 15b. Specifically, the source-drain connection layer 17b includes a source connection layer 171b located on and connected to the first source contact 151b, and a drain connection layer 172b located on and connected to the first drain contact 152b. The first gate connection layer 18b is located on and connected to the first gate contact 16b.
[0102] The source-drain connection layer 17b has the same structure as the target source-drain connection layer 17a, that is, the source-drain connection layer 17b has the same size, shape, and material as the target source-drain connection layer 17a, and the positional relationship between the source-drain connection layer 17b and the first gate structure 13b is the same as the positional relationship between the target source-drain connection layer 17a and the target gate structure 13a. Therefore, a parasitic capacitance C also exists between the source-drain connection layer 17b and the first gate structure 13b. g2m And the parasitic capacitance C of the connection layer g2m Parasitic capacitance C of the connection layer between the target source-drain connection layer 17a and the target gate structure 13a g2m They are the same size.
[0103] Therefore, the difference between the first test structure 10b and the target transistor 10a is that the first well region 11b of the first test structure 10b and the target well region 11a of the target transistor 10a have different conductivity types. For example, the target well region 11a is a P-type well region PW, and the first well region 11b is an N-type well region NW.
[0104] like Figure 1c As shown, the third test structure 10c of the target transistor 10a is a test structure based on the structure of the target transistor 10a. The third test structure 10c may include a third well region 11c located in the substrate 1, and the third well region 11c is disposed close to the upper surface of the substrate 1. Through ion implantation, the third well region 11c can be formed into a P-type well region or an N-type well region, but the conductivity type of the third well region 11c is different from that of the target well region 11a. When the target well region 11a is a P-type well region, the third well region 11c is an N-type well region (NW).
[0105] The third test structure 10c may further include a third source-drain region 12c and a third gate structure 13c. The third source-drain region 12c is located in the third well region 11c, and the third source-drain region 12c may include a third source region S3 and a third drain region D3 spaced apart. The third source region S3 and the third drain region D3 have the same conductivity type. The third source-drain region 12c and the third well region 11c have the same conductivity type, so that the third source region S3 and the third drain region D3 can be short-circuited. In this embodiment, both the third source-drain region 12c and the third well region 11c may be doped with N-type ions. The third gate structure 13c is located on the third well region 11c, and the third gate structure 13c includes a third gate oxide layer (not shown in the figure) located on the third well region 11c, and a third gate layer (not shown in the figure) located on the third gate oxide layer.
[0106] The third source-drain region 12c has the same structure as the target source-drain region 12a, and the third gate structure 13c has the same structure as the target gate structure 13a. That is, the third source-drain region 12c has the same size, shape and doped ions as the target source-drain region 12a, and the third gate structure 13c has the same size, shape and material as the target gate structure 13a. Furthermore, the positional relationship between the third source-drain region 12c and the third gate structure 13c is the same as the positional relationship between the target source-drain region 12a and the target gate structure 13a.
[0107] The third test structure 10c may further include a third source-drain contact 15c and a third gate contact 16c. The third source-drain contact 15c is located on and connected to the third source-drain region 12c. Specifically, the third source-drain contact 15c may include a third source contact 151c located on and connected to the third source region S3, and a third drain contact 152c located on and connected to the third drain region D3. The third gate contact 16c is located on and connected to the third gate structure 13c. Specifically, the third gate contact 16c is connected to the third gate layer in the third gate structure 13c.
[0108] The third source-drain contact 15c has the same structure as the target source-drain contact 15a, meaning that the size, shape, number, and material of the third source-drain contact 15c and the target source-drain contact 15a are exactly the same. Furthermore, the positional relationship between the third source-drain contact 15c and the third gate structure 13c is the same as the positional relationship between the target source-drain contact 15a and the target gate structure 13a. Therefore, a parasitic capacitance C also exists between the third source-drain contact 15c and the third gate structure 13c. g2c And the parasitic capacitance C of this contact g2c The contact parasitic capacitance C between the target source-drain contact 15a and the target gate structure 13a g2c They are the same size.
[0109] The third test structure 10c may further include a third gate connection layer 18c, which is located on and connected to the third gate contact 16c. The third test structure 10c does not have a source-drain connection layer, meaning it does not have a parasitic capacitance C for the connection layer. g2m .
[0110] Therefore, the difference between the third test structure 10c and the target transistor 10a is that the third well region 11c of the third test structure 10c has a different conductivity type than the target well region 11a of the target transistor 10a, and the third test structure 10c does not have a source-drain connection layer. The difference between the third test structure 10c and the first test structure 10b is that the first test structure 10b has a source-drain connection layer 17b, while the third test structure 10c does not.
[0111] like Figure 1d As shown, the second test structure 10d of the target transistor 10a is a test structure based on the structure of the target transistor 10a. The second test structure 10d may include a second well region 11d located in the substrate 1, and the second well region 11d is disposed close to the upper surface of the substrate 1. Through ion implantation, the second well region 11d can be formed into a P-type well region or an N-type well region, but the conductivity type of the second well region 11d is different from that of the target well region 11a. When the target well region 11a is a P-type well region PW, the second well region 11d is an N-type well region NW.
[0112] The second test structure 10d may further include a second source-drain region 12d and a second gate structure 13d. The second source-drain region 12d is located in the second well region 11d, and the second source-drain region 12d may include a second source region S4 and a second drain region D4 spaced apart. The second source region S4 and the second drain region D4 have the same conductivity type. The second source-drain region 12d and the second well region 11d have the same conductivity type, so that the second source region S4 and the second drain region D4 can be short-circuited. In this embodiment, both the second source-drain region 12d and the second well region 11d may be doped with N-type ions. The second gate structure 13d is located on the second well region 11d, and the second gate structure 13d includes a second gate oxide layer (not shown in the figure) located on the second well region 11d, and a second gate layer (not shown in the figure) located on the second gate oxide layer.
[0113] The second source / drain region 12d has the same structure as the target source / drain region 12a, and the second gate structure 13d has the same structure as the target gate structure 13a. That is, the second source / drain region 12d has the same size, shape, and doped ions as the target source / drain region 12a, and the second gate structure 13d has the same size, shape, and material as the target gate structure 13a. Furthermore, the positional relationship between the second source / drain region 12d and the second gate structure 13d is the same as the positional relationship between the target source / drain region 12a and the target gate structure 13a.
[0114] The second test structure 10d may further include a second gate contact 16d. The second gate contact 16d is located on and connected to the second gate structure 13d; specifically, the second gate contact 16d is connected to the second gate layer in the second gate structure 13d. The second test structure 10d does not have source-drain contacts, meaning it does not have contact parasitic capacitance C. g2c .
[0115] The second test structure 10d may further include a second gate connection layer 18d, which is located on and connected to the second gate contact 16d. The second test structure 10d does not have a source-drain connection layer, meaning it does not have a parasitic capacitance C. g2m .
[0116] Therefore, the difference between the second test structure 10d and the target transistor 10a lies in the different conductivity types of the second well region 11d of the second test structure 10d and the target well region 11a of the target transistor 10a, and the second test structure 10d does not have source-drain contacts and a source-drain connection layer. The difference between the second test structure 10d and the first test structure 10b lies in the absence of source-drain contacts and a source-drain connection layer in the third test structure 10c. The difference between the second test structure 10d and the third test structure 10c lies in the absence of source-drain contacts in the second test structure 10d.
[0117] Based on the target transistor 10a, the first test structure 10b, the second test structure 10d, and the third test structure 10c in the semiconductor structure, the parasitic capacitance of the target transistor 10a can be detected.
[0118] See Figure 2 This is a flowchart illustrating the semiconductor structure detection method provided in this embodiment of the invention.
[0119] like Figure 2 As shown, this embodiment provides a method for detecting a semiconductor structure, wherein the semiconductor structure is the one described above, and will not be elaborated further here. The method includes steps 101 to 103, as follows:
[0120] Step 101: Detect the first capacitance between the first well region and the first gate structure in the first test structure.
[0121] In this embodiment of the invention, since the first source-drain region 12b and the first well region 11b in the first test structure 10b have the same conductivity type, the first source region S2 and the first drain region D2 in the first source-drain region 12b are shorted through the first well region 11b. When performing capacitance detection on the first test structure 10b, a test signal is applied to the first gate layer in the first well region 11b and the first gate structure 13b, respectively, to detect the first capacitance C1 between the first well region 11b and the first gate structure 13b.
[0122] Because there is a contact parasitic capacitance C in the first test structure 10b. g2c and the parasitic capacitance C of the connection layer g2m Therefore, the first capacitor C1 includes, in addition to the actual capacitor C to be detected, m1 It also includes contact parasitic capacitance C g2c and the parasitic capacitance C of the connection layer g2m That is, C1 = C m1 +C g2c +C g2m .
[0123] Step 102: Detect the second capacitance between the second well region and the second gate structure in the second test structure.
[0124] In this embodiment of the invention, since the second source-drain region 12d and the second well region 11d in the second test structure 10d have the same conductivity type, the second source region S4 and the second drain region D4 in the second source-drain region 12d are shorted through the second well region 11d. When performing capacitance detection on the second test structure 10d, a test signal is applied to the second gate layer in the second well region 11d and the second gate structure 13d, respectively, to detect the second capacitance C3 between the second well region 11d and the second gate structure 13d.
[0125] Since there is no contact parasitic capacitance C in the second test structure 10d. g2c and the parasitic capacitance C of the connection layer g2m Therefore, the second capacitor C3 only includes the actual capacitance C that needs to be detected. m3 That is, C3 = C m3 .
[0126] Step 103: Calculate the total parasitic capacitance of the target transistor based on the first capacitor and the second capacitor.
[0127] In this embodiment of the invention, the total parasitic capacitance includes the contact parasitic capacitance C. g2c and the parasitic capacitance C of the connection layerg2m Since the difference between the first test structure 10b and the second test structure 10d is that the second test structure 10d does not have a source-drain connection layer and source-drain contacts, while other structures are the same, the actual capacitance C to be detected by the first test structure 10b is... m1 The actual capacitance C to be detected in the second test structure 10d. m3 Same, i.e., C m1 =C m3 Therefore, the total parasitic capacitance of the first test structure 10b can be calculated based on the first capacitor C1 and the second capacitor C3. The contact parasitic capacitance C of the first test structure 10b is... g2c Parasitic capacitance C at the contact with the target transistor 10a g2c Similarly, the parasitic capacitance C of the connection layer in the first test structure 10b is... g2m Parasitic capacitance C of the connection layer with the target transistor 10a g2m Since they are the same, the total parasitic capacitance of the first test structure 10b is the same as the total parasitic capacitance of the target transistor 10a.
[0128] Specifically, step 103, which involves calculating the parasitic capacitance of the target transistor based on the first capacitance and the second capacitance, includes:
[0129] Calculate the first difference between the first capacitor and the second capacitor, and use the first difference as the total parasitic capacitance of the target transistor.
[0130] Calculate the first difference between the first capacitor C1 and the second capacitor C3, i.e., C1 - C3 = C m1 +C g2c +C g2m -C m3 =C g2c +C g2m And C g2c +C g2m This is the total parasitic capacitance of the target transistor 10a.
[0131] This embodiment can accurately calculate the total parasitic capacitance of the target transistor 10a, which helps to analyze the impact of the total parasitic capacitance on the performance of the target transistor 10a.
[0132] This embodiment can also calculate the contact parasitic capacitance and the connection layer parasitic capacitance of the target transistor 10a respectively.
[0133] Furthermore, the method also includes:
[0134] Detect the third capacitance between the third well region and the third gate structure in the third test structure;
[0135] Calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor;
[0136] The contact parasitic capacitance of the target transistor is calculated based on the second capacitor and the third capacitor.
[0137] Since the third source-drain region 12c and the third well region 11c in the third test structure 10c have the same conductivity type, the third source region S3 and the third drain region D3 in the third source-drain region 12c are shorted through the third well region 11c. When performing capacitance detection on the third test structure 10c, the test signal is applied to the third gate layer in the third well region 11c and the third gate structure 13c respectively to detect the third capacitance C2 between the third well region 11c and the third gate structure 13c.
[0138] Because of the contact parasitic capacitance C in the third test structure 10c. g2c Therefore, the third capacitor C2 includes not only the actual capacitor C that needs to be detected, but also... m2 It also includes contact parasitic capacitance C g2c That is, C2 = C m2 +C g2c .
[0139] The difference between the third test structure 10c and the first test structure 10b is that the third test structure 10c does not have a source-drain connection layer, while the other structures are the same. Therefore, the actual capacitance C to be detected by the first test structure 10b is different. m1 The actual capacitance C to be tested in the third test structure 10c m2 Same, i.e., C m1 =C m2 The contact parasitic capacitance C in the first test structure 10b g2c Parasitic capacitance C of the contacts in the third test structure 10c g2c The same applies. Therefore, the parasitic capacitance C of the connection layer of the first test structure 10b can be calculated based on the first capacitor C1 and the third capacitor C2. g2m The parasitic capacitance C of the connection layer of the first test structure 10b... g2m Parasitic capacitance C of the connection layer with the target transistor 10a g2m The same applies, therefore the parasitic capacitance C of the connection layer of the first test structure 10b is... g2m This refers to the parasitic capacitance C of the connection layer of the target transistor 10a. g2m .
[0140] Specifically, the step of calculating the parasitic capacitance of the connection layer of the target transistor based on the first capacitance and the third capacitance includes:
[0141] Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
[0142] Calculate the second difference between the first capacitor C1 and the third capacitor C2, i.e., C1 - C2 = C m1 +C g2c +C g2m -(C m2 +C g2c ) = C g2m And C g2m This refers to the parasitic capacitance of the connection layer of the target transistor 10a.
[0143] This embodiment calculates the parasitic capacitance of the connection layer of the target transistor 10a, which helps in the subsequent analysis of the impact of the setting of the target source-drain connection layer 17a on the performance of the target transistor 10a.
[0144] The difference between the third test structure 10c and the second test structure 10d is that the second test structure 10d does not have source-drain contacts, while the other structures are the same. Therefore, the actual capacitance C to be detected by the second test structure 10d is different. m3 The actual capacitance C to be tested in the third test structure 10c m2 Same, i.e., C m3 =C m2 Therefore, the contact parasitic capacitance C of the third test structure 10c can be calculated based on the third capacitor C2 and the second capacitor C3. g2c The parasitic capacitance C at the contact of the third test structure 10c. g2c Parasitic capacitance C at the contact with the target transistor 10a g2c The same applies, therefore the contact parasitic capacitance C of the third test structure 10c is... g2c This refers to the contact parasitic capacitance C of the target transistor 10a. g2c .
[0145] Specifically, the step of calculating the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor includes:
[0146] Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
[0147] Calculate the third difference between the third capacitor C2 and the second capacitor C3, i.e., C2 - C3 = C m2 +C g2c -C m3 =C g2c And C g2c This refers to the contact parasitic capacitance of the target transistor 10a.
[0148] This embodiment calculates the contact parasitic capacitance of the target transistor 10a, which helps to analyze the impact of the setting of the target source-drain contact 15a on the performance of the target transistor 10a.
[0149] In this embodiment, after calculating the total parasitic capacitance of the target transistor 10a, the actual capacitance of the target transistor 10a can also be calculated based on the total parasitic capacitance.
[0150] Furthermore, the method also includes:
[0151] Short-circuit the target source-drain regions in the target transistor;
[0152] Detect the fourth capacitance between the target source / drain region and the target gate structure;
[0153] Calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and use the fifth difference as the actual capacitance of the target transistor.
[0154] Since the target well region 11a and the target source-drain region 12a in the target transistor 10a have different conductivity types, when performing capacitance detection on the target transistor 10a, it is necessary to first connect the target source region S1 and the target drain region D1 in the target source-drain region 12a to short-circuit the target source region S1 and the target drain region D1. Then, the test signal is applied to the target gate layer in the target source-drain region 12a and the target gate structure 13a respectively to detect the fourth capacitance C0 between the target source-drain region 12a and the target gate structure 13a.
[0155] Because of the contact parasitic capacitance C in the target transistor 10a g2c and the parasitic capacitance C of the connection layer g2m Therefore, the fourth capacitor C0 includes not only the actual capacitor C that needs to be detected, but also... m0 It also includes contact parasitic capacitance C g2c and the parasitic capacitance C of the connection layer g2m That is, C0 = C m0 +C g2c +C g2m The total parasitic capacitance of the target transistor 10a is C. g2c +C g2m Therefore, the fourth capacitor C0 and the total parasitic capacitance C are calculated. g2c +C g2m The fifth difference can be used to obtain the actual capacitance C of the target transistor 10a. m0 The actual capacitance C of the target transistor 10a is obtained. m0 This helps in simulating and testing the target transistor 10a to detect its electrical performance.
[0156] The semiconductor structure detection method provided in this invention can detect the first capacitance between the well region and the gate structure in the first test structure and the second capacitance between the well region and the gate structure in the second test structure by setting a first test structure and a second test structure for the target transistor. The first test structure has source-drain contacts and a source-drain connection layer, and the well region of the first test structure has the same conductivity type as the source-drain region. The second test structure does not have source-drain contacts and a source-drain connection layer, and the well region of the second test structure has the same conductivity type as the source-drain region. The method can detect the first capacitance between the well region and the gate structure in the first test structure and the second capacitance between the well region and the gate structure in the second test structure. The total parasitic capacitance of the target transistor can be calculated based on the first capacitance and the second capacitance, which can effectively improve the detection accuracy of the parasitic capacitance of the target transistor and help in the subsequent analysis of the performance of the target transistor.
[0157] This invention also provides a semiconductor structure detection device capable of performing the semiconductor structure detection method described in the above embodiments.
[0158] See Figure 3 This is a schematic diagram of the semiconductor structure detection device provided in an embodiment of the present invention.
[0159] like Figure 3 As shown, this embodiment provides a semiconductor structure detection device. The semiconductor structure is the same as that in the above embodiments, and will not be described in detail here. The device includes:
[0160] The first detection module 10 is used to detect the first capacitance between the first well region and the first gate structure in the first test structure;
[0161] The second detection module 20 is used to detect the second capacitance between the second well region and the second gate structure in the second test structure; and
[0162] The first calculation module 30 is used to calculate the total parasitic capacitance of the target transistor based on the first capacitor and the second capacitor.
[0163] Furthermore, the first computing module 30 is specifically used for:
[0164] Calculate the first difference between the first capacitor and the second capacitor, and use the first difference as the total parasitic capacitance of the target transistor.
[0165] Furthermore, the device also includes:
[0166] The third detection module is used to detect the third capacitance between the third well region and the third gate structure in the third test structure.
[0167] The second calculation module is used to calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor; and,
[0168] The third calculation module is used to calculate the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor.
[0169] Furthermore, the second calculation module is specifically used for:
[0170] Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
[0171] Furthermore, the third calculation module is specifically used for:
[0172] Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
[0173] Furthermore, the device also includes:
[0174] A shorting module is used to short-circuit the target source-drain region in the target transistor.
[0175] The fourth detection module is used to detect the fourth capacitance between the target source / drain region and the target gate structure; and,
[0176] The fourth calculation module is used to calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and to use the fifth difference as the actual capacitance of the target transistor.
[0177] The semiconductor structure detection device provided in this embodiment of the invention sets up a first test structure and a second test structure for the target transistor. The first test structure has source-drain contacts and a source-drain connection layer, and the well region of the first test structure has the same conductivity type as the source-drain region. The second test structure does not have source-drain contacts and a source-drain connection layer, and the well region of the second test structure has the same conductivity type as the source-drain region. This allows for the detection of a first capacitance between the well region and the gate structure in the first test structure, and a second capacitance between the well region and the gate structure in the second test structure. The total parasitic capacitance of the target transistor is calculated based on the first and second capacitances, effectively improving the detection accuracy of the parasitic capacitance of the target transistor and facilitating subsequent performance analysis of the target transistor.
[0178] See Figure 4 This is a schematic diagram of the memory structure provided in an embodiment of the present invention.
[0179] like Figure 4 As shown, the memory includes a memory array structure 100 and a peripheral structure 200. The memory array structure 100 can be a non-volatile memory array structure, such as NAND flash memory, NOR flash memory, etc.
[0180] Specifically, the memory array structure 100 may include a substrate 101 and a stacked layer 102 located on the substrate 101. The stacked layer 102 includes a plurality of vertically alternating gate layers 103 and interlayer insulating layers 104. Here, "vertical" refers to the direction perpendicular to the upper surface of the substrate 101. The number of stacked gate layers 103 and interlayer insulating layers 104 is not limited, for example, 48 layers, 64 layers, etc. The memory array structure 100 may also include a memory channel structure 105 that extends vertically through the stacked layer 102 and into the substrate 101. The memory channel structure 105 may include a vertically extending channel layer (not shown in the figure) and a memory dielectric layer (not shown in the figure) disposed around the periphery of the channel layer.
[0181] The peripheral structure 200 may include devices such as CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.
[0182] Specifically, the peripheral structure 200 can be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. The peripheral structure 200 can include the semiconductor structure in the above embodiments, which will not be described in detail here. For example, the peripheral structure 200 can include a device region and a free region (i.e., a region without any function). The first test structure 10b, the second test structure 10d, and the third test structure 10c in the semiconductor structure can be located in the free region of the peripheral structure 200, and the target transistor 10a in the semiconductor structure can be located in the device region of the peripheral structure 200.
[0183] The storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms. For example, the peripheral structure 200 is located below the storage array structure 100, i.e., the PUC (periphery under core array) architecture, or the peripheral structure 200 and the storage array structure 100 are set up side by side, i.e., the PNC (periphery near core array) architecture, etc. No specific limitation is made here.
[0184] The memory provided in this embodiment of the invention can accurately determine the corresponding electrical performance based on the parasitic capacitance of the target transistor.
[0185] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.
Claims
1. A method for detecting semiconductor structures, characterized in that, The semiconductor structure includes a first test structure and a second test structure for the target transistor. The first test structure includes a first well region, a first source-drain region located within the first well region, a first gate structure located on the first well region, a first source-drain contact located on and connected to the first source-drain region, and a source-drain connection layer located on and connected to the first source-drain contact. The first well region and the first source-drain region have the same conductivity type, such that the first source-drain region is short-circuited through the first well region. The second test structure includes a second well region, a second source-drain region located within the second well region, and a second gate structure located on the second well region. The second well region and the second source-drain region have the same conductivity type, such that the second source-drain region is short-circuited through the second well region. The difference between the first test structure and the target transistor is that the first well region and the target well region of the target transistor have different conductivity types, wherein the target well region of the target transistor has different conductivity types than the target source-drain region of the target transistor. The method includes: Detect the first capacitance between the first well region and the first gate structure in the first test structure; Detect the second capacitance between the second well region and the second gate structure in the second test structure; Calculate the first difference between the first capacitor and the second capacitor, and use the first difference as the total parasitic capacitance of the target transistor.
2. The method for detecting semiconductor structures according to claim 1, characterized in that, The semiconductor structure further includes a third test structure for the target transistor. The third test structure includes a third well region, a third source-drain region located in the third well region, a third gate structure located on the third well region, and a second source-drain contact located on and connected to the third source-drain region. The third well region has the same conductivity type as the third source-drain region. The method further includes: Detect the third capacitance between the third well region and the third gate structure in the third test structure; Calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor; The contact parasitic capacitance of the target transistor is calculated based on the second capacitor and the third capacitor.
3. The method for detecting semiconductor structures according to claim 2, characterized in that, The step of calculating the parasitic capacitance of the connection layer of the target transistor based on the first capacitance and the third capacitance includes: Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
4. The method for detecting semiconductor structures according to claim 2, characterized in that, The step of calculating the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor includes: Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
5. The method for detecting semiconductor structures according to claim 1, characterized in that, The semiconductor structure further includes the target transistor, which includes a target well region, a target source-drain region located in the target well region, a target gate structure located on the target well region, a target source-drain contact located on and connected to the target source-drain region, and a target source-drain connection layer located on and connected to the target source-drain contact. The target well region has a different conductivity type than the target source / drain region; The method further includes: Short-circuit the target source-drain regions in the target transistor; Detect the fourth capacitance between the target source / drain region and the target gate structure; Calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and use the fifth difference as the actual capacitance of the target transistor.
6. A semiconductor structure, characterized in that, Includes a first test structure and a second test structure for the target transistor; The first test structure includes: First well region; The first source-drain region is located in the first well region. The first well region and the first source-drain region have the same conductivity type, so that the first source-drain region is short-circuited through the first well region. A first gate structure located on the first well region; A first source-drain contact located on and connected to the first source-drain region; and, A source-drain connection layer located on and connected to the first source-drain contact; the difference between the first test structure and the target transistor is that the first well region and the target well region of the target transistor have different conductivity types, wherein the target well region of the target transistor has different conductivity types than the target source-drain region of the target transistor. The second test structure includes: Second trap region; The second source / drain region is located within the second well region, and the second well region and the second source / drain region have the same conductivity type, such that the second source / drain regions are short-circuited through the second well region; and... The second gate structure is located on the second well region.
7. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes a third test structure for the target transistor; The third test structure includes: Third trap region; The third source / drain region is located in the third well region, and the third well region has the same conductivity type as the third source / drain region; The third gate structure located on the third well region; and, The second source-drain contact is located on and connected to the third source-drain region.
8. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes the target transistor; The target transistor includes: Target trap area; The target source / drain region is located in the target well region, and the target well region has a different conductivity type from the target source / drain region. The target gate structure located on the target well region; A target source / drain contact located on and connected to the target source / drain region; and, The target source-drain connection layer is located on and connected to the target source-drain contact.
9. The semiconductor structure according to claim 8, characterized in that, The target transistor is a fin field-effect transistor.
10. A semiconductor structure detection device, characterized in that, The semiconductor structure includes a first test structure and a second test structure for the target transistor. The first test structure includes a first well region, a first source-drain region located within the first well region, a first gate structure located on the first well region, a first source-drain contact located on and connected to the first source-drain region, and a source-drain connection layer located on and connected to the first source-drain contact. The first well region and the first source-drain region have the same conductivity type, such that the first source-drain region is short-circuited through the first well region. The second test structure includes a second well region, a second source-drain region located within the second well region, and a second gate structure located on the second well region. The second well region and the second source-drain region have the same conductivity type, such that the second source-drain region is short-circuited through the second well region. The difference between the first test structure and the target transistor is that the first well region and the target well region of the target transistor have different conductivity types, wherein the target well region of the target transistor has different conductivity types than the target source-drain region of the target transistor. The device includes: The first detection module is used to detect the first capacitance between the first well region and the first gate structure in the first test structure. The second detection module is used to detect the second capacitance between the second well region and the second gate structure in the second test structure; and... A first calculation module is used to calculate a first difference between the first capacitor and the second capacitor, and to use the first difference as the total parasitic capacitance of the target transistor.
11. The semiconductor structure detection device according to claim 10, characterized in that, The semiconductor structure further includes a third test structure for the target transistor. The third test structure includes a third well region, a third source-drain region located in the third well region, a third gate structure located on the third well region, and a second source-drain contact located on and connected to the third source-drain region. The third well region has the same conductivity type as the third source-drain region. The device further includes: The third detection module is used to detect the third capacitance between the third well region and the third gate structure in the third test structure. The second calculation module is used to calculate the parasitic capacitance of the connection layer of the target transistor based on the first capacitor and the third capacitor; and, The third calculation module is used to calculate the contact parasitic capacitance of the target transistor based on the second capacitor and the third capacitor.
12. The semiconductor structure detection device according to claim 11, characterized in that, The second calculation module is specifically used for: Calculate the second difference between the first capacitor and the third capacitor, and use the second difference as the parasitic capacitance of the connection layer.
13. The semiconductor structure detection device according to claim 11, characterized in that, The third calculation module is specifically used for: Calculate the third difference between the third capacitor and the second capacitor, and use the third difference as the contact parasitic capacitance.
14. The semiconductor structure detection device according to claim 10, characterized in that, The semiconductor structure further includes the target transistor, which includes a target well region, a target source-drain region located in the target well region, a target gate structure located on the target well region, a target source-drain contact located on and connected to the target source-drain region, and a target source-drain connection layer located on and connected to the target source-drain contact. The target well region has a different conductivity type than the target source / drain region; The device further includes: A shorting module is used to short-circuit the target source-drain region in the target transistor. The fourth detection module is used to detect the fourth capacitance between the target source / drain region and the target gate structure; and, The fourth calculation module is used to calculate the fifth difference between the fourth capacitor and the total parasitic capacitance, and to use the fifth difference as the actual capacitance of the target transistor.
15. A memory, characterized in that, It includes a storage array structure and peripheral structures connected to the storage array structure; The peripheral structure includes the semiconductor structure as described in any one of claims 6 to 9.