Residual polarization capacitor structure, memory cell and method thereof

Abstract

According to various aspects, a method for forming one or more residual polarization capacitor structures includes: forming one or more capacitor structures, each of the one or more capacitor structures including: one or more electrodes; one or more precursor structures, arranged adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range of about 1 nm to 100 nm and a second dimension in a range of about 1 nm to about 30 nm; and subsequently forming one or more residual polarization structures including crystallized residual polarization material based on crystallization of precursor materials of the one or more precursor structures.

Description

Technical Field

[0001] Various aspects relate to remanent polarization capacitor structures, memory cells, and methods thereof, such as methods of forming capacitor structures or memory cells. Background Art

[0002] In general, various computer memory technologies have been developed in the semiconductor industry. The basic building block of a computer memory may be referred to as a memory cell. A memory cell may be an electronic circuit configured to store at least one information (e.g., in a bitwise manner). As an example, a memory cell may have at least two memory states representing, for example, a logical "1" and a logical "0". Typically, information may be retained (stored) in a memory cell until the memory state of the memory cell is modified, for example, in a controlled manner. The information stored in the memory cell may be obtained by determining in which memory state the memory cell resides. Currently, various types of memory cells may be used to store data. For example, one type of memory cell may include a thin film of a ferroelectric material, the polarization state of which may be changed in a controlled manner to store data in the memory cell, for example, in a non-volatile manner. The memory cell may be integrated, for example, on a wafer or chip, together with one or more logic circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, like reference numerals generally refer to like parts in different views. The drawings are not necessarily drawn to scale, with emphasis generally being placed on illustrating the principles of the invention. In the following description, various aspects of the invention are described with reference to the following drawings, in which:

[0004] Figures 1A to 1E schematically illustrating a capacitor structure according to various aspects;

[0005] FIG. 2A to FIG. 2F A schematic cross-sectional view showing a method for forming a capacitor structure using a precursor structure according to various aspects;

[0006] FIG. 3A to FIG. 3F A schematic cross-sectional view showing a method for forming a capacitor structure according to various aspects;

[0007] Figure 4 A schematic diagram showing dimensions of a remanent polarization structure according to various aspects;

[0008] Figure 5 schematically illustrates a field effect transistor structure according to various aspects;

[0009] Figure 6 schematically illustrates an equivalent circuit diagram of a memory cell according to various aspects;

[0010] 7A to 7Eeach schematically illustrates a memory cell according to various aspects; and

[0011] Figure 8 A schematic flow chart of a method for forming a memory cell according to various aspects is shown. DETAILED DESCRIPTION

[0012] The following detailed description refers to the accompanying drawings, which show by way of illustration specific details and aspects that can implement the present invention. These aspects are described in sufficient detail to enable those skilled in the art to practice the present invention. Without departing from the scope of the present invention, other aspects may be utilized and structural, logical and electrical changes may be made. Various aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. Various aspects are described in conjunction with methods and various aspects are described in conjunction with devices (e.g., field effect transistor structures, memory cells, or electronic devices). However, it is understood that the aspects described in conjunction with methods may be similarly applied to devices, and vice versa.

[0013] The terms "at least one" and "one or more" may be understood to include any integer greater than or equal to one, i.e., one, two, three, four, ..., etc. The terms "plurality" or "multiple" may be understood to include any integer greater than or equal to two, i.e., two, three, four, five, ..., etc.

[0014] The phrase "at least one" with respect to a group of elements may be used herein to indicate at least one element from the group consisting of these elements. For example, the phrase "at least one of" with respect to a group of elements may be used herein to indicate the following options: one of the listed elements, a plurality of the listed elements, a plurality of individual listed elements, or a plurality of multiple listed elements.

[0015] In the semiconductor industry, the integration of non-volatile memory technology may be useful for system-on-chip (SoC) products such as microcontrollers (MCUs). According to various aspects, the non-volatile memory may be integrated next to the processor core of the processor. As another example, one or more non-volatile memories may be used as part of a large-capacity storage device. In some aspects, the non-volatile memory technology may be based on at least one field effect transistor (FET) structure. In some aspects, the memory cell may include a field effect transistor structure and a capacitor structure coupled to the gate electrode of the field effect transistor structure. The amount of charge stored in the capacitor structure may affect the threshold voltage of the field effect transistor structure. The threshold voltage of the field effect transistor structure may define the memory state in which the memory cell is located. In some aspects, the capacitor structure may be a ferroelectric capacitor structure (FeCAP) coupled to the gate electrode of the field effect transistor structure to provide a ferroelectric field effect transistor (FeFET) structure. The term "ferroelectric" may be used herein, for example, to describe a material that exhibits a hysteresis charge-voltage relationship (QV). Since ferroelectric materials can have at least two stable polarization states, they can be used to shift the threshold voltage of a field effect transistor in a nonvolatile manner; therefore, they can be used to transform a field effect transistor into a nonvolatile field effect transistor-based memory structure. For example, by controlling the amount of charge stored in the capacitor structure, ferroelectric materials can transform a ferroelectric capacitor structure into a nonvolatile capacitor-based memory structure.

[0016] The term "over" as used herein to describe forming a feature (e.g., a layer) "over" a side or surface may be used to indicate that the feature (e.g., layer) may be formed "directly" (e.g., in direct contact with) the side or surface shown. The term "over" as used herein to describe forming a feature (e.g., a layer) "over" may be used to indicate that the feature (e.g., layer) may be formed "indirectly" "on" the side or surface shown, with one or more additional layers disposed between the side or surface shown and the formed layer.

[0017] The term "lateral" is used in relation to the lateral dimensions (in other words, the lateral extent) of a structure, part, structural element, layer, etc., such as being disposed above and / or in a carrier (e.g., a layer, a substrate, a wafer, etc.), or "laterally" close to a carrier, etc., and may be used herein to indicate an extent or positional relationship along a surface of the carrier. This means that, in some instances, a surface of the carrier (e.g., a surface of a layer, a surface of a substrate, a surface of a wafer, etc.) may be used as a reference, typically referred to as a primary processing surface. Furthermore, the term "width" used in relation to the "width" of a structure, part, structural element, layer, etc. may be used herein to indicate a lateral dimension (or in other words, a lateral extent) of a structure. Furthermore, the term "height" used in relation to the height of a structure, part, structural element, layer, etc. may be used herein to indicate a dimension (in other words, an extent) of the structure in a direction perpendicular to the surface of the carrier (e.g., perpendicular to the primary processing surface of the carrier).

[0018] The term "connection" may be used herein to refer to an electrical connection with respect to a node, terminal, integrated circuit element, etc., which may include a direct connection or an indirect connection, wherein an indirect connection may only include additional structures in the current path that do not affect the basic function of the described circuit or device. The term "conductive connection" used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc. may be understood as a conductive connection having, for example, ohmic properties, such as provided by a metal or a degenerate semiconductor in the absence of a pn junction in the current path. The term "conductive connection" may also be referred to as an "electrical connection".

[0019] The terms used with respect to "source region", "drain region", "channel region", etc.: region, may be used herein to refer to a continuous region of a semiconductor portion (e.g., a semiconductor wafer or a portion of a semiconductor wafer, a semiconductor layer, a fin, a semiconductor nanosheet, a semiconductor nanowire, etc.). In some aspects, the continuous region of the semiconductor portion may be provided by a semiconductor material having only one main doping type.

[0020] The term "thickness" as used with respect to the "thickness" of a layer may be used herein to refer to the size (in other words, extent) of a layer perpendicular to the surface of a support (material or material structure) on which the layer is formed (e.g., deposited or grown). If the surface of the support is parallel to the surface of the carrier (e.g., parallel to the main processing surface), the "thickness" of a layer formed on the surface of the support may be the same as the height of the layer.

[0021] Figure 1A , Figure 1B , Figure 1C , Figure 1D and Figure 1E 1 shows a schematic cross-sectional view of a capacitor structure 100 according to various aspects. In various aspects, as described in more detail below, a memory cell may include a capacitor structure 100, such as Figures 1A to 1E In various aspects, a memory cell (eg, memory cell 600 as described below) may also include a field effect transistor structure. The field effect transistor structure may include a gate electrode, wherein, for example, Figure 6 As shown and described in more detail below, the gate electrode may be conductively connected to the first electrode 102 of the capacitor structure 100 .

[0022] The capacitor structure 100 may include a first electrode 102, a second electrode 106, and at least one residual polarization structure 104 disposed between the first electrode 102 and the second electrode 106. Figure 1A As shown in the equivalent circuit 100a in FIG. 1 , the first electrode 102, the second electrode 106 and the residual polarization structure 104 may have a capacitance C associated therewith. CAP .

[0023] At least one remnant polarization structure 104 may include at least one ferroelectric structure. For example, at least one remnant polarization structure 104 may be or may include ferroelectric HfO2. The remnant polarization structure 104 may have a single grain structure (indicated by an arrow). The single grain structure may be a single crystal structure substantially free of an amorphous region. The remnant polarization structure 104 may have a ferroelectric dipole moment having an orientation ranging from about vertical (about 90°) to about parallel (about 1°) with respect to the surface of the first electrode 102, for example, ranging from about 10° to about 90°, for example, ranging from about 45° to about 90°.

[0024] The remnant polarization structure 104 may have a lateral extension in the range of about 1 nm to about 100 nm, such as in the range of about 1 nm to about 50 nm, such as in the range of about 5 nm to about 30 nm. The remnant polarization structure 104 may have a thickness in the range of about 1 nm to about 30 nm, such as in the range of about 2 nm to about 20 nm, such as in the range of about 2 nm to about 10 nm.

[0025] The lateral extension of the at least one remanent polarization structure 104 may be equal to or greater than the thickness of the at least one remanent polarization structure 104. Thus, the remanent polarization structure 104 may have an aspect ratio (lateral extension to thickness) ranging from about 1 to about 3 according to various aspects.

[0026] The at least one remnant polarization structure 104 may include any type of remnant polarization and / or spontaneous polarization material, such as a ferroelectric material, an antiferroelectric material, an antiferroelectric-like material, or the like.

[0027] At least one remanent polarization structure 104 may form a functional structure of the capacitor structure 100 in a memory cell (e.g., in the memory cell 600 described below) to store information, for example, by at least two remanent polarization states, wherein the at least one remanent polarization structure 104 may be selectively switched to the at least two remanent polarization states. The at least one remanent polarization structure 104 may be selectively switched to the at least two remanent polarization states by providing an electric field between the first electrode 102 and the second electrode 106 (e.g., as described with respect to Figure 6 As described, writing of the capacitive structure 100 (illustratively storing information therein) is performed by adjusting a potential difference between a first node and a second node associated with the first electrode 102 and the second electrode 106 , respectively, thereby setting or changing a remanent polarization state of the at least one remanent polarization structure 104 .

[0028] It should be understood that the remanent polarization structure 104 is only an example of a possible functional layer for the capacitive structure 100 , and any other functional layer whose state can be changed by the electric field provided by the transcapacitive structure 100 may be used in the same manner.

[0029] In general, if a material layer can retain polarization when an applied electric field (E) is reduced to zero, there may be a remanent polarization (also referred to as retentiveness or residual magnetization) in the material layer. Therefore, a certain value of the electric polarization (P) of the material layer can be detected. Illustratively, the polarization that remains in the material when the electric field is reduced to zero can be referred to as the remanent polarization. Therefore, the remanence of the material can be a measure of the residual polarization in the material when the applied electric field is removed. In general, ferroelectricity and antiferroelectricity can be concepts that describe the remanent polarization of a material, similar to ferromagnetism and antiferromagnetism used to describe the remanent magnetization in magnetic materials.

[0030] According to various aspects, ferroelectric materials can be used as part of a capacitor structure 100 of a memory cell (eg, as described in detail in relation to FIG. 1 ). 7A to 7E A portion of the capacitor structure 100 of the memory cells 700a, 700b, 700c, 700d, 700e or see Figure 6 The ferroelectric material may be a portion of the capacitor structure 100 of the memory cell 600. Figure 3B ) (eg, remanent polarization structure 104). By one or more precursor structures 202a, 202b (see FIG. 2A to FIG. 2F ) forms a remanent polarization structure 104. According to various aspects, ferroelectric materials can be used to store data in a non-volatile manner in an integrated circuit.

[0031] The ferroelectric material may be or may include ferroelectric HfO2 and / or ferroelectric ZrO2. Ferroelectric HfO2 may include any form of hafnium oxide that may exhibit ferroelectric properties. Ferroelectric ZrO2 may include any form of hafnium oxide that may exhibit ferroelectric properties. The ferroelectric material may include, for example, a solid solution of HfO2 and ZrO2 (for example, but not limited to a 1:1 mixture) or HfO2 doped, alloyed, or substituted with one or more of the following elements (a non-exhaustive list): silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, zirconium, any rare earth element, or any other suitable dopant (also referred to as a dopant) that provides or maintains ferroelectricity in the hafnium oxide. By way of example only, the ferroelectric material may be doped at a concentration of about 2 mol % to about 6 mol %.

[0032] Ferroelectric HfO2 (FE-HfO) or any other suitable material may exhibit a variety of benefits when used as a non-volatile memory (e.g., for CMOS applications). The single-grain structure of the remnant polarization structure 104 may enable the formation of a capacitor structure 100 with low cell-to-cell variability. The material forming the remnant polarization structure 104 or included in the remnant polarization structure 104 may be in a non-centrosymmetric crystalline phase (e.g., not in a body-centered phase). In this way, the device can be easily scaled to a size on the order of the grain size of the ferroelectric material (e.g., FE-HfO). Therefore, the cell-to-cell variability can be improved by reducing or eliminating the grain-to-grain variability of the ferroelectric material (e.g., FE-HfO).

[0033] The crystallization of a material (e.g., HfO2, ZrO2, or a mixture thereof) may be affected by a variety of factors. A single grain structure may be achieved by maintaining the material in a non-crystalline phase (e.g., an amorphous phase) during a deposition process (e.g., during layering by chemical vapor deposition, physical vapor deposition (e.g., thermal deposition, atomic layer deposition)), during a structuring (also referred to as patterning) process of the layer stack. After the structuring process, the material may be sealed with a dielectric structure (e.g., a stress liner) and subsequently crystallized by using sufficient heat treatment, as described in more detail below (see FIG. 3A to FIG. 3F ).

[0034] like Figure 1A As shown, the capacitor structure 100 may further include a dielectric structure 108 that is in physical contact with the remnant polarization structure 104 and at least laterally surrounds the remnant polarization structure 104 .

[0035] The dielectric structure 108 may be formed over (eg, directly on) the second electrode 106. Figure 1BAs shown, the dielectric structure 108 can seal the first electrode 102, the second electrode 106, and the at least one remnant polarization structure 104. In some aspects, the dielectric structure 108 can seal at least the remnant polarization structure 104, such as the sidewalls of the remnant polarization structure 104, such as all surfaces of the remnant polarization structure 104 that are not covered by the first electrode 102 and the second electrode 106.

[0036] The capacitor structure 100 may include a plurality of capacitor substructures (e.g., capacitors) 100-1, 100-2, 100-n (n is an integer equal to or greater than 1), which together form the capacitance of the capacitor structure 100. In some aspects, at least a first remanent polarization structure 104 and a second remanent polarization structure 104 may be disposed between the first electrode 102 and the second electrode 106. In other aspects, a plurality of capacitor substructures 100-1, 100-2, 100-n may be formed (e.g., laterally adjacent to each other) and a first capacitor substructure among the capacitor substructures 100-1, 100-2, 100-n may include at least a first remanent polarization structure 104, and a second capacitor substructure among the capacitor substructures 100-1, 100-2, 100-n may include a second remanent polarization structure 104 disposed between the first electrode 102 and the second electrode 106. Each of the first and second remanent polarization structures 104 may have a single grain structure (in Figure 1C The single grain structure of each of the first and second remanent polarization structures 104 may be achieved by keeping their volumes relatively small before performing a crystallization process.

[0037] A gap may be formed between the first remanent polarization structure 104 and the second remanent polarization structure 104. In some aspects, the dielectric structure 108 may be in direct physical contact with the first and second remanent polarization structures 104 and laterally surround the first and second remanent polarization structures 104. The dielectric structure 108 may be formed in the gap between the first and second remanent polarization structures 104. In other words, Figure 1A or Figure 1B The structures shown may be formed adjacently on a common substrate 110 to form a plurality of remnant polarization structures 104 .

[0038] In various aspects, the first remanent polarization structure 104 and the second remanent polarization structure 104 can be electrically coupled to a common electrode, such as a common node 524, 526. Figure 1D , Figure 1E and Figure 2F The common electrode may be one of the first electrode 102 and the second electrode 106 or connected to one of the first electrode 102 and the second electrode 106. The plurality of remanent polarization structures 104 may be arranged in a grid structure, for example on or above a common substrate 110, for example to collectively form a single capacitor structure (see Figure 1E). The capacitance of the capacitor structure 100 can be increased by increasing the number of remanent polarization structures 104 having a common electrode or node. In addition, in this way, potential non-ferroelectric capacitor structures can be avoided.

[0039] FIG. 2A to FIG. 2F A schematic cross-sectional view of a method for forming a capacitive structure using one or more precursor structures according to various aspects is shown by illustrating different processing stages. The capacitive structure formed by the illustrated method can be based on reference Figures 1A to 1C Aspects of a memory cell or capacitor memory structure are described.

[0040] exist FIG. 2A to FIG. 2F In the illustrated aspect, one or more remanent polarization structures 104, 104a, 104b are formed from one or more precursor structures 202, 202a, 202b and a crystallization process (e.g., see Figure 2D , Figure 2F ).

[0041] The method may include forming one or more capacitor structures 100. Each of the one or more capacitor structures 100 may include one or more electrodes 102, 106, and one or more precursor structures 202, 202a, 202b are disposed adjacent to the one or more electrodes 102, 106, wherein each of the one or more precursor structures 202, 202a, 202b may have a first size in the range of about 1 nm to 100 nm and a second size in the range of about 1 nm to about 30 nm. The method may also include, for example, subsequently forming one or more remanent polarization structures 104 that may include a crystalline remanent polarization material based on the crystallization of the precursor material of the one or more precursor structures 202, 202a, 202b. The precursor material may include a non-remanent polarization material. Alternatively, the precursor material may include a remanent polarization material that may be different from the crystalline remanent polarization material (e.g., different crystallinity and / or different crystal structure). Crystallization may be induced by at least one thermal treatment. The crystalline remanent polarization structure 104 may have a single grain structure.

[0042] Prior to initiating crystallization of the precursor material, a dielectric structure 108 (also referred to as a capping layer or capping structure) may be formed (see, for example, Figure 2C ). The dielectric structure 108 may contact and may at least partially surround one or more precursor structures 202, 202a, 202b. It should be noted that the dielectric structure 108 may at least cover the sidewalls of one or more precursor structures 202, 202a, 202b, such as Figure 2C and Figure 2D However, the dielectric structure 108 may contact and may additionally partially or completely cover the second electrode 106, which is disposed, for example, above one or more precursor structures 202, 202a, 202b.

[0043] In various aspects, forming one or more capacitive structures 100 may include forming a stack that may include one or more electrode layers and a precursor layer disposed adjacent to the one or more electrode layers, and constructing the layer stack to form one or more precursor structures 202 from the precursor layer. The precursor layer may include at least one material that is remanently polarized at least after a crystallization process.

[0044] Constructing the layer stack may include forming one or more capacitors, each of the one or more capacitors may include one or more electrodes 102, 106 formed from one or more electrode layers, and each of the one or more capacitors may include a corresponding precursor structure 202 of the one or more precursor structures 202. Each of the one or more capacitors may include a first electrode 102 and a second electrode 106, wherein the corresponding precursor structure 202 may be disposed between the first electrode 102 and the second electrode 106, and wherein the dielectric structure 108 at least partially seals the corresponding precursor structure 202, the first electrode 102, and the second electrode 106.

[0045] In various aspects, the one or more precursor structures 202 may include at least two precursor structures 202. Constructing the layer stack may include forming a capacitor, which may include the first electrode 102, the second electrode 106, and the at least two precursor structures 202 disposed therebetween.

[0046] In various aspects, the one or more precursor structures 202 may include a first precursor structure 202a and a second precursor structure 202b. The first precursor structure 202a and the second precursor structure 202b may be stacked on top of each other (see FIG. 2A to FIG. 2C ) and can together form a remanent polarization structure 104 (see Figure 2D ).

[0047] Alternatively, the first precursor structure 202a and the second precursor structure 202b may be formed on a common substrate (eg, a common first electrode 102 (see Figure 2E )) are formed adjacent to each other on the first precursor structure 202a and the second precursor structure 202b. A gap may be provided between the first precursor structure 202a and the second precursor structure 202b. The dielectric structure 108 may be formed in the gap. Therefore, the one or more remanent polarization structures 104 may include a first remanent polarization structure 104a and a second remanent polarization structure 104b, wherein a gap may be provided between the first remanent polarization structure 104a and the second remanent polarization structure 104b (see Figure 2F ).

[0048] The lateral extension of each of the one or more precursor structures 202 may be equal to or greater than the thickness of the corresponding precursor structure 202. The maximum volume of each of the one or more precursor structures 202 may be equal to or less than 0.0003 μm3 .

[0049] In various aspects, a method of forming one or more remanent polarization capacitor structures 100 may include: forming one or more capacitor structures 100, each of which may include one or more electrodes 102, 106 and one or more precursor structures 202 adjacent to the one or more electrodes 102, 106; forming a capping layer over the one or more capacitor structures 100, the capping layer covering at least one surface of the one or more precursor structures 202; and after forming the capping layer, forming one or more remanent polarization structures 104 adjacent to the one or more electrodes 102, 106 based on crystallization of precursor materials of the one or more precursor structures 202. The one or more remanent polarization structures 104 may include a crystallized remanent polarization material.

[0050] The capping layer may be or may include a dielectric structure 108 as described. According to various aspects, the capping layer may be or may include a stress liner. The capping layer may include silicon carbide (SiC), silicon oxide (SiO x ), silicon nitride (SiN), or silicon oxynitride (SiON) or may be formed thereof. The capping layer may be formed to have a layer thickness ranging from about 1 nm to about 30 nm. The capping layer may be formed by plasma enhanced atomic layer deposition (PE-ALD) or any other suitable layering process. The capping layer may act as a stress liner and / or a stress spacer. For example, the capping layer may include one or more layers of SiO x , SiN and / or SiON layer stack.

[0051] In various aspects, a method for forming a residual polarization capacitor structure may include: forming a first electrode 102; forming one or more first precursor structures 202a above the first electrode 102; forming one or more first residual polarization structures 104a that may include crystallized residual polarization material based on crystallization of a first precursor material of the one or more first precursor structures 202a; subsequently, forming one or more second precursor structures 202b above the one or more first residual polarization structures 104a; forming one or more second residual polarization structures 104b that may include crystallized residual polarization material based on crystallization of a second precursor material of the one or more second precursor structures 202b; and forming a second electrode 106 above the one or more second residual polarization structures 104b.

[0052] In various aspects, the one or more first precursor structures 202a can be disposed adjacent to (e.g., in direct physical contact), wherein the one or more second precursor structures 202b can be disposed adjacent to (e.g., in direct physical contact) the second electrode 106. In various aspects, each of the one or more first and / or second precursor structures 202a, 202b has a first dimension in a range of about 1 nm to 100 nm and a second dimension in a range of about 1 nm to about 30 nm.

[0053] although Figure 2F The capacitor structure shown has a common first electrode 102 and a separated second electrode 106, but in other aspects, the first electrode 102 can be physically separated (see Figure 1C to Figure 1E ) and / or the second electrode 106 may be a common second electrode 106 (see Figure 1C to Figure 1E ).

[0054] FIG. 3A to FIG. 3F A schematic cross-sectional view of a method of forming a capacitor structure according to various aspects is shown by showing different processing stages. The capacitor structure formed by the method shown can be based on reference Figures 1A to 1C Aspects of a memory cell or capacitor memory structure are described.

[0055] exist FIG. 3A to FIG. 3F In the illustrated aspect, one or more remnant polarization structures 104 are formed by structuring a remnant polarization layer 302 and a subsequent crystallization process.

[0056] The method may include providing or forming a first electrode 102 (eg, see Figure 3A ). The first electrode 102 may be a bottom or top electrode of the capacitor structure 100 to be formed (eg, see Figures 1A to 1C and Figure 3F ). The first electrode 102 may be formed on a substrate (not shown). The substrate may include a field effect transistor as described in more detail below. The first electrode 102 may be formed in an amorphous state or a crystalline state. The first electrode 102 may be formed to have a thickness in a range of about 1 nm to about 30 nm. By way of example only, the first electrode 102 may include or may consist of a metal, such as a noble metal, a transition metal.

[0057] The first electrode 102 may be structured (also referred to as patterned) before forming the residual polarization layer. In addition, the first electrode 102 may be cleaned, the surface energy may be adjusted, and / or surface treated as it may facilitate further processing. Alternatively or additionally, one or more crystallization seeds may be formed on the surface of the first electrode 102.

[0058] The method may further include forming at least one remanent polarization layer 302 (eg, directly on) the first electrode 102. Figure 3B ). At least one remnant polarization structure 302 may include at least one ferroelectric material. For example, at least one remnant polarization layer 302 may be or may include ferroelectric HfO2, ferroelectric ZrO2, or a mixture of ferroelectric HfO2 / ZrO2. According to various aspects, the remnant polarization layer 302 is formed in an amorphous state. The remnant polarization layer 302 may be maintained in an amorphous state until the remnant polarization layer 302 is configured to have predetermined dimensions in thickness and lateral extension. In various aspects, the remnant polarization layer 302 may be formed to have a thickness in a range of about 2 nm to about 50 nm.

[0059] According to various aspects, the thickness of remnant polarization layer 302 can be adjusted by forming a multilayer structure, for example, a stack of a predetermined number of sublayers that together form remnant polarization layer 302. In one aspect, a sublayer is crystallized before adding another sublayer on top of a previously formed sublayer.

[0060] The ferroelectric material forming the remnant polarization layer 302 may be an example of a material for the remnant polarization layer 302. The ferroelectric material may be or may include ferroelectric HfO2. The ferroelectric HfO2 may include any form of hafnium oxide that may exhibit ferroelectric properties. This may include, for example, HfO2, a solid solution of HfO2 and ZrO2 (for example, but not limited to a 1:1 mixture), or HfO2 or ZrO2 doped or substituted with one or more of the following elements (a non-exhaustive list): silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, zirconium, any rare earth element, or any other suitable dopant (also referred to as a dopant) that provides or maintains ferroelectricity in hafnium oxide or zirconium oxide.

[0061] In addition, the remnant polarization layer 302 may be formed on the seed layer. In some aspects, the first electrode 102 may include a seed layer or may serve as a seed layer. In some aspects, the seed layer may be formed above (e.g., directly on) the first electrode 102. The seed layer may promote the formation of the remnant polarization layer 302. According to various aspects, the first electrode 102 or the seed layer may be configured to induce single crystal growth and / or epitaxial crystallization in the remnant polarization layer 302.

[0062] The method may further include forming a second electrode 106 (eg, directly on) the remanent polarization layer 302. Figure 3C ). The second electrode 106 may be formed in an amorphous state or a crystalline state. The second electrode 106 may be formed to have a thickness in a range of about 1 nm to about 30 nm. As an example only, the second electrode 106 may include or may consist of a metal, such as a noble metal, such as a transition metal.

[0063] The method may further include constructing at least one residual polarization layer 302 to form at least one residual polarization structure (see Figure 3D). In addition, the first electrode 102 and / or the second electrode 106 may be structured during the structuring process of the residual polarization layer 302. Therefore, the first electrode 102 and / or the second electrode 106 may have a structure that corresponds to the structure of one or more residual polarization structures. In some aspects, the first electrode 102 and / or the second electrode 106 may have the same lateral size (width) as the one or more residual polarization structures.

[0064] According to various aspects, the remnant polarization layer 302 may be configured such that one or more remnant polarization structures are formed, each structure having a lateral extension in the range of about 1 nm to about 100 nm and a thickness in the range of about 1 nm to about 30 nm. In other words, a single remnant polarization structure may have a lateral extension in the range of about 1 nm to about 100 nm and may have a thickness in the range of about 1 nm to about 30 nm. The lateral extension of at least one remnant polarization structure may be equal to or greater than the thickness of at least one remnant polarization structure. The remnant polarization structure may have an aspect ratio (lateral extension of at least one lateral side relative to thickness) in the range of about 1 to about 5, for example, in the range of about 1 to about 3 (for example, between 1 and 3)

[0065] The specific dimensions of the remanent polarization structure may be a function of the specific remanent polarization material used to form the remanent polarization layer 302 , for example, the doping concentration of the specific remanent polarization material, and / or a specified crystalline phase of the single grain remanent polarization structure (eg, face-centered cubic structure versus hexagonal structure).

[0066] Structuring the remnant polarization layer 302 before the material of the remnant polarization structure is crystallized can enable the formation of one or more remnant polarization structures each having a single grain structure. In other words, by selecting the size of the remnant polarization structure within the above range, a single crystalline remnant polarization structure substantially free of an amorphous region and thus having a single grain structure can be formed during the crystallization process (see Figure 4 ).

[0067] In addition, a plurality of remanent polarization structures may be formed on or above a common substrate by a structuring process, for example, at least a first remanent polarization structure and a second remanent polarization structure (eg, Figure 3D As shown). A gap may be formed between the first remanent polarization structure and the second remanent polarization structure. As described above, the first and second remanent polarization structures may be amorphous in this regard. The gap may be in the range of 10 nm to 100 nm, for example, in the range of 20 nm to 50 nm.

[0068] The method may further include forming a dielectric structure 108 ( Figure 3EThe dielectric structure 108 may include silicon carbide (SiC), silicon oxide (SiO x ), silicon nitride (SiN), or silicon oxynitride (SiON) or may be formed thereof. The dielectric structure 108 may be formed to have a layer thickness ranging from about 1 nm to about 30 nm. The dielectric structure 108 may be formed by plasma enhanced atomic layer deposition (PE-ALD) or any other suitable layering process. The dielectric structure 108 may act as a stress liner and / or a stress spacer. For example, the dielectric structure 108 may include one or more layers of SiO x , SiN and / or SiON layer stack. In this way, the dielectric structure 108 can be used for stress engineering, such as for tensile or compressive stress adjustment, such as compared to the interface between air and the material of the remnant polarization structure, such as during a crystallization process. The dielectric structure 108 can be formed before the remnant polarization layer 302 is crystallized. The dielectric structure 108 can form a limitation or boundary of the remnant polarization structure during the crystallization process. The dielectric structure 108 can promote the formation of a single grain structure of the remnant polarization structure during the crystallization process. The dielectric structure 108 can be further formed on the second electrode 106 and can seal or surround the first electrode 102 and the second electrode 106 and at least one remnant polarization structure.

[0069] In aspects having two or more remanent polarization structures 104, the dielectric structure 108 may be formed to be in physical contact with the two or more remanent polarization structures (e.g., the first and second remanent polarization structures) and to at least laterally surround them. The dielectric structure 108 may also be formed in a space between adjacent remanent polarization structures, such as between the first and second remanent polarization structures and in physical contact with both. In various aspects, a region may be formed in the space between the first and second remanent polarization structures in which the dielectric structure 108 is directly formed in physical contact with the first electrode 102 and / or the substrate (or a carrier carrying the first electrode 102).

[0070] The method may further include crystallizing at least one remanent polarization structure (the resulting single grain and single crystal state are composed of Figure 3F ). The crystallization process may be a dedicated annealing, for example, in a temperature range of about 350° C. to 1050° C. The crystallization process may be performed in an inert or reactive annealing environment. Depending on the crystallization state and material of the first electrode 102 and the second electrode 106 before the crystallization process, the first electrode 102 and / or the second electrode 106 may be in an amorphous state or a crystalline state after the crystallization process.

[0071] In other aspects, and as described in more detail below, forming a memory cell may also include forming a field effect transistor structure that may include a gate electrode. The gate electrode may be conductively connected to the first electrode 102 or the second electrode 106 of the capacitor structure 100. The field effect transistor structure may be at least partially embedded in the substrate on which the first electrode is formed. Alternatively, the field effect transistor structure may be formed on or above the second electrode of the capacitor structure or adjacent to the capacitor structure.

[0072] The memory cell arrangement may include a plurality of memory cells distributed over a wafer. Each memory cell in the plurality of memory cells may include: a residual polarization capacitor structure 100, which may include a first electrode 102, a second electrode 106, and one or more residual polarization structures 104 disposed between the first electrode 102 and the second electrode 106, each of the one or more residual polarization structures 104 may include a residual polarization material having a single grain structure with a crystal orientation; wherein, for all memory cells in the plurality of memory cells, the crystal orientation of the single grain structure is aligned in the same direction.

[0073] In various aspects, the one or more remanent polarization structures 104 may include at least two remanent polarization structures 104. A space may be formed between respectively adjacent portions of the at least two remanent polarization structures 104. All remanent polarization structures of the one or more remanent polarization structures 104 may be electrically coupled to a common electrode, wherein the common electrode may be one of the first electrode 102 and the second electrode 106, or wherein the common electrode may be connected to one of the first electrode 102 and the second electrode 106.

[0074] In various aspects, a method of forming one or more memory cells may include forming one or more field effect transistor structures, each of which may include a gate electrode; and forming one or more residual polarization capacitor structures 100 as described above. A corresponding gate electrode of each of the one or more field effect transistor structures may be coupled to at least one corresponding residual polarization capacitor structure 100 of the one or more residual polarization capacitor structures 100.

[0075] In various aspects, a method of forming one or more memory cells may include: forming one or more field effect transistor structures, each of the one or more field effect transistor structures may include a gate electrode; forming one or more residual polarization capacitor structures 100 as described; wherein the corresponding gate electrode of each of the one or more field effect transistor structures may be coupled to at least one corresponding residual polarization capacitor structure 100 in the one or more residual polarization capacitor structures 100.

[0076] In various aspects, a method for forming a memory cell may include: forming a field effect transistor structure that may include a gate electrode; forming a first electrode 102 layer, a second electrode 106 layer, and a precursor layer 202 disposed between the first electrode 102 layer and the second electrode 106 layer, wherein the precursor layer 202 may include a precursor material that allows a crystalline residual polarization material to be formed therefrom, and wherein the gate electrode may be conductively connected to the first electrode 102 layer; constructing at least the second electrode 106 layer and the residual polarization layer 302 to form a plurality of capacitors, each of the plurality of capacitors may include one or more precursor structures 202 formed by the precursor layer 202; after structuring at least the second electrode 106 layer and the precursor layer 202, forming a covering layer over the plurality of capacitors, the covering layer covering at least one surface of the one or more precursor structures 202; and after forming the covering layer, crystallizing the precursor material of the one or more precursor structures 202 to form one or more residual polarization structures 104.

[0077] In various aspects, a method for forming a memory cell may include: forming a field effect transistor structure that may include a gate electrode; forming a first electrode 102 layer, a second electrode 106 layer, and a precursor layer 202 disposed between the first electrode 102 layer and the second electrode 106 layer, wherein the precursor layer 202 may include a precursor material that allows a crystalline ferroelectric material to be formed therefrom, and wherein the gate electrode may be conductively connected to the first electrode 102 layer; structuring at least the second electrode 106 layer and the precursor layer 202 to form a plurality of capacitors, each of the plurality of capacitors may include one or more precursor structures 202 formed by the precursor layer 202; after structuring at least the second electrode 106 layer and the precursor layer 202, forming a covering layer over the plurality of capacitors, the covering layer covering at least one surface of the one or more precursor structures 202; and after forming the covering layer, crystallizing the precursor material of the one or more precursor structures 202 of the plurality of capacitors.

[0078] Figure 4400 shows the functional relationship between the lateral extension 402 and the thickness 404 of the remanent polarization structure 104 with respect to the crystallinity of the remanent polarization structure 104. It can be seen that within the range of thickness 404 and lateral extension 402 (below thresholds 406, 408), a single-grain remanent polarization structure 104 can be formed. However, beyond the thresholds 406, 408, a remanent polarization structure having an amorphous region and / or a polycrystalline region will be formed. The thresholds 406, 408 may depend on the material composition of the remanent polarization structure 104 and / or the presence and thickness of the dielectric structure. However, a single-grain remanent polarization structure 104 may be achieved by reducing the structural size or dimensions of the remanent polarization structure. Two or more remanent polarization structures 104 (e.g., multiple remanent polarization structures 104) may be formed, used, and / or connected to one or more common electrodes 102, 106 to provide a capacitive structure having a predetermined capacitance or a minimum threshold capacitance. Alternatively, two or more capacitor structures may be formed on or over a common substrate by a structuring process to form two or more capacitor structures 100 on a common substrate.

[0079] Figure 5 Schematic functions of a field effect transistor structure 500 according to various aspects are shown. The field effect transistor structure 500 may include a gate structure 508, wherein the gate structure 508 may include a gate isolation 504 and a gate electrode 506. The gate structure 508 is illustratively shown as a planar gate stack, however, it is understood that Figure 4 The planar configuration shown is an example, and other field effect transistor designs may include a gate structure 508 having a non-planar shape, such as, for example, a trench gate transistor design, a vertical field effect transistor design, or a Fig.7D and Fig. 7E . The gate structure 508 may define, for example, a channel region 502 disposed in a semiconductor portion (e.g., in a semiconductor layer, in a semiconductor die, etc.). The gate structure 508 may allow the electrical characteristics of the channel region 502 to be controlled. For example, the gate structure 508 may, for example, be used to control (e.g., allow or prevent) a current in the channel region 502. In other words, the gate structure 508 may, for example, allow the source / drain current I from the first source / drain region of the field effect transistor structure 500 to the second source / drain region of the field effect transistor structure 500 to be controlled (e.g., allow or prevent). SD (The source / drain is located in the channel or adjacent to the channel but not in the Figure 4 ). In some aspects, gate structure 508 can control (e.g., increase or decrease) the resistance R of channel region 502 and, therefore, control the amount of current that can flow through channel region 502. With respect to operation of field effect transistor structure 500, a voltage (illustratively a potential) can be provided at (e.g., supplied to) gate electrode 506 to control the current I in channel region 502.SD , the current I in the channel region 502 SD Caused by the voltage supplied via the source / drain regions.

[0080] The gate electrode 506 may include a conductive material, such as polysilicon, aluminum, etc. However, the gate electrode 506 may include any suitable conductive material, such as a metal, a metal alloy, a degenerate semiconductor (in other words, a semiconductor material with such a high doping level that it acts like a metal and no longer a semiconductor). According to various aspects, the gate electrode 506 may include one or more conductive portions, layers, etc. The gate electrode 506 may include, for example, one or more metal layers (also referred to as metal gates), one or more polysilicon layers (also referred to as polysilicon gates), etc. The metal gate may include, for example, at least one work function adaptation metal layer disposed above the gate isolation 504 and an additional metal layer disposed above the work function adaptation metal layer. The polysilicon gate may be, for example, p-type doped or n-type doped.

[0081] According to various aspects, the gate isolation 504 can be configured to provide electrical isolation of the gate electrode 506 from the channel region and further influence the channel region through an electric field generated by the gate electrode 506. The gate isolation 504 can include one or more electrically insulating portions, layers, and the like.

[0082] like Figure 4 As shown in the equivalent circuit in FIG. 1 , the channel region 502, the gate isolation 504, and the gate electrode 506 may have capacitance C associated therewith. FET , which originates from the strongly conductive or weakly conductive regions (channel region 502 and gate electrode 506) separated from each other by gate isolation 504. Illustratively, channel region 502 can be considered as a first capacitor electrode, gate electrode 506 can be considered as a second capacitor electrode, and gate isolation 504 can be considered as a dielectric between the two capacitor electrodes. The capacitance C of field effect transistor structure 500 FET One or more operational characteristics may be defined for the field effect transistor structure 500. As described in more detail below, the configuration of the field effect transistor structure 500 (eg, of the gate isolation 504) may be adapted according to desired characteristics or applications of the field effect transistor structure 500 during operation (eg, according to desired capacitance).

[0083] Figure 6 An equivalent circuit of a memory cell 600 according to various aspects (eg, as described above) is shown, the memory cell 600 including a field effect transistor structure 500 (eg, as described in reference Figure 5 The memory transistor 500 shown in the figure may have a first capacitor C associated therewith. FET, and the capacitor structure 100 may have a second capacitor C associated therewith CAP .

[0084] The field effect transistor structure 500 and the capacitor structure 100 may be coupled (e.g., electrically connected) to each other to provide a capacitive voltage divider. The channel or body node of the field effect transistor structure 500 may provide or be connected to a first node 622, the capacitor structure 100 may provide or be connected to a second node 626, and the intermediate conductive portion (electrode, layer, etc.) may provide or be connected to a floating intermediate node 624. Exemplary implementations of such connection structures are described in more detail below, for example with respect to 7A to 7E .

[0085] The capacitive voltage divider formed by the field effect transistor structure 500 and the capacitor structure 100 allows the capacitance C of the corresponding capacitor to be adjusted. FET , C CAP , to allow efficient programming of the capacitor structure 100. When the voltage distribution across the field effect transistor structure 500 and the capacitor structure 100 is adapted so that there is more applied gate voltage drop across the functional layers of the capacitor structure 100 (e.g., across the residual polarization layer 302 such as a ferroelectric layer) compared to the gate isolation across the field effect transistor structure 500, the total gate voltage required to switch the memory cell 600 from one memory state to another memory state (e.g., from a high threshold voltage state to a low threshold voltage state as described below) may become smaller. Therefore, the total write voltage (illustratively, the total write voltage applied via the nodes 622, 626 to which the field effect transistor structure 500 and the capacitor structure 100 are connected) can be reduced by adapting the capacitor voltage divider. The voltage distribution can be determined by the voltage divider calculation of the series connection of the capacitors.

[0086] That is, the capacitance C of the field effect transistor structure 500 FET increase (eg, by providing appropriate gate isolation, as described above) and / or the capacitance C of the capacitor structure 100 CAP In the case of reduction, the voltage applied to the higher portion of the series connection drops across the capacitor structure 100. Therefore, the electric field generated by the gate isolation of the field effect transistor structure 500 below the capacitor structure 100 is reduced because the voltage drop across this area is reduced.

[0087] This results in reduced interface field stress, which may result in reduced interface wear due to, for example, charge injection. Thus, the reduced electric field generated across the gate isolation may result in improved endurance characteristics of the memory cell 600, i.e., increasing the amount of possible polarization reversals until the memory cell 600 may lose its storage characteristics.

[0088] According to various aspects, a memory cell (e.g., memory cell 100, 600, 700a, 700b, 700c, 700d, 700e) may have at least two different memory states associated therewith, such as represented by two different conductivities or two different amounts of stored charge that may be determined to determine which of the at least two different states the memory cell is in. According to various aspects, the memory state in which the memory cell is in may be a "programmed state" or an "erased state". For example, a programmed state may be a conductive state or a state with a positive stored charge (e.g., associated with a logical "1"), and an erased state may be a non-conductive state or a state with a negative stored charge (e.g., associated with a logical "0"). However, the definition of programmed states and erased states may be arbitrarily selected. According to various aspects, the polarization of the residual polarization layer 302 may define the memory state in which the memory cell is in. The polarization state of the residual polarization layer 302 may be switched by a capacitive structure. The polarization state of the residual polarization layer 302 may also be read out by the capacitive structure. According to various aspects, the memory cell can be in a first memory state when the remnant polarization layer 302 is in a first polarization state, and can be in a second memory state when the remnant polarization layer 302 is in a second polarization state (e.g., opposite to the first polarization state). As an example, the polarization state of the remnant polarization layer 302 can determine the amount of charge stored in the capacitor structure. The amount of charge stored in the capacitor structure can be used to define the memory state of the memory cell. The threshold voltage of the field effect transistor structure in the memory cell can be a function of the amount and / or polarity of the charge stored in the capacitor structure, for example, depending on the polarization state of the remnant polarization layer 302. The first threshold voltage, for example, a high threshold voltage V H-th , may be associated with a first polarization state (eg, with a first amount and / or polarity of stored charge), and a second threshold voltage, such as a low threshold voltage V L-th , may be associated with a second polarization state (eg, with a second amount and / or polarity of stored charge). Illustratively, the first memory state may be associated with a first threshold voltage, and the second memory state may be associated with a second threshold voltage.

[0089] In some aspects, the functional layer of the capacitor structure 100 may be the residual polarization layer 302. By increasing the capacitance C of the field effect transistor structure 500 FET The depolarization field of the residual polarization layer 302 can be reduced (for example, by providing a gate isolation comprising a relatively thick layer of material having a high dielectric constant). E Dep The depolarization field may be represented by the following system of equations, wherein the subscript "FET" refers to the capacitor provided by the field effect transistor structure 500 and the subscript "CAP" refers to the capacitor provided by the capacitive structure 100, as described herein:

[0090] 0,

[0091] D = = ,

[0092] .

[0093] Depolarization Field E Dep may be detrimental to data retention because, depending on its magnitude, it may depolarize the residual polarization layer 302. However, it can be reduced by increasing the capacitance ratio C FET / C CAP Therefore, the capacitance C of the field effect transistor structure 500 is FET As φ increases, the depolarization field decreases. This in turn improves the data retention of the memory cell 600.

[0094] In a first approximation, the voltage dropped across the memory structure capacitor is V CAP It can be estimated by the following formula:

[0095] ,

[0096] in, V 626 represents the voltage drop applied to the top node 626 (e.g., the top electrode of the capacitor structure 100, e.g., assuming that the node 622 associated with the body of the field effect transistor structure 500 is connected to the base potential, e.g., ground or 0 V), and the definition of general capacitance is as described above. Suitable parameters for influencing the voltage drop across the capacitor structure 100 (e.g., across the ferroelectric capacitor) can be represented by the area ratio between the capacitor structure 100 and the field effect transistor structure 500 and / or by the relative dielectric constant of the field effect transistor structure 500 (e.g., the gate isolation of the field effect transistor structure 500).

[0097] In some aspects, improved performance of memory cell 600 may be provided where the applied voltage across capacitor structure 100 is reduced by approximately 75% (and across field effect transistor structure 500 by approximately 25%). For example, this effect may be provided where the capacitor area of ​​field effect transistor structure 500 is three times the capacitor area of ​​capacitor structure 100, as described by the following equation,

[0098] .

[0099] However, adjusting the voltage distribution by providing the field effect transistor structure 500 with a large capacitor area may hinder the application of the memory cell 600 at a small technology node (e.g., at a 28 nm technology node). As described above, adjusting the voltage distribution in the voltage divider provided by adapting the dielectric constant (and thickness) of the gate isolation of the field effect transistor structure 500 (e.g., its second gate isolation layer) may allow a smaller footprint to be provided for the memory cell 600.

[0100] In some aspects, the gate isolation of the field effect transistor structure 500 can be configured such that the (first) capacitance C of the field effect transistor structure 500 FET and the (second) capacitor C of the capacitor structure 100 CAP The ratio of the first capacitor C FET With the second capacitor C CAP The ratio may be 4. In some aspects, the capacitor structure 100 (the entire area or total area of ​​all residual polarization structures of one capacitor structure) may have the same capacitor area as the field effect transistor structure 500 so that the first capacitor C of the field effect transistor structure 500 may be adapted. FET and the second capacitor C of the capacitor structure 100 CAP Ratio.

[0101] Increase the capacitance C of the field effect transistor structure 500 FET Adjusting the gate voltage divider may allow the thickness of the functional layer (e.g., the residual polarization layer 302) of the capacitor structure 100 to be maintained within an optimal range. For example, changing the ferroelectric film thickness may affect the ferroelectric properties of the ferroelectric layer. Therefore, being able to change the gate stack voltage divider without changing the film thickness of the ferroelectric layer as the memory layer may allow a memory cell 600 with optimal performance to be achieved.

[0102] 7A to 7E Schematically showing a possible implementation of the corresponding memory cells 700a, 700b, 700c, 700d, 700e. These memory cells 700a, 700b, 700c, 700d, 700e can be configured so that the field effect transistor structure 500 of the corresponding memory cells 700a, 700b, 700c, 700d, 700e is connected to the capacitor structure 100 to form a capacitive voltage divider C FET / C CAP , as referenced Figure 6 The memory cell 600 is described in detail.

[0103] Each of the depicted memory cells 700a, 700b, 700c, 700d, 700e may include a field effect transistor structure 500 including a channel 502, a gate isolation 504, and a gate electrode 506, which may be configured as described above.

[0104] Each of the depicted memory cells 700a, 700b, 700c, 700d, 700e may include a capacitor structure 100 electrically connected (in other words, electrically coupled) to the field effect transistor structure 500. The capacitor structure 702b may include any type of planar or non-planar design having at least a first electrode 102, a second electrode 106, and at least one remanent polarization structure 104 disposed between the first electrode 102 and the second electrode 106, for example to provide a memory function.

[0105] As mentioned above Figure 6 As described in the memory cell 600 in FIG. 1 , for example, by connecting the capacitor structure 100 (eg, the first electrode 102) to the gate electrode 506 of the field effect transistor structure 500, the field effect transistor structure 500 can be connected to the capacitor structure 100 to form a capacitive voltage divider C FET / C CAP , such as Fig. 7A As shown. The conductive connection of the capacitor structure 100 and the field effect transistor structure 500 (e.g., the first electrode 102 and the gate electrode 506) can provide a series capacitive connection between the capacitor formed by the capacitor structure 100 and the field effect transistor structure 500. In a planar configuration, the first electrode 102 of the capacitor structure 100 can be a first capacitor electrode 102, the second electrode 106 can be a second capacitor electrode 106, and the at least one remanent polarization structure 104 can be a dielectric 104 between the first electrode 102 and the second electrode 106.

[0106] In some aspects, the gate electrode 506 of the field effect transistor structure 500 can be conductively connected to the first electrode 102 of the capacitor structure 100 via a conductive (eg, ohmic) connection 710, such as Fig. 7A In some aspects, the first electrode 102 of the capacitor structure 100 can be in direct physical contact with the gate electrode 506 of the field effect transistor structure 500 .

[0107] In some aspects, the capacitor structure 100 and the field effect transistor structure 500 may share a common electrode that serves as a gate electrode of the field effect transistor structure 500 and an electrode of the capacitor structure 100, such as Figure 7B shown.

[0108] In some aspects, the conductive (eg, ohmic) connection 710 between the field effect transistor structure 500 and the capacitor structure 100 may be provided by one or more metallization structures disposed above the field effect transistor structure 500, such as Figure 7C shown.

[0109] According to various aspects, the semiconductor portion may be made of silicon or may include silicon. However, various types of other semiconductor materials, such as germanium, III to V groups (e.g., SiC) or other types, including, for example, carbon nanotubes, organic materials (e.g., organic polymers), etc., may be used in a similar manner. In various aspects, the semiconductor portion may be a wafer made of silicon (e.g., p-type doped or n-type doped). In other aspects, the semiconductor portion may be a silicon-on-insulator (SOI) wafer. In other aspects, the semiconductor portion may be provided by a semiconductor structure disposed at a carrier, such as provided by one or more semiconductor fins, one or more semiconductor nanosheets, one or more semiconductor nanowires, etc.

[0110] Figure 7C An exemplary integration scheme of a memory cell 700c according to various aspects is schematically shown, wherein a metallization structure is provided to electrically connect the field effect transistor structure 500 to the capacitor structure 100. It should be understood that the metallization structure may include multiple metallization structures, for example, multiple single-level or multi-level contact structures.

[0111] The metallization structure may be configured to conductively connect the gate electrode 506 of the field effect transistor structure 500 to the first electrode 102 of the capacitor structure 100. For example, the metallization structure may include a contact metallization. The contact metallization may be at least partially disposed between the field effect transistor structure 500 and the capacitor structure 100. As another example, the metallization structure may include a contact metallization and a single layer or multiple layers of metallization disposed above the contact metallization. In this case, both the contact metallization and at least one layer of the single layer or multiple layers of metallization may be disposed between the field effect transistor structure 500 and the capacitor structure 100.

[0112] In some aspects, a metallization structure can be disposed over an active region of field effect transistor structure 500, and capacitive structure 100 can be disposed over the metallization structure. By arranging capacitive structure 100 (eg, as a ferroelectric capacitor) over field effect transistor structure 500, full scaling potential can be maintained.

[0113] The metallization structure may include a gate contact structure 744 (also referred to as a gate contact). The gate contact structure 744 may be embedded in (e.g., may laterally surround) an insulator layer 742. The insulator layer 742 may include a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN2), or a dielectric material having a thickness in a range of, for example, about 10 nm to about 100 nm (e.g., a thickness of 40 nm). x ), etc. The gate contact structure 744 may include, for example, at least one metal layer including tungsten (W), cobalt (Co), etc. The gate contact structure 744 may be in direct physical contact with the gate electrode 506 of the field effect transistor structure 500. The gate contact structure 744 may be in direct physical contact with the first electrode 102 of the capacitor structure 100. According to various aspects, the electrical connection between the first electrode 102 of the capacitor structure 100 and the gate electrode 506 of the field effect transistor structure 500 may be formed by the gate contact structure 744.

[0114] Additional metallization structures may be formed over the capacitor structure 100 (eg, Fig.7D and Fig. 7E ). The further metallization structure may include a memory contact structure (also referred to as a memory contact). The memory contact structure may be embedded in (eg, may laterally surround) a further (eg, second) insulator layer.

[0115] Fig.7D and Fig. 7E A possible non-planar structure for a memory cell 700d, 700e is shown, for example for the field effect transistor structure 500 (eg for the memory transistor described above).

[0116] exist Fig.7D In the illustrated integration scheme, at least the field effect transistor structure 500 of the memory cell 700d may be configured as a fin field effect transistor (FinFET). The semiconductor portion 704 provided with the channel region may have the shape of a vertical fin, wherein the gate isolation 504 and the gate electrode 506 may at least partially surround the fin.

[0117] exist Fig. 7E In the integration scheme shown, at least the field effect transistor structure 500 of the memory cell 700e can be configured as a nanosheet or nanowire field effect transistor. One or more semiconductor portions 704 provided with a channel region can each have the shape of a nanosheet or a nanowire. The gate isolation 504 and the gate electrode 506 can at least partially surround the corresponding nanosheet or nanowire.

[0118] Figure 8 A schematic flow chart showing a method 800 for forming a memory cell according to various aspects, for example, Figure 8 The memory unit 600 described and / or referenced 7A to 7E Memory cells 700a, 700b, 700c, 700d, 700e are depicted.

[0119] According to various aspects, method 800 may include: forming a capacitor structure in 810; and forming a field effect transistor structure including a gate isolation and a gate electrode in 820, wherein the capacitor structure and the field effect transistor structure are coupled to each other to form a capacitive voltage divider.

[0120] In some aspects, the capacitor structure can include a first electrode, a second electrode, and at least one residual polarization layer 302 disposed between the first electrode and the second electrode. In some aspects, an electrode of the capacitor structure (eg, the first electrode) can be conductively connected to a gate electrode of the field effect transistor structure.

[0121] In some aspects, method 800 may include one or more layering and patterning processes for forming a memory cell, such as one or more layering and patterning processes for forming a memory structure and / or a field effect transistor structure. Patterning may include forming a mask (e.g., a silicon nitride hard mask having a thickness ranging from about 1 nm to about 100 nm) that defines the lateral dimensions of the field effect transistor structure (e.g., its gate structure) and partially removing a gate isolation layer and a gate electrode.

[0122] Forming the field effect transistor structure may include forming doped regions in a carrier (e.g., in a semiconductor substrate or portion), for example, to form at least two source / drain regions of the field effect transistor structure. Various doping techniques (e.g., diffusion doping, ion implantation, etc.) may be used to form the at least two source / drain regions. Forming the field effect transistor structure may include layering and patterning a gate structure at a (channel) region between the doped regions forming the at least two source / drain regions.

[0123] The layering may include forming a first electrode layer (e.g., a bottom electrode layer), a second electrode layer (e.g., a top electrode layer), and at least one residual polarization layer 302 disposed between the two electrode layers. The patterning may include forming a mask (e.g., a silicon nitride hard mask having a thickness in a range of about 1 nm to about 100 nm) that defines the lateral dimensions of the capacitor structure and partially removing the electrode layers and the at least one residual polarization layer 302 to form the capacitor structure. The capacitor structure may be formed over a metallization structure (illustratively, a contact metallization) including a gate contact structure.

[0124] According to various aspects, a gate contact structure may be formed by depositing an insulator material (e.g., SiO2 or SiN) across the entire carrier and by forming a contact hole over the gate structure of each field effect transistor structure for the memory cell (e.g., by one or more photolithography processes and wet or dry chemical etching). The contact hole may be formed directly over the gate structure, i.e., over the active area, or, if this is not possible (e.g., due to design rules), contacting the gate structure may be accomplished by offsetting to the active area.

[0125] According to various aspects, one or more patterning processes may be used, for example, to form a field effect transistor structure and / or a capacitor structure on or in a carrier. Thus, a mask may be used. The mask may include a material for transferring a photolithographic mask pattern to one or more material layers. The mask may include, for example, a positive or negative photoresist (also referred to as a soft mask) or a hard mask. The photoresist itself may be patterned by a standard photolithography process. The patterning of the hard mask material may include a combination of patterning of the photoresist and subsequent etching of the hard mask material (e.g., wet or dry chemical etching). However, any other suitable process may be used to transfer the desired pattern to one or more material layers.

[0126] According to various aspects, a memory cell as described herein may be integrated into an electronic device (e.g., a microcontroller, a central processing unit, a system on a chip (SoC), a memory device), for example, integrated into the same electronic device with other elements, such as elements for controlling logic operations and / or input / output operations of the electronic device. Illustratively, one or more memory transistors may be integrated (and formed) on or in the same carrier as one or more logic transistors and / or one or more input / output transistors.

[0127] The processing (eg, fabrication) of memory transistors may be integrated into a process flow for processing electronic devices. Illustratively, the processing of memory transistors may be performed in parallel with the processing of logic transistors and / or I / O transistors used in electronic devices, for example to provide electronic devices with data storage capabilities.

[0128] Hereinafter, various aspects of the present invention will be illustrated.

[0129] Example 1 is a method of forming a capacitor structure, the method may include forming a first electrode, a second electrode, and at least one remnant polarization layer disposed between the first electrode and the second electrode; constructing at least one remnant polarization layer to form at least one remnant polarization structure, wherein the remnant polarization structure includes a first dimension (e.g., lateral extension) in a range of about 1 nm to 100 nm and a second dimension (e.g., thickness or vertical extension) in a range of about 1 nm to 30 nm; and crystallizing at least one remnant polarization structure. According to various aspects, the remnant polarization structure may include a third dimension (e.g., additional lateral extension) in a range of about 1 nm to 100 nm. In some aspects, Example 1 may be a method of forming a capacitor structure, the method may include forming a first electrode, a second electrode, and at least one remnant polarization layer disposed between the first electrode and the second electrode; constructing at least one remnant polarization layer to form at least one remnant polarization structure, wherein the remnant polarization structure includes a first dimension (e.g., lateral extension) less than 100 nm and a second dimension (e.g., thickness or vertical extension) less than 30 nm; and crystallizing at least one remnant polarization structure. According to various aspects, the remnant polarization structure can include a third dimension (eg, an additional lateral extension) that is less than 100 nm.

[0130] In Example 2, Example 1 may optionally further include: forming a dielectric structure that is in physical contact with the remnant polarization structure and at least laterally surrounds the remnant polarization structure before the remnant polarization structure is crystallized.

[0131] In Example 3, Example 1 or 2 may optionally include: a dielectric structure is further formed on the second electrode and seals the first electrode and the second electrode and the at least one remanent polarization structure.

[0132] In Example 4, any one of Examples 1 to 3 may optionally include: forming at least a first remanent polarization structure and a second remanent polarization structure, wherein a gap is formed between the first remanent polarization structure and the second remanent polarization structure.

[0133] In Example 5, Example 3 may optionally further include: forming a dielectric structure that is in physical contact with the first remanent polarization structure and the second remanent polarization structure and at least laterally surrounds the first remanent polarization structure and the second remanent polarization structure before the remanent polarization layer is crystallized, wherein the dielectric structure is also formed in a gap between the first remanent polarization structure and the second remanent polarization structure. In some aspects, the dielectric structure may be or may include a stress layer, or may be a part of a stress layer. In some aspects, the dielectric structure may be a stress liner or may be a part of a stress liner.

[0134] In Example 8, any one of Examples 1 to 5 may optionally include: at least one remnant polarization layer includes at least one ferroelectric material.

[0135] In Example 7, any one of Examples 1 to 8 may optionally include: at least one remanent polarization layer is or includes ferroelectric HfO 2 .

[0136] In Example 8, any one of Examples 1 to 7 may optionally include: a lateral extension of the at least one remnant polarization structure is equal to or greater than a thickness of the at least one remnant polarization structure.

[0137] Example 9 is a method for processing a memory cell, which may include: forming a capacitor structure, which may include: forming a first electrode, a second electrode, and at least one residual polarization layer disposed between the first electrode and the second electrode; constructing at least one residual polarization layer to form at least one residual polarization structure, wherein the residual polarization structure includes a lateral extension in a range of approximately 1 nm to 100 nm and a thickness in a range of approximately 1 nm to 30 nm; crystallizing the at least one residual polarization structure; and forming a field effect transistor structure that may include a gate electrode, wherein the gate electrode is conductively connected to the first electrode of the capacitor structure.

[0138] In Example 10, Example 9 may optionally further include: forming a dielectric structure that is in physical contact with the remnant polarization structure and at least laterally surrounds the remnant polarization structure before the remnant polarization structure is crystallized.

[0139] In Example 11, any one of Examples 9 to 10 may optionally include: a dielectric structure is further formed on the second electrode and seals the first electrode and the second electrode and the at least one remanent polarization structure.

[0140] In Example 12, any one of Examples 9 to 11 may optionally include: forming at least a first remanent polarization structure and a second remanent polarization structure, wherein a gap is formed between the first remanent polarization structure and the second remanent polarization structure.

[0141] In Example 13, any one of Examples 9 to 12 may optionally include: forming a dielectric structure that is in physical contact with the first remanent polarization structure and the second remanent polarization structure and at least laterally surrounds the first remanent polarization structure and the second remanent polarization structure before the remanent polarization layer is crystallized, wherein the dielectric structure is also formed in a gap between the first remanent polarization structure and the second remanent polarization structure.

[0142] In Example 14, any one of Examples 9 to 13 may optionally include: at least one remnant polarization layer includes at least one ferroelectric material.

[0143] In Example 15, any one of Examples 9 to 12 may optionally include: at least one remanent polarization layer is or includes ferroelectric HfO 2 .

[0144] In Example 16, any one of Examples 9 to 14 may optionally include: a lateral extension of the at least one remnant polarization structure is equal to or greater than a thickness of the at least one remnant polarization structure.

[0145] Example 17 is a memory cell that may include a capacitor structure, the capacitor structure may include a first electrode, a second electrode, and at least one remnant polarization structure disposed between the first electrode and the second electrode, the remnant polarization structure having a single grain structure.

[0146] In Example 18, Example 17 may optionally further include a dielectric structure in physical contact with the remnant polarization structure and at least laterally surrounding the remnant polarization structure.

[0147] In Example 19, any one of Examples 17 or 18 may optionally include: a dielectric structure is further formed on the second electrode and seals the first electrode and the second electrode and the at least one remanent polarization structure.

[0148] In Example 20, any one of Examples 17 to 19 may optionally include: at least one remnant polarization structure includes at least one ferroelectric structure.

[0149] In Example 21, any one of Examples 17 to 20 may optionally include: at least one remnant polarization structure is or includes ferroelectric HfO2.

[0150] In Example 22, any one of Examples 17 to 21 may optionally include: at least a first residual polarization structure and a second residual polarization structure disposed between the first electrode and the second electrode, each of the first residual polarization structure and the second residual polarization structure having a single grain structure, wherein a gap is formed between the first residual polarization structure and the second residual polarization structure.

[0151] In Example 23, Example 22 may optionally include: the first remnant polarization structure and the second remnant polarization structure are electrically coupled to a common electrode, wherein the common electrode is one of the first electrode and the second electrode or is connected to one of the first electrode and the second electrode.

[0152] In Example 24, any one of Examples 17 to 23 may optionally include: a dielectric structure that is in physical contact with the first remanent polarization structure and the second remanent polarization structure and laterally surrounds the first remanent polarization structure and the second remanent polarization structure, wherein the dielectric structure is formed in a gap between the first remanent polarization structure and the second remanent polarization structure.

[0153] In Example 25, any one of Examples 17 to 24 may optionally include that the remnant polarization structure includes a lateral extension in a range of approximately 1 nm to 100 nm and a thickness in a range of approximately 1 nm to 30 nm.

[0154] In Example 26, any one of Examples 17 to 25 may optionally include: a lateral extension of the at least one remnant polarization structure is equal to or greater than a thickness of the at least one remnant polarization structure.

[0155] In Example 27, any one of Examples 17 to 26 may optionally include: the field effect transistor structure may include a gate electrode, wherein the gate electrode is conductively connected to the first electrode of the capacitor structure.

[0156] Example 28 is a memory cell arrangement, comprising: a plurality of memory cells distributed over a wafer. Each memory cell in the plurality of memory cells may include a capacitor structure, the capacitor structure including a first electrode, a second electrode, and a residual polarization material disposed between the first electrode and the second electrode, the residual polarization material having a single grain structure oriented into a corresponding crystal orientation. For all memory cells in the plurality of memory cells, the corresponding crystal orientation of the single grain structure is substantially the same.

[0157] In Example 29, Example 28 may also include a dielectric structure in physical contact with the remnant polarization structure and at least laterally surrounding the remnant polarization structure.

[0158] In Example 30, Example 29 can include: a dielectric structure is further formed on the second electrode and at least partially seals the first electrode and the second electrode and the at least one remanent polarization structure.

[0159] In Example 31, any one of Examples 28 to 30 may optionally include: at least one remnant polarization structure includes at least one ferroelectric material.

[0160] In Example 32, any one of Examples 28 to 31 may optionally include: at least a first remanent polarization structure and a second remanent polarization structure disposed between the first electrode and the second electrode, each of the first remanent polarization structure and the second remanent polarization structure having a single grain structure. A gap may be formed between the first remanent polarization structure and the second remanent polarization structure.

[0161] In Example 33, any one of Examples 28 to 32 may optionally include: the first remnant polarization structure and the second remnant polarization structure are electrically coupled to a common electrode, wherein the common electrode is one of the first electrode and the second electrode or is connected to one of the first electrode and the second electrode.

[0162] In Example 34, any one of Examples 28 to 33 may optionally include: a dielectric structure that is in physical contact with the first remanent polarization structure and the second remanent polarization structure and laterally surrounds the first remanent polarization structure and the second remanent polarization structure, wherein the dielectric structure is formed in a gap between the first remanent polarization structure and the second remanent polarization structure.

[0163] In Example 35, any one of Examples 28 to 34 may optionally include: the remnant polarization structure includes a lateral extension in a range of approximately 1 nm to 100 nm and a thickness in a range of approximately 1 nm to 30 nm.

[0164] In Example 36, any one of Examples 28 to 35 may optionally include: a lateral extension of the at least one remnant polarization structure is equal to or greater than a thickness of the at least one remnant polarization structure.

[0165] In Example 37, any one of Examples 28 to 35 may optionally include: the field effect transistor structure includes a gate electrode, wherein the gate electrode is conductively connected to the first electrode of the capacitor structure.

[0166] Example 38 is a method of forming one or more residual polarization capacitor structures. The method may include: forming one or more capacitor structures. Each of the one or more capacitor structures may include: one or more electrodes; one or more precursor structures, which are arranged adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first size in the range of about 1 nm to 100 nm and a second size in the range of about 1 nm to about 30 nm. The method may also include, for example, subsequently forming one or more residual polarization structures that may include crystallized residual polarization materials based on the crystallization of the precursor material of the one or more precursor structures.

[0167] In Example 39, Example 38 may optionally include: the precursor material may include a non-remanent polarization material, or wherein the precursor material may include a remanent polarization material that is different from the crystalline remanent polarization material (e.g., different in crystallinity and / or different in crystal structure).

[0168] In Example 40, Example 38 or 39 may optionally include: crystallization is initiated by at least one thermal treatment.

[0169] In Example 41, any one of Examples 38 to 40 may optionally include: the crystalline remnant polarization structure has a single grain structure.

[0170] In Example 42, any of Examples 38 to 41 can optionally include, prior to crystallization of the precursor material, forming a dielectric structure contacting and at least partially surrounding the one or more precursor structures.

[0171] In Example 43, any one of Examples 38 to 42 may optionally include: forming one or more capacitor structures may include: forming a stack, the stack may include one or more electrode layers and a precursor layer disposed adjacent to the one or more electrode layers, and constructing the layer stack to form one or more precursor structures from the precursor layers.

[0172] In Example 44, Example 43 may optionally include: constructing the layer stack may include forming one or more capacitors, each of the one or more capacitors may include one or more electrodes formed by one or more electrode layers, and each of the one or more capacitors may include a corresponding precursor structure in one or more precursor structures.

[0173] In Example 45, Example 44 may optionally include: each of the one or more capacitors may include a first electrode and a second electrode, wherein the corresponding precursor structure is disposed between the first electrode and the second electrode, and wherein the dielectric structure at least partially seals the corresponding precursor structure, the first electrode, and the second electrode.

[0174] In Example 46, any one of Examples 44 to 45 may optionally include: one or more precursor structures may include at least two precursor structures, wherein each of the one or more capacitive structures may include a first electrode and a second electrode, and wherein the structural layer stack may include forming a capacitor, and the capacitor may include a first electrode, a second electrode, and at least two precursor structures disposed between the first electrode and the second electrode.

[0175] In Example 47, any one of Examples 38 to 46 may optionally include: one or more precursor structures include a first precursor structure and a second precursor structure, wherein a gap is provided between the first precursor structure and the second precursor structure, and / or one or more residual polarization structures include a first residual polarization structure and a second residual polarization structure, wherein a gap is provided between the first residual polarization structure and the second residual polarization structure.

[0176] In Example 48, Example 47 can optionally include forming a dielectric structure in a space between the first precursor structure and the second precursor structure.

[0177] In Example 49, any one of Examples 43 to 47 can optionally include that the precursor layer includes at least one material, the at least one material being remanently polarized at least after a crystallization process.

[0178] In Example 50, any of Examples 38 to 49 may optionally include: each of the one or more precursor structures having a lateral extension that is equal to or greater than a thickness of the corresponding precursor structure.

[0179] In Example 51, any one of Examples 38 to 50 may optionally include: each of the one or more precursor structures has a maximum volume equal to or less than 0.0003 μm 3 .

[0180] Example 52 is a method of forming one or more memory cells. The method may include: forming one or more field effect transistor structures, each of the one or more field effect transistor structures may include a gate electrode; and forming one or more residual polarization capacitor structures according to any one of Examples 38 to 51; wherein the corresponding gate electrode of each of the one or more field effect transistor structures is coupled to at least one corresponding residual polarization capacitor structure of the one or more residual polarization capacitor structures.

[0181] Example 53 is a method of forming one or more residual polarization capacitor structures, the method may include: forming one or more capacitor structures, each of the one or more capacitor structures may include one or more electrodes and one or more precursor structures adjacent to the one or more electrodes; forming a covering layer above the one or more capacitor structures, the covering layer covering at least one surface of the one or more precursor structures; and after forming the covering layer, based on the crystallization of the precursor material of the one or more precursor structures, forming one or more residual polarization structures adjacent to the one or more electrodes, the one or more residual polarization structures may include crystallized residual polarization material. In some aspects, the covering layer may be formed so that the covering layer is in direct physical contact with one or more surfaces of the corresponding capacitor structure. The covering layer may be formed so that the covering layer is in direct physical contact with the top electrode of the corresponding capacitor structure. The covering layer may be formed so that the covering layer is in direct physical contact with the precursor material of the one or more precursor structures.

[0182] The capping layer may be or may include a dielectric structure as described herein. According to various aspects, the capping layer may be or may include a stress liner. The capping layer may include silicon carbide (SiC), silicon oxide (SiO x ), silicon nitride (SiN), or silicon oxynitride (SiON) or may be formed thereof. The capping layer may be formed to have a layer thickness ranging from about 1 nm to about 30 nm. The capping layer may be formed by plasma enhanced atomic layer deposition (PE-ALD) or any other suitable layering process. The capping layer may act as a stress liner and / or a stress spacer. For example, the capping layer may include one or more layers of SiO x , SiN and / or SiON layer stack.

[0183] Example 54 is a method of forming one or more memory cells, which may include: forming one or more field effect transistor structures, each of the one or more field effect transistor structures may include a gate electrode; and forming one or more residual polarization capacitor structures according to Example 53; wherein the corresponding gate electrode of each of the one or more field effect transistor structures is coupled to at least one corresponding residual polarization capacitor structure of the one or more residual polarization capacitor structures.

[0184] Example 55 is a memory cell arrangement that may include: a plurality of memory cells distributed over a wafer. Each of the plurality of memory cells may include: a remanent polarization capacitor structure that may include a first electrode, a second electrode, and one or more remanent polarization structures disposed between the first electrode and the second electrode, each of the one or more remanent polarization structures may include a remanent polarization material having a single grain structure with a crystal orientation; wherein, for all memory cells in the plurality of memory cells, the crystal orientation of the single grain structure is aligned in substantially the same direction. In some aspects, the crystal orientation of the single grain structure is aligned along a predetermined alignment direction with a deviation of less than ±20°.

[0185] In Example 56, Example 55 may include: the one or more remanent polarization structures may include at least two remanent polarization structures. A space may be formed between respectively adjacent portions of the at least two remanent polarization structures.

[0186] In Example 57, Example 55 or 56 may optionally include: all of the one or more residual polarization structures are electrically coupled to a common electrode, wherein the common electrode is one of the first electrode and the second electrode, or wherein the common electrode is connected to one of the first electrode and the second electrode.

[0187] Embodiment 58 is a method for forming a memory cell, which may include: forming a field effect transistor structure that may include a gate electrode; forming a first electrode layer, a second electrode layer, and a precursor layer disposed between the first electrode layer and the second electrode layer, wherein the precursor layer may include a precursor material that allows a crystalline residual polarization material to be formed therefrom; and wherein the gate electrode is conductively connected to the first electrode layer; structuring at least the second electrode layer and the residual polarization layer to form a plurality of capacitors, each of the plurality of capacitors may include one or more precursor structures formed by the precursor layer; after structuring at least the second electrode layer and the precursor layer, forming a covering layer over the plurality of capacitors, the covering layer covering at least one surface of the one or more precursor structures; and after forming the covering layer, crystallizing the precursor material of the one or more precursor structures to form one or more residual polarization structures.

[0188] Embodiment 59 is a method for forming a memory cell, which may include: forming a field effect transistor structure that may include a gate electrode; forming a first electrode layer, a second electrode layer, and a precursor layer disposed between the first electrode layer and the second electrode layer, wherein the precursor layer may include a precursor material that allows a crystalline ferroelectric material to be formed therefrom; and wherein the gate electrode is conductively connected to the first electrode layer; structuring at least the second electrode layer and the precursor layer to form a plurality of capacitors, each of the plurality of capacitors may include one or more precursor structures formed by the precursor layer; after structuring at least the second electrode layer and the precursor layer, forming a covering layer over the plurality of capacitors, the covering layer covering at least one surface of the one or more precursor structures; and after forming the covering layer, crystallizing the precursor material of the one or more precursor structures of the plurality of capacitors.

[0189] Embodiment 60 is a method for forming a residual polarization capacitor structure, which may include: forming a first electrode; forming one or more first precursor structures above the first electrode; forming one or more first residual polarization structures that may include crystallized residual polarization material based on crystallization of a first precursor material of the one or more first precursor structures; subsequently, forming one or more second precursor structures above the one or more first residual polarization structures; forming one or more second residual polarization structures that may include crystallized residual polarization material based on crystallization of a second precursor material of the one or more second precursor structures; and forming a second electrode above the one or more second residual polarization structures.

[0190] In Example 61, any of Examples 38 to 60 may optionally include: one or more first precursor structures are disposed adjacent to (e.g., in direct physical contact with) the first electrode, wherein one or more second precursor structures are disposed adjacent to (e.g., in direct physical contact with) the second electrode.

[0191] In Example 61, any of Examples 38 to 60 may optionally include: each of the one or more first and / or second precursor structures has a first dimension in a range of about 1 nm to 100 nm and a second dimension in a range of about 1 nm to about 30 nm.

[0192] According to various aspects, the precursor structure as referred to herein may include one or more patterned and / or unpatterned layers, patterned and / or unpatterned portions of one or more precursor materials. In some aspects, the precursor material may be any material or mixture of materials that allows crystallization, such as by thermal treatment, to form a crystalline residual polarization material. In some aspects, the precursor structure may include at least a portion of an amorphous material. The amorphous material may be crystallized to form a crystalline residual polarization material, such as by thermal treatment.

[0193] According to various aspects, the precursor material can include a non-remanent polarization material. In other aspects, the precursor material can include a remanent polarization material that is different (eg, with respect to chemical composition, with respect to a corresponding crystal structure, with respect to a corresponding microstructure) from the crystalline remanent polarization material.

[0194] According to various aspects, the stress layer can be used to support and / or induce the formation of a crystalline residual polarization material from a precursor material. In some aspects, the precursor structure can be directly covered with a stress layer, for example, the sidewalls and top surface of the precursor structure can be directly covered with a stress layer. The bottom surface of the precursor structure can be adjacent to the bottom electrode. In other aspects, at least one or more sidewalls of the precursor structure can be directly covered with a stress layer. The top surface and bottom surface of the precursor structure can be adjacent to the top electrode and the bottom electrode, respectively.

[0195] Various aspects are described with reference to remanent polarization materials, remanent polarization layers, and remanent polarization structures. Remanent polarization materials, remanent polarization layers, and remanent polarization structures are examples of remanent polarization materials, remanent polarization layers, and remanent polarization structures, respectively. Therefore, the aspects described with remanent polarization materials, remanent polarization layers, and remanent polarization structures can be applied to spontaneous polarization materials, spontaneous polarization layers, and spontaneous polarization structures, respectively, in the same or similar manner. Spontaneous polarization materials may include ferroelectric materials and / or antiferroelectric materials, spontaneous polarization layers may include ferroelectric layers and / or antiferroelectric layers, and spontaneous polarization structures may include ferroelectric structures and / or antiferroelectric structures.

[0196] Although the present invention has been particularly shown and described with reference to specific aspects of the present invention, it will be understood by those skilled in the art that various changes may be made to it in form and details without departing from the spirit and scope of the present invention as defined by the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and therefore it is intended to include all changes that fall within the equivalent meaning and range of the claims.

Claims

1. A method for forming one or more residual polarization capacitor structures, the method comprising: forming one or more capacitive structures in a layer stack, the layer stack comprising one or more electrode layers and a precursor layer disposed adjacent to the one or more electrode layers, wherein forming the one or more capacitive structures comprises patterning the precursor layer into a plurality of precursor structures, each of the plurality of precursor structures being separated by a space within the precursor layer, wherein each of the one or more capacitive structures comprises: one or more electrodes formed in the one or more electrode layers; one or more precursor structures of the plurality of precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range of 1 nm to 100 nm and a second dimension in a range of 1 nm to 30 nm; and After patterning the precursor layer into a plurality of precursor structures, one or more remanent polarization structures including a crystallized remanent polarization material are formed based on crystallization of a precursor material of one or more of the precursor structures.

2. The method according to claim 1, in, The precursor material comprises a non-remanent polarization material, or Wherein, the precursor material includes a remanent polarization material different from the crystalline remanent polarization material.

3. The method according to claim 1, in, The crystallization is initiated by at least one thermal treatment.

4. The method according to claim 1, in, The crystalline remanent polarization material has a single grain structure.

5. The method according to claim 1, further comprising: Prior to said crystallization of said precursor material, a dielectric structure is formed, said dielectric structure contacting and at least partially surrounding a plurality of said precursor structures.

6. The method according to claim 1, in, Forming the one or more capacitive structures includes forming one or more capacitors, each of the one or more capacitors including one or more electrodes formed by the one or more electrode layers, and each of the one or more capacitors including a corresponding precursor structure in one or more of the precursor structures, wherein adjacent capacitors in the one or more capacitors are separated by spacing.

7. The method according to claim 6, in, Each of the one or more capacitors includes a first electrode and a second electrode, wherein the corresponding precursor structure is disposed between the first electrode and the second electrode, and wherein a dielectric structure at least partially seals the corresponding precursor structure, the first electrode, and the second electrode.

8. The method according to claim 1, in, Each of the one or more remanent polarization structures of the one or more capacitive structures is formed in a remanent polarization layer, wherein the gap extends into the remanent polarization layer between the one or more remanent polarization structures of the one or more capacitive structures.

9. The method according to claim 1, further comprising: A dielectric structure is formed in the space.

10. The method according to claim 1, in, After forming the one or more remanent polarization structures, the precursor layer includes at least one material, the at least one material being remanent polarized.

11. The method according to claim 1, in, Each precursor structure of the plurality of precursor structures has a third dimension in a range from 1 nm to 100 nm, the third dimension being perpendicular to the first dimension and perpendicular to the second dimension.

12. The method according to claim 1, in, The maximum volume of each of the plurality of precursor structures is equal to or less than 0.0003 μm 3 .

13. A method of forming one or more memory cells, the method comprising: forming one or more field effect transistor structures, each of the one or more field effect transistor structures comprising a gate electrode; as well as The method for forming one or more residual polarization capacitor structures according to claim 1; Wherein, a corresponding gate electrode of each of the one or more field effect transistor structures is coupled to at least one corresponding residual polarization capacitor structure of the one or more residual polarization capacitor structures.

14. A memory comprising: A plurality of memory cells are distributed above the carrier; Each memory cell of the plurality of memory cells comprises: A remanent polarization capacitor structure, comprising a first electrode, a second electrode and a plurality of remanent polarization structures, the plurality of remanent polarization structures comprising at least two remanent polarization structures and being spaced apart from each other by a spacer, and formed by crystallization of a precursor layer, the precursor layer having a plurality of precursor structures spaced apart by a spacer, wherein each of the plurality of precursor structures has a first size in a range of 1 nm to 100 nm and a second size in a range of 1 nm to 30 nm, and wherein the plurality of remanent polarization structures are disposed between the first electrode and the second electrode and in direct physical contact with both the first electrode and the second electrode, each of the plurality of remanent polarization structures comprising a remanent polarization material having a single grain structure with a crystal orientation; Wherein, for all memory cells in the plurality of memory cells, the crystal orientations of the single grain structure are aligned in the same direction.

15. A method of forming one or more residual polarization capacitor structures, the method comprising: forming one or more capacitive structures in a layer stack, the layer stack comprising one or more electrode layers and a precursor layer disposed adjacent to the one or more electrode layers, wherein forming the one or more capacitive structures comprises patterning the precursor layer into a plurality of precursor structures, each of the plurality of precursor structures being separated by a space within the precursor layer, wherein each of the one or more capacitive structures comprises: one or more electrodes formed in the one or more electrode layers, one or more precursor structures of the plurality of the precursor structures disposed adjacent to the one or more electrodes, wherein each of the one or more precursor structures has a first dimension in a range of 1 nm to 100 nm and a second dimension in a range of 1 nm to 30 nm; and After patterning the precursor layer into a plurality of precursor structures, one or more remnant polarization structures are formed based on crystallization of a precursor material of one or more of the precursor structures, the one or more remnant polarization structures including a crystallized remnant polarization material.

16. The method of claim 15, further comprising subsequently forming one or more capacitive structures: A capping layer is formed over the one or more capacitive structures, the capping layer covering at least one surface of the one or more precursor structures.

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