A filtering device, a signal processing method and an electronic device

Abstract

The application discloses a filtering device, a signal processing method and electronic equipment, and relates to the technical field of radio frequency signal processing. The filtering device comprises a shift register and a data processor in communication with the shift register. The shift register is configured to perform data processing based on an input signal sequence to obtain a shift signal sequence. The data processor is configured to perform data extraction based on the shift signal sequence to obtain an extracted signal sequence. The output signal sequence is obtained by performing logical operation processing based on the extracted signal sequence. The execution subject of the signal processing method is the filtering device of the above technical solution. The method provided by the application first performs data extraction to obtain an extracted signal, and then performs logical operation processing. Since the data extraction is performed first, the logical operation circuit required in the logical operation processing process is simplified, the filtering device can work at a higher clock frequency, and the filtering device can adapt to a higher input signal bandwidth under the condition that the input signal precision is sufficient.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal processing technology, and in particular to a filtering device, a signal processing method, and an electronic device. Background Technology

[0002] With the development of wireless communication technology, receivers based on direct radio frequency (DRF) architecture have been widely used. DRF receivers can directly sample radio frequency signals to obtain high-sampling-rate data. After obtaining the high-sampling-rate data, a digital down-converter can be used to process it.

[0003] Currently, the key component determining the overall circuit performance of a digital downconverter is the decimation filter bank. The function of the decimation filter bank is to filter out noise from the signal and reduce the signal sampling rate. Typically, a decimation filter bank consists of multiple cascaded decimation filters, which can be Finite Impulse Response Digital Filters (FIRs). A typical decimation filter includes a register, a decimation unit, a multiplier, and an adder connected in sequence; that is, the signal is first decimated before logical operations are performed to reduce the signal sampling rate.

[0004] However, the delay of multipliers and adders increases with the increase of data bit width, which reduces the data processing speed and accuracy, causing the decimation filter to fail to work properly at higher clock frequencies. Furthermore, this reduces the acceptable input signal bandwidth range of the decimation filter. Summary of the Invention

[0005] The purpose of this invention is to provide a filtering device, a signal processing method, and an electronic device to solve the problem that the decimation unit cannot work normally at a high clock frequency, resulting in a reduction in the acceptable input signal bandwidth range of the decimation unit.

[0006] In a first aspect, the present invention provides a filtering device, comprising: a shift register and a data processor communicating with the shift register; wherein,

[0007] The shift register is used to process data based on the input signal sequence to obtain a shift signal sequence;

[0008] The data processor is used to extract data based on the shift signal sequence to obtain an extracted signal sequence; and to perform logical operations based on the extracted signal sequence to obtain an output signal sequence.

[0009] With the above technical solution, the filtering device uses a data processor to extract data based on the shift signal sequence to obtain an extracted signal sequence; and performs logical operations on the extracted signal sequence to obtain an output signal sequence. This allows the filtering device to operate at a higher clock frequency without changing its filtering principle. The data processor first extracts data to obtain the extracted signal, and then performs logical operations. Compared to traditional filtering devices, the data extraction simplifies the logic circuitry required for logical operations, and allows the filtering device to operate at a higher clock frequency, ensuring that it can adapt to higher input signal bandwidth while maintaining sufficient input signal accuracy.

[0010] In one possible implementation, the data processor is configured to perform addition operations on the decimated signal sequence to obtain a decimated sum signal sequence; perform addition operations on the decimated signal sequence to obtain a decimated sum signal sequence; and perform multiplication operations on the decimated sum signal sequence to obtain an output signal sequence.

[0011] In one possible implementation, the data processor includes an extraction unit and a logic operation circuit, wherein the shift register is connected to the extraction unit and the extraction unit is connected to the logic operation circuit.

[0012] In one possible implementation, the logic operation circuit includes an adder sub-circuit and a multiplier sub-circuit, the decimation unit is connected to the adder sub-circuit, and the adder sub-circuit is connected to the multiplier circuit;

[0013] The adder sub-circuit is used to perform addition operations based on the decimated signal sequence to obtain a decimated sum signal sequence.

[0014] The multiplication sub-circuit is used to perform multiplication operations based on the decimation and signal sequences to obtain an output signal sequence.

[0015] Secondly, the present invention also provides a signal processing method applied to a data processor, wherein the data processor and a shift register constitute a filtering device, and the method includes:

[0016] Obtain the shift signal sequence obtained by the shift register through data processing based on the input signal sequence;

[0017] Data is extracted based on multiple shift signals to obtain an extracted signal sequence;

[0018] The extracted signal sequence is processed to obtain the output signal sequence.

[0019] The beneficial effects of the signal processing method provided in the second aspect are the same as those of the filtering device described in the first aspect or any possible implementation of the first aspect, and will not be repeated here.

[0020] Thirdly, the present invention also provides a digital downconverter, including the filtering device described in any one of the first aspects.

[0021] The beneficial effects of the digital downconverter provided in the third aspect are the same as those of the filtering device described in the first aspect or any possible implementation of the first aspect, and will not be repeated here.

[0022] Fourthly, the present invention also provides an electronic device including the digital down-converter described in the third aspect.

[0023] The beneficial effects of the electronic equipment provided in the fourth aspect are the same as those of the digital down-converter described in the third aspect, and will not be repeated here.

[0024] Fifthly, the present invention also provides a readable storage medium on which a program or instructions are stored, wherein when the program or instructions are executed by a processor, they achieve the same beneficial effects as the signal processing method described in the second aspect or any possible implementation of the second aspect, which will not be elaborated here. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0026] Figure 1 A circuit diagram of a conventional filter device is shown;

[0027] Figure 2 A circuit diagram of a filtering device provided in an embodiment of the present invention is shown;

[0028] Figure 3 A circuit diagram of another filtering device provided in an embodiment of this application is shown;

[0029] Figure 4 A circuit diagram of yet another filtering device provided in an embodiment of this application is shown;

[0030] Figure 5 A schematic flowchart of a signal processing method provided in an embodiment of this application is shown;

[0031] Figure 6 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present invention;

[0032] Figure 7This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Detailed Implementation

[0033] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0034] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0035] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0036] Figure 1 A schematic diagram of a traditional filter device is shown, such as... Figure 1 As shown, the traditional filtering device includes a traditional shift register (DFF) 01, a traditional logic operation circuit 02, and a traditional decimation unit 03. The traditional shift register 01 and the traditional logic operation circuit 02 are connected, and the traditional logic operation circuit 02 and the traditional decimation unit 03 are connected. After the signal sequence x(n) passes through the shift register, the signal at the tap first passes through an adder, then a multiplier, and finally sums to obtain the filtered signal sequence y(n). This filtered signal is then decimated by a factor of 2 to obtain the sequence y(2n).

[0037] Considering that the calculated data is decimated by a factor of 2, which essentially means discarding every other data point, if the output signal sequence is y(m) = y(2n), then the difference equation after decimation satisfies:

[0038]

[0039] Where x(m) = x(2n) represents the input signal sequence after being decimated by a factor of 2. is the tap coefficient. Where k = 2j, that is, j = k / 2, k is an odd number and k ≠ (N-1) / 2.

[0040] A typical decimation filter consists of a register, a decimation unit, a multiplier, and an adder connected in sequence. That is, the signal is decimated before logical operations are performed to reduce the signal sampling rate. However, the delays of the multipliers and adders increase with the data bit width, leading to a reduction in data processing speed and accuracy. This causes the decimation filter to malfunction at higher clock frequencies, further reducing the acceptable input signal bandwidth range.

[0041] Figure 2 A schematic diagram of a filtering device provided in an embodiment of the present invention is shown, as follows: Figure 2 As shown, the filtering device includes a shift register 10 and a data processor 20 that communicates with the shift register 10.

[0042] The shift register 10 is used to process data based on the input signal sequence to obtain a shift signal sequence.

[0043] The data processor 20 is used to extract data based on the shift signal sequence to obtain the extracted signal sequence; and to perform logical operations based on the extracted signal sequence to obtain the output signal sequence.

[0044] Optionally, the data processor 20 is used to perform addition operations based on the decimated signal sequence to obtain a decimated sum signal sequence; perform addition operations based on the decimated signal sequence to obtain a decimated sum signal sequence; and perform multiplication operations based on the decimated sum signal sequence to obtain an output signal sequence.

[0045] In summary, this filtering device uses a data processor to extract data from a shifted signal sequence to obtain an extracted signal sequence; then, it performs logical operations on the extracted signal sequence to obtain an output signal sequence. This allows the filtering device to operate without altering its fundamental filtering principle. The data processor first extracts the data to obtain the extracted signal, and then performs logical operations. Compared to traditional filtering devices, the data extraction simplifies the logic circuitry required for logical operations. Furthermore, this allows the filtering device to operate at higher clock frequencies, ensuring that it can adapt to higher input signal bandwidths while maintaining sufficient input signal accuracy.

[0046] Optional, Figure 3 A schematic diagram of another filtering device provided in an embodiment of this application is shown, such as... Figure 3 As shown, the data processor 20 includes an extraction unit 201 and a logic operation circuit 202. The shift register 10 is connected to the extraction unit 201, and the extraction unit 201 is connected to the logic operation circuit 202.

[0047] The extraction unit 201 is used to extract data based on the shift signal sequence to obtain the extracted signal sequence.

[0048] The logic operation circuit 202 is used to perform addition operations based on the decimated signal sequence to obtain a decimated sum signal sequence; perform addition operations based on the decimated signal sequence to obtain a decimated sum signal sequence; and perform multiplication operations based on the decimated sum signal sequence to obtain an output signal sequence.

[0049] Optional, Figure 4 A schematic diagram of another filtering device provided in an embodiment of this application is shown, such as... Figure 4 As shown, the logic operation circuit 202 includes an adder circuit 202A and a multiplier circuit 202B. The extraction unit 201 is connected to the adder circuit 202A, and the adder circuit 202A and the multiplier circuit 202B are connected.

[0050] The adder circuit 202A is used to perform addition operations based on the decimated signal sequence to obtain the decimated sum signal sequence.

[0051] The multiplier circuit 202B is used to perform multiplication operations based on the decimation and signal sequences to obtain the output signal sequence.

[0052] The multiplication sub-circuit 202B performs multiplication operations on the decimated signal sequence, and then segments the signal sequence obtained from the multiplication operation to obtain the output signal sequence.

[0053] In this application, an addition-then-multiplication logic circuit is used, which can reduce the number of multipliers by nearly half. This allows the filtering device to operate without changing the filtering principle. The data processor first extracts the data to obtain the extracted signal, and then performs logic operations. Compared with traditional filtering devices, the logic operation circuit required during the logic operation process is simplified because data extraction is performed first. Furthermore, the filtering device can operate at a higher clock frequency, ensuring that it can adapt to higher input signal bandwidth while maintaining sufficient input signal accuracy.

[0054] For example, see Figure 4 Where x(n) is the input signal sequence and y(2n) is the output signal sequence. The tap coefficients are used. After the input signal sequence enters the shift register 10, the signal sequence at the tap first passes through the decimation unit 201, and then through the adder circuit 202A and the multiplier circuit 202B to obtain the output signal sequence.

[0055] The difference equation for a typical N-tap FIR digital filter is:

[0056]

[0057] Among them, b k Let n be the sequence value of the unit impulse response h(n). n represents the index in the input signal sequence. N represents the number of taps in the filter. In this application, the filter can be a half-band (HB) FIR filter. The characteristics of an HB FIR filter include that its amplitude-frequency response is symmetrical about one-quarter of the sampling frequency, and that the passband ripple is equal to the stopband ripple. This characteristic determines that the number of taps N in the HB FIR filter is odd, and b... k Nearly half of the values ​​are zero, and it exhibits symmetry:

[0058] b k =b N-(k+1) (3);

[0059] b k =0, k is odd and k≠(N-1) / 2 (4);

[0060] A coefficient of zero means that, compared to an FIR filter, the HB FIR filter eliminates nearly half the number of multipliers; symmetrical coefficients mean that by extracting common factors, the calculation order is changed from multiplication before addition to addition before multiplication, further reducing the number of multipliers by nearly half. Compared to a regular FIR filter, the HB FIR filter reduces the number of multipliers, saving circuit resources.

[0061] Substituting equation (4) into equation (2), and transforming equation (2), we can obtain:

[0062]

[0063]

[0064] In summary, the difference equation for an N-tap HB FIR filter is:

[0065]

[0066] Where k = 2j, that is, j = k / 2, k is an odd number and k ≠ (N-1) / 2.

[0067] In summary, this filtering device uses a data processor to extract data from a shifted signal sequence to obtain an extracted signal sequence; then, it performs logical operations on the extracted signal sequence to obtain an output signal sequence. This allows the filtering device to operate without altering its fundamental filtering principle. The data processor first extracts the data to obtain the extracted signal, and then performs logical operations. Compared to traditional filtering devices, the data extraction simplifies the logic circuitry required for logical operations. Furthermore, this allows the filtering device to operate at higher clock frequencies, ensuring that it can adapt to higher input signal bandwidths while maintaining sufficient input signal accuracy.

[0068] Figure 5 This illustration shows a schematic flowchart of a signal processing method provided in an embodiment of this application. The method is applied to a data processor, and the data processor and shift register form a filtering device, such as... Figure 5 As shown, the method includes:

[0069] Step 301: Obtain the shift signal sequence obtained by the shift register based on the input signal sequence through data processing.

[0070] The shift register can store data signals and can shift the data signals to the left or right sequentially under the action of the clock signal.

[0071] It should be noted that the specific model of the shift register is not limited in the embodiments of this application, and the calibration can be adjusted according to the actual application scenario.

[0072] After obtaining the shift signal sequence obtained by the shift register through data processing based on the input signal sequence, step 302 is executed.

[0073] Step 302: Extract data based on multiple shift signals to obtain the extracted signal sequence.

[0074] After extracting data based on multiple shift signals to obtain the extracted signal sequence, step 303 is executed.

[0075] Step 303: Perform calculations based on the extracted signal sequence to obtain the output signal sequence.

[0076] Optionally, the data establishment can first be based on the decimated signal sequence by performing addition operations to obtain the decimated sum signal sequence; then, based on the decimated sum signal sequence by performing multiplication operations to obtain the output signal sequence.

[0077] For example, see Figure 4 Where x(n) is the input signal sequence and y(2n) is the output signal sequence. The tap coefficients are used. After the input signal sequence enters the shift register 10, the signal sequence at the tap first passes through the decimation unit 201, and then through the adder circuit 202A and the multiplier circuit 202B to obtain the output signal sequence.

[0078] The difference equation for a typical N-tap FIR digital filter is:

[0079]

[0080] Among them, b k Let n be the sequence value of the unit impulse response h(n). n represents the index in the input signal sequence. N represents the number of taps in the filter. In this application, the filter can be a half-band (HB) FIR filter. The characteristics of an HB FIR filter include that its amplitude-frequency response is symmetrical about one-quarter of the sampling frequency, and that the passband ripple is equal to the stopband ripple. This characteristic determines that the number of taps N in the HB FIR filter is odd, and b... k Nearly half of the values ​​are zero, and it exhibits symmetry:

[0081] b k =b N-(k+1) (3);

[0082] b k =0, k is odd and k≠(N-1) / 2 (4);

[0083] In this embodiment, a coefficient of zero means that the HB FIR filter eliminates nearly half the number of multipliers compared to an FIR filter; symmetrical coefficients mean that by extracting common factors, the calculation order is changed from multiplication followed by addition to addition followed by multiplication, further reducing the number of multipliers by nearly half. Compared to a regular FIR filter, the HB FIR filter reduces the number of multipliers, saving circuit resources.

[0084] Substituting equation (4) into equation (2), and transforming equation (2), we can obtain:

[0085]

[0086] In summary, the difference equation for an N-tap HB FIR filter is:

[0087]

[0088] Where k = 2j, that is, j = k / 2, k is an odd number and k ≠ (N-1) / 2.

[0089] In summary, the signal processing method provided in this embodiment of the invention uses a data processor to extract data based on a shift signal sequence to obtain an extracted signal sequence; and performs logical operations based on the extracted signal sequence to obtain an output signal sequence. This allows the filtering device to operate without changing the filtering principle. The data processor first extracts data to obtain an extracted signal, and then performs logical operations. Compared with traditional filtering devices, the data extraction simplifies the logic operation circuit required during logical operations. Furthermore, the filtering device can operate at a higher clock frequency, ensuring that it can adapt to higher input signal bandwidth while maintaining sufficient input signal accuracy.

[0090] This invention provides a digital down-converter, including... Figures 2 to 4 Any of the filtering devices shown.

[0091] In this invention, the filtering device in the digital down-converter uses a data processor to extract data based on a shift signal sequence to obtain an extracted signal sequence; then, logical operations are performed on the extracted signal sequence to obtain an output signal sequence. This allows the filtering device to operate at a higher clock frequency without changing its working principle. The data processor first extracts data to obtain the extracted signal, and then performs logical operations. Compared with traditional filtering devices, the data extraction simplifies the logic operation circuitry required for logical operations. Furthermore, the filtering device can operate at a higher clock frequency, ensuring that it can adapt to higher input signal bandwidth while maintaining sufficient input signal accuracy.

[0092] Figure 6 A schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention is shown. Figure 6 As shown, the electronic device 400 includes a processor 410.

[0093] like Figure 6As shown, the processor 410 described above can be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits used to control the execution of the program of the present invention.

[0094] like Figure 6 As shown, the electronic device 400 may further include a communication line 440. The communication line 440 may include a path for transmitting information between the components.

[0095] Optional, such as Figure 6 As shown, the above-described electronic device may further include a communication interface 420. There may be one or more communication interfaces 420. The communication interface 420 may use any transceiver-like device for communicating with other devices or communication networks.

[0096] Optional, such as Figure 6 As shown, the electronic device may further include a memory 430. The memory 430 stores computer execution instructions for implementing the present invention, and its execution is controlled by a processor. The processor executes the computer execution instructions stored in the memory to implement the method provided in the embodiments of the present invention.

[0097] like Figure 6 As shown, memory 430 can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. Memory 430 can exist independently and be connected to processor 410 via communication line 440. Memory 430 can also be integrated with processor 410.

[0098] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0099] In a specific implementation, as one example, such as Figure 6 As shown, processor 410 may include one or more CPUs, such as Figure 6 CPU0 and CPU1 in the CPU.

[0100] In a specific implementation, as one example, such as Figure 6 As shown, the terminal device may include multiple processors, such as Figure 6 The processors 410 and 450 are included. Each of these processors can be a single-core processor or a multi-core processor.

[0101] Figure 7 This is a schematic diagram of the chip structure provided in an embodiment of the present invention. Figure 7 As shown, the chip 500 includes one or more processors 510.

[0102] Optional, such as Figure 7 As shown, the chip also includes a communication interface 520 and a memory 530. The memory 530 may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include non-volatile random access memory (NVRAM).

[0103] In some implementations, such as Figure 7 As shown, memory 530 stores the following elements: execution modules or data structures, or subsets thereof, or extended sets thereof.

[0104] In embodiments of the present invention, such as Figure 7 As shown, the corresponding operation is executed by calling the operation instructions stored in the memory (which can be stored in the operating system).

[0105] like Figure 7 As shown, the processor 510 controls the processing operations of any one of the terminal devices. The processor 510 can also be called a central processing unit (CPU).

[0106] like Figure 7 As shown, memory 530 may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory 530 may also include NVRAM. For example, in an application, memory, communication interfaces, and memory are coupled together via a bus system, which may include, in addition to a data bus, a power bus, a control bus, and a status signal bus, etc. However, for clarity, in... Figure 7 The general labeled all buses as Bus System 540.

[0107] like Figure 7 As shown, the methods disclosed in the above embodiments of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0108] On the one hand, a computer-readable storage medium is provided, which stores instructions that, when executed, implement the functions performed by the terminal device in the above embodiments.

[0109] On the one hand, a chip is provided that is used in a terminal device. The chip includes at least one processor and a communication interface. The communication interface and at least one processor are coupled together. The processor is used to run instructions to implement the functions performed by the filtering device in the above embodiments.

[0110] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0111] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0112] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A filtering device, characterized in that, Comprise: A shift register and a data processor in communication with the shift register; wherein, The data processor comprises an extraction unit and a logic operation circuit, the shift register and the extraction unit are connected, and the extraction unit and the logic operation circuit are connected; The shift register is used for data processing based on an input signal sequence to obtain a shift signal sequence; The data processor is used for data extraction based on the shift signal sequence to obtain an extraction signal sequence; and logic operation processing based on the extraction signal sequence to obtain an output signal sequence.

2. The filtering device of claim 1, wherein, The data processor is used for addition operation processing based on the extraction signal sequence to obtain an extraction and signal sequence; addition operation processing based on the extraction signal sequence to obtain an extraction and signal sequence; and multiplication operation processing based on the extraction and signal sequence to obtain an output signal sequence.

3. The filtering device of claim 1, wherein, The logic operation circuit comprises an addition sub-circuit and a multiplication sub-circuit, the extraction unit and the addition sub-circuit are connected, and the addition sub-circuit and the multiplication sub-circuit are connected; The addition sub-circuit is used for addition operation processing based on the extraction signal sequence to obtain an extraction and signal sequence; The multiplication sub-circuit is used for multiplication operation processing based on the extraction and signal sequence to obtain an output signal sequence.

4. A signal processing method characterized by, Applied to a data processor, the data processor and a shift register constitute a filter device, the data processor comprises an extraction unit and a logic operation circuit, the shift register and the extraction unit are connected, and the extraction unit and the logic operation circuit are connected; The method comprises: Obtaining a shift signal sequence obtained by the shift register based on data processing of an input signal sequence; Based on a plurality of the shift signals, data extraction is performed to obtain an extraction signal sequence; Based on the extraction signal sequence, operation processing is performed to obtain an output signal sequence.

5. The signal processing method of claim 4, wherein, The operation processing based on the extraction signal sequence to obtain an output signal sequence comprises: Based on the extraction signal sequence, addition operation processing is performed to obtain an extraction and signal sequence; Based on the extraction and signal sequence, multiplication operation processing is performed to obtain an output signal sequence.

6. A digital down converter characterized by The filter device of any one of claims 1 to 3.

7. An electronic device, comprising: The digital down converter of claim 6.

8. A readable storage medium, characterized by, The readable storage medium stores programs or instructions, and the programs or instructions are executed by a processor to realize the signal processing method of claim 4 or 5.

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