Frequency Multiplier Using a Recirculation Delay Circuit and Method Thereof

Abstract

A frequency multiplier and a frequency doubling method are provided. The frequency doubling method includes: receiving a first clock, where the first clock has a 50% duty cycle and is a two-phase clock including a first phase and a second phase; using a multiplexer to select and output one of the first phase and the second phase of the first clock according to a third clock as a second clock; using a recirculating delay circuit to delay the second clock into a fourth clock; and using a 1:2 frequency divider circuit to output the third clock according to the fourth clock.

Description

Technical Field

[0001] The present disclosure relates to frequency multipliers, and more particularly to frequency multiplier circuits and methods with high energy efficiency duty cycle control. Background Art

[0002] Many modern electronic circuits require an accurate clock to operate correctly. A clock is a voltage signal that periodically switches back and forth between a low potential and a high potential. The percentage of time that the voltage signal remains at the high potential is called the duty cycle. Many circuits require a specific clock duty cycle to provide optimal performance. For example, in a multi-phase clock system where both the rising edge and the falling edge of the clock are used, a duty cycle of 50% is typically desired.

[0003] A Taiwan, China patent application (application number: 109145668) proposes a frequency multiplier that employs duty cycle control. This duty cycle control uses a digital control delay circuit, has the characteristics of a digital circuit, and is not limited to generating an output with a duty cycle of 50%. This case uses a digital control delay circuit. However, there is a need to improve such circuits and methods to further increase efficiency. Summary of the Invention

[0004] An embodiment of the present disclosure provides a frequency multiplier, comprising: a multiplexer configured to receive a first clock and output a second clock according to a third clock, wherein the first clock has a duty cycle of fifty percent and is a two-phase clock including a first phase and a second phase; a recirculating delay circuit (RDC) configured to receive the second clock and output a fourth clock and a fifth clock; and a divide-by-two circuit configured to receive the fourth clock and output the third clock, wherein the recirculating delay circuit includes a logic gate and a delay chain, the delay chain includes a plurality of clock buffers, the clock buffers include an intermediate clock buffer and a final clock buffer, the logic gate is configured to receive the second clock and the fifth clock and output a sixth clock, and the clock buffers are cascaded and configured to receive the sixth clock, output the fourth clock from the intermediate clock buffer, and output the fifth clock from the final clock buffer.

[0005] An embodiment of the present invention provides a frequency doubling method, comprising: receiving a first clock, the duty cycle of the first clock being fifty percent and being a two-phase clock including a first phase and a second phase; using a multiplexer to select and output one of the first phase and the second phase of the first clock according to a third clock as a second clock; using a recycling delay circuit to delay the second clock into a fourth clock; and using a divide-by-two circuit to output the third clock according to the fourth clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A Schematic diagram showing a frequency doubler according to an embodiment of the present disclosure;

[0007] Figure 1B Show Figure 1A An example of a timing diagram of the frequency doubler;

[0008] Figure 2A Schematic diagram showing a duty cycle detector;

[0009] Figure 2B Schematic diagram showing another duty cycle detector;

[0010] Figure 3 Schematic diagram showing a power supply circuit;

[0011] Figure 4 Schematic diagram showing a controller and a power supply circuit based on an analog control scheme; and

[0012] Figure 5 Flowchart showing a frequency doubling method according to an embodiment of the present disclosure.

[0013] SYMBOLS AND NOTATIONS

[0014] 100: Frequency doubler

[0015] 110: Multiplexer

[0016] 120: Recycling delay circuit

[0017] 121: NAND gate

[0018] 122: Delay chain

[0019] 122A, 122B, 122C, 122D: Clock buffer

[0020] 130: Divide-by-two circuit

[0021] 131: Data flip-flop

[0022] 140: Duty cycle detector

[0023] 150: Controller

[0024] 160: Power supply circuit

[0025] INV1, INV2, 270: Inverters

[0026] M1, M2, M3, M4, 320, 420: Transistors

[0027] 200A: Duty cycle detection circuit

[0028] 210: Low-pass filter

[0029] 211, 221, 241, 251: Resistors

[0030] 212, 222, 242, 252, 410: Capacitors

[0031] 220: Resistive voltage divider

[0032] 230, 260: Comparators

[0033] 200B: Duty cycle detector

[0034] 240: First low-pass filter

[0035] 250: Second low-pass filter

[0036] 300: Power supply circuit

[0037] 310: Digital-to-analog converter

[0038] 320: Transistor

[0039] 400: Control circuit

[0040] 510, 520, 530, 540: Steps Detailed implementation manners

[0041] The present disclosure relates to a frequency multiplier. Although the specification describes several exemplary embodiments of implementing the present invention in the present disclosure, it should be understood that the present invention can be implemented in various ways and is not limited to the specific examples described below or any specific manner of implementing the features of the examples. In other cases, well-known details are not shown or described in order to focus on discussing various aspects of the present disclosure.

[0042] Those skilled in the art understand the terms and basic concepts related to microelectronics used in the present disclosure, such as "voltage", "current", "signal", "power supply", "(ground)", "complementary metal oxide semiconductor (CMOS)", "n-channel metal oxide semiconductor (NMOS)", "p-channel metal oxide semiconductor (PMOS)", "resistor", "capacitor", "comparator", "transconductance amplifier", "inverter", "logic signal", "multiplexer", "switch", "data flip flop", "logic gate", "NAND gate", "low-pass filter", "digital", "analog", and "duty cycle". Such terms are used in the field of microelectronics, and the related concepts are obvious to those skilled in the art, so they will not be described in detail here.

[0043] Those skilled in the art recognize the symbols of resistors and metal-oxide semiconductor (MOS) transistors (including PMOS transistors and NMOS transistors), and can identify their terminals such as "source", "gate", and "drain". Those skilled in the art can read the schematic diagrams of circuits including resistors, NMOS transistors, and PMOS transistors, and do not require a detailed description of how one transistor or resistor is connected to another transistor or resistor in the schematic diagram.

[0044] The present disclosure is described in engineering concepts. For example, regarding two variables X and Y, when it is said that "X is equal to Y", it means that "X is approximately equal to Y", that is, "the difference between X and Y is less than the specified engineering tolerance". When it is said that "X is zero", it means that "X is approximately zero", that is, "X is less than the specified engineering tolerance". When it is said that "X is significantly less than Y", it means that "X is negligible relative to Y", that is, "the ratio of X to Y is less than the engineering tolerance, so X is negligible compared to Y".

[0045] Throughout the present disclosure, "V DD " represents the power supply node. Note that the power supply node is a node with a substantially fixed voltage level. In the present disclosure, depending on the context that is obvious to those skilled in the art, sometimes V DD refers to the power supply node V DDThe voltage level at a certain point. For example, it is obvious that when we say "V DD is 1.05V", it means the voltage level on the power supply node V DD is 1.05V. The ground node is the node where the voltage level is basically zero.

[0046] In the present disclosure, a signal is a voltage or current whose level varies (with time), or a number that has a value that can vary with time. When the signal is a voltage, it is called a voltage signal, and the level of the signal at a certain moment represents the state of the signal at that moment. When the signal is a number, it is called a numerical signal (also called a digital signal), and the value of the signal at a certain moment represents the state of the signal at that moment.

[0047] A logic signal is a voltage signal with two states: a low level state and a high level state. The low level state is also called the "0" state, and the high level is also called the "1" state. Regarding the logic signal Q, when it is said that "Q is at a high level" or "Q is at a low level", it means that "Q is in the high level state" or "Q is in the low level state". Similarly, when it is said that "Q is 1" or "Q is 0", it means that "Q is in the state of 1" or "Q is in the state of 0".

[0048] When a logic signal switches from a low level to a high level, it undergoes a transition from a low level to a high level and exhibits a rising edge. When a logic signal switches from a high level to a low level, it undergoes a transition from a high level to a low level and exhibits a falling edge.

[0049] When using a MOS transistor to implement a switch, it is controlled by a control signal, which is a logic signal applied to the gate of the MOS transistor. When the control signal is at a high level, the switch implemented by the NMOS transistor is in the "on" state, and when the control signal is at a low level, it is in the "off" state.

[0050] If the first logic signal and the second logic signal are always in opposite states, then we say that the first logic signal is the inverse or inverse logic of the second logic signal. That is, when the first logic signal is at a low level, the second logic signal is at a high level; when the first logic signal is at a high level, the second logic signal is at a low level. When we say that the first logic signal is the inverse logic of the second logic signal, it means that the first logic signal and the second logic signal are complementary to each other.

[0051] A two-phase clock is a clock that has two phases (including a first phase and a second phase), where the second phase is the inverse logic of the first phase (i.e., the second phase is complementary to the first phase); when both the first phase and the second phase have a 50% duty cycle, this two-phase clock is considered to have a 50% duty cycle.

[0052] A clock buffer is a circuit that receives a first clock as an input and outputs a second clock as an output, where, except that the timing delay is significantly less than the period of the first clock, the second clock is substantially the same as the first clock. For example (not intended to limit the present invention), the timing delay is 1% of the period of the first clock.

[0053] A "NAND gate" is a logic gate that receives first and second logic signals and outputs a third logic signal. If both the first logic signal and the second logic signal are at a high level, the third logic signal is at a low level, and in other cases the third logic signal is at a high level. Those skilled in the art of this technology can recognize the circuit symbol of the NAND gate and understand its function without further explanation.

[0054] A digital word is a numerical signal of an integer value, and the numerical signal can be a set that contains multiple logic signals according to a certain coding scheme.

[0055] A transduction amplifier is a circuit that receives a voltage signal and outputs a current signal proportional to the voltage signal.

[0056] A circuit is a collection of transistors, resistors, and / or other electronic devices, and the transistors, resistors, and / or other electronic devices are interconnected in a certain way to achieve a certain function.

[0057] Figure 1ASchematic diagram showing a frequency doubler 100 according to an embodiment of the present disclosure. The frequency doubler 100 includes: a multiplexer 110 for receiving a first clock S1, the first clock S1 having a 50% duty cycle and being a two-phase clock including a first phase S1[0] and a second phase S1[1], and the multiplexer 110 outputting a second clock S2 according to a third clock S3; a recirculating delay circuit (RDC) 120 for receiving the second clock S2 and outputting a fourth clock S4 and a fifth clock S5; and a divide-by-two circuit 130 for receiving the fourth clock S4 and outputting the third clock S3. The RDC 120 includes a NAND gate 121 and a delay chain 122. The NAND gate 121 is used to receive the second clock S2 and the fifth clock S5 and output a sixth clock S6. The delay chain 122 includes a plurality of clock buffers 122A, 122B, …, 122C and 122D, which are connected in a cascade topology and are used to receive the sixth clock S6 and output the fourth clock S4 and the fifth clock S5, where the clock buffer 122D is the last clock buffer for outputting the fifth clock S5, and the clock buffer 122C is the intermediate clock buffer for outputting the fourth clock S4.

[0058] For simplicity, in the following description, the first clock S1 is abbreviated as S1; the first phase S1[0] of the first clock S1 is abbreviated as S1[0]; the second phase S1[1] of the first clock S1 is abbreviated as S1[1]; the second clock S2 is abbreviated as S2; the third clock S3 is abbreviated as S3; the fourth clock S4 is abbreviated as S4; the fifth clock S5 is abbreviated as S5; and the sixth clock S6 is abbreviated as S6.

[0059] In one embodiment, each of the clock buffers 122A, 122B, …, 122C and 122D includes two inverters, and the two inverters are connected in series to form a non-inverting buffer. As shown in the detail box COB122D, the clock buffer 122D includes two inverters INV1 and INV2, which are configured in a cascade topology to receive the fourth clock S4 and output the fifth clock S5. The fifth clock S5 is logically the same as S4, but when the state of S4 switches, the fifth clock S5 has a timing delay, that is, the rising (falling) edge of S4 causes the rising (falling) edge of S5 after a timing delay. The inverter INV1 includes an NMOS transistor M1 and a PMOS transistor M2, and the inverter INV2 includes an NMOS transistor M3 and a PMOS transistor M4. Here, "V SP” represents the power node of the delay chain 122. The timing delay of the clock buffer 122D depends on the voltage level at the power node “V SP ”: a higher (lower) voltage level results in a shorter (longer) delay because MOS transistors respond faster when the power supply voltage is higher. This is obvious to those skilled in the art and thus requires no further explanation.

[0060] In one embodiment, the clock buffers 122A, 122B, …, and 122C are implemented by the same circuit as the circuit shown in the detailed block COB122D.

[0061] The multiplexer 110 selects S1[0] or S1[1] as S2 according to S3 and outputs S2, and its function can be described by the following formula:

[0062]

[0063] The multiplexer (e.g., the multiplexer of the multiplexer 110 that can be implemented based on Equation (1) Figure 1A is well known in the prior art and thus will not be described in detail here.

[0064] The RDC 120 receives S2 and outputs S4 and S5. When S2 is at a low level, regardless of S5, S6 will be at a high level, and the RDC 120 will remain in the halted state, where the outputs of the clock buffers 122A, 122B, etc. (including S4 and S5) are all at a high level. Upon the rising edge of S2, the RDC 120 enters the recycle state, and as long as S2 remains at a high level, the RDC 120 remains in the recycle state, where the NAND gate 121 effectively acts as an inverter (because S6 will be the inverse logic of S5), and moreover, the NAND gate 121 and the delay chain 122 form a negative feedback loop to allow the recycling of the clock, where the falling edge of S6 will propagate in the delay chain 121 and cause the falling edge of S4, followed by the falling edge of S5, and then cause the rising edge of S6. On the other hand, the rising edge of S6 will propagate in the delay chain 121 and cause the rising edge of S4, followed by the rising edge of S5, and then cause the falling edge of S6 (if S2 still remains at a high level). In this way, the delay function is achieved such that the rising edge of S2 can trigger the rising edge of S4, and the timing delay between the two is determined by the propagation delay of the delay chain 122, and this propagation delay is the sum of the timing delays of all the clock buffers 122A, 122B, …, 122C and 122D.

[0065] The 1:2 frequency divider circuit 130 includes a data flip-flop 131. The data flip-flop 131 is triggered by S4 and configured in a negative feedback topology to achieve the 1:2 frequency division function, such that the rising edge of S4 triggers S3 to switch states, thereby resulting in the rising edge or falling edge of S3. If the rising edges of S4 are numbered, the even rising edges of S4 trigger S3 to switch from a low potential to a high potential (i.e., the rising edge of S3), while the odd rising edges of S4 trigger S3 to switch from a high potential to a low potential (i.e., the falling edge of S3). Since only one rising edge of S3 is triggered by every two rising edges of S4, S3 is referred to as the 1:2 frequency division clock of S4. The data flip-flop 131 has an input pin (labeled D), an output pin (labeled Q), a complementary output pin (labeled QB), and a trigger pin (marked with a wedge). The data flip-flop 131 is obvious to those skilled in the art and does not require further explanation.

[0066] S1 is a two-phase clock with a 50% duty cycle. Let the period of S1 be T. The purpose of the frequency multiplier 100 is to make S2 a frequency-multiplied clock. In other words, since frequency multiplication means halving the period, the period of S2 is equal to T / 2. S4 is a delay of S2, so the period is also T / 2. S3 is the 1:2 frequency division clock of S4, so the period of S3 is twice the period of S4, that is, the period of S3 is T.

[0067] Figure 1B An example of the timing diagram showing the frequency multiplier 100 is presented. Here, S1[0], S1[1], S2, S3, S4, S5, and S6 are all clocks, that is, logic signals. These logic signals are either at a high potential (V DD 、V SP or whatever voltage level of the power supply voltage) or at a low potential (0V). As shown in the figure, S1[0] and S1[1] are complementary. The period of S1[0] is T, as shown by the time difference T between the rising edge 190a (at time point t a ) and the subsequent rising edge 190g (at time point t g ). The duty cycle of S1[0] is 50%, as shown by the time difference T / 2 between the rising edge 190a and the subsequent falling edge 190d (at time point t d ), indicating that S1[0] maintains a high potential for 50% of the time in one clock cycle. Obviously, the period of S1[1] is T and the duty cycle of S1[1] is 50%. Initially, S1[0] is at a low potential, S1[1] is at a high potential, S3 is at a low potential, and the multiplexer 110 selects S1[0] as S2, so S2 is at a low potential, causing the RDC 120 to be in a stopped state, where S6, S4, and S5 are all at high potentials. At time point ta , the rising edge 190a of S1[0] causes the rising edge 192a of S2, putting the RDC 120 into the recirculation state; the RDC 120 entering the recirculation state activates the falling edge 196a of S6 (through the NAND gate 121), and the falling edge 196a propagates in the delay chain 122 and causes the falling edge 195b of S5 (time point tb), and thus causes the rising edge 196b of S6 (through the NAND gate 121). The rising edge 196b of S6 propagates in the delay chain 122 and causes the rising edge 194c of S4 (time point t c ), the rising edge 194c of S4 triggers a divide-by-two circuit 130 to switch S3 to the high potential, thereby causing the multiplexer 110 to select S1[1] as S2, thus causing the falling edge 192c of S2, and thus putting the RDC 120 into the stop state, where S6, S4, and S5 are all at the high potential. At time point t d , the rising edge 191d of S1[1] causes the rising edge 192d of S2, putting the RDC 120 into the recirculation state; the RDC 120 entering the recirculation state activates the falling edge 196d of S6 (through the NAND gate 121), and the falling edge 196d propagates in the delay chain 122 and causes the falling edge 195e of S5 (time point t e ), and thus causes the rising edge 196e of S6 (through the NAND gate 121). The rising edge 196e of S6 propagates in the delay chain 122 and causes the rising edge 194f of S4 (time point t f ), the rising edge 194f of S4 triggers a divide-by-two circuit 130 to switch S3 to the low potential, thereby causing the multiplexer 110 to select S1[0] as S2, thus causing the falling edge 192f of S2, and thus putting the RDC 120 into the stop state, where S6, S4, and S5 are all at the high potential. This completes one operation cycle, waiting for the next cycle starting with the rising edge 190g of S1[0] (time point t g ). In this way, S2 is a doubled-frequency clock, whose working cycle is determined by the propagation delay of the RDC 120, and the propagation delay of the RDC 120 depends on the voltage at the power supply node V SP .

[0068] Due to the reuse of the circuit, one of the advantages of using a recirculation delay circuit to introduce timing delay is performance. By recycling the clock, the delay can be approximately doubled, so the total number of clock buffers can be reduced by about half.

[0069] In one embodiment, the voltage level at the power supply node V SP is fixed. Such an embodiment is useful in applications where there is no strict requirement for the working cycle of S2.

[0070] In another embodiment (which includes a duty cycle corrector and is useful in applications that require a specific and precise duty cycle of S2), the frequency multiplier 100 further includes: a duty cycle detector 140 for receiving the second clock S2 and outputting a duty cycle error signal E dc ; a controller 150 for receiving the duty cycle error signal E dc and outputting a control signal S ctl ; and a power supply circuit 160 for establishing a voltage level at the power supply node V ctl according to the control signal S SP . For the sake of simplicity, hereinafter the duty cycle error signal E dc will be abbreviated as E dc , and the control signal S ctl will be abbreviated as S ctl . In one embodiment, a higher (lower) value of S ctl results in a higher (lower) voltage level at the power supply node V SP , and thus results in a shorter (longer) delay of the RDC 120. E dc is the comparison result of D out and D tgt , where D out is the duty cycle value of S2, and D tgt is the target duty cycle value. If E dc indicates that D out is greater than (less than) D tgt and needs to be decreased (increased), then the controller 150 will increase (decrease) the value of S ctl to shorten (lengthen) the delay of the RDC 120 and cause a decrease (increase) in the duty cycle of S2. Thereby, the duty cycle of S2 is regulated in a closed-loop manner such that the duty cycle of S2 is equal to the target duty cycle.

[0071] Further embodiments can be based on a digital control scheme or an analog control scheme. First, the digital control scheme will be introduced below, and then the analog control scheme will be introduced.

[0072] In an embodiment based on a digital control scheme, E dc is a logic signal, and the duty cycle detector 140 outputs E dc according to the following formula:

[0073]

[0074] When E dc is 1, it means that the duty cycle of S2 is greater than the target duty cycle value D tgt , so it needs to be decreased. When E dc is 0, it means that the duty cycle of S2 is less than the target duty cycle value Dtgt , so it needs to be increased.

[0075] In an embodiment based on a digital control scheme, S ctl is an integer, and the larger the value of S ctl , the smaller the propagation delay of RDC120. In one embodiment, the controller 150 periodically updates the value of S according to the following formula ctl :

[0076]

[0077] Here, represents the old value of S ctl before the update, and represents the new value of S ctl after the update. When the duty cycle of S2 is too large (i.e., D out > D tgt ), E dc is 1, and the controller 150 increases the value of S ctl , resulting in a smaller propagation delay of RDC 120, so the duty cycle of S2 decreases. When the duty cycle of S2 is too small (i.e., D out < D tgt ), E dc is 0, and the controller 150 decreases the value of S ctl , resulting in a larger propagation delay of RDC 120, so the duty cycle of S2 increases.

[0078] Note that Equation (3) describes an integrator function, where S ctl is the integral of E dc , provided that the potential represented by the second state of E dc (E dc = 0) is the inverse of the potential represented by the first state of E dc (E dc = 1).

[0079] Figure 2A FIG. shows a schematic diagram of the duty cycle detection circuit 200A. The duty cycle detection circuit 200A can be used to implement the duty cycle detector 140 based on a digital control scheme. The duty cycle detection circuit 200A includes: a low-pass filter 210, which includes a resistor 211 and a capacitor 212; a resistive voltage divider 220, which includes a resistor 221 and a resistor 222; and a comparator 230. The low-pass filter 210 receives S2 and outputs an average voltage V a , and the average voltage V a is approximately D out V DD , where V DDis the supply voltage of S2, and thus the voltage level when S2 is at a high potential. For example, if the duty cycle of S2 is 40%, then since S2 remains at the high potential V DD , V a will be approximately 0.4·V DD . The resistor divider 220 outputs the target voltage V tgt , where D tgt is the target duty cycle value of S2. Assume that the resistances of resistor 221 and resistor 222 are R tgt and R 221 respectively, and R 222 is determined according to the following formula. 221 is determined according to the following formula.

[0080]

[0081] The target voltage V DD is established based on the voltage division of V tgt across resistors 221 and 222, that is:

[0082]

[0083] where Equation (4) is applied. The comparator 230 compares V a with V tgt and outputs E dc to indicate whether V a is higher than V tgt . When V a is higher (lower) than V tgt , E dc is 1 (0), indicating that D out V DD is greater (less) than D tgt V DD , so D out is greater (less) than D tgt . When D out is greater (less) than D tgt , E dc is 1 (0), and the controller 150 increases (decreases) the value of S ctl , resulting in a decrease (increase) in the propagation delay of RDC120 and the duty cycle of S2. Therefore, the duty cycle of S2 is regulated in a closed-loop manner to tend to be equal to D tgt .

[0084] In the special case where the target duty cycle value D tgt is 50%, based on a digital control scheme, Figure 2B as shown, another duty cycle detector 200B can be used to achieve Figure 1AThe duty cycle detector 140. The duty cycle detector 200B includes: a first low-pass filter 240 including a resistor 241 and a capacitor 242, an inverter 270, a second low-pass filter 250 including a resistor 251 and a capacitor 252, and a comparator 260. The inverter 270 receives S2 and outputs a complementary signal S'2, and the complementary signal S'2 is the inverted logic of S2. Since S'2 is complementary to S2 and the duty cycle of S2 is D out , the duty cycle of S'2 is 1-D out . The first low-pass filter 240 receives S2 and outputs an approximate D out V DD of the first average voltage V p . For example, if the duty cycle of S2 is 40%, then since S2 remains at the high potential V DD for 40% of the time, V p will be approximately 0.4·V DD . The second low-pass filter 250 receives S'2 and outputs a second average voltage V out of approximately (1-D DD )V n . For example, if the duty cycle of S2 is 40%, then since S'2 remains at the high potential V DD for 60% of the time (because it is complementary to S2), so V n will be approximately 0.6·V DD . The comparator 260 compares V p with V n and outputs E dc , to indicate whether V p is higher than V n . When V p is higher than / lower than V n , E dc is 1(0), indicating that D out V DD is greater than / less than (1-D out )V DD , so D out is greater than / less than (1-D out ), and indicates that D out is greater than / less than 50%. Therefore, if the target duty cycle value D tgt is 50%, the duty cycle detector 200B can perform duty cycle detection on S2.

[0085] Comparator (such as Figure 2A the comparator 230 in Figure 2BComparator 260) is a circuit that receives two voltages and outputs a logic signal (the logic signal indicates which of the two voltages is higher), and any known circuit in the prior art can be used to implement it at the discretion of the circuit designer. An inverter (such as inverter 270) is used to perform logical inversion, which is well known in the prior art and will not be described in detail here.

[0086] Figure 3 FIG. 4 shows a schematic diagram of a power supply circuit 300, which can be used to implement the power supply circuit 160 based on a digital control scheme. The power supply circuit 300 includes a digital-to-analog converter (DAC) 310 and an NMOS transistor 320. The DAC 310 is used to convert S ctl into a control voltage V ctl . The NMOS transistor 320 is configured as a source follower, which establishes a voltage level at the power supply node V ctl according to the control voltage V SP . Here, V DDH represents a power supply node whose voltage level is at least 200 mV higher than the voltage level on the power supply node V SP . The DAC and the source follower are both well known in the prior art and thus do not require further explanation.

[0087] In the analog control scheme, E dc is a current signal proportional to D out -D tgt , while S ctl is an analog voltage signal without discrete states. By replacing the comparator 230 with a transconductance amplifier, the duty cycle detection circuit 200A of Figure 2A can be modified for the analog control scheme such that E dc becomes a current proportional to V a -V tgt (ultimately proportional to D out -D tgt ) instead of a logic signal that is either high or low. Similarly, by replacing the comparator 260 with a transconductance amplifier, the duty cycle detection circuit 200B of Figure 2B can be modified for the analog control scheme. In the analog control scheme, the controller 150 and the power supply circuit 160 can be combined into the control circuit 400 shown in Figure 4 . The control circuit 400 includes a capacitor 410 and an NMOS transistor 420. The capacitor 410 is configured as a load for receiving E dc and establishing S ctl , while the NMOS transistor 420 is configured as a source follower, which according to S ctlEstablish a voltage level at the power supply node V SP The capacitor 410 implements an integration function similar to Equation (3).

[0088] As Figure 5 shown in the flowchart of, a frequency doubling method includes: (step 510) receiving a first clock, the first clock having a 50% duty cycle and being a two-phase clock including a first phase and a second phase; (step 520) using a multiplexer to select and output one of the first phase and the second phase of the first clock according to a third clock as a second clock; (step 530) using a recycling delay circuit to delay the second clock to be a fourth clock; (step 540) using a 1:2 frequency divider circuit to output the third clock according to the fourth clock.

[0089] Those skilled in the art will readily observe that various modifications and changes can be made to the apparatus and method while maintaining the teachings of the present disclosure. Therefore, the above disclosure should not be construed as being limited only by the bounds of the claims.

Claims

1. A frequency multiplier, comprising: A multiplexer for receiving a first clock and outputting a second clock according to a third clock, wherein the first clock has a 50% duty cycle and the first clock is a two-phase clock including a first phase and a second phase; A recirculating delay circuit for receiving the second clock and outputting a fourth clock and a fifth clock; And A 1:2 frequency divider for receiving the fourth clock and outputting the third clock, wherein the recirculating delay circuit includes a logic gate and a delay chain, the delay chain includes a plurality of clock buffers, the plurality of clock buffers include an intermediate clock buffer and a last clock buffer, the logic gate is for receiving the second clock and the fifth clock and outputting a sixth clock, the plurality of clock buffers are cascaded and are for receiving the sixth clock, outputting the fourth clock from the intermediate clock buffer, and outputting the fifth clock from the last clock buffer.

2. The frequency multiplier according to claim 1, further comprising: a duty cycle detector for receiving the second clock and outputting a duty cycle error signal; a controller for receiving the duty cycle error signal and outputting a control signal; and a power supply circuit for receiving the control signal and establishing a voltage level of a power supply node of the delay chain; wherein the control signal is for controlling a delay of the delay chain, and the controller is an integrator.

3. The frequency multiplier according to claim 2, wherein the duty cycle error is a logic signal indicating whether a duty cycle of the second clock is higher than a target duty cycle value, and the control signal is a digital signal, and the power supply circuit includes a digital-to-analog converter and a source follower, the digital-to-analog converter is for receiving the digital signal and outputting a control voltage, and the source follower is for receiving the control voltage and establishing the voltage level of the power supply node of the delay chain.

4. The frequency multiplier according to claim 2, wherein the duty cycle error is a current signal proportional to a difference, and the difference is a difference between a duty cycle value of the second clock and a target duty cycle value.

5. The frequency multiplier according to claim 1, further comprising: a duty cycle detector for receiving the second clock and outputting a duty cycle error signal; a controller for receiving the duty cycle error signal and outputting a control signal; and a power supply circuit for receiving the control signal and establishing a voltage level of a power supply node of the delay chain; wherein the control signal is for controlling a delay of the delay chain; wherein the controller includes a capacitor for receiving the duty cycle error signal and establishing a control voltage as the control signal, and the power supply circuit includes a source follower for receiving the control voltage and establishing the voltage level of the power supply node of the delay chain.

6. The frequency multiplier according to claim 1, wherein the 1:2 frequency divider includes a data flip-flop configured in a negative feedback topology.

7. A frequency multiplying method, comprising: Receive a first clock, where the first clock has a 50% duty cycle and the first clock is a two-phase clock including a first phase and a second phase; Use a multiplexer to select and output one of the first phase and the second phase of the first clock according to a third clock as a second clock; Use a recycling delay circuit to delay the second clock to become a fourth clock; and Use a 1:2 frequency divider circuit to output the third clock according to the fourth clock; Among them, The recycling delay circuit includes a logic gate and a delay chain. The logic gate is used to receive the second clock and a fifth clock and output a sixth clock. The delay chain delays the sixth clock and outputs the fifth clock.

8. The frequency doubling method according to claim 7, wherein the delay chain includes a plurality of clock buffers. The plurality of clock buffers include an intermediate clock buffer and a final clock buffer, and the plurality of clock buffers are cascaded and used to receive the sixth clock, output the fourth clock from the intermediate clock buffer, and output the fifth clock from the final clock buffer. The frequency doubling method further includes: controlling a delay of the delay chain through a power supply circuit controlled by a control signal, and outputting a duty cycle error signal according to a difference between a duty cycle value of the second clock and a target duty cycle value, and establishing the control signal by integrating the duty cycle error signal.

9. The frequency doubling method according to claim 8, wherein the duty cycle error is a logic signal indicating whether a duty cycle of the second clock is higher than the target duty cycle value, and the control signal is a digital signal. The power supply circuit includes a digital-to-analog converter and a source follower. The digital-to-analog converter is used to receive the digital signal and output a control voltage, and the source follower is used to receive the control voltage and establish a voltage level of a power supply node of the delay chain.

10. The frequency doubling method according to claim 8, wherein the duty cycle error is a current signal proportional to a difference, and the difference is a difference between the duty cycle value of the second clock and the target duty cycle value. The step of integrating the duty cycle error signal includes: using a capacitor to receive the duty cycle error signal and establish a control voltage as the control signal, and the power supply circuit includes a source follower. The source follower is used to receive the control voltage and establish a voltage level of a power supply node of the delay chain.

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