Switching circuit

Abstract

The present disclosure provides a switching circuit. The switching circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control terminal, a first output terminal, and a first input terminal, and the first input terminal receives a first input signal with a logic level of one. The first P-type control transistor is coupled to the first input terminal and the first control terminal. The first P-type control transistor includes a second control terminal, and the second control terminal receives a second input signal with a logic level of zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, it transmits the first input signal to the first control terminal of the P-type transistor switch to turn off the P-type transistor switch.

Description

Technical Field

[0001] The present disclosure relates to a switching circuit. Background Art

[0002] Metal Oxide Semiconductor (MOS) is a transistor that can be widely used in analog circuits and digital circuits. According to the polarity of its channel, Metal Oxide Semiconductor can be divided into N-channel type with majority electrons and P-channel type with majority holes, which are usually called N-type Metal Oxide Semiconductor (NMOS) and P-type Metal Oxide Semiconductor (PMOS) respectively. Both NMOS and PMOS can receive logic levels of zero or one of input signals through the gate to control the conduction or cutoff of NMOS and PMOS. Among them, the gate of NMOS conducts according to the input signal with a logic level of one, and the gate of NMOS cuts off according to the input signal with a logic level of zero; the gate of PMOS conducts according to the input signal with a logic level of zero, and the gate of PMOS cuts off according to the input signal with a logic level of one.

[0003] When the switching circuit is provided with PMOS and the power supply of the switching circuit is turned off, based on the characteristics of PMOS, the logic potential of the gate of PMOS is zero and PMOS is in a conducting state, and PMOS cannot be completely turned off, thus resulting in leakage of parasitic circuits and PMOS leakage. The leakage current may leak from the source of PMOS to the body or drain. Summary of the Invention

[0004] In some embodiments, a switching circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control terminal, a first output terminal, and a first input terminal, and the first input terminal receives a first input signal with a logic level of one. The first P-type control transistor is coupled to the first input terminal and the first control terminal. The first P-type control transistor includes a second control terminal, and the second control terminal receives a second input signal with a logic level of zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, it transmits the first input signal to the first control terminal of the P-type transistor switch to turn off the P-type transistor switch. Brief Description of the Drawings

[0005] Figure 1 is a circuit schematic diagram of an embodiment of the switching circuit according to the present disclosure.

[0006] Figure 2 is a circuit schematic diagram of another embodiment of the switching circuit according to the present disclosure.

[0007] Figure 3 is according to Figure 1 a circuit schematic diagram of an embodiment of the inverter of the switching circuit. Detailed implementation manners

[0008] Please refer to Figure 1 , Figure 1 which is a circuit schematic diagram of an embodiment of a switching circuit according to the present disclosure. The switching circuit includes a P-type metal oxide semiconductor field effect transistor (PMOS) as one of the switches in the switching circuit, hereinafter referred to as the P-type transistor switch 11. The P-type transistor switch 11 includes a control terminal (for convenience of description, hereinafter referred to as the first control terminal 111), an input terminal (hereinafter referred to as the first input terminal 112), and an output terminal (hereinafter referred to as the first output terminal 113). The first control terminal 111 is the gate of the P-type transistor switch 11. The first input terminal 112 can be the source of the P-type transistor switch 11, and the first output terminal 113 can be the drain of the P-type transistor switch 11. The P-type transistor switch 11 can control the conduction or cut-off of the P-type transistor switch 11 according to whether the logic level of the control signal received by the first control terminal 111 is zero or one. When the first control terminal 111 receives a control signal with a logic level of zero, the P-type transistor switch 11 can be turned on, and the P-type transistor switch 11 transmits the input signal received by the first input terminal 112, and the input signal can be transmitted from the first input terminal 112 to the first output terminal 113; when the first control terminal 111 receives an input signal with a logic level of one, the P-type transistor switch 11 can be turned off. Among them, when the power supply of the switching circuit is turned off, the logic level at the first control terminal 111 is zero. At this time, the P-type transistor switch 11 is turned on, and the current outside the switching circuit can leak from the first input terminal 112 to the first output terminal 113 according to the path P1 as shown in Figure 1 , or leak from the first input terminal 112 to the body 114 of the P-type transistor switch 11 according to the path P2.

[0009] To avoid the aforementioned leakage situation, please refer to Figure 2 , Figure 2 which is a circuit schematic diagram of another embodiment of the switching circuit according to the present disclosure. The switching circuit includes a P-type transistor switch 11 as shown in Figure 1 and a P-type control transistor (hereinafter referred to as the first P-type control transistor 12). The first P-type control transistor 12 is coupled between the first input terminal 112 and the first control terminal 111 of the P-type transistor switch 11, that is, the source of the first P-type control transistor 12 is coupled to the first input terminal 112, and the drain of the first P-type control transistor 12 is coupled to the first control terminal 111. The first P-type control transistor 12 further includes a control terminal (hereinafter referred to as the second control terminal 121), and the second control terminal 121 is the gate of the first P-type control transistor 12.

[0010] When the power supply of the switch circuit is turned off, the first input terminal 112 of the P-type transistor switch 11 receives a first input signal S1 with a logic level of one. Among them, the first input signal S1 is the current signal with leakage as described above. The second control terminal 121 of the first P-type control transistor 12 receives an input signal with a logic level of zero (hereinafter referred to as the second input signal S2), causing the first P-type control transistor 12 to conduct according to the second input signal S2. When the first P-type control transistor 12 conducts, the first input signal S1 with a logic level of one received at the first input terminal 112 is transmitted to the first control terminal 111 of the P-type transistor switch 11 through the first P-type control transistor 12, that is, the first control terminal 111 receives the first input signal S1 with a logic level of one, causing the P-type transistor switch 11 to turn off according to the logic level of the first input signal S1. Thus, the first input signal S1 with a logic level of one received at the first input terminal 112 is blocked from being transmitted to the first output terminal 113 through the P-type transistor switch 11.

[0011] Based on this, a first P-type control transistor 12 is provided in the switch circuit and coupled to the P-type transistor switch 11, and the first P-type control transistor 12 is controlled to conduct, so that the first input signal S1 with a logic level of one is transmitted to the P-type transistor switch 11 to turn off the P-type transistor switch 11, which can eliminate the leakage phenomenon generated when the power supply of the switch circuit is turned off. When the first input signal S1 received at the first input terminal 112 of the P-type transistor switch 11 is a leakage current signal, the first input signal S1 can be completely blocked from being transmitted to the first output terminal 113 according to the turn-off of the P-type transistor switch 11, ensuring that the P-type transistor switch 11 is indeed turned off when the power supply of the switch circuit is turned off.

[0012] In some embodiments, the switch circuit further includes an N-type transistor switch 13. The N-type transistor switch 13 is coupled between the first input terminal 112 and the first output terminal 113 of the P-type transistor switch 11. That is, the drain of the N-type transistor switch 13 is coupled to the first input terminal 112, and the source of the N-type transistor switch 13 is coupled to the first control terminal 111. The N-type transistor switch 13 further includes a control terminal (hereinafter referred to as the third control terminal 131), and the third control terminal 131 receives an input inverted signal S3. Wherein, the logic level of the input inverted signal S3 is the inverse of the logic level of the first input signal S1. That is to say, when the logic level of the first input signal S1 is one, the logic level of the input inverted signal S3 is zero, and both the N-type transistor switch 13 and the P-type transistor switch 11 are turned off; when the logic level of the first input signal S1 is zero, the logic level of the input inverted signal S3 is one, and both the N-type transistor switch 13 and the P-type transistor switch 11 are turned on. Therefore, the N-type transistor switch 13 and the P-type transistor switch 11 can jointly form a complementary metal oxide semiconductor (CMOS) switch.

[0013] In some embodiments, the switch circuit further includes an inverter 2. The inverter 2 is used to control components of the P-type transistor switch 11 and the N-type transistor switch 13. Please refer to Figure 2 and Figure 3 , Figure 3 is Figure 1 a schematic circuit diagram of an embodiment of the inverter 2 of the switch circuit according to. The inverter 2 is coupled between the third control terminal 131 of the N-type transistor switch 13 and the first control terminal 111 of the P-type transistor switch 11. The inverter 2 includes a P-type transistor 21 and an N-type transistor 22. The P-type transistor 21 includes a fourth control terminal 211, a second input terminal 213, and a second output terminal 212. The fourth control terminal 211 is the gate of the P-type transistor 21. The second input terminal 213 can be the source of the P-type transistor 21, and the second output terminal 212 can be the drain of the P-type transistor 21. The N-type transistor 22 includes a sixth control terminal 221. The sixth control terminal 221 can be the gate of the N-type transistor 22. Wherein, the N-type transistor 22 and the P-type transistor 21 are connected in series, and the drain of the N-type transistor 22 is coupled to the second output terminal 212 of the P-type transistor 21. The second output terminal 212 is coupled to the first control terminal 111 of the P-type transistor switch 11, that is, the first control terminal 111 is coupled between the P-type transistor 21 and the N-type transistor 22. The fourth control terminal 211 of the P-type transistor 21 and the sixth control terminal 221 of the N-type transistor 22 are mutually coupled, and the fourth control terminal 211 and the N-type transistor 22 are jointly coupled to the third control terminal 131 of the N-type transistor switch 13, that is, the third control terminal 131 is coupled between the fourth control terminal 211 and the sixth control terminal 221.

[0014] In some embodiments, the switching circuit further includes another P-type control transistor (hereinafter referred to as the second P-type control transistor 23). The second P-type control transistor 23 is coupled between the fourth control terminal 211 and the second output terminal 212 of the P-type transistor 21. The second P-type control transistor 23 also includes a control terminal (hereinafter referred to as the fifth control terminal 231). When the power supply of the switching circuit is turned off, the second input signal S2 with a logic level of zero, which is the same as that of the second control terminal 121, is received at the second input terminal 213 of the P-type transistor 21. Since the first control terminal 111 and the second output terminal 212 are coupled to each other, the first input signal S1, which is the leakage current signal as described above, is received at the second output terminal 212 of the P-type transistor 21. That is, the first input signal S1 received at the first input terminal 112 of the P-type transistor switch 11 is transmitted to the second output terminal 212 via the first P-type control transistor 12 and the first control terminal 111, so that the second output terminal 212 receives the first input signal S1.

[0015] The fifth control terminal 231 of the second P-type control transistor 23 receives the second input signal S2 with a logic level of zero, which is the same as that of the second control terminal 121, to turn on the second P-type control transistor 23 according to the second input signal S2. When the second P-type control transistor 23 is turned on, the first input signal S1 with a logic level of one, which is received at the second output terminal 212 of the P-type transistor 21, is transmitted to the fourth control terminal 211 of the P-type transistor 21 via the second P-type control transistor 23. That is, the fourth control terminal 211 receives the first input signal S1 with a logic level of one, so that the P-type transistor 21 is turned off according to the logic level of the first input signal S1. Thus, the first input signal S1 with a logic level of one, which is received at the second output terminal 212, is blocked from being transmitted to the second input terminal 213 via the P-type transistor 21.

[0016] In some embodiments, the switching circuit further includes a resistor 31. The resistor 31 functions to protect the switching circuit. The resistor 31 is coupled between the P-type transistor switch 11 and the first P-type control transistor 12. That is, one end of the resistor 31 is coupled to the first input terminal 112 of the P-type transistor switch 11, and the other end of the resistor 31 is coupled to the source of the first P-type control transistor 12.

[0017] In some embodiments, when the power supply of the switching circuit is turned off, in order to prevent the first control terminal 111 of the P-type transistor switch 11 from being turned on due to a logic level of zero, resulting in the first input signal S1 with a logic level of one being able to be transmitted according to Figure 1The path P2 shown, from the first input terminal 112 to the base 114 of the P-type transistor switch 11, so the base 114 of the P-type transistor switch 11 can be set to floating, making the logic level of the base 114 non-zero. In addition, by the same token, the base 122 of the first P-type control transistor 12 can be set to floating, the base 214 of the P-type transistor 21 can be set to floating, and the base 232 of the second P-type control transistor 23 can be set to floating, to prevent the first input signal S1 with a logic level of one from leaking to the bases 122, 214, 232 of the first P-type control transistor 12, the P-type transistor 21, and the second P-type control transistor 23 respectively due to the conduction of the first P-type control transistor 12, the P-type transistor 21, and the second P-type control transistor 23.

[0018] In some embodiments, the switching circuit is implemented by a chip, and the input terminal of the chip is coupled to the external circuit of the chip. Among them, the first input terminal 112, the second input terminal 213, the second control terminal 121, and the fifth control terminal 231 are the input terminals of the chip. The first input signal S1 received at the first input terminal 112 comes from the external circuit of the chip, and the second input signal S2 received at the second input terminal 213, the second control terminal 121, and the fifth control terminal 231 also comes from the external circuit of the chip. In addition, the second output terminal 212, the control terminals 111, 131, 211, 221 are located in the internal circuit of the chip, and the user cannot directly set the logic levels of the input signals S1, S2 received at the second output terminal 212, the control terminals 111, 131, 211, 221. Therefore, in order to completely turn off the P-type transistor switch 11 and the P-type transistor 21, to prevent the first input signal S1, which is a leakage current from the external circuit, from leaking from the first input terminal 112 of the P-type transistor switch 11 to the first output terminal 113 and the base 114, and to prevent the first input signal S1 from leaking from the second output terminal 212 of the P-type transistor 21 to the second input terminal 213 and the base 214, the switching circuit can transmit the first input signal S1 to the first control terminal 111 through the first P-type control transistor 12 by means of the second input signal S2 set to zero by the user in the external circuit of the chip and the first input signal S1 received at the first input terminal 112 to completely turn off the P-type transistor switch 11, and the first input signal S1 is transmitted to the fourth control terminal 211 through the first P-type control transistor 12, the first control terminal 111, the second output terminal 212, and the second P-type control transistor 23 to completely turn off the P-type transistor 21.

[0019] In summary, a P-type control transistor is coupled to the P-type transistor switch and the P-type transistor of the switching circuit, and the P-type control transistor is controlled to conduct, so as to transmit an input signal with a logic level of one to the P-type transistor switch and the P-type transistor, so as to turn off the P-type transistor switch and the P-type transistor, which can block the path from the input ends of the P-type transistor switch and the P-type transistor to the output end formed when the power supply of the switching circuit is turned off, and block the path from the input end to the bases of the P-type transistor switch and the P-type transistor, so as to eliminate the leakage phenomenon generated when the power supply of the switching circuit is turned off, so that when the P-type transistor switch and the input ends of the P-type transistor receive an input signal of a leakage current signal, it can be ensured that the P-type transistor switch is indeed turned off, and the input signal is completely blocked from being transmitted to the base and the output end of the P-type transistor switch.

[0020] Although the present disclosure has been disclosed as above with embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make many changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the appended claims.

[0021]

Symbol Description

[0022] 11: P-type transistor switch

[0023] 111: First control end

[0024] 112: First input end

[0025] 113: First output end

[0026] 114: Base

[0027] 12: First P-type control transistor

[0028] 121: Second control end

[0029] 122: Base

[0030] 13: N-type transistor switch

[0031] 131: Third control end

[0032] 2: Inverter

[0033] 21: P-type transistor

[0034] 211: Fourth control end

[0035] 212: Second output end

[0036] 213: Second input end

[0037] 214: Base

[0038] 22: N-type transistor

[0039] 221: Sixth control terminal

[0040] 23: Second P-type control transistor

[0041] 231: Fifth control terminal

[0042] 232: Base

[0043] 31: Resistor

[0044] P1: Path

[0045] P2: Path

[0046] S1: First input signal

[0047] S2: Second input signal

[0048] S3: Input inverted signal

Claims

1. A switching circuit, comprising: A P-type transistor switch, comprising: A first control terminal; A first output terminal; and A first input terminal, configured to: when the power supply of the switching circuit is turned off, receive a first input signal with a logic level of one, wherein the first input signal is a current signal in which the current outside the switching circuit leaks to the first input terminal when the power supply of the switching circuit is turned off; and A first P-type control transistor, coupled to the first input terminal and the first control terminal, comprising: A second control terminal, configured to: when the power supply of the switching circuit is turned off, receive a second input signal with a logic level of zero to turn on the first P-type control transistor, and when the first P-type control transistor is turned on, transmit the first input signal to the first control terminal of the P-type transistor switch to turn off the P-type transistor switch.

2. The switching circuit according to claim 1, further comprising: An N-type transistor switch, coupled to the first input terminal and the first output terminal, comprising: A third control terminal for receiving a first input inverted signal, wherein the first input inverted signal is the inverse of the first input signal.

3. The switching circuit according to claim 2, wherein the switching circuit is implemented by a chip, the first control terminal and the third control terminal are located inside the chip, the first input terminal and the second control terminal are the input terminals of the chip, and the first input signal and the second input signal come from an external circuit coupled to the chip.

4. The switching circuit according to claim 2, further comprising: An inverter, coupled to the third control terminal and the first control terminal, comprising: A P-type transistor, comprising: A second input terminal for receiving the second input signal; A fourth control terminal, coupled to the third control terminal; and A second output terminal, coupled to the first control terminal, enabling the first input signal to be transmitted from the first control terminal to the second output terminal; And An N-type transistor, coupled to the second output terminal; And A second P-type control transistor, coupled to the fourth control terminal and the second output terminal, comprising: A fifth control terminal for receiving the second input signal with a logic level of zero to turn on the second P-type control transistor, and when the second P-type control transistor is turned on, transmit the first input signal to the fourth control terminal of the P-type transistor to turn off the P-type transistor.

5. The switching circuit according to claim 4, wherein the switching circuit is implemented by a chip, the first control terminal and the third control terminal are located inside the chip, the first input terminal, the second input terminal, the second control terminal and the fifth control terminal are the input terminals of the chip, and the first input signal and the second input signal come from an external circuit coupled to the chip.

6. The switching circuit according to claim 2, further comprising a resistor, the resistor being coupled to the N-type transistor switch and the first input terminal.

7. In the switching circuit according to claim 1, the base of the P-type transistor switch is floating.

8. The switch circuit according to claim 1, wherein the base of the first P-type control transistor is floating.

9. The switch circuit according to claim 4, wherein the base of the P-type transistor is floating.

10. The switch circuit according to claim 4, wherein the base of the second P-type control transistor is floating.

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