A coupler and a signal transmission system

Abstract

The present application provides a coupler and a signal transmission system, relating to the technical field of isolated signal transmission. The coupler includes a first voltage domain, a second voltage domain, and an isolation device. The first voltage domain is connected to the second voltage domain through the isolation device. The first voltage domain includes a plurality of first signal ports, and the second voltage domain includes a plurality of second signal ports. The number of isolation devices is less than the number of the first signal ports or the second signal ports. Among them, the first voltage domain is configured to generate an encoded signal based on data of some or all of the plurality of first signal ports, and transmit the encoded signal to the second voltage domain. The second voltage domain is configured to receive the encoded signal and decode the encoded signal to output the decoded signal through the second signal ports. The coupler and the signal transmission system provided by the present application have the advantage of relatively low cost.

Description

Technical Field

[0001] The present application relates to the technical field of isolated signal transmission, and more particularly, to a coupler and a signal transmission system. Background Art

[0002] Digital isolators use chip-integrated transformers or capacitors as isolation devices to transmit data. Compared with traditional optocouplers, digital isolators have advantages such as low power consumption, long lifespan, and stable performance.

[0003] However, in systems that require isolation, there are usually multiple isolated signal channels for transmitting control signals from the low-voltage side to the high-voltage side or from the high-voltage side to the low-voltage side. On this basis, when using a digital isolator for isolation, each signal channel requires a set of isolation devices (such as capacitors or transformers). Due to the large number of channels, the transceiver circuit and the isolation devices occupy a relatively large area and the number of isolation devices is large, resulting in a high cost of the digital isolator.

[0004] In summary, the digital isolators provided in the prior art have a high cost and a large area. Summary of the Invention

[0005] The purpose of the present application is to provide a coupler and a signal transmission system to solve the problems of high cost and large area of digital isolators in the prior art.

[0006] To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] On the one hand, an embodiment of the present application provides a coupler. The coupler includes a first voltage domain, a second voltage domain, and an isolation device. The first voltage domain is connected to the second voltage domain through the isolation device. The first voltage domain includes a plurality of first signal ports, and the second voltage domain includes a plurality of second signal ports. The number of isolation devices is less than the number of the first signal ports or the second signal ports. Among them, the first voltage domain is used to generate an encoded signal based on the data of some or all of the plurality of first signal ports and transmit the encoded signal to the second voltage domain. The second voltage domain is used to receive the encoded signal and decode the encoded signal to output the decoded signal through some or all of the second signal ports.

[0008] Optionally, the first voltage domain is further used to generate a trigger signal before sending the encoded signal and send the trigger signal to the second voltage domain. The second voltage domain is used to reset the clock of the second voltage domain after receiving the trigger signal so that the clock of the second voltage domain is aligned with the clock of the first voltage domain.

[0009] Optionally, the second voltage domain includes a receiver and a decoding circuit. The receiver is respectively connected to the isolation device and the decoding circuit. The receiver further includes a first threshold comparator and a second threshold comparator. The first threshold comparator and the second threshold comparator are respectively connected to the isolation device and the decoding circuit. Among them, the threshold of the first threshold comparator is greater than the threshold of the second threshold comparator. Both the first threshold comparator and the second threshold comparator are used to receive the differential signal transmitted through the isolation device. The decoding circuit is used to determine that the differential signal is the trigger signal when the differential signal is greater than the second threshold and less than the first threshold.

[0010] Optionally, the second voltage domain includes a decoding circuit. The decoding circuit includes a NAND gate, a first NOT gate, and a second NOT gate. The first input terminal of the NAND gate is used to receive the trigger signal. The second input terminal of the NAND gate is connected to the output terminal of the second NOT gate. The output terminal of the NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate to form a ring oscillator through the NAND gate, the first NOT gate, and the second NOT gate, and use the ring oscillator for clock reset.

[0011] Optionally, the first voltage domain includes an encoding circuit and a transmitter. The second voltage domain includes a decoding circuit and a receiver. The input terminal of the encoding circuit is connected to some or all of the plurality of first signal ports. The output terminal of the encoding circuit is connected to the isolation device. The input terminal of the receiver is connected to the isolation device. The output terminal of the receiver is connected to the input terminal of the decoding circuit. The output terminal of the decoding circuit is connected to some or all of the plurality of second signal ports.

[0012] Optionally, the encoding circuit and the transmitter are integrated on the same chip, and the decoding circuit and the receiver are integrated on another chip.

[0013] Optionally, the second voltage domain is further used to generate an encoding signal based on the data of some or all of the plurality of second signal ports, and transmit the encoding signal to the first voltage domain. The first voltage domain is used to receive the encoding signal and decode the encoding signal to output the decoded signal through the first signal port.

[0014] Optionally, the first voltage domain includes a first codec circuit and a first transceiver, the second voltage domain includes a second codec circuit and a second transceiver, the first codec circuit is respectively connected to the first transceiver and some or all of the plurality of first signal ports, the second codec circuit is respectively connected to the second transceiver and some or all of the plurality of second signal ports, and the first transceiver is connected to the second transceiver through the isolation device.

[0015] Optionally, the first voltage domain includes a first codec circuit, a first receiver, and a first transmitter, the second voltage domain includes a second codec circuit, a second receiver, and a second transmitter, and the isolation device includes a first isolation device and a second isolation device; the first codec circuit is respectively connected to some or all of the plurality of first signal ports, the first receiver, and the first transmitter, the second codec circuit is respectively connected to some or all of the plurality of second signal ports, the second receiver, and the second transmitter, the first transmitter is connected to the second receiver through the first isolation device, and the second transmitter is connected to the first receiver through the second isolation device.

[0016] On the other hand, the present embodiment of the application further provides a signal transmission system, the signal transmission system includes a first power supply, a second power supply, and the above-mentioned coupler, the first power supply is connected to the first voltage domain and is used to supply power to the first voltage domain, and the second power supply is connected to the second voltage domain and is used to supply power to the second voltage domain.

[0017] Compared with the prior art, the present application has the following beneficial effects:

[0018] The embodiment of the present application provides a coupler and a signal transmission system. The coupler includes a first voltage domain, a second voltage domain, and an isolation device. The first voltage domain is connected to the second voltage domain through the isolation device. The first voltage domain includes a plurality of first signal ports, the second voltage domain includes a plurality of second signal ports, and the number of isolation devices is less than the number of first signal ports or second signal ports; wherein, the first voltage domain is used to generate an encoded signal based on the data of some or all of the plurality of first signal ports and transmit the encoded signal to the second voltage domain; the second voltage domain is used to receive the encoded signal and decode the encoded signal to output the decoded signal through the second signal port. Since the number of isolation devices in the coupler provided by the present application is less than the number of first signal ports or second signal ports, a plurality of signal ports can share the isolation device, thereby reducing the occupied area and number of isolation devices, and reducing the manufacturing cost of the coupler.

[0019] To make the above objects, features, and advantages of the present application more obvious and understandable, the following provides preferred embodiments in conjunction with the accompanying drawings and makes a detailed description as follows. Brief Description of the Drawings

[0020] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0021] Figure 1 A schematic diagram of a digital isolator with 4 isolated signal channels.

[0022] Figure 2 Another schematic diagram of a digital isolator with 4 isolated signal channels.

[0023] Figure 3 The first schematic diagram of the coupler provided by the embodiment of the present application.

[0024] Figure 4 The second schematic diagram of the coupler provided by the embodiment of the present application.

[0025] Figure 5 A schematic diagram of the timing relationship between the first voltage domain and the second voltage domain clocks.

[0026] Figure 6 A schematic diagram of the timing relationship between the first voltage domain and the second voltage domain clocks after setting the trigger signal provided by the embodiment of the present application.

[0027] Figure 7 A schematic diagram of a module of the receiver provided by the embodiment of the present application.

[0028] Figure 8 A timing diagram of the receiver provided by the embodiment of the present application.

[0029] Figure 9 Another timing diagram of the receiver provided by the embodiment of the present application.

[0030] Figure 10 A schematic diagram of a timing reset scheme provided by the embodiment of the present application.

[0031] Figure 11 A timing diagram of a timing reset scheme provided by the embodiment of the present application.

[0032] Figure 12 The third schematic diagram of the coupler provided by the embodiment of the present application.

[0033] Figure 13 The timing diagram provided by the embodiments of the present application Figure 12 .

[0034] Figure 14 The fourth schematic diagram of the coupler provided by the embodiments of the present application

[0035] In the figure: 100 - coupler; 110 - first voltage domain; 111 - encoding circuit; 112 - transmitter; 113 - first encoding and decoding circuit; 114 - first transceiver; 115 - first transmitter; 116 - first receiver; 120 - second voltage domain; 121 - decoding circuit; 122 - receiver; 123 - second encoding and decoding circuit; 124 - second transceiver; 135 - second receiver; 136 - second transmitter; 130 - isolation device; 131 - first isolation device; 132 - second isolation device Specific embodiments

[0036] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Usually, the components of the embodiments of the present application described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations

[0037] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application claimed, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application

[0038] It should be noted that: like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for differential description and cannot be understood as indicating or implying relative importance

[0039] It should be noted that in this text, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising said element.

[0040] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is customarily placed during use. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0041] In the description of the present application, it should also be noted that unless otherwise clearly specified and defined, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0042] The following will describe in detail some embodiments of the present application with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0043] As described in the background art, digital isolators use chip-integrated transformers or capacitors as isolation devices to transmit data. Compared with traditional optocouplers, digital isolators have advantages such as low power consumption, long lifespan, and stable performance.

[0044] However, in systems that require isolation, there are usually multiple isolated signal channels for transmitting control signals from the low-voltage side to the high-voltage side or from the high-voltage side to the low-voltage side. When using optocouplers, usually one optocoupler corresponds to each channel, and each optocoupler is encapsulated in a separate plastic package. When using digital isolators, usually a single plastic package is used, but the integrated circuit chips inside the plastic package usually contain multiple independent isolation channels. For example, usually 4 - 6 independent isolation channels can be placed in a plastic package of SOP16.

[0045] Due to the large number of channels, the transceiver circuits and isolation devices in the digital isolator occupy a relatively large area and the number of isolation devices is relatively large, resulting in the digital isolator being more costly than the optocoupler in terms of cost.

[0046] For example, please refer to Figure 1 and Figure 2 , the figure shows a schematic diagram of a digital isolator with 4 isolated signal channels. Among them, TX is Transmit (tx) Data, that is, the transmitted data, and RX is the abbreviation of Receive (rx) Data, that is, the received data. It can be seen from the figure that when the digital isolator contains 4 isolated signal channels, whether using a transformer or a capacitor as the isolation device, 4 isolation devices are required. On the one hand, the large number of isolation devices makes the cost of the digital isolator relatively high; on the other hand, the area occupied by the isolation devices is relatively large, which further increases the layout cost during circuit layout.

[0047] Similarly, when the number of isolated signal channels is 6, the number of isolation devices also needs to be 6. When the number of isolated signal channels is 8, the number of isolation devices also needs to be 8.

[0048] It can be seen that as the number of isolated signal channels increases, the number of isolation devices will also increase accordingly, resulting in an increase in the cost of the digital isolator.

[0049] In view of this, to solve the above problems, the present application provides a coupler, which reduces the number of isolation devices by sharing one isolation device among two or more isolated signal channels, thereby achieving the effect of reducing the cost of the coupler.

[0050] The following is an exemplary description of the coupler provided by the embodiments of the present application:

[0051] As an optional implementation, please refer to Figure 3, the coupler 100 includes a first voltage domain 110, a second voltage domain 120, and an isolation device 130. The first voltage domain 110 and the second voltage domain 120 are connected through the isolation device. The first voltage domain 110 includes a plurality of first signal ports, the second voltage domain 120 includes a plurality of second signal ports, and the number of isolation devices 130 is less than the number of first signal ports or second signal ports. Among them, the first voltage domain 110 is used to generate an encoded signal based on the data of some or all of the plurality of first signal ports, and transmit the encoded signal to the second voltage domain 120. The second voltage domain 120 is used to receive the encoded signal and decode the encoded signal to output the decoded signal through the second signal port.

[0052] Among them, as an implementation, the first voltage domain 110 is the end for sending signals, and the second voltage domain 120 is the end for receiving signals. And in the entire signal transmission system, there are also two supply voltages, which are the first supply voltage VDD1 and the second supply voltage VDD2 respectively. Among them, the first supply voltage VDD1 supplies power to the first voltage domain 110, so that the first voltage domain 110 realizes signal input and encoding. The second supply voltage VDD2 supplies power to the second voltage domain 120, so that the second voltage domain 120 realizes signal encoding and output. On this basis, the first signal port is the digital input port, and the second signal port is the digital output port. Generally, the number of first signal ports is equal to the number of second signal ports.

[0053] As an implementation, when the first voltage domain 110 encodes a signal, all the first signal ports will be sampled, and the sampled signals will be encoded into a serial signal. A serial signal is to integrate the signals of multiple ports into a string of signals and transmit the signal bit by bit through the isolation device 130. For example, when the number of first signal ports is 4, the signal to be transmitted by the first signal port is "1", the signal to be transmitted by the second signal port is "0", the signal to be transmitted by the third signal port is "1", and the signal to be transmitted by the fourth signal port is "0". After encoding, the signals of the four signal ports can be encoded into the serial signal "1010", and then transmitted to the second voltage domain 120.

[0054] It should be noted that the encoded serial signal can be transmitted to the second voltage domain 120 through a single isolation signal channel. At the same time, after receiving the serial signal, the second voltage domain 120 decodes the serial signal and outputs the decoded signal through the second signal port.

[0055] In this embodiment, the number of isolation devices 130 can be less than the number of the first signal ports or the second signal ports. In other words, the number of isolation signal channels can be less than the number of the first signal ports or the second signal ports, thereby achieving the effect of cost reduction. For example, when the number of the first signal ports and the second signal ports is 8, the number of isolation devices 130 can be only 5, or 3, or 1, etc. When the number of isolation devices 130 is one, the serial signal generated after the first voltage domain 110 samples and encodes the 8 first signal ports can be transmitted to the second voltage domain 120 through this isolation device 130. When the number of isolation devices 130 is greater than one, for example, when it is 3, the serial signal generated after the first voltage domain 110 samples and encodes the 8 first signal ports can be transmitted to the second voltage domain 120 through any one of the isolation devices 130. Alternatively, in one period, the serial signal can be transmitted to the second voltage domain 120 through the first isolation device 130, and in another period, the serial signal can be transmitted to the second voltage domain 120 through the second isolation device 130. No specific limitation is made thereto.

[0056] Among them, the isolation device 130 described in this embodiment can be an isolation device 130 such as a transformer or a capacitor.

[0057] As an implementation manner, please refer to Figure 4 , the first voltage domain 110 includes an encoding circuit 111 and a transmitter 112, and the second voltage domain 120 includes a decoding circuit 121 and a receiver 122. The input end of the encoding circuit 111 is connected to some or all of the ports among a plurality of first signal ports. The output end of the encoding circuit 111 is connected to the isolation device 130. The input end of the receiver 122 is connected to the isolation device 130. The output end of the receiver 122 is connected to the input end of the decoding circuit 121. The output end of the decoding circuit 121 is connected to some or all of the ports among a plurality of second signal ports. Optionally, the output end of the encoding circuit 111 is connected to the first end of the isolation device 130, and the input end of the receiver 122 is connected to the second end of the isolation device 130.

[0058] Through this setting manner, the encoding and decoding circuit 121 of the first voltage domain 110 can sample each first signal port, encode it into a serial signal, and then transmit the serial signal through the transmitter 112 circuit to the receiver 122 of the second voltage domain 120 through a single isolation channel, and then restore the serial signal to the second signal ports of the second voltage domain 120 through the decoding circuit 121.

[0059] Optionally, in an isolated signal transmission system, since there are a first voltage domain 110 and a second voltage domain 120 that need to achieve electrical isolation, in order to ensure electrical isolation between the two voltage domains, the encoding circuit 111 and the transmitter 112 are integrated on the same chip, and the decoding circuit 121 and the receiver 122 are integrated on another chip.

[0060] Understandably, the operating environments of the two chips are very different. On the one hand, since they are in different voltage domains, the supply voltages of the two chips cannot be exactly equal; on the other hand, the operating temperatures of the two chips may also be different, which may lead to different key performances of the two chips, such as different signal transmission delays and clock frequencies.

[0061] For example, please refer to Figure 5 , the clock signal of the chip in the first voltage domain 110 has a period of T1 at its supply voltage and temperature, and the clock signal of the chip in the second voltage domain 120 has a period of T2 at its supply voltage and temperature. Since the signal transmitted by the first voltage domain 110 is on the same chip, the clock has a definite timing relationship.

[0062] For example, on the transmitter 112 chip, the rising edge of the clock is designed to align with the center of the transmitted signal (as shown by the hollow arrow). There is a difference in the clock periods between the second voltage domain 120 and the first voltage domain 110. For example, T2 is 10% larger or 10% smaller than T1, etc., and the receiver 122 also receives the signal at the rising edge of the clock in the second voltage domain 120 (as shown by the solid arrow). In the first few bits, the solid arrow can still receive near the center of the transmitted signal, but as the transmitted data increases, the phase error begins to accumulate. When a certain number of bits are reached, the timing of the receiving moment will mismatch with the transmitted signal, resulting in signal transmission errors. Although the difference between T1 and T2 can be minimized as much as possible through circuit design optimization, since the two circuits are in electrically isolated voltage domains, the difference in the operating environments determines that the two clocks cannot achieve perfect matching, and the error will eventually accumulate to the level that causes errors.

[0063] In other words, due to the different environments of the first voltage domain 110 and the second voltage domain 120, the periods T1 and T2 of the two can never be exactly the same. Therefore, when one bit of data is transmitted, the phase error between the two is |T2 - T1|; when two bits of data are transmitted, the phase error between the two is 2|T2 - T1|, when three bits of data are transmitted, the phase error between the two is 3|T2 - T1|…, and so on, and the error gradually accumulates.

[0064] In addition to the problem of unequal clock cycles caused by environmental factors such as the supply voltages and temperatures of the first voltage domain 110 and the second voltage domain 120, the supply voltages of the first voltage domain 110 and the second voltage domain 120 may also change over time during operation, thereby bringing about clock changes, resulting in a large difference between the period T1 of the first voltage domain 110 and the period T2 of the second voltage domain 120.

[0065] For example, if the first voltage domain 110 has been operating at 5V with a clock cycle of 10ns, while the second voltage domain 120 has been operating at 3V with a clock cycle of 11ns, the period of the second voltage domain 120 is definitely longer (the clock is slower) than that of the first voltage domain 110 at this time. However, it is also possible that the supply voltage of the first voltage domain 110 fluctuates randomly between 3V and 5V, and the supply voltage of the second voltage domain 120 also fluctuates randomly between 3V and 5V, thereby resulting in no definite fast or slow relationship between the clock T1 of the first voltage domain 110 and the clock T2 of the second voltage domain 120, causing a large phase error and ultimately leading to errors.

[0066] In view of this, as an implementation, the first voltage domain 110 is also capable of generating a trigger signal before sending the encoded signal and sending the trigger signal to the second voltage domain 120. The second voltage domain 120 is configured to reset the clock of the second voltage domain 120 after receiving the trigger signal, so as to align the clock of the second voltage domain 120 with the clock of the first voltage domain 110.

[0067] In other words, the start of the clock of the second voltage domain 120 is controlled by the trigger signal of the first voltage domain 110. Since the error between the first voltage domain 110 and the second voltage domain 120 accumulates gradually, that is, the error will become larger and larger until the error is greater than a certain value, ultimately leading to errors. By setting the trigger signal and resetting the clock of the second voltage domain 120 after the second voltage domain 120 receives the trigger signal, the clocks of the second voltage domain 120 and the second voltage domain 120 are aligned once, thereby clearing the error between the clocks of the first voltage domain 110 and the second voltage domain 120, ensuring that the coupler 100 can continue to operate without errors.

[0068] For example, please refer to Figure 6 , taking the transmission of a 4-bit signal as an example. At a specified moment of the clock of the first voltage domain 110, the transmitter 112 of the first voltage domain 110 sends a trigger signal. After the second voltage domain 120 receives the trigger signal, it resets the clock of the second voltage domain 120. At this time, the clock of the second voltage domain 120 is aligned with the clock of the first voltage domain 110 once, and the error accumulated due to the difference in the two clock cycles before is cleared after the clock reset, thereby ensuring that the coupler 100 will not make errors during continuous operation.

[0069] After the trigger signal is sent in the first voltage domain 110, the transmission of normal data bits begins, such as the 4 bits shown in the figure. After the data transmission is completed, the clock phase of the second voltage domain 120 is no longer important and enters the invalid period. Since the number of bits transmitted is known, the time point to enter the invalid period is determined. For example, when transmitting 4 bits, it is 4×T2 after the trigger signal, and then enters the invalid period. Here, it should be noted that the number of bits transmitted is associated with the number of the first signal ports. That is, when the number of the first signal ports is 4, the number of bits transmitted after the trigger signal is 4; when the number of the first signal ports is 8, the number of bits transmitted after the trigger signal is 8.

[0070] And, optionally, during the invalid period, there are two ways to handle the clock of the second voltage domain 120. One is to turn it off to reduce power consumption; the other is to make it continue to work, but only reset when the next trigger signal arrives, and there is no limitation here.

[0071] It can be understood that in the above implementation, at a certain moment corresponding to the clock of the first voltage domain 110, the trigger signal of the transmitter 112 is sent and transmitted to the receiver 122 through the isolation device 130. When the receiver 122 receives the trigger signal, the clock is reset (restarted from the off state or reset at the edge moment). After sending the trigger signal, the transmitter 112 starts to transmit data bits. Since the isolation signal transmission system needs to transmit a small number of bits, such as 2 - 10 bits, a certain error between T2 and T1 is allowed. As long as the magnitude of the error N*(T2 - T1) does not exceed a certain proportion of a single bit, such as 0.3×T1, the correct transmission timing can be ensured, where N represents the number of bits. Optionally, the clock error can be controlled within 5% through appropriate circuit design.

[0072] That is, in this embodiment, based on the clock of the first voltage domain 110, the moment when the first voltage domain 110 sends the trigger signal and the subsequent moments when data bits are transmitted are both determined. As long as the clock error between the second voltage domain 120 and the first voltage domain 110 is controlled within a range that can be achieved by design, the accuracy of data transmission can be ensured. Therefore, by sending a trigger signal from the first voltage domain 110 to the second voltage domain 120 and resetting the clock of the second voltage domain 120 after receiving the trigger signal, the transmission timing between the first voltage domain 110 and the second voltage domain 120 can always be correct, thereby ensuring the stable operation of the coupler 100. At the same time, since digital circuits can operate at very high frequencies and the width of each bit is at the ns level, the delay caused by this encoding is smaller than the delay of the traditional optocoupler itself, and the transmission characteristics of the system will not deteriorate when replacing the traditional optocoupler.

[0073] Meanwhile, it should be noted that there are many forms and types of trigger signals, and the embodiments of the present application do not limit the specific forms and types of trigger signals. As long as the trigger signal has a preset feature and can be recognized by the receiver 122 in the second voltage domain 120, it is acceptable.

[0074] For example, a specific identification code can be used as the calibration of the start bit, so as to achieve the purpose of transmitting the trigger signal. As commonly used in the prior art, a digital signal is used for calibration, and a fixed bit string "0110" is transmitted as the calibration of the start bit. However, this method will greatly waste bandwidth. For example, if only 4 bits need to be transmitted and the start calibration bit also requires 4 bits, then half of the available system bandwidth will be wasted.

[0075] Therefore, as an alternative implementation, the present invention uses the combination of analog signals and digital signals as the calibration of the start bit. Please refer to Figure 7 , the receiver 122 further includes a first threshold comparator and a second threshold comparator. The first threshold comparator and the second threshold comparator are respectively connected to the isolation device 130 and the decoding circuit 121. Among them, the threshold of the first threshold comparator is greater than the threshold of the second threshold comparator; both the first threshold comparator and the second threshold comparator are used to receive the differential signal transmitted through the isolation device 130, and the decoding circuit 121 is used to determine that the differential signal is a trigger signal when the differential signal is greater than the second threshold and less than the first threshold. Moreover, the first threshold is for the normally transmitted digital signal, and the second threshold is for the trigger signal, that is, it is judged through the threshold of an analog signal.

[0076] As Figure 7 shown, the differential signal transmitted from the isolation device 130 enters the receiver 122. The receiver 122 includes a first threshold comparator and a second threshold comparator, which respectively have a first threshold and a second threshold. Among them, the threshold described in the present application may include the threshold of the pulse width and the threshold of the pulse amplitude, which can be determined according to different isolation devices 130.

[0077] As Figure 8 shown, if the pulse width is used as a marker, since the second threshold has a smaller threshold, shorter pulses can be recognized. As shown in the figure, the width of the fourth pulse signal is shorter than that of the normal digital signal and cannot be recognized by the first threshold comparator, so the output is 0 after being processed by it; however, the threshold of the second threshold comparator is smaller and can recognize shorter pulses, so it is recognized as 1. From this difference in the output, the subsequent logic circuit can determine the occurrence of the trigger signal.

[0078] As Figure 9As shown, if the pulse amplitude is used as a marker, for example, the signal amplitude of the fourth bit is relatively small, and the first threshold comparator with a relatively large threshold cannot recognize this signal, but the second threshold comparator with a lower threshold can recognize this signal. Based on the difference in the outputs, the subsequent logic circuit can also determine the occurrence of the trigger signal.

[0079] It should be noted that due to the influence of noise, temperature, voltage, and process in the system, in order to ensure reliability, the second threshold can be 50% less than the first threshold, thereby ensuring the effective recognition of the trigger signal.

[0080] On this basis, the clock reset scheme can also be diverse. As an implementation method, please refer to Figure 10 , the decoding circuit 121 includes a NAND gate, a first NOT gate, and a second NOT gate. The first input terminal of the NAND gate is used to receive the trigger signal. The second input terminal of the NAND gate is connected to the output terminal of the second NOT gate. The output terminal of the NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate to form a ring oscillator through the NAND gate, the first NOT gate, and the second NOT gate, and use the ring oscillator for clock reset.

[0081] When the decoding circuit 121 receives the enable signal, 1 is input to the first input terminal of the NAND gate; when the decoding circuit 121 does not receive the enable signal, 0 is input to the first input terminal of the NAND gate. When 1 is input to the first input terminal of the NAND gate, the NAND gate is equivalent to an inverter, and the circuit is a ring oscillator. When 0 is input to the first input terminal, regardless of the logic state of C, A must output 1, and correspondingly B is set to 0 and C is set to 1. The entire oscillator stops working. When EN changes from 0 back to 1, C = 1 sets A to 0 after a delay, and then according to the principle of the ring oscillator, the clock resumes oscillation. Therefore, after a definite delay after the trigger signal changes from 0 to 1, the clock signal resumes from 0, that is, every time the trigger signal changes from 0 to 1, the phase of the clock is reset. The timing diagram of this clock reset method is as Figure 11 shown.

[0082] Based on the above implementation, the second voltage domain 120 can also generate an encoded signal according to the signals of some or all of the multiple second signal ports, and transmit the encoded signal to the first voltage domain 110; the first voltage domain 110 receives the encoded signal and decodes the encoded signal to output the decoded signal through the first signal port. In other words, not only can signals be transmitted from the first voltage domain 110 to the second voltage domain 120, but also signals can be transmitted from the second voltage domain 120 to the first voltage domain 110. For example, in the previous time period, the first voltage domain 110 transmits signals to the second voltage domain 120, and in the current time period, the second voltage domain 120 transmits signals to the first voltage domain 110; in the next time period, signals are transmitted from the first voltage domain 110 to the second voltage domain 120 again.

[0083] In this embodiment, two implementation methods are provided to achieve bidirectional signal transmission:

[0084] The first one is as follows. Refer to Figure 12 . The first voltage domain 110 includes a first encoding / decoding circuit 113 and a first transceiver 114, and the second voltage domain 120 includes a second encoding / decoding circuit 123 and a second transceiver 124. The first encoding / decoding circuit 113 is respectively connected to the first transceiver 114 and some or all of the multiple first signal ports, and the second encoding circuit 111 is respectively connected to the second transceiver 124 and some or all of the multiple second signal ports. The first transceiver 114 and the second transceiver 124 are connected through an isolation device 130. That is, between the first voltage domain 110 and the second voltage domain 120, bidirectional signal transmission is achieved through a single isolation device 130.

[0085] As Figure 13 shown, for example, taking the first transceiver 114 being in the transmitting state first as an example, when the first transceiver 114 is in the transmitting state, its working principle is the same as the above implementation and will not be elaborated here. After the data transmission of the first voltage domain 110 is completed, the transceiver of the first voltage domain 110 switches from the transmitting state to the receiving state (it can switch immediately or after a specified time, for example, in the figure, wait for one cycle after transmitting the last bit and then switch). The delay from transmitting the last bit to switching to the receiving state is TD1. In the figure, TD1 = T1. Other times can also be selected, such as TD1 = 0.5×T1, or TD1 = 2×T1, etc., and no specific limitation is made on this.

[0086] When the first transceiver 114 is in the transmitting state, the second transceiver 124 is in the receiving state. After receiving a known number of bits, it changes from the receiving state to the transmitting state. The delay from receiving the last bit to changing to the transmitting state is TD2. In the example shown in the figure, TD2 = 1.5×T2. In other words, it is necessary to ensure that when the second transceiver 124 enters the transmitting state, the first transceiver 114 is already in the receiving state, that is, TD2 is greater than TD1.

[0087] After the second voltage domain 120 enters the transmitting state, it sends a trigger signal to the first voltage domain 110, and the first voltage domain 110 receives the trigger signal and resets the clock signal of the first voltage domain 110. The subsequent process is the same as the above implementation method, except that the whole process is reversed in direction, and the signal is transmitted from the second voltage domain 120 to the first voltage domain 110. The processing after the data bits are transmitted is also similar. The second voltage domain 120 first enters the receiving state, and then the first voltage domain 110 enters the transmitting state, and the direction is reversed again. The first voltage domain 110 transmits signals to the second voltage domain 120, which will not be elaborated here.

[0088] Therefore, in this implementation method, from the perspective of the isolation device 130, there are different signal transmission directions in different time periods. Whether it is the first voltage domain 110 or the second voltage domain 120, their clocks are not continuous, but are reset by each other's clocks alternately. The two clocks cancel the accumulation of each other's clock phase errors, so that the coupler 100 can work continuously and stably.

[0089] Second, please refer to Figure 14 Figure [reference number not provided in the original text], the first voltage domain 110 includes a first encoding and decoding circuit 113, a first receiver 116, and a first transmitter 115. The second voltage domain 120 includes a second encoding and decoding circuit 123, a second receiver 135, and a second transmitter 136. The isolation device 130 includes a first isolation device 131 and a second isolation device 132. The first encoding and decoding circuit 113 is respectively connected to a plurality of first signal ports, the first receiver 116, and the first transmitter 115. The second encoding and decoding circuit 123 is respectively connected to some or all of the plurality of second signal ports, the second receiver 135, and the second transmitter 136. The first transmitter 115 is connected to the second receiver 135 through the first isolation device 131. The second transmitter 136 is connected to the first receiver 116 through the second isolation device 132.

[0090] That is, in this implementation manner, the number of isolation devices 130 is two, and the signal isolation channels also include two. One of the signal isolation channels is only responsible for transmitting signals from the first voltage domain 110 to the second voltage domain 120, while the other channel is only responsible for transmitting signals from the second voltage domain 120 to the first voltage domain 110. At this time, both the first voltage domain 110 and the second voltage domain 120 have two clocks. The clocks corresponding to the first transmitter 115 and the second transmitter 136 are not reset, but can reset the clocks of the opposite side; while the clocks corresponding to the first receiver 116 and the second receiver 135 can be reset by the trigger signals of the opposite side.

[0091] Based on the above implementation manner, the embodiment of the present application further provides a signal transmission system. The signal transmission system includes a first power supply, a second power supply, and the above-mentioned coupler 100. The first power supply is connected to the first voltage domain 110 and is used to supply power to the first voltage domain 110. The second power supply is connected to the second voltage domain 120 and is used to supply power to the second voltage domain 120.

[0092] In summary, the embodiment of the present application provides a coupler and a signal transmission system. The coupler includes a first voltage domain, a second voltage domain, and an isolation device. The first voltage domain is connected to the second voltage domain through the isolation device. The first voltage domain includes a plurality of first signal ports, and the second voltage domain includes a plurality of second signal ports. The number of isolation devices is less than the number of the first signal ports or the second signal ports. Among them, the first voltage domain is used to generate an encoded signal according to the data of some or all of the plurality of first signal ports, and transmit the encoded signal to the second voltage domain. The second voltage domain is used to receive the encoded signal, decode the encoded signal, and output the decoded signal through the second signal port. Since the number of isolation devices in the coupler provided by the present application is less than the number of the first signal ports or the second signal ports, multiple signal ports can share the isolation device, thereby reducing the occupied area and the number of isolation devices, and reducing the manufacturing cost of the coupler.

[0093] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0094] It is obvious to those skilled in the art that the present application is not limited to the details of the above-mentioned exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or basic characteristics of the present application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present application is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A coupler, characterized in that, The coupler includes a first voltage domain, a second voltage domain, and an isolation device. The first voltage domain is connected to the second voltage domain through the isolation device. The first voltage domain includes a plurality of first signal ports, and the second voltage domain includes a plurality of second signal ports. The number of isolation devices is less than the number of first signal ports or the number of second signal ports. Among them, the first voltage domain is configured to generate an encoded signal based on data of some or all of the plurality of first signal ports, and transmit the encoded signal to the second voltage domain; the second voltage domain is configured to receive the encoded signal, decode the encoded signal, and output the decoded signal through some or all of the second signal ports; the first voltage domain is further configured to generate a trigger signal before transmitting the encoded signal, and transmit the trigger signal to the second voltage domain. The second voltage domain is configured to reset the clock of the second voltage domain after receiving the trigger signal, so that the clock of the second voltage domain is aligned with the clock of the first voltage domain; the second voltage domain includes a receiver and a decoding circuit. The receiver is respectively connected to the isolation device and the decoding circuit. The receiver further includes a first threshold comparator and a second threshold comparator. The first threshold comparator and the second threshold comparator are both respectively connected to the isolation device and the decoding circuit. Among them, the threshold of the first threshold comparator is greater than the threshold of the second threshold comparator, and the thresholds of the first threshold comparator and the second threshold comparator are both pulse width thresholds; both the first threshold comparator and the second threshold comparator are configured to receive differential signals transmitted through the isolation device. The decoding circuit is configured to determine that the differential signal is the trigger signal when the differential signal is greater than the second threshold and less than the first threshold.

2. The coupler according to claim 1, characterized in that, the second voltage domain includes a decoding circuit. The decoding circuit includes a NAND gate, a first NOT gate, and a second NOT gate. The first input terminal of the NAND gate is configured to receive a trigger signal. The second input terminal of the NAND gate is connected to the output terminal of the second NOT gate. The output terminal of the NAND gate is connected to the input terminal of the first NOT gate. The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate, so as to form a ring oscillator through the NAND gate, the first NOT gate, and the second NOT gate, and use the ring oscillator for clock reset.

3. The coupler according to claim 1, wherein the first voltage domain includes an encoding circuit and a transmitter. The second voltage domain includes a decoding circuit and a receiver. The input terminal of the encoding circuit is connected to some or all of the plurality of first signal ports. The output terminal of the encoding circuit is connected to the isolation device; the input terminal of the receiver is connected to the isolation device. The output terminal of the receiver is connected to the input terminal of the decoding circuit. The output terminal of the decoding circuit is connected to some or all of the plurality of second signal ports.

4. The coupler according to claim 3, wherein The encoding circuit and the transmitter are integrated on the same chip, and the decoding circuit and the receiver are integrated on another chip.

5. The coupler according to claim 1, wherein The second voltage domain is further configured to generate an encoded signal based on data of some or all of the plurality of second signal ports, and transmit the encoded signal to the first voltage domain; The first voltage domain is configured to receive the encoded signal, decode the encoded signal, and output the decoded signal through some or all of the first signal ports.

6. The coupler according to claim 5, characterized in that, The first voltage domain includes a first codec circuit and a first transceiver, the second voltage domain includes a second codec circuit and a second transceiver, the first codec circuit is respectively connected to the first transceiver and some or all of the plurality of first signal ports, the second codec circuit is respectively connected to the second transceiver and some or all of the plurality of second signal ports, and the first transceiver is connected to the second transceiver through the isolation device.

7. The coupler according to claim 5, characterized in that, The first voltage domain includes a first codec circuit, a first receiver, and a first transmitter, the second voltage domain includes a second codec circuit, a second receiver, and a second transmitter, and the isolation device includes a first isolation device and a second isolation device; The first codec circuit is respectively connected to some or all of the plurality of first signal ports, the first receiver, and the first transmitter, the second codec circuit is respectively connected to some or all of the plurality of second signal ports, the second receiver, and the second transmitter, the first transmitter is connected to the second receiver through the first isolation device, and the second transmitter is connected to the first receiver through the second isolation device.

8. A signal transmission system, characterized in that, The signal transmission system includes a first power supply, a second power supply, and a coupler according to any one of claims 1 to 7, the first power supply is connected to the first voltage domain and is configured to supply power to the first voltage domain, and the second power supply is connected to the second voltage domain and is configured to supply power to the second voltage domain.

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