Power amplifier chips and communication equipment

Abstract

An embodiment of the present application provides a power amplifier chip and a communication device, wherein the power amplifier chip includes: a packaging shell; a plurality of power amplifier bare chips, wherein the plurality of power amplifier bare chips are sealed in the packaging shell; wherein each of the plurality of power amplifier bare chips includes at least one stage of power amplifier, thereby reducing the layout area of ​​the terminal device occupied by the power amplifier, and further reducing the layout area of ​​the terminal device occupied by the communication device, which is conducive to the realization of highly integrated terminal devices.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and in particular to a power amplifier chip and a communication device. Background Art

[0002] With the advancement of science and technology, communication technology has advanced by leaps and bounds. Wireless communication technology has evolved over a long period of time. To improve information transmission rates, current wireless communication technologies typically support dual connectivity for simultaneous access to 4G and 5G networks. Base stations in 4G or 5G networks can use either the 4G or 5G frequency bands, respectively, to transmit data to terminal devices.

[0003] In related communication technologies, it is usually necessary to set up two independent radio frequency units in the terminal device to support data transmission of 4G network and 5G network respectively. Each radio frequency unit includes a power amplifier module and a power supply module. These two independent radio frequency units usually occupy a relatively high layout area of ​​the terminal device, which is not conducive to the development of terminal devices towards small size and high integration. In other possible dual-connection communication scenarios, such as multi-card multi-standby or multi-mode simultaneous transmission, multiple independent radio frequency units will also cause similar problems. Therefore, how to reduce the layout area occupied by the radio frequency unit in terminal devices that support dual-connection data transmission has become a problem that needs to be solved. Summary of the Invention

[0004] The power amplifier chip and communication device provided by this application are conducive to reducing the layout area of ​​electronic equipment occupied by the communication device. To achieve the above purpose, this application adopts the following technical solutions.

[0005] In a first aspect, an embodiment of the present application provides a power amplifier chip, comprising: a packaging shell; a plurality of power amplifier bare chips, wherein the plurality of power amplifier bare chips are sealed in the packaging shell; wherein each of the plurality of power amplifier bare chips includes at least one stage of power amplifier.

[0006] The embodiment of the present application can reduce the area of ​​the terminal device's layout occupied by the power amplifier by packaging multiple power amplifier bare chips in the same package shell, which is conducive to the realization of highly integrated terminal devices.

[0007] Based on the first aspect, in a possible implementation, the multiple power amplifier bare chips respectively support different radio frequency bands.

[0008] The different radio frequency bands may include, but are not limited to, N41 band (2496 MHz–2690 MHz), B39 band (1880 MHz–1920 MHz), or B1 band (1920 MHz–1980 MHz).

[0009] Based on the first aspect, in a possible implementation, the power amplifier chip also includes: a first switch, located in the packaging shell, for connecting the first capacitor between the common ground and the power supply end of the first power amplifier bare chip among the multiple power amplifier bare chips or disconnecting the connection.

[0010] Based on the first aspect, in a possible implementation, the power amplifier chip also includes a second capacitor and a second switch, which are located in the packaging shell; the second switch is used to connect the second capacitor between the common ground and the power supply end of the second power amplifier bare chip among the multiple power amplifier bare chips or disconnect the connection.

[0011] Optionally, the second power amplifier bare chip may be the first power amplifier bare chip. In addition, the second power amplifier bare chip may also be a power amplifier bare chip different from the first power amplifier bare chip.

[0012] By encapsulating the first switch, the second capacitor and the second switch inside the power amplifier chip, the layout area of ​​the terminal device occupied by the communication device can be further reduced in the scenario of a power amplifier with multiple power supply modes.

[0013] Based on the first aspect, in a possible implementation, the power amplifier chip also includes: a controller, located in the packaging shell, the controller being used to receive indication information for indicating the power amplifier configuration from the wireless radio frequency integrated circuit, and based on the indication information, controlling the enabling of at least one power amplifier stage in at least one power amplifier bare chip among the multiple power amplifier bare chips, and adjusting the gain of the enabled at least one power amplifier stage; wherein the indication information includes at least one of the following: the enabled at least one power amplifier stage, the gain of the power amplifier, the power supply mode of the power amplifier, the time for controlling the start-up of the power amplifier, the time for adjusting the gain of the power amplifier, or the output port of the power amplifier chip used.

[0014] Based on the first aspect, in a possible implementation, the power amplifier chip also includes: multiple switch groups, located in the packaging shell, the first switch group among the multiple switch groups includes a first input end and multiple output ends; the output end of the third power amplifier bare chip among the multiple power amplifier bare chips is connected to the first input end of at least one first switch group among the multiple first switch groups, and the multiple output ends of each first switch group in the at least one first switch group are correspondingly connected to at least some of the multiple output ports of the power amplifier chip.

[0015] Optionally, the third power amplifier bare chip may be the first power amplifier bare chip or the second power amplifier bare chip.

[0016] Based on the first aspect, in one possible implementation, the second switch group in the at least one first switch group includes a second input end; the second input end is connected to the RF signal receiving end of the power amplifier chip; and the switch in the second switch group connects the RF signal receiving end to one of the multiple output ends in the second switch group based on a control signal.

[0017] Based on the first aspect, in a possible implementation, the first power amplifier integrated in the second power amplifier bare chip among the multiple power amplifier bare chips includes a first gain and a second gain; wherein, the first time period between the moment when the first power amplifier is started and the moment when the first power amplifier starts to transmit signals is greater than the second time period between the moment when the first power amplifier starts to adjust from the first gain to the second gain and the moment when the first power amplifier starts to transmit signals using the second gain.

[0018] In a second aspect, an embodiment of the present application provides a communication device, which may include a power supply device and a power amplifier chip as described in the first aspect; wherein, the first power supply device in the power supply device is used to supply power to the first power amplifier bare chip in the power amplifier chip; and the second power supply device in the power supply device is used to supply power to the remaining power amplifier bare chips in the power amplifier chip.

[0019] Based on the second aspect, in a possible implementation, the communication device further includes: a wireless radio frequency integrated circuit, configured to transmit a radio frequency signal to a power amplifier integrated in at least one power amplifier bare chip among the multiple power amplifier bare chips.

[0020] Based on the second aspect, in a possible implementation, the power supply device is also used to: receive an indication signal from the wireless radio frequency integrated circuit, and based on the indication signal, adopt the power supply mode indicated by the indication signal to power the power amplifier; the power supply mode includes an average power tracking mode or an envelope tracking mode.

[0021] Based on the second aspect, in a possible implementation, the communication device further includes a first capacitor; the first capacitor is connected between a common ground and a power supply terminal of the first power amplifier bare chip or disconnects the connection based on control of a first switch.

[0022] Based on the second aspect, in a possible implementation manner, the wireless radio frequency integrated circuit is further used to: transmit instruction information to a controller in the power amplifier chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of the present application;

[0025] Figure 2 This is a schematic structural diagram of a power amplifier chip provided in an embodiment of the present application;

[0026] Figure 3 This is a schematic diagram of the structure of a communication device provided in an embodiment of the present application;

[0027] Figure 4 This is a schematic diagram of the internal structure of the power supply device provided in an embodiment of the present application;

[0028] Figure 5 This is another structural diagram of the power amplifier chip provided in an embodiment of the present application;

[0029] Figure 6 This is another structural diagram of a communication device provided in an embodiment of the present application;

[0030] Figure 7 This is another structural diagram of the power supply device provided in an embodiment of the present application;

[0031] Figure 8 This is another structural diagram of a communication device provided in an embodiment of the present application;

[0032] Figure 9 This is another structural diagram of a communication device provided in an embodiment of the present application;

[0033] Figure 10 This is another structural diagram of a communication device provided in an embodiment of the present application;

[0034] Figure 11 This is a schematic diagram of the frame format sent by the network device provided in an embodiment of the present application;

[0035] Figure 12 It is a timing diagram of the time for adjusting the gain of a power amplifier in the prior art;

[0036] Figure 13 This is a timing diagram of the time for adjusting the gain of the power amplifier provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0038] The terms "first", "second" and the like in this application are only used to distinguish the purpose of description and should not be understood as indicating or implying relative importance, nor as indicating or implying order. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, including a series of steps or units. Methods, systems, products or devices are not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or devices. In the description of the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner.

[0039] The terminal device in the embodiments of the present application may also be referred to as user equipment (UE), mobile station (MS), mobile terminal (MT), access terminal, subscriber unit, subscriber station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent or user apparatus, etc. The terminal device may be a device that provides voice / data connectivity to a user, for example, a handheld device or vehicle-mounted device with wireless connection function. At present, some examples of terminals include: mobile phones, tablet computers, laptop computers, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to wireless modems, vehicle-mounted devices, wearable devices, terminal devices in future 5G networks or future evolved public land mobile communication networks (PLMNs). The terminal equipment in the network (PLMN), etc., is not limited to this in the embodiments of the present application.

[0040] The network device in the embodiment of the present application can be a device for communicating with a terminal device. The network device can also be referred to as an access network device or a wireless access network device. It can be an evolved NodeB (eNB or eNodeB) in an LTE system, or a wireless controller in a cloud radio access network (CRAN) scenario. Alternatively, the access device can be a relay station, an access point, an on-board device, a wearable device, an access device in a future 5G network, or an access device in a future evolved PLMN network. It can be an access point (AP) in a WLAN, or a gNB in ​​a new radio (NR) system. The embodiment of the present application is not limited thereto. In addition, in the embodiment of the present application, the network device can also be a device in a RAN (Radio Access Network), or in other words, a RAN node that connects a terminal device to a wireless network. For example, as an example and not a limitation, network devices include: gNB, transmission reception point (TRP), evolved Node B (eNB), radio network controller (RNC), Node B (NB), base station controller (BSC), base transceiver station (BTS), home base station (e.g., home evolved NodeB, or home Node B, HNB), base band unit (BBU), or wireless fidelity (Wifi) access point (AP), etc.

[0041] Please refer to Figure 1 , which shows a scenario diagram applied to an embodiment of the present application. Figure 1The scenario shown includes a terminal device, a network device A1, and a network device A2. Among them, the terminal device can access the network device A1 and the network device A2 at the same time, and this access mode is called dual-connectivity (DC). In an exemplary scenario, among the two network devices, the one responsible for interacting with the terminal device for radio resource control messages and interacting with the core network control plane entity can be called the primary network device, and the other network device is the secondary network device. Similarly, the terminal device can also have communication connections with multiple network devices at the same time and can send and receive data, which can be called multi-connectivity (MC). Among the multiple network devices, there can be a network device responsible for interacting with the terminal device for radio resource control messages and interacting with the core network control plane entity. Then, the network device can be called the primary network device, and the remaining network devices can be called secondary network devices. The following embodiments of this application are described in detail using dual connection as an example.

[0042] In such Figure 1 In the illustrated scenario, network device A1 and network device A2 can be network devices of the same radio access type. For example, network device A1 and network device A2 can be network devices of an LTE system, or they can be network devices of an NR system. Network device A1 and network device A2 can also be network devices of different radio access types. In a specific implementation, network device A1 can be a network device of an LTE system, and network device A2 can be a network device of an NR system. Both network device A1 and network device A2 can serve as master network devices. Furthermore, network device A1 and network device A2 can serve terminal devices using different radio frequency bands.

[0043] The terminal device may be provided with a communication device, which can send data to network device A1 and network device A2 via the communication device, or receive data from network device A1 and network device A2 via the communication device. The communication device typically includes a power amplifier (PA), a power supply device that provides power to the power amplifier, and an RFIC (Radio Frequency Integrated Circuit) for providing radio frequency signals to the PA, and may optionally include a modem and an antenna.

[0044] When a terminal device uses dual or multiple connections to transmit data with network devices, two or more power amplifiers are required to facilitate multi-channel data transmission. For example, when using dual connections, two power amplifiers are required to transmit data between the terminal device and network devices A1 and A2, respectively; when using triple connections, three power amplifiers are required to transmit data between the terminal device and the corresponding network devices. Furthermore, to improve the performance of the power amplifiers corresponding to each connection channel in the communication device, multiple independent power modules are typically required to independently power each power amplifier. This often results in the communication equipment occupying an excessive amount of board space within the terminal device, hindering the realization of highly integrated terminal devices.

[0045] based on Figure 1 The application scenario shown below is Figure 2-Figure 8 The illustrated embodiment describes in detail the structure of the communication device in the terminal device to solve the technical problem of reducing the layout area.

[0046] The communication device may include one or more power amplifier chips. Each power amplifier chip may be integrated with at least two power amplifiers. In other words, a power amplifier chip may be integrated with two power amplifiers, three power amplifiers, or four power amplifiers, etc., which is not limited in the present embodiment. For example, a power amplifier chip includes two power amplifiers. Figure 2 , describes the internal structure of the power amplifier chip in detail.

[0047] exist Figure 2 In the figure, power amplifier chip 11 may include a PA1 bare chip and a PA2 bare chip. A bare chip, also referred to as a die, is an integrated circuit formed on a semiconductor through processes such as growth, doping, etching, or development, and has a power amplification function. In practice, the PA1 bare chip and the PA2 bare chip can be placed together within a packaging material through processes such as gluing or sintering. The packaging material is used to form a package shell. Then, through processes such as jumper wires or embedded wires, the lead ends of the PA1 bare chip and the PA2 bare chip are connected to the pins of the package shell for connecting to external devices, thereby enabling signal exchange between the PA1 bare chip and the PA2 bare chip and external devices or equipment.

[0048] In the power amplifier chip 11, the package is used to encapsulate the internal components, for example, using standard packaging processes. The encapsulated internal components include, but are not limited to, the multiple bare chips described above, as well as other necessary components, such as switches, switch groups, capacitors, or controllers described in subsequent embodiments. For details, please refer to the description of the subsequent embodiments.

[0049] The power amplifiers PA1 and PA2 integrated in the PA1 and PA2 bare chips can be used to amplify signals in different frequency bands. Specifically, PA1 can support power amplification in the N41 band (2496MHz–2690MHz), while PA2 can support power amplification in the B39 band (1880MHz–1920MHz), the B3 band (1710MHz–1785MHz), or the B1 band (1920MHz–1980MHz).

[0050] from Figure 2 As can be seen in FIG, the power amplifier chip 11 includes multiple pins, which are: the signal input terminal N1 of PA1, the signal input terminal N2 of PA2, the power terminal V1 of PA1, the power terminal V2 of PA2, the common ground terminal G of PA1 and PA2, the output port Po1 of PA1 and the output port Po2 of PA2. These multiple pins are respectively connected to external devices or components such as power supply equipment, RFIC, or antenna equipment to achieve the following functions: Figure 1 The power amplification of multiple uplink communication signals is shown.

[0051] The embodiment of the present application can reduce the area of ​​the terminal device's layout occupied by the power amplifier by packaging multiple power amplifier bare chips in the same power amplifier chip, which is conducive to the realization of highly integrated terminal devices.

[0052] based on Figure 2 The power amplifier chip 11 shown in the embodiment of the present application provides a Figure 3 The communication device 100 shown includes an RFIC, a power supply device 12 and a power amplifier chip 11.

[0053] In which, the power supply device 12 may include two output terminals and a common ground terminal, one of the output terminals is connected to the power terminal V1 of the power amplifier chip to supply power to PA1 in the power amplifier chip 11; the other output terminal is connected to the power terminal V2 of the power amplifier chip 11 to supply power to the power amplifier PA2 in the power amplifier chip, and the common ground terminal is connected to the common ground terminal G of the power amplifier chip 11.

[0054] In a possible implementation, the power supply device 12 may include a first power supply chip 121 and a second power supply chip 122. Figure 4 The first power chip 121 and the second power chip 122 can be independent bare chips, which are packaged in the power supply device 12. The first power chip 121 supplies power to PA1, and the second power chip 122 supplies power to PA2.

[0055] The first RF signal output terminal F1 of the RFIC is connected to the signal input terminal N1 of the power amplifier chip 11, and the second RF signal output terminal F2 of the RFIC is connected to the signal input terminal N2 of the power amplifier chip 11. The first RF signal output terminal F1 and the second RF signal output terminal F2 of the RFIC are respectively used to provide signals in a first frequency band and a second frequency band. The signals in the first frequency band can be the signals in the N41 frequency band described above, and the signals in the second frequency band can be the signals in the B39 frequency band, the B1 frequency band, or the B3 frequency band described above.

[0056] In an embodiment of the present application, each of the multiple power amplifier bare chips included in the power amplifier chip may further integrate multiple cascaded PAs. These multiple cascaded PAs may be integrated into the same bare chip through processes such as growth on the same silicon substrate, ion doping, etching, and development. The PA used to receive signals input from an external device (e.g., an RFIC) is referred to as a front-stage PA, and the PA used to output signals to an external device (e.g., an antenna) is referred to as a back-stage PA. Furthermore, in certain scenarios, one or more intermediate-stage PAs may be provided between the front-stage PA and the back-stage PA. Each PA requires power during operation. The supply voltage of the front-stage PA may be a DC constant voltage; the back-stage PA may support multiple power supply modes. These multiple power supply modes may include, but are not limited to, APT (Average Power Tracker) mode and ET (Envelope Tracker) mode. The power supply mode of the intermediate-stage PA may be selected from a DC constant voltage mode, APT mode, or ET mode, depending on the scenario. In APT mode, in order to improve the linearity of the wide bandwidth download wave, a capacitor is set between the power supply terminal and the common ground of the power amplifier; in ET mode, due to the rapid change of the power supply voltage, the capacitor will affect the envelope tracking characteristics. In this case, no capacitor is required in ET mode. Figure 5 , the power amplifier chip is described in detail.

[0057] Please continue to refer to Figure 5 , which shows another structural diagram of the power amplifier chip provided in the embodiment of the present application. Figure 5In the embodiment, the power amplifier chip 11 includes two PA bare chips, namely PA1 bare chip and PA2 bare chip. Among them, PA1 bare chip integrates two cascaded PAs, and PA2 bare chip also integrates two cascaded PAs. When the power amplifier chip 11 is packaged, from the outside, the pins of the power amplifier chip 11 include: a first power supply terminal V1, a second power supply terminal V2, a third power supply terminal V3, a fourth power supply terminal V4, a signal input terminal N1, a signal input terminal N2, an output port Po1, an output port Po2 and a common ground terminal G. Figure 2 The power amplifier chip 11 shown is similar. The corresponding terminals of the PA1 and PA2 bare chips are connected to the respective pins of the power amplifier chip 11 via jumpers or embedded wires. The connection relationships are not detailed here. The signal input terminal N1 is used to provide the first-band signal input by the RFIC to the previous PA stage in PA1; the output port Po1 is used to provide the signal output by the next PA stage in PA1 to the antenna; the signal input terminal N2 is used to provide the second-band signal input by the RFIC to the previous PA stage in PA2; the output port Po2 is used to provide the signal output by the next PA stage in PA2 to the antenna. The first power supply terminal V1 is used to provide an externally inputted DC constant voltage to the previous PA stage in PA1; the second power supply terminal V2 is used to provide an externally inputted PAT mode voltage or ET mode voltage to the next PA stage in PA1. The third power supply terminal V3 is used to provide an externally inputted DC constant voltage to the previous PA stage in PA2; and the fourth power supply terminal V4 is used to provide an externally inputted PAT mode voltage or ET mode voltage to the next PA stage in PA2. The common ground terminal G is used to provide an externally provided common reference voltage signal to each level of PA in PA1 and each level of PA in PA2.

[0058] Continue to refer Figure 5 ,exist Figure 5In the embodiment, the power amplifier chip 11 also contains capacitors C1, C2, switches K1, and K2. The external pins of the power amplifier chip 11 also include control terminals CL1 and CL2. The first terminal of capacitor C1 is connected to the second power supply terminal V2, and the second terminal of capacitor C1 is connected to one end of switch K1. The other end of switch K1 is connected to the common ground G, and the control terminal of switch K1 is connected to the control terminal CL1. The first terminal of capacitor C2 is connected to the fourth power supply terminal V4, and the second terminal of capacitor C2 is connected to one end of switch K2. The other end of switch K2 is connected to the common ground G, and the control terminal of switch K2 is connected to the control terminal CL2. It should be noted that in actual products, the positions of capacitor C1 and switch K1 can be interchanged. Specifically, one end of switch K1 is connected to the second power supply terminal V2, the other end of switch K1 is connected to the first terminal of capacitor C1, and the second terminal of capacitor C1 is connected to the common ground G. In addition, the positions of capacitor C2 and switch K2 can also be interchanged. The specific interchange method can be referred to the relevant description of the position interchange between capacitor C1 and switch K1, which will not be repeated here. The control terminal CL1 is used to receive an external control signal to control the on / off state of switch K1. When the second power supply terminal V2 inputs an APT mode voltage to the subsequent PA stage in PA1, the external control signal, through the control terminal CL1, turns switch K1 on, connecting capacitor C1 to the common ground G. When the second power supply terminal V2 inputs an ET mode voltage to the subsequent PA stage in PA1, the external control signal, through the control terminal CL1, turns switch K1 off, disconnecting capacitor C1 from the common ground G. The principles for turning switch K2 on and off are the same as those for switch K1 and will not be further described here. Switches K1 and K2 may include, but are not limited to, transistors or MOS transistors. When switches K1 and K2 are MOS transistors, the control terminals of switches K1 and K2 are gates, and the other two terminals of switches K1 and K2 are sources and drains, respectively. The specific source or drain terminal is determined by whether the selected transistor is a PMOS transistor or an NMOS transistor. It should be noted that the capacitor C1, capacitor C2, switch K1 and switch K2 packaged inside the power amplifier chip 11 are also bare chips. For example, these devices can be located in one or more bare chips; or, these devices can also be implemented as discrete devices, which is not limited in this embodiment.

[0059] The embodiment of the present application encapsulates capacitor C1, capacitor C2, switch K1 and switch K2 inside the power amplifier chip 11, so that in the scenario of a power amplifier with multiple power supply modes, the layout area of ​​the terminal device occupied by the communication device can be further reduced.

[0060] based on Figure 5 The power amplifier chip 11 shown in the embodiment of the present application provides a Figure 6The communication device 100 shown includes an RFIC, a first power chip 121 , a second power chip 122 , a power amplifier chip 11 , an antenna device T1 , and an antenna device T2 .

[0061] The RFIC includes a first RF signal output terminal F1, a second RF signal output terminal F2, a first control signal output terminal Cr1, a second control signal output terminal Cr2, a third control signal output terminal Cr3, and a fourth control signal output terminal Cr4. The first RF signal output terminal F1 of the RFIC is connected to the signal input terminal N1 of the power amplifier chip 11, the second RF signal output terminal F2 of the RFIC is connected to the signal input terminal N2 of the power amplifier chip 11, the first control signal output terminal Cr1 of the RFIC is connected to the control terminal CL1 of the power amplifier chip 11, the second control signal output terminal Cr2 of the RFIC is connected to the control terminal CL2 of the power amplifier chip 11, the third control signal output terminal Cr3 of the RFIC is connected to the control terminal Cr3 of the first power supply chip 121, and the fourth control signal output terminal Cr4 of the RFIC is connected to the control terminal Cr4 of the second power supply chip 122.

[0062] The output terminal Vcc1 of the first power chip 121 is connected to the first power terminal V1 of the power amplifier chip 11, and the output terminal Vcc2 of the first power chip 121 is connected to the second power terminal V2 of the power amplifier chip 11. The output terminal Vcc3 of the second power chip 122 is connected to the third power terminal V3 of the power amplifier chip 11, and the output terminal Vcc4 of the second power chip is connected to the fourth power terminal V4 of the power amplifier chip 11. In a specific implementation, the first power chip 121 and the second power chip 122 can be packaged in the same power supply device 12, and they are respectively connected to external chips or devices through pins or ports exposed to the outside for signal exchange, such as Figure 7 shown.

[0063] In addition, in Figure 6 In the aforementioned communication device, to improve the performance of a power amplifier supporting frequency bands such as the aforementioned B41 in the APT power supply mode, a capacitor C3 and a switch K3 are typically connected in series between the second output terminal Vcc2 of the first power chip 121 and the common ground G. The first electrode of the capacitor C3 is connected to the second output terminal Vcc2, the second electrode of the capacitor C3 is connected to one end of the switch K3, and the other end of the switch K3 is connected to the common ground G. Furthermore, the positions of the capacitor C3 and the switch K3 can also be interchanged. For the specific interchangeability, reference can be made to the description of the interchangeability between the capacitor C1 and the switch K1, which will not be repeated here. Furthermore, the RFIC further includes a fifth control signal output terminal Cr5, the control end of the switch K3 being connected to the fifth control signal output terminal Cr5 of the RFIC.

[0064] In order to further reduce the terminal device layout area occupied by the communication device, in a possible implementation, the switch K3 can also be set inside the power amplifier chip 11, such as Figure 8 At this time, the pin of the power amplifier chip 11 further includes a control terminal CL3, so as to connect the control terminal of the switch K3 to the fifth control signal output terminal Cr5 of the RFIC through the control terminal CL3. Figure 8 visibility, Figure 8 It is not shown that the control terminal CL1, the control terminal CL2, and the control terminal CL3 are respectively connected to the first control signal output terminal Cr1, the second control signal output terminal Cr2, and the third control signal output terminal Cr3.

[0065] In addition, it should be noted that the first power chip 121 , the second power chip 122 , the power amplifier chip 11 and the RFIC all include a common ground terminal, and all of the common ground terminals can be connected together. Figure 6 and Figure 8 Except for the power amplifier chip 11, the common ground terminals of other chips or devices are not shown.

[0066] In such Figure 6 In the illustrated communication device, in a scenario where dual-connection is used for signal transmission, the output terminal Vcc1 of the first power supply chip 121 provides a constant DC voltage to the preceding PA stage in PA1, and the output terminal Vcc3 of the second power supply chip 122 provides a constant DC voltage to the preceding PA stage in PA2. Based on the power of the RF signal to be transmitted, the RFIC can control the output terminal Vcc2 of the first power supply chip 121 to supply power to the subsequent PA stage of PA1 in either the APT mode or the ET mode, or control the output terminal Vcc4 of the second power supply chip 122 to supply power to the subsequent PA stage of PA2 in either the APT mode or the ET mode. Specifically, when the RFIC detects that the RF signal to be transmitted is a high-power signal, the RFIC can control the first power supply chip 121 and the second power supply chip 122 to respectively adopt the APT mode for power supply. At this time, the RFIC can control switches K1, K2, and K3 to be closed, capacitor C1 is connected between the output terminal Vcc2 of the first power chip 121 and the common ground G, capacitor C2 is connected between the output terminal Vcc4 of the second power chip 122 and the common ground G, and capacitor C3 is connected between the output terminal Vcc2 of the first power chip 121 and the common ground G. When the RFIC detects that the RF signal to be transmitted is a small or medium power signal, the RFIC can control the first power chip and the second power chip to respectively adopt the ET mode for power supply. At this time, the RFIC can respectively control switches K1, K2, and K3 to be disconnected, and capacitors C1, C2, and C3 are not connected to the circuit at this time.

[0067] By adopting Figure 6 or Figure 8 The communication equipment shown can ensure independent power supply for each PA while reducing the layout area occupied by the communication equipment, which is conducive to the realization of highly integrated terminal equipment.

[0068] Please continue to refer to Figure 9 , which shows another structural diagram of the electronic device 100 provided in an embodiment of the present application. Figure 9 In the embodiment, the electronic device 100 includes a first power supply chip 121, a second power supply chip 122, an RFIC, and a power amplifier chip 11. The connection relationship between the RFIC and the first power supply chip 121 and the signal interaction between the two, and the connection relationship between the RFIC and the second power supply chip 122 and the signal interaction between the two can be referred to. Figure 6 The relevant descriptions in the illustrated embodiments will not be repeated here.

[0069] The power amplifier chip 11 includes four PA bare chips, namely PA1 bare chip, PA2 bare chip, PA3 bare chip and PA4 bare chip, wherein the PA1 bare chip, PA2 bare chip, PA3 bare chip and PA4 bare chip can respectively integrate two cascaded PAs. The corresponding ends of the PA1 bare chip, PA2 bare chip, PA3 bare chip and PA4 bare chip are respectively connected to the pins of the power amplifier chip 11 by jumpers, buried wires or switches. The power amplifier chip 11 also includes capacitors C1 and C2, switches K1, K2 and K3. Figure 2-Figure 8 The difference between the power amplifier chip 11 shown in the embodiment of the present application is that the power amplifier chip 11 shown in the embodiment of the present application also includes a controller CR. The control terminals of the switches K1, K2 and K3 are controlled to be turned on or off by the controller CR. In addition, the functions, beneficial effects and connection relationships between the capacitors C1, C2, switches K1, K2 and K3 and other components are similar to those of the embodiment of the present application. Figure 5-Figure 8 The same as the power amplifier chip 11 shown in FIG. Figure 5-Figure 8 The description of the power amplifier chip 11 is omitted here. The function of the controller CR and the connection relationship between it and other components are described below.

[0070] and Figure 5The PA1 bare chip shown is identical and is used to amplify RF signals in a first frequency band (e.g., a 5G band). The first-stage PA in the PA1 bare chip can be connected to the output terminal Vcc1 of the first power supply chip via the first power supply terminal V1. The second-stage PA in the PA1 bare chip can be connected to the output terminal Vcc2 of the first power supply chip via the second power supply terminal V2. The PA1 bare chip is connected to the first RF signal output terminal F1 of the RFIC via the signal input terminal N1. The PA2 bare chip is used to amplify RF signals in a second frequency band (e.g., a low-frequency band in 4G). The PA3 bare chip is used to amplify RF signals in a third frequency band (e.g., a mid-frequency band in 4G). The PA4 bare chip is used to amplify RF signals in a fourth frequency band (e.g., a high-frequency band in 4G). Among them, the first-stage PA in the PA2 bare chip, the PA3 bare chip and the PA4 bare chip can be connected to the output terminal Vcc3 of the second power supply chip through the third power supply terminal V3, and the second-stage PA in the PA2 bare chip, the PA3 bare chip and the PA4 bare chip can be connected to the output terminal Vcc4 of the second power supply chip through the fourth power supply terminal V4. The PA2 bare chip is connected to the second RF signal output terminal F2 of the RFIC through the signal input terminal N2, the PA3 bare chip is connected to the third RF signal output terminal F3 of the RFIC through the signal input terminal N3, and the PA4 bare chip is connected to the fourth RF signal output terminal F4 of the RFIC through the signal input terminal N4. For the specific working method of the PA1 bare chip, please refer to Figure 5 For the detailed description of PA1, please refer to the working methods of PA2 bare chip, PA3 bare chip and PA4 bare chip. Figure 5 The description of PA2 shown is omitted here.

[0071] Generally, for signals in the same frequency band, there are slight differences in the communication frequency bands adopted by different countries or regions. For example, for signals in the low-frequency band, some regions may adopt the frequency band with the frequency band number LB1 in the standard 38101-3-g21, and some regions may adopt the frequency band with the frequency band number LB2 in the standard 38101-3-g21. Based on this, in order to be applicable to a variety of communication frequency bands, a power amplifier (such as PA1) for amplifying signals in the same frequency band range can provide multiple output ports, each output port is applicable to a radio frequency band, and the output end of the PA bare chip is connected to one of the output ports through a switch in the switch group. In addition, the switch group also includes nodes connected to the output ports in a one-to-one correspondence, and each node is connected to each output port in a one-to-one correspondence through a different radio frequency signal line. Among them, the radio frequency signal line used to connect each node to each output port is determined based on the radio frequency band provided by the output port. Specifically, such as Figure 9As shown, the output end of the PA1 bare chip rear-stage PA is connected to the output port Po1 or the output port Po2 through the switch group 1, wherein the RF signal line used to connect one node of the switch group 1 and the output port Po1 may be an RF signal line with a frequency band number of N40 applicable to the standard 38101-3-g21, and the RF signal line used to connect another node of the switch group 1 and the output port Po2 may be an RF signal line with a frequency band number of N41 applicable to the standard 38101-3-g21; the output end of the PA3 bare chip rear-stage PA is connected to the output port Po4, the output port Po5 or the output port Po6 through the switch group 2, wherein the RF signal line used to connect the first node of the switch group 2 and the output port Po4 may be an RF signal line with a frequency band number of MB39 applicable to the standard 38101-3-g21, and the RF signal line used to connect the second node of the switch group 2 and the output port Po5 may be an RF signal line with a frequency band number of MB39 applicable to the standard 38101-3-g21. The RF signal line with the frequency band number MB3 in 101-3-g21 and the RF signal line used to connect the third node of the switch group 2 and the output port Po6 can be a RF signal line with the frequency band number MB1 applicable to the standard 38101-3-g21; the output end of the PA of the subsequent stage of the PA4 bare chip is connected to the output port Po7, the output port Po8 or the output port Po9 through the switch group 3, wherein the RF signal line used to connect the first node of the switch group 3 and the output port Po7 can be a RF signal line with the frequency band number LB8 applicable to the standard 38101-3-g21, the RF signal line used to connect the second node of the switch group 3 and the output port Po8 can be a RF signal line with the frequency band number LB28 applicable to the standard 38101-3-g21, and the RF signal line used to connect the third node of the switch group 3 and the output port Po9 can be a RF signal line with the frequency band number LB20 applicable to the standard 38101-3-g21. It should be noted that the number of output terminals corresponding to PA1, PA3 and PA4 is only illustrative. It is understandable that PA1, PA3 and PA4 may correspond to more or fewer output terminals, and accordingly, each switch group may include more or fewer switches. Figure 9 The power amplifier chip 11 shown also includes an output port Po3. The output of the subsequent PA stage of the PA2 bare chip is connected to the output port Po3 via a radio frequency signal line. The output port Po3 can support radio frequency signals in the standard 38101-3-g21 frequency band MHB3.

[0072] Please continue to see Figure 9 ,exist Figure 9In the embodiment, the controller CR is connected to the data output terminal SD of the RFIC through the data input terminal SDATA, the controller CR is connected to the clock output terminal SC of the RFIC through the clock signal terminal SCLK, and the controller CR is connected to the external battery through the battery terminal VBAT. Inside the power amplifier chip 11, the control terminal A1 of the controller CR is connected to the gain adjustment terminal A1 of PA1, and the control terminal A11 of the controller CR is connected to the enable terminal A11 of PA1; the control terminal A2 of the controller CR is connected to the gain adjustment terminal A2 of PA2, and the control terminal A12 of the controller CR is connected to the enable terminal A12 of PA2; the control terminal A3 of the controller CR is connected to the gain adjustment terminal A3 of PA3, and the control terminal A13 of the controller CR is connected to the enable terminal A13 of PA3; the control terminal A4 of the controller CR is connected to the gain adjustment terminal A4 of PA4, and the control terminal A14 of the controller CR is connected to the enable terminal A14 of PA4; the control terminal A5 of the controller CR is connected to the control terminal A5 of the first switch group 1; the control terminal A6 of the controller CR is connected to the control terminal A6 of the second switch group 2; the control terminal A7 of the controller CR is connected to the control terminal A3 of the third switch group 3; the control terminal A8 of the controller CR is connected to the control terminal of the switch K1; the control terminal A9 of the controller CR is connected to the control terminal of the switch K2; and the control terminal A10 of the controller CR is connected to the control terminal of the switch K3.

[0073] Specifically, the controller CR can operate based on the clock cycle provided by the clock signal terminal SCLK. Based on the clock cycle provided by the clock signal terminal SCLK, the controller CR can receive data from the data input terminal SDATA. This data is sent to the controller CR by the RFIC via the bus to implement operating mode control. The controller CR can parse the received data and, based on the analysis results, determine information such as the power amplifier used for signal transmission, the selected power amplifier gain, the selected communication frequency band, and the power supply mode of each power amplifier (PAT power supply mode or ET power supply mode). Based on this determined information, the controller CR can then control the enabling of one or more of PA1, PA2, PA3, or PA4, adjust the gain of one or more of PA1, PA2, PA3, or PA4, and control the path of the switch group K1, switch group K3, or switch group K4. This allows one or more PAs to transmit the signal output from their output terminals to the network device via the antenna.

[0074] As an example, assume that PA1 transmits a first RF signal and PA3 transmits a second RF signal. PA1's subsequent PA stage is powered in APT mode, while PA3's subsequent PA stage is powered in APT mode. PA1 transmits signals in the N41 frequency band specified in the communication protocol, while PA3 transmits signals in the MB39 frequency band specified in the communication protocol. The RFIC can transmit PA1 and PA3 configuration information to the data input terminal SDATA of the power amplifier chip 11 via a bus connected to the data output terminal SD. The configuration information is then provided to the controller CR via the data input terminal SDATA. Based on the received data, the controller CR enables PA1 and PA3, adjusts their gains, connects the output of PA1 to the output port Po1 (assuming that output port Po1 supports the N41 frequency band), and connects the output of PA3 to the output port Po4 (assuming that output port Po4 supports the MB39 frequency band). Furthermore, the controller CR can also control switches K1, K2, and K3 to be conductive.

[0075] The above configuration information can be carried in a frame format for transmission. The frame format may include a field for indicating a power amplifier, a field for indicating the radio frequency band used, and a field for indicating the power supply mode used, etc. In specific scenarios, more or fewer fields than the fields included in the above frame format may be included, which are set according to the needs of the scenario. Each field can be indicated by multiple bits. For example, taking the field indicating PA as an example, four bits can be used, each bit representing a PA. For example, when PA1 and PA3 are used to transmit radio frequency signals, the corresponding bits of this field can be set to "1010". In addition, the controller CR can also control switches K1, K3, and K4 to be turned on.

[0076] In a possible implementation of this embodiment, the terminal device can multiplex the output end of the power amplifier chip 11 to receive the downlink signal, and then transmit it to the RFIC through the output end of the power amplifier chip 11. Specifically, Figure 10 As shown. Figure 10In the embodiment, the power amplifier chip 11 further includes a signal receiving terminal RX1 and a signal receiving terminal RX2. The signal receiving terminal RX1 and the signal receiving terminal RX2 are respectively used to receive radio frequency signals of different frequencies. In addition, the output port Po1 and the output port Po2 of the power amplifier chip 11 are respectively connected to the signal receiving terminal RN1 and the signal receiving terminal RN2 of the RFIC; the switch group 1 inside the power amplifier chip 11 further includes a switch for connecting the output port Po1 to the output end of PA1 or to the signal receiving terminal RX1, and the switch group 1 further includes a switch for connecting the output port Po2 to the output end of PA1 or to the signal receiving terminal RX2. The control terminal A5 of the controller CR is also used to control the switches in the switch group 1 so that the output port Po2 is connected to the output end of PA1 or to the signal receiving terminal RX2. Specifically, the RFIC sends the indication information for indicating the transmission signal or the reception signal to the controller CR through the data input terminal SDATA, and the controller CR controls each switch in the switch group 1 based on the analysis result.

[0077] It should be noted that if Figure 9 and Figure 10 The power amplifier chip 11 shown also includes a common ground terminal G. All the terminals inside the power amplifier chip 11 can be connected to the common ground terminal G. The common ground terminal G can be connected to the common ground terminals of the first power supply chip, the second power supply chip and the RFIC, so that the power amplifier chip 11, the first power supply chip, the second power supply chip and the RFIC can have a common common voltage reference signal.

[0078] The PA shown in each embodiment of the present application is applicable to various physical channels of the communication system, that is to say, it can power amplify the signals transmitted by various channels. The channel may include but is not limited to: PUCCH channel, PUSCH channel, PRACH channel and SRS channel. Among them, the gains adopted by different channels may be different. Before the terminal device needs to transmit a signal (at this time, the PA is switched from the off state to the enabled state), or before the signal is transmitted from the first type of channel (such as the PUCCH channel) to the second type of channel (such as the PUSCH channel) (at this time, the PA is switched from using the first gain to send the signal to using the second gain to send the signal), the PA needs to be configured (including controlling the PA to enable or changing the PA gain, etc.). Among them, the RFIC can configure the power of the PA based on the information carried by the frame format sent by the network device, and then transmit the configuration information of the PA to the controller CR, so that the controller CR controls the PA to enable and adjust the gain of the PA so that the PA can work normally. In a specific scenario, the communication device in the terminal device (such as the baseband processor, RFIC and antenna) can monitor the measurement information sent by the network device, and then parse the received measurement information. Based on the parsing results, it determines the frame format used to carry data when transmitting data with the network device, the time for transmitting each type of data, the channel used for data transmission, and other information. Please refer to Figure 11 , which schematically shows a schematic diagram of the frame format sent by the network device. Figure 11 As can be seen from the figure, each frame of data can include two time slots, and each time slot can include 14 symbols. Figure 11 The information in the frame format shown also includes the starting symbol of signal transmission and which symbols use which channel for signal transmission. Figure 11 In the figure, it is schematically shown that the symbol 12 in time slot 8 starts signal transmission. Among them, symbols 12 and 13 in time slot 8 use the PUCCH channel for signal transmission; symbols 0 to 11 in time slot 9 use the PUSCH channel for signal transmission; symbols 12 to 13 in time slot 9 use the SRS channel for signal transmission. That is, before the start of symbol 12 in time slot 8, the PA is in the off state, and starting from symbol 12 in time slot 8, the PA changes from the off state to the enabled state. Before symbol 0 in time slot 9, the PA uses the first gain for signal transmission, and starting from symbol 0 in time slot 9, the PA uses the second gain for signal transmission. The PA configuration information transmitted by the RFIC to the controller CR also includes the time to control the PA enablement and the time to adjust the PA gain. Usually, the PA enablement is controlled, or the PA gain is adjusted, in the first preset time period before the distance signal starts to be transmitted or in the second preset time period before the distance channel is switched. For example, in Figure 12In the timing shown, it is assumed that starting from time T2, PA adopts the first gain to transmit the signal, which corresponds to Figure 11 At the start time of symbol 12 in time slot 8 shown in FIG, it is assumed that starting from time T3, PA adopts the second gain for signal transmission, which corresponds to Figure 11 The starting time of symbol 0 in time slot 9 shown. Then, in the traditional technology, at time T1, the PA gain is adjusted and the PA is controlled to be enabled, and at time T2, the PA gain is adjusted so that the PA adopts the second to transmit the signal. Among them, the time period t1 of T2 minus T1 is the same as or has a small difference with the time period t2 of T3 minus T2. It is usually about 2us. Since there is a large time delay in the process of PA changing from the off state to the enabled state, and due to the influence of external factors during the startup process, the output signal is usually unstable, which in turn causes the transmitted signal to have a high bit error rate. Based on this, in an embodiment of the present application, the time period t1 and the time period t2 are set to different time periods, wherein the length of the time period t1 is set to be greater than the length of the time period t2, that is, the PA is started in advance. Specifically, as Figure 13 The timing shown in the figure can adjust the PA gain and control the PA enable at time T1, and the rest of the time is the same as Figure 12 The times shown are identical. This allows the PA sufficient time to stabilize, reducing the bit error rate (BER). Furthermore, it improves the error vector magnitude (EVM) of the first symbol.

[0079] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A power amplifier chip, characterized in that: include: Package shell; A plurality of power amplifier bare chips, wherein the plurality of power amplifier bare chips are sealed in the packaging shell; a first power supply terminal, wherein the first power supply terminal is a power supply terminal of a first power amplifier bare chip among the plurality of power amplifier bare chips; a second power supply terminal, wherein the second power supply terminal is a power supply terminal of a second power amplifier bare chip among the plurality of power amplifier bare chips; a first switch, located in the package, for connecting the first capacitor between the common ground and the first power supply terminal or disconnecting the connection; Wherein, each of the plurality of power amplifier bare chips includes at least one stage of power amplifier; The multiple power amplifier bare chips respectively support different radio frequency bands, and the multiple power amplifier bare chips support dual connection or multi-connection.

2. The power amplifier chip according to claim 1, wherein: The power amplifier chip further includes a second capacitor and a second switch, which are located in the packaging shell; The second switch is used to connect the second capacitor between the common ground and the second power supply terminal or disconnect the connection.

3. The power amplifier chip according to claim 1 or 2, characterized in that: The power amplifier chip further includes: a controller, located in the package, configured to receive instruction information for instructing power amplifier configuration from the wireless radio frequency integrated circuit, and based on the instruction information, control the enabling of at least one power amplifier stage in at least one power amplifier bare chip among the plurality of power amplifier bare chips, and adjust the gain of the enabled at least one power amplifier stage; Among them, the indication information includes at least one of the following items: the at least one stage power amplifier enabled, the gain of the power amplifier, the power supply mode of the power amplifier, the start-up time of the power amplifier, the time for adjusting the gain of the power amplifier, or the output port of the power amplifier chip used.

4. The power amplifier chip according to any one of claims 1 to 3, characterized in that: The power amplifier chip further includes: A plurality of switch groups are located in the package shell, wherein a first switch group among the plurality of switch groups includes a first input terminal and a plurality of output terminals; The output end of the third power amplifier bare chip among the multiple power amplifier bare chips is connected to the first input end of at least one first switch group among the multiple switch groups, and the multiple output ends of each first switch group in the at least one first switch group are connected to at least part of the multiple output ports of the power amplifier chip.

5. The power amplifier chip according to claim 4, characterized in that: A second switch group in the at least one first switch group includes a second input terminal; The second input end is connected to the radio frequency signal receiving end of the power amplifier chip; The switch in the second switch group connects the radio frequency signal receiving end to one of the multiple output ends in the second switch group based on a control signal.

6. The power amplifier chip according to any one of claims 1 to 5, characterized in that: The first power amplifier of the at least one stage power amplifier in each power amplifier bare chip includes a first gain and a second gain; wherein, A first time period between the moment the first power amplifier is started and the moment the first power amplifier starts transmitting signals is greater than a second time period between the moment the first power amplifier starts adjusting from the first gain to the second gain and the moment the first power amplifier starts transmitting signals using the second gain.

7. A communication device, characterized in that: The communication device comprises a power supply device and a power amplifier chip according to any one of claims 1 to 6; wherein, The first power supply device in the power supply device is used to supply power to the first power amplifier bare chip in the power amplifier chip; The second power supply device in the power supply device is used to supply power to the remaining power amplifier bare chips in the power amplifier chip.

8. The communication device according to claim 7, wherein: The communication device further includes: A wireless radio frequency integrated circuit is used to transmit a radio frequency signal to a power amplifier integrated in at least one power amplifier bare chip among a plurality of power amplifier bare chips.

9. The communication device according to claim 8, wherein: The power supply device is also used for: An indication signal is received from the wireless radio frequency integrated circuit, and based on the indication signal, power is supplied to the power amplifier using a power supply mode indicated by the indication signal, where the power supply mode includes an average power tracking mode or an envelope tracking mode.

10. The communication device according to any one of claims 7 to 9, characterized in that: The communication device further includes a first capacitor; The first capacitor is connected between the common ground and the first power supply terminal or disconnected based on control of the first switch.

Images