A bypass thyristor and a manufacturing method thereof

Abstract

The present invention provides a bypass thyristor and a method for manufacturing the same, which comprises a cathode side aluminum layer, a cathode N+ region, a cathode P-region, an N-base region, an anode P-region, an anode P+ region and an anode aluminum layer, arranged in sequence from top to bottom. A groove is provided in the center of the cathode side, a gate P+ region is provided on its surface, a protruding wavy P-base region is provided directly below the gate P+ region, and a high-concentration N+ region is provided on the anode side surface directly opposite the wavy P-region. When a trigger signal is applied to the gate of the structure of the present invention, the thyristor can achieve forward conduction; when the anode-cathode exceeds the reverse breakdown voltage, the thyristor can achieve precise voltage breakdown, and the breakdown is located at the center gate, and has an explosion-proof function. The structure of the present invention is mainly used in flexible direct current transmission systems to protect the safe operation of the converter valve power submodule.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor device manufacturing, and in particular relates to a bypass thyristor and a manufacturing method thereof. Background Art

[0002] In recent years, modular multilevel converters (MMCs) have been used in engineering. MMCs contain a large number of cascaded power submodules. Once a submodule fails, the converter will not work properly or may even stop operating, which greatly reduces the reliability of the system. Each submodule contains two insulated gate bipolar transistors (IGBTs) T1 and T2, two fast recovery diodes (FRDs) D1 and D2, and one energy storage capacitor C. Figure 1 As shown in the figure. In the event of a DC-side short-circuit fault, the fast recovery diode (FRD) sustains the short-circuit current for a long time, requiring the bypass thyristor to quickly open for shunt protection to prevent converter valve failure. Furthermore, if a failure in the energy source or control board causes the power submodule in the bridge arm to become uncontrollable and the mechanical switch to fail, the capacitor in the circuit will continue to charge, causing the capacitor voltage to exceed its tolerance range, eventually leading to breakdown or even explosion, causing the converter valve to lock, affecting normal system operation.

[0003] To avoid the above situation, a bypass thyristor needs to be connected in parallel at the input end of the power module. The thyristor needs to achieve fast forward conduction at a low FRD voltage drop and have precise reverse voltage breakdown characteristics (breakdown voltage deviation range ±100V), so that the faulty sub-module can exit operation in short-circuit mode, ensuring that the converter valve can operate normally without replacing the faulty sub-module.

[0004] In view of the above problems, there is an urgent need for a bypass thyristor and a manufacturing method thereof that meet engineering requirements. Summary of the Invention

[0005] The present invention aims to provide a bypass thyristor and a manufacturing method thereof.

[0006] The technical solution adopted by the present invention is a bypass thyristor, which is arranged, from top to bottom, in the following order: a cathode aluminum layer, a cathode N+ region, a cathode P- region, an N-base region, an anode P- region, an anode P+ region, and an anode aluminum layer. A trench is provided in the center of the cathode side, and a gate P+ region is provided on its surface. A protruding wavy P-base region is provided directly below the gate P+ region. A high-concentration N+ region is provided on the anode side surface directly opposite the wavy P- region.

[0007] The cathode N+ region has a depth of 10 to 20 μm and a doping concentration of 5×10 19 ~5×10 20 cm-3 .

[0008] The gate P+ region has a depth of 5 to 10 μm and a doping concentration of 1×10 19 ~5×10 19 cm -3 .

[0009] The cathode P-region has a depth of 80 to 140 μm and a doping concentration of 1×10 14 ~5×10 16 cm -3 .

[0010] The thickness of the N-base region is 200-500 μm, and the doping concentration is 5×10 12 ~1×10 14 cm -3 .

[0011] The depth of the anode P-region is 80 to 140 μm, and the doping concentration is 1×10 14 ~5×10 16 cm -3 .

[0012] The depth of the anode P+ region is 5 to 10 μm, and the doping concentration is 1×10 19 ~5×10 19 cm -3 .

[0013] The gate trench depth is 10-30 μm, the corresponding wavy P-region ripple height directly below the trench is 10-30 μm, the anode N+ region depth is 10-20 μm, and the doping concentration is 5×10 19 ~5×10 20 cm -3 .

[0014] The method for manufacturing a bypass thyristor is implemented according to the following steps:

[0015] (1) Select the original defect-free, dislocation-free high-resistance zone melt-irradiated single crystal silicon wafer as n - The substrate material of the N-base region is 200 to 500 μm thick and has a doping concentration of 5×10 12 ~1×10 14 cm -3 ;

[0016] (2) Anode surface protection, cathode surface photolithography, selective etching of the silicon wafer to form a gate trench with a depth of 10 to 30 μm;

[0017] (3) Aluminum impurities are pre-deposited on both sides of the silicon wafer, followed by wet oxygen oxidation and high-temperature diffusion at 1200-1250°C for 20-50 hours to form cathode P-region and anode P-region with a depth of 80-140 μm and a doping concentration of 1×10 14 ~5×10 16 cm -3 At this point, a wavy P-region is formed directly below the trench, where the height of the ripples in the protruding portion of the P-region is equal to the trench depth.

[0018] (4) Double-sided photolithography to form N+ diffusion windows, double-sided selective pre-deposition of phosphorus, wet oxygen oxidation and high-temperature advancement, conditions of 1100-1250°C, time 3-5h, to form cathode high-concentration N+ region and anode high-concentration N+ region, with a depth of 10-20μm and a doping concentration of 5×10 19 ~5×10 20 cm -3 At this point, a parasitic NPN transistor structure is formed on the anode side.

[0019] (5) Double-sided photolithography, selective pre-deposition of high-concentration boron, wet oxygen oxidation and high-temperature advancement, conditions are 1100-1250°C, time 3-5h, forming gate high-concentration P+ region and anode high-concentration P+ region, with a depth of 5-10μm and a doping concentration of 1×10 19 ~5×10 19 cm -3 .

[0020] (6) Aluminum is evaporated on both sides of the silicon wafer for the first time and reverse-etched to form an aluminum layer. Then, aluminum is evaporated and reverse-etched for the second time to form an aluminum layer. Then, alloying is performed. Typical alloying conditions are: temperature 400-500°C, time 0.5-2 hours. Then, laser cutting is performed to cut into wafers with a diameter of 80-130 mm.

[0021] (7) The mesa is shaped and etched to form a double negative angle structure with an angle of 1° to 3°, and then coated with glue for protection to form a complete chip. After that, it is irradiated with electrons to complete the blocking voltage test.

[0022] The structure of the present invention has the following beneficial effects:

[0023] The thickness of the N-base region of the structure of the present invention has been optimized, and the reverse electric field lines penetrate to the PN-junction, which is a strong punch-through structure and can achieve precise voltage breakdown. The breakdown voltage deviation range is only ±100V. The wavy P-region below the groove provides an additional peak electric field under blocking, and the anode directly below the wavy P-region is parasitic with an NPN transistor, which provides a multiplied current after breakdown and controls the explosion position after breakdown at the groove, which has an explosion-proof function. When a trigger signal is applied to the gate of the structure of the present invention, the thyristor can achieve forward conduction; when the anode-cathode exceeds the reverse breakdown voltage, the thyristor can achieve precise voltage breakdown, and the breakdown is located at the center gate, which has an explosion-proof function. Therefore, the structure of the present invention has the functions of forward conduction, reverse precise voltage breakdown and explosion-proof. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the MMC half-bridge power module.

[0025] Figure 2 It is a schematic cross-sectional view of the structure of the present invention.

[0026] Figure 3 Schematic diagram of front and back cross-section of the present invention.

[0027] Figure 4 It is a structural schematic diagram of the key process steps of the manufacturing method of the present invention.

[0028] Figure 5 Process flow chart of the manufacturing method of the present invention.

[0029] Figure 6 Schematic diagram of the IV characteristic curve of the structure of the present invention.

[0030] Description of reference numerals:

[0031] Reference Figure 2 , 10-cathode aluminum layer; 11-enlarged gate aluminum layer; 12-gate aluminum layer; 13-gate trench; 14-cathode N+ region; 15-gate P+ region; 16-P- region below the trench; 17-cathode P- region; 2-N-base region; 30-anode aluminum layer; 31-anode P+ region; 32-anode P- region; 33-anode N+ region; 40-negative bevel terminal.

[0032] Reference Figure 3 , 50 - gate trench region; 51 - amplifying gate; 52 - anode N+ region; 53 - active region; 54 - terminal region. DETAILED DESCRIPTION

[0033] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] Reference Figure 2The present invention provides a bypass thyristor structure, which is sequentially provided with cathode side aluminum layers 10, 11 and 12, cathode N+ region 14, cathode P- region 17, N-base region 2, anode P- region 32, anode P+ region 31 and anode aluminum layer 30 from top to bottom. A trench 13 is provided in the center of the cathode side, and a gate P+ region 15 is provided on its surface. A protruding wavy P-base region 16 is provided directly below the gate P+ region. A high-concentration N+ region 33 is provided on the anode side surface directly opposite the wavy P-region. The cathode N+ region 14 has a depth of 10 to 20 μm and a doping concentration of 5×10 19 ~5×10 20 cm -3 The gate P+ region 15 has a depth of 5 to 10 μm and a doping concentration of 1×10 19 ~5×10 19 cm -3 The cathode P-region 17 has a depth of 80 to 140 μm and a doping concentration of 1×10 14 ~5×10 16 cm -3 The thickness of the N-base region 2 is 200-500 μm, and the doping concentration is 5×10 12 ~1×10 14 cm -3 The depth of the anode P-region 32 is 80-140 μm, and the doping concentration is 1×10 14 ~5×10 16 cm -3 The anode P+ region 31 has a depth of 5 to 10 μm and a doping concentration of 1×10 19 ~5×10 19 cm -3 The gate trench 13 has a depth of 10 to 30 μm, the corrugation height of the wavy P- region 16 directly below the trench is 10 to 30 μm, the depth of the anode N+ region 33 is 10 to 20 μm, and the doping concentration is 5×10 19 ~5×10 20 cm -3 .

[0035] Reference Figure 3 The gate consists of a central gate 50 and an amplifying gate 51. The gate trench is located in the central gate region, with a depth of 10 to 30 μm and a width of 200 to 1000 μm. Directly below the gate trench, on the back anode side, a high-concentration N+ region 52 is provided, typically with a diameter of 400 to 2000 μm.

[0036] Combine Figure 2 and Figure 3 The structure of the present invention is characterized by:

[0037] (1) The thickness of the N-base region 2 of the structure of the present invention has been optimized, and the reverse electric field lines penetrate to the PN-junction, which is a strong punch-through structure and can achieve precise voltage breakdown. The breakdown voltage deviation range is only ±100V.

[0038] (2) The wavy P-region 16 below the trench 13 provides an additional peak electric field under blocking. The anode directly below the wavy P-region 16 is parasitic with an NPN transistor, which provides a multiplied current after breakdown and controls the explosion position after breakdown at the trench, thus having an explosion-proof function.

[0039] Therefore, the structure of the present invention has both forward conduction and reverse blocking capabilities. It not only has a low forward on-state voltage drop, but also has reverse precise voltage breakdown and explosion-proof functions.

[0040] Its IV characteristic diagram is as follows Figure 6 shown.

[0041] Combine Figure 4 and Figure 5 Explain the manufacturing process:

[0042] (1) Select the original defect-free, dislocation-free high-resistance zone melt-irradiated single crystal silicon wafer as n - The thickness of the N-base region 2 is 200 to 500 μm, and the doping concentration is 5×10 12 ~1×10 14 cm -3 ;

[0043] (2) Protecting the anode surface, photolithography of the cathode surface, and selectively etching the silicon wafer to form a gate trench 13 with a depth of 10 to 30 μm;

[0044] (3) Aluminum impurities are pre-deposited on both sides of the silicon wafer, followed by wet oxygen oxidation and high-temperature diffusion at 1200-1250°C for 20-50 hours to form a cathode P-region 17 and an anode P-region 32, both with a depth of 80-140 μm and a doping concentration of 1×10 14 ~5×10 16 cm -3 At this point, a wavy P-region 16 is formed directly below the trench, wherein the height of the ripples of the protruding portion of the wavy P-region 16 is equal to the depth of the trench 13 .

[0045] (4) Double-sided photolithography to form the N+ diffusion window, selectively pre-deposit phosphorus on both sides, and wet oxygen oxidation and high-temperature advancement at 1100-1250°C for 3-5 hours to simultaneously form the cathode high-concentration N+ region 14 and the anode high-concentration N+ region 33, both with a depth of 10-20 μm and a doping concentration of 5×10 19 ~5×10 20 cm -3At this point, a parasitic NPN transistor structure is formed on the anode side.

[0046] (5) Double-sided photolithography, selective pre-deposition of high-concentration boron, wet oxygen oxidation and high-temperature advancement, conditions are 1100-1250°C, time 3-5h, and simultaneously form the gate high-concentration P+ region 15 and the anode high-concentration P+ region 31, both with a depth of 5-10μm and a doping concentration of 1×10 19 ~5×10 19 cm -3 .

[0047] (6) Aluminum is evaporated and reverse-etched on both sides of the silicon wafer for the first time to form aluminum layers 10, 12, and 30. Aluminum is then evaporated and reverse-etched for the second time to form aluminum layer 11. This is followed by alloying, typically at 400-500°C for 0.5-2 hours. Laser cutting is then performed to cut the wafers into 80-130 mm diameter wafers.

[0048] (7) The mesa is shaped and etched to form a double negative angle structure 40 with an angle of 1° to 3°, and then coated with glue for protection to form a complete chip. After that, it is electron irradiated to complete the blocking voltage test.

Claims

1. A bypass thyristor, comprising, from top to bottom, cathode side aluminum layers (10, 11 and 12), a cathode N+ region (14), a cathode P- region (17), an N-base region (2), an anode P- region (32), an anode P+ region (31) and an anode aluminum layer (30); characterized in that: A groove (13) is provided at the center of the cathode side, a gate P+ region (15) is provided on the surface thereof, a protruding wavy P-base region (16) is provided directly below the gate P+ region, and a high-concentration N+ region (33) is provided on the surface of the anode side directly opposite the wavy P-region.

2. A bypass thyristor according to claim 1, characterized in that: The cathode N+ region (14) has a depth of 10-20 mm and a doping concentration of 5×10 19 ~5×10 20 cm -3 The gate P+ region (15) has a depth of 5 to 10 mm and a doping concentration of 1×10 19 ~5×10 19 cm -3 The cathode P-region (17) has a depth of 80-140 mm and a doping concentration of 1×10 14 ~5×10 16 cm -3 The thickness of the N-base region (2) is 200~500mm, and the doping concentration is 5×10 12 ~1×10 14 cm -3 The depth of the anode P-region (32) is 80-140 mm, and the doping concentration is 1×10 14 ~5×10 16 cm -3 The depth of the anode P+ region (31) is 5-10 mm, and the doping concentration is 1×10 19 ~5×10 19 cm -3 The depth of the groove (13) is 10~30mm, the corrugation height of the wavy P-region (16) directly below the groove is 10~30mm, the depth of the high concentration N+ region (33) is 10~20mm, and the doping concentration is 5×10 19 ~5×10 20 cm -3 .

3. The method for manufacturing a bypass thyristor according to claim 1-2, characterized in that: The following steps are involved: (1) Select the original defect-free, dislocation-free high-resistance zone melt-irradiated single crystal silicon wafer as n - The substrate material of the N-base region (2) has a thickness of 200~500mm and a doping concentration of 5×10 12 ~1×10 14 cm -3 ; (2) Anode surface protection, cathode surface photolithography, selective etching of the silicon wafer to form a gate trench (13) with a depth of 10~30mm; (3) Aluminum impurities are pre-deposited on both sides of the silicon wafer, followed by wet oxygen oxidation and high-temperature diffusion at 1200-1250°C for 20-50 hours to form a cathode P-region (17) and an anode P-region (32). The depths of the cathode P-region (17) and the anode P-region (32) are both 80-140 mm, and the doping concentration is 1×10 14 ~5×10 16 cm -3 ; At this point, a wavy P-region (16) is formed directly below the trench, wherein the corrugation height of the protruding portion of the P-region (16) is equal to the depth of the trench (13); (4) Double-sided photolithography to form N+ diffusion window, double-sided selective pre-deposition of phosphorus, wet oxygen oxidation and high temperature advancement, the conditions are 1100~1250℃, time 3~5h, to form cathode high concentration N+ region (14) and anode high concentration N+ region (33), the depth of each is 10~20mm, the doping concentration is 5×10 19 ~5×10 20 cm -3 ; At this point, a parasitic NPN transistor structure is formed on the anode side; (5) Double-sided photolithography, selective pre-deposition of high-concentration boron, wet oxygen oxidation and high-temperature advancement, conditions are 1100~1250℃, time 3~5h, forming the gate high-concentration P+ region (15) and the anode high-concentration P+ region (31), the depth of which is 5~10mm, and the doping concentration is 1×10 19 ~5×10 19 cm -3 ; (6) Aluminum is evaporated on both sides of the silicon wafer for the first time and reversed to form aluminum layers (10, 12 and 30), followed by a second aluminum evaporation and reversed to form an aluminum layer (11); alloying is then performed, with typical alloying conditions being: temperature 400-500°C, time 0.5-2h; laser cutting is then performed to cut the wafers into wafers with a diameter of 80-130mm; (7) The mesa is shaped and etched to form a double negative angle structure (40) with an angle of 1°~3°, and then coated with glue for protection to form a complete chip. After that, it is irradiated with electrons to complete the blocking voltage test.

Images