Kernel Fusion for Machine Learning

Abstract

Apparatus, systems and techniques for compiling code are described. In at least one embodiment, one or more compilers are used to compile one or more compiled code portions using one or more intermediate representations of one or more code portions.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This is a PCT application and claims priority to U.S. Application No. 16 / 591,306, filed on October 2, 2019, entitled “KERNEL FUSION FOR MACHINE LEARNING”; the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] At least one embodiment is directed to processing resources for performing and facilitating artificial intelligence. For example, at least one embodiment is directed to a processor or computing system for training a neural network according to the various novel techniques described herein. Background Art

[0004] Applications that target a specific processor architecture may have difficulty maximizing performance on a specific device. Hardware providers may provide specialized compute implementations for different device types, but may not wish to expose functions related to those specialized implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various embodiments according to the present disclosure will be described with reference to the accompanying drawings, in which:

[0006] Figure 1 shows a block representation according to at least one embodiment;

[0007] Figure 2 illustrates a computing architecture according to at least one embodiment;

[0008] Figure 3 illustrates a compiler pipeline according to at least one embodiment;

[0009] Figure 4 A compiler architecture according to at least one embodiment is shown;

[0010] Figure 5 A process for compiling a fusion function according to at least one embodiment is shown;

[0011] Fig. 6A Inference and / or training logic according to at least one embodiment is shown;

[0012] Figure 6B Inference and / or training logic according to at least one embodiment is shown;

[0013] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0014] Figure 8A computer system according to at least one embodiment is shown;

[0015] Fig. 9 A computer system according to at least one embodiment is shown;

[0016] Fig.10 A computer system according to at least one embodiment is shown;

[0017] Fig.11 A computer system according to at least one embodiment is shown;

[0018] Fig. 12A A computer system according to at least one embodiment is shown;

[0019] Fig. 12B A computer system according to at least one embodiment is shown;

[0020] Fig. 12C A computer system according to at least one embodiment is shown;

[0021] Fig.12D A computer system according to at least one embodiment is shown;

[0022] Fig.12E and Fig.12F illustrates a shared programming model according to at least one embodiment;

[0023] Fig.13 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0024] Figures 14A-14B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0025] Figures 15A-15B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0026] Fig.16 A computer system according to at least one embodiment is shown;

[0027] Fig.17A illustrates a parallel processor according to at least one embodiment;

[0028] Fig. 17B shows a partition unit according to at least one embodiment;

[0029] Fig. 17C illustrates a processing cluster according to at least one embodiment;

[0030] Fig.17D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0031] Fig.18 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0032] Fig.19 A graphics processor according to at least one embodiment is shown;

[0033] Fig. 20 shows a microarchitecture of a processor according to at least one embodiment;

[0034] Fig.21 A deep learning application processor according to at least one embodiment is shown;

[0035] Fig. 22 An example neuromorphic processor is shown in accordance with at least one embodiment;

[0036] Fig.23 and Fig.24 illustrates at least a portion of a graphics processor according to at least one embodiment;

[0037] Fig.25 illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0038] Figures 26A-26B illustrates at least a portion of a graphics processor core according to at least one embodiment;

[0039] Fig. 27 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0040] Fig.28 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0041] Fig.29 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment; and

[0042] Fig.30 A streaming multiprocessor in accordance with at least one embodiment is shown. DETAILED DESCRIPTION

[0043] In at least one embodiment, separate compilation can be performed for compute intensive kernels, convolutions, or matrices. In at least one embodiment, separate compilation can involve processing kernels, such as kernels for a graphics processing unit (GPU) for just-in-time kernel fusion. In at least one embodiment, active components can be used to fuse GPU kernels that are separately compiled and distributed in a low-level portable representation.

[0044] In at least one embodiment, the programmer may have implemented one or more computations in a high-level programming language, such as C++ or CUDA C++ from NVIDIA. In at least one embodiment, these computations may have explicitly configured callbacks at key stages of a matrix product or convolution kernel. In at least one embodiment, such callbacks may have explicitly defined function signatures and semantics. In at least one embodiment, the high-level representation may be compiled using various stages of a compilation stack to compile into an intermediate representation, which may then be distributed in a library as bitcode. In at least one embodiment, compilation may be performed from a representation such as CUDA to an NVVM intermediate representation (IR), and the resulting NVVM bitcode is distributed in a library. In at least one embodiment, the call site may remain explicitly represented, such as by using the NVVM function call syntax.

[0045] In at least one embodiment, while the application is running, the active component may expose an application programming interface (API) where the client application may provide function objects for some or all callbacks.

[0046] In at least one embodiment, this may include one or more CUDA device function objects. In at least one embodiment, these source representations may be compiled by an active component with a just-in-time compiler, producing an intermediate representation, such as NVVMIR, or an intermediate representation generated by a separate compilation or program. In at least one embodiment, the active component may perform a compiler inline pass to insert these functions at the appropriate call sites within the containing kernel. In at least one embodiment, once inlined, interprocedural optimizations may be performed, followed by a just-in-time code generation pass. In at least one embodiment, such optimizations and code generation may produce a complete GPU binary. In at least one embodiment, inlining and optimizations may occur before register allocation and final instruction scheduling, so that the kernel fused by the active component has zero additional overhead.

[0047] In at least one embodiment, after the compute kernel and one or more operators defined by the application have been inlined and optimized by the active component, the resulting low-level intermediate representation can be cached or compiled to native machine code and then cached. In at least one embodiment, this mechanism can facilitate a two-stage deployment strategy, where operators are first fused and performance is tuned. In at least one embodiment, the invariant representation is deployed for execution in the second stage. In at least one embodiment, this capability can be exploited with deep learning software libraries to avoid long overhead and can be used in safety-critical environments where fused kernels require safety certification.

[0048] In at least one embodiment, kernel fusion is partially performed to obtain improved performance for applications for various accelerator processor architectures. In at least one embodiment, separate compilation can be used to avoid defining functions behind dedicated hooks in implementations generated for specific types of devices. In at least one embodiment, performance advantages can be obtained by combining operations with compute-limited workloads (such as matrix multiplication or convolution kernels), which can help expand functions in an application-specific manner or improve performance by exploiting locality. In at least one embodiment, if a matrix multiplication computes a result, the corresponding data resides on the chip, and another operation can use the data without having to extract the data from device memory.

[0049] In at least one embodiment, the matrix multiplication convolution kernel can be partially compiled and then fused with a lower level representation of the function provided by the user or application. In at least one embodiment, this can then be compiled with a specialized compiler tool chain. In at least one embodiment, the user or application will not receive a high-level form of the matrix multiplication, or directly access a specialized compiler. In at least one embodiment, the user will still be able to fuse their operations with the vendor-provided implementation and achieve optimal performance.

[0050] In at least one embodiment, the implementation of compute-bound workloads may assume that the input will be divided into tiles and extracted or streamed into the chip or device in units of entire tiles. In at least one embodiment, a representation of tiles may be utilized, such as Figure 1 As shown in the example map view 100 of . In at least one embodiment, an abstraction layer can be used between frameworks to generate runtime kernels. In at least one embodiment, this includes a set of input feature maps 102, which can be used to build other layers of feature maps, such as a layer of intermediate feature maps 104 and an output feature map 106. In at least one embodiment, each map can be composed of a set of tiles, and overlapping tile portions correspond to overlapping calculations. In at least one embodiment, for the output feature map, each tile can correspond to an output pixel value. In at least one embodiment, a graph of tensor operations can be represented and compiler algorithms can be applied for optimization. In at least one embodiment, kernels can be constructed as well as specialized general matrix multiplication (GEMM) and convolution variants. In at least one embodiment, for kernel fusion, element-by-element operations can be fused with GEMMs, convolutions, and reductions, and consecutive convolution operations can also be fused. In at least one embodiment, a rich interface can be provided between the framework and the code generator. In at least one embodiment, the data flow can have several points where it is feasible to combine other operations without affecting the inner loop that performs the corresponding mathematical calculations.

[0051] In at least one embodiment, a computational compilation architecture 202 may be used, such as Figure 2 200. In at least one embodiment, the architecture may include a compute front end 206 that may pass input to a compiler optimization module 208, which in at least some embodiments may provide an optimization and analysis pass. In at least one embodiment, the optimization may utilize information from one or more device libraries 204 for a target type of device. In at least one embodiment, one or more compute reductions and optimizations may be applied 210 to provide functions such as vectorization. In at least one embodiment, the architecture may utilize DCI reduction 212 and one or more libraries, such as may include an engine library 214 and an ELF library 216.

[0052] In at least one embodiment, a unified intermediate representation may be used, which may include, for example, a unified NVVMIR. In at least one embodiment, such a unified intermediate representation may utilize enhancements to the ORI, such as register allocation, optimization instructions, and instruction scheduling. In at least one embodiment, this approach may also provide improved compiler intrinsics that are capable of providing support for new types of instructions. In at least one embodiment, a deep learning template library that can provide reusable abstractions as C++ templates may be used. In at least one embodiment, template parameters may include tile size, input type, accumulation type, and mathematical operations. In at least one embodiment, orthogonal components may be decoupled where possible. In at least one embodiment, optimized instructions and special functions may be represented as intrinsics and code generator channels. In at least one embodiment, binary deployment may be performed through a static library, an API into a compiled template instance, or source code may be deployed as a header-only library.

[0053] In at least one embodiment, compiler pipeline 300 may be used, such as Figure 3 As shown. In at least one embodiment, the mixed mode input file 302 is provided to the computing platform front end 304. In at least one embodiment, the front end 304 can pass the host IR 306 and the device IR 308, wherein the device IR 308 can be processed using the device code generator 310. In at least one embodiment, the device code generator includes an IR optimizer 312 and a code generator 314. In at least one embodiment, the device code generator 310 produces PTX, ELF, and LLVM-IR, which are packaged into a fat binary 316. In at least one embodiment, the fat binary 316 is provided to the host compiler 320 together with the code from the host code generator 318, and the host compiler 320 can compile the code into a single output object.

[0054] In at least one embodiment, a procedural code generation method can be used that can force the construction of IR objects for functions, tiles, and instructions. In at least one embodiment, this can be parameterized on tile size, data type, and mathematical operations. In at least one embodiment, the deployment strategy can be to embed procedural code generators, IR code caches, binaries, and JITs, and provide a compilation manager component to invoke code generation. In at least one embodiment, this approach can be flexible because any IR code sequence can be explicitly constructed. In at least one embodiment, compile time is advantageous because there is no code parsing or template specialization. In at least one embodiment, the code is not exposed to the user because the user only receives the binary that builds the program.

[0055] In at least one embodiment, a user may attempt to combine operations with matrix multiplication. In at least one embodiment, matrix multiplication has a very regular structured data access pattern. In at least one embodiment, hardware vendors may leave hooks in the code that are opportunities to inject and compile custom functions. In at least one embodiment, the compiler toolchain may compile this workload into an intermediate representation, such as LVM-IR. In at least one embodiment, these hooks or fusion sites may be retained in the intermediate representation as device function calls. In at least one embodiment, application programmers may define functions based at least in part on the possible semantics of each of these hooks, and the compiler may compile their functions into an intermediate representation, inline them at the call site, within the compute-constrained workload, and apply specialized compiler variants to generate the final reduced machine code. In at least one embodiment, the types of operations to be included may depend at least in part on the corresponding application and use case.

[0056] In at least one embodiment, a platform 400 including a hybrid IR build may be used, e.g. Figure 4 . In at least one embodiment, a programmer has written an implementation of a basic convolution with hooks, as represented by a static kernel 402 to be compiled by a language-appropriate compiler 404. In at least one embodiment, a program code generator 408 or other application program interface can compile user-provided functions to be fused with the kernel. In at least one embodiment, a compilation manager 416 can assist in the compilation, which can include various instances of compiled code 406 to be fused. In at least one embodiment, a conversion and optimization module 412 can be used together with a code generator module 414 as discussed herein to generate a final compiled binary or reduced machine code for execution. In at least one embodiment, this compilation architecture can run within a low-level deep learning framework, such as TensorRT from NVIDIA, where most of the functions can be executed on one or more GPUs.

[0057] In at least one embodiment, one or more application-provided functions may be fused with an encoded implementation of one or more compute-constrained workloads. In at least one embodiment, such fusion may provide performance and energy improvements relative to separate executions. In at least one embodiment, an architecture may utilize specialized compiler behaviors where publicly compiling an entire application is not feasible. In at least one embodiment, such an architecture may enable hardware vendors to combine sensitive IP or proprietary functions with user-provided functions without exposing the proprietary functions. In at least one embodiment, such fusion may also reduce the overall code size of the functions.

[0058] In at least one embodiment, the Figure 5 500 of the compilation process shown. In at least one embodiment, one or more function objects are received 502 through an API while the application is running. In at least one embodiment, these function objects are provided by or for the application. In at least one embodiment, each function object is compiled 504 to obtain an intermediate representation. In at least one embodiment, an intermediate or partially compiled representation of a computationally limited operation is obtained 506, such as a convolution kernel. In at least one embodiment, an inline pass is performed 508 to insert one or more compiled functions at one or more call locations corresponding to hooks in the partially compiled kernel. In at least one embodiment, one or more optimizations are performed. In at least one embodiment, a final compilation is performed 512 to generate an output, which can take the form of a final executable code.

[0059] Reasoning and training logic

[0060] Fig. 6A Inference and / or training logic 615 is shown for performing reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0061] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 601 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 601 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, the code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, the code and / or data storage 601 stores input / output data during training and / or inference using aspects of one or more embodiments and / or weight parameters during forward propagation of each layer of a neural network trained or used in conjunction with one or more embodiments. In at least one embodiment, any portion of code and / or data storage 601 may be included within other on-chip or off-chip data storage, including a processor's L1, L2, or L3 cache or system memory.

[0062] In at least one embodiment, any portion of code and / or data storage 601 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 601 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 601 is internal or external to a processor, e.g., or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available storage space on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0063] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, code and / or data storage 605 for storing reverse and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, the code and / or data storage 605 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during back propagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 615 may include or be coupled to code and / or data storage 605 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, which includes integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into a processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, any portion of code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 605 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 605 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 605 is internal or external to the processor, for example, whether it is composed of DRAM, SRAM, flash memory, or some other storage type, depends on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0064] In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be separate storage structures. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be the same storage structure. In at least one embodiment, code and / or data storage 601 and code and / or data storage 605 may be partially the same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and / or data storage 601 and code and / or data storage 605 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0065] In at least one embodiment, the inference and / or training logic 615 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 610 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 620, which is a function of input / output and / or weight parameter data stored in code and / or data storage 601 and / or code and / or data storage 605. In at least one embodiment, activations stored in activation storage 620 are generated in response to executing instructions or other code based on linear algebra and / or matrix-based mathematics performed by ALU 610, with weight values ​​stored in code and / or data store 605 and / or in code and / or data store 601 used as operands, as well as other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 605 or code and / or data store 601 or other on-chip or off-chip storage.

[0066] In at least one embodiment, one or more ALUs 610 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 610 may be outside a processor or other hardware logic device or circuit that uses them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 610 may be included within an execution unit of a processor, or otherwise included in an ALU bank accessible by an execution unit of a processor, which may be within the same processor or distributed between different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed function unit, etc.). In at least one embodiment, code and / or data storage 601, code and / or data storage 605, and activation storage 620 may be on the same processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 620 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to a processor or other hardware logic or circuitry and may be retrieved and / or processed using the processor's fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0067] In at least one embodiment, activation storage 620 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, activation storage 620 may be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, activation storage 620 may be internal or external to the processor, for example, or include DRAM, SRAM, flash memory, or other storage types, based on available storage on-chip versus off-chip, latency requirements for performing training and / or inference functions, batch sizes of data used in inferring and / or training neural networks, or some combination of these factors. In at least one embodiment, Fig. 6A The inference and / or training logic 615 shown in FIG. 6 may be used in conjunction with an application specific integrated circuit (“ASIC”), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Fig. 6A The illustrated inference and / or training logic 615 may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0068] Figure 6B Inference and / or training logic 615 is shown in accordance with at least one embodiment. In at least one embodiment, the reasoning and / or training logic 615 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 6B The inference and / or training logic 615 shown in FIG. 6 can be used in conjunction with an application specific integrated circuit (ASIC), such as the ASIC from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU) from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 6BThe reasoning and / or training logic 615 shown in can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field programmable gate array (FPGA)). In at least one embodiment, the reasoning and / or training logic 615 includes, but is not limited to, code and / or data storage 601 and code and / or data storage 605, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 6B In at least one embodiment shown in , each of code and / or data storage 601 and code and / or data storage 605 is associated with a dedicated computing resource (e.g., computing hardware 602 and computing hardware 606). In at least one embodiment, each of computing hardware 602 and computing hardware 606 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) solely on the information stored in code and / or data storage 601 and code and / or data storage 605, respectively, and the results of performing the functions are stored in activation storage 620.

[0069] In at least one embodiment, each of the code and / or data stores 601 and 605 and the corresponding computing hardware 602 and 606 corresponds to a different layer of the neural network, such that activations from one "storage / compute pair 601 / 602" of the code and / or data store 601 and computing hardware 602 are provided as inputs to the next "storage / compute pair 605 / 606" of the code and / or data store 605 and computing hardware 606, so as to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / compute pair 601 / 602 and 605 / 606 can correspond to more than one neural network layer. In at least one embodiment, additional storage / compute pairs (not shown) can be included in the inference and / or training logic 615 after or in parallel with the storage / compute pairs 601 / 602 and 605 / 606.

[0070] Data Center

[0071] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0072] In at least one embodiment, Figure 7As shown, the data center infrastructure layer 710 may include a resource coordinator 712, group computing resources 714, and node computing resources ("node CRs") 716 (1)-716 (N), where "N" represents a positive integer. In at least one embodiment, the node CRs 716 (1)-716 (N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716 (1)-716 (N) may be a server having one or more of the above computing resources.

[0073] In at least one embodiment, the grouped computing resources 714 may include a separate grouping (not shown) of node CRs housed in one or more racks, or many racks (also not shown) housed in data centers at various geographic locations. The separate grouping of node CRs within the grouped computing resources 714 may include computing, networks, memory, or storage resources that can be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs including a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0074] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may include a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may include hardware, software, or some combination thereof.

[0075] In at least one embodiment, Figure 7As shown, the framework layer 720 includes a job scheduler 722, a configuration manager 724, a resource manager 726, and a distributed file system 728. In at least one embodiment, the framework layer 720 may include a framework that supports software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include a web-based service software or application, such as a service or application provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software network application framework, such as Apache SparkTM (hereinafter referred to as "Spark") that can utilize the distributed file system 728 for large-scale data processing (e.g., "big data"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by various layers of the data center 700. In at least one embodiment, the configuration manager 724 may be able to configure different layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 728 for supporting large-scale data processing. In at least one embodiment, the resource manager 726 can manage clustered or grouped computing resources mapped to or allocated to support the distributed file system 728 and the job scheduler 722. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 726 can coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0076] In at least one embodiment, software 732 included in software layer 730 may include software used by at least a portion of node CRs 716(1)-716(N), grouped computing resources 714, and / or distributed file system 728 of framework layer 720. One or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0077] In at least one embodiment, one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 728 of the framework layer 720. The one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0078] In at least one embodiment, any of the configuration manager 724, resource manager 726, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data acquired in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of the data center 700 from making potentially bad configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0079] In at least one embodiment, the data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to the data center 700. In at least one embodiment, by using weight parameters calculated by one or more training techniques described herein, information may be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to the data center 700.

[0080] In at least one embodiment, the data center can use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0081] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BProvide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 7 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case described herein.

[0082] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0083] Computer Systems

[0084] Figure 8 800 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to the present disclosure, such as the embodiments described herein, the computer system 800 may include, but is not limited to, components, such as a processor 802, whose execution unit includes logic to execute algorithms for processing data. In at least one embodiment, the computer system 800 may include a processor, such as a processor available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 800 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0085] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (Internet Protocol) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0086] In at least one embodiment, the computer system 800 may include, but is not limited to, a processor 802, which may include, but is not limited to, one or more execution units 808 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the computer system 800 is a single-processor desktop or server system, but in another embodiment, the computer system 800 may be a multi-processor system. In at least one embodiment, the processor 802 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements an instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 802 may be coupled to a processor bus 810, which may transmit data signals between the processor 802 and other components in the computer system 800.

[0087] In at least one embodiment, processor 802 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 804. In at least one embodiment, processor 802 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 802. Other embodiments may also include a combination of internal and external caches, depending on the particular implementation and needs. In at least one embodiment, register file 806 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and instruction pointer registers.

[0088] In at least one embodiment, an execution unit 808, including but not limited to logic to perform integer and floating point operations, is also located in the processor 802. In at least one embodiment, the processor 802 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 808 may include logic for processing a packed instruction set 809. In at least one embodiment, by including the packed instruction set 809 in the instruction set of a general-purpose processor, and the associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 802. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on packed data, which may not require the transfer of smaller units of data on the processor's data bus to perform one or more operations one data element at a time.

[0089] In at least one embodiment, execution unit 808 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 800 may include, but is not limited to, memory 820. In at least one embodiment, memory 820 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other memory device. In at least one embodiment, memory 820 may store instructions 819 and / or data 821 represented by data signals that may be executed by processor 802.

[0090] In at least one embodiment, the system logic chip can be coupled to the processor bus 810 and the memory 820. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 816, and the processor 802 can communicate with the MCH 816 via the processor bus 810. In at least one embodiment, the MCH 816 can provide a high-bandwidth memory path 818 to the memory 820 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 816 can initiate data signals between the processor 802, the memory 820, and other components in the computer system 800, and bridge data signals between the processor bus 810, the memory 820, and the system I / O interface 822. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 816 can be coupled to the memory 820 via a high-bandwidth memory path 818, and the graphics / video card 812 can be coupled to the MCH 816 via an Accelerated Graphics Port ("AGP") interconnect 814.

[0091] In at least one embodiment, the computer system 800 may use a system I / O interface 822, which is a proprietary hub interface bus that couples the MCH 816 to an I / O controller hub ("ICH") 830. In at least one embodiment, the ICH 830 may provide direct connection to certain I / O devices through a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 820, the chipset, and the processor 802. Examples may include, but are not limited to, an audio controller 829, a firmware hub ("Flash BIOS") 828, a wireless transceiver 826, a data store 824, a traditional I / O controller 823 including a user input and keyboard interface 825, a serial expansion port 827 (e.g., a universal serial bus (USB)), and a network controller 834. The data store 824 may include a hard drive, a floppy drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0092] In at least one embodiment, Figure 8 A system comprising interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 8 An exemplary system on chip (SoC) may be shown. In at least one embodiment, Figure 8The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 800 are interconnected using a Compute Express Link (CXL) interconnect.

[0093] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Figure 8 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case described herein.

[0094] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0095] Fig. 9 is a block diagram illustrating an electronic device 900 for utilizing a processor 910 according to at least one embodiment. In at least one embodiment, the electronic device 900 may be, for example but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0096] In at least one embodiment, system 900 may include, but is not limited to, a processor 910 communicatively coupled to any suitable number or variety of components, peripherals, modules, or devices. In at least one embodiment, processor 910 is coupled using a bus or interface, such as an I 2 C bus, system management bus ("SMBus"), low pin count (LPC) bus, serial peripheral interface ("SPI"), high-definition audio ("HDA") bus, serial advanced technology attachment ("SATA") bus, universal serial bus ("USB") (version 1, 2, 3, etc.), or universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Fig. 9 A system is shown that includes interconnected hardware devices or "chips", while in other embodiments, Fig. 9 An exemplary system on chip (SoC) may be shown. In at least one embodiment, Fig. 9 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, Fig. 9 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0097] In at least one embodiment, Fig. 9 The display 924, touch screen 925, touch pad 930, near field communication unit ("NFC") 945, sensor hub 940, thermal sensor 946, fast chipset ("EC") 935, trusted platform module ("TPM") 938, BIOS / firmware / flash memory ("BIOS, FW Flash") 922, DSP 960, drive 920 (e.g., solid state disk ("SSD") or hard disk drive ("HDD")), wireless local area network unit ("WLAN") 950, Bluetooth unit 952, wireless wide area network unit ("WWAN") 956, global positioning system (GPS) 955, camera ("USB 3.0 camera") 954 (e.g., USB 3.0 camera) and / or low power double data rate ("LPDDR") memory unit ("LPDDR3") 915 implemented in, for example, the LPDDR3 standard may be included. Each of these components may be implemented in any suitable manner.

[0098] In at least one embodiment, other components may be communicatively coupled to the processor 910 through the components described herein. In at least one embodiment, the accelerometer 941, ambient light sensor ("ALS") 942, compass 943, and gyroscope 944 may be communicatively coupled to the sensor hub 940. In at least one embodiment, the thermal sensor 939, fan 937, keyboard 936, and touchpad 930 may be communicatively coupled to the EC 935. In at least one embodiment, the speaker 963, earphone 964, and microphone ("mic") 965 may be communicatively coupled to the audio unit ("audio codec and class D amplifier") 962, which in turn may be communicatively coupled to the DSP 960. In at least one embodiment, the audio unit 962 may include, for example, but not limited to, an audio encoder / decoder ("codec") and a class D amplifier. In at least one embodiment, the SIM card ("SIM") 957 may be communicatively coupled to the WWAN unit 956. In at least one embodiment, components such as the WLAN unit 950 and the Bluetooth unit 952 and the WWAN unit 956 may be implemented as a next generation form factor (NGFF).

[0099] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig. 9for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case described herein.

[0100] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0101] Fig.10 A computer system 1000 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1000 is configured to implement the various processes and methods described throughout this disclosure.

[0102] In at least one embodiment, computer system 1000 includes, but is not limited to, at least one central processing unit ("CPU") 1002 connected to a communication bus 1010 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1000 includes, but is not limited to, main memory 1004 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1004 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1022 provides an interface to other computing devices and networks for receiving data from computer system 1000 and transmitting data to other systems.

[0103] In at least one embodiment, computer system 1000 includes, but is not limited to, input device 1008, parallel processing system 1012, and display device 1006, which may be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1008 (such as a keyboard, mouse, touch pad, microphone, etc.). In at least one embodiment, each of the foregoing modules may be located on a single semiconductor platform to form a processing system.

[0104] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Provide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig.10for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case described herein.

[0105] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0106] Fig.11 A computer system 1100 according to at least one embodiment is shown. In at least one embodiment, the computer system 1100 includes, but is not limited to, a computer 1110 and a USB disk 1120. In at least one embodiment, the computer 1110 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, the computer 1110 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0107] In at least one embodiment, the USB disk 1120 includes, but is not limited to, a processing unit 1130, a USB interface 1140, and a USB interface logic 1150. In at least one embodiment, the processing unit 1130 may be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 1130 may include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1130 includes an application specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1130 is a tensor processing unit ("TPC") that is optimized to perform machine learning reasoning operations. In at least one embodiment, the processing core 1130 is a visual processing unit ("VPU") that is optimized to perform machine vision and machine learning reasoning operations.

[0108] In at least one embodiment, USB interface 1140 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1140 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1140 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1150 can include any number and type of logic that enables processing unit 1130 to connect to a device (e.g., computer 1110) via USB connector 1140.

[0109] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BProvide details about the reasoning and / or training logic 615. In at least one embodiment, the reasoning and / or training logic 615 may be Fig.11 for use in a system for inference or prediction operations based at least in part on weight parameters computed using a neural network training operation, a neural network function and / or architecture, or a neural network use case described herein.

[0110] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0111] Fig. 12A An exemplary architecture is shown in which multiple GPUs 1210-1213 are communicatively coupled to multiple multi-core processors 1205-1206 via high-speed links 1240-1243 (e.g., bus / point-to-point interconnect, etc.). In one embodiment, the high-speed links 1240-1243 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughput. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0112] Furthermore, in one embodiment, two or more GPUs 1210-1213 are interconnected via high-speed links 1229-1230, which may be implemented using the same or different protocols / links as used for high-speed links 1240-1243. Similarly, two or more multi-core processors 1205-1206 may be connected via high-speed link 1228, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect fabric) may be used to accomplish Fig. 12A All communications between the various system components shown in .

[0113] In one embodiment, each multi-core processor 1205-1206 is communicatively coupled to processor memory 1201-1202 via memory interconnects 1226-1227, respectively, and each GPU 1210-1213 is communicatively coupled to GPU memory 1220-1223 via GPU memory interconnects 1250-1253, respectively. Memory interconnects 1226-1227 and 1250-1253 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1201-1202 and GPU memory 1220-1223 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1201-1202 may be volatile memory while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0114] As described below, although the various processors 1205-1206 and GPUs 1210-1213 may be physically coupled to specific memories 1201-1202, 1220-1223, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed among the various physical memories. For example, the processor memories 1201-1202 may each contain 64GB of system memory address space, and the GPU memories 1220-1223 may each contain 32GB of system memory address space (resulting in a total of 256GB of addressable memory in this example).

[0115] Fig. 12B Additional details for the interconnection between the multi-core processor 1207 and the graphics acceleration module 1246 are shown according to an exemplary embodiment. The graphics acceleration module 1246 may include one or more GPU chips integrated on a line card that is coupled to the processor 1207 via a high-speed link 1240. Alternatively, the graphics acceleration module 1246 may be integrated on the same package or chip with the processor 1207.

[0116] In at least one embodiment, the processor 1207 shown includes a plurality of cores 1260A-1260D, each core having a translation lookaside buffer 1261A-1261D and one or more caches 1262A-1262D. In at least one embodiment, the cores 1260A-1260D may include various other components not shown for executing instructions and processing data. The caches 1262A-1262D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1256 may be included in the caches 1262A-1262D and shared by each group of cores 1260A-1260D. For example, one embodiment of the processor 1207 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1207 and the graphics acceleration module 1246 are connected to the system memory 1214, which may include Fig. 12A Processor memory 1201-1202 in.

[0117] Coherence is maintained for data and instructions stored in the various caches 1262A-1262D, 1256 and the system memory 1214 via inter-core communications over the coherence bus 1264. In at least one embodiment, for example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1264 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1264 to snoop cache accesses.

[0118] In at least one embodiment, the proxy circuit 1225 communicatively couples the graphics acceleration module 1246 to the coherence bus 1264, thereby allowing the graphics acceleration module 1246 to participate in a cache coherence protocol as a peer of the cores 1260A-1260D. In particular, in at least one embodiment, the interface 1235 provides a connection to the proxy circuit 1225 via a high-speed link 1240 (e.g., a PCIe bus, NVLink, etc.), and the interface 1237 connects the graphics acceleration module 1246 to the link 1240.

[0119] In one implementation, the accelerator integrated circuit 1236 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 1231, 1232, N of the graphics acceleration module 1246. In at least one embodiment, the graphics processing engines 1231, 1232, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1231, 1232, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1246 may be a GPU having multiple graphics processing engines 1231-1232, N, or the graphics processing engines 1231-1232, N may be individual GPUs integrated on a common package, line card, or chip.

[0120] In one embodiment, the accelerator integrated circuit 1236 includes a memory management unit (MMU) 1239 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation), and also includes a memory access protocol for accessing the system memory 1214. The MMU 1239 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 1238 stores commands and data for efficient access by the graphics processing engines 1231-1232, N. In one implementation, the data stored in the cache 1238 and the graphics memory 1233-1234, M, is kept consistent with the core caches 1262A-1262D, 1256 and the system memory 1214. As previously described, this task may be accomplished via proxy circuitry 1225 acting on behalf of cache 1238 and graphics memory 1233-1234, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1262A-1262D, 1256 to cache 1238 and receiving updates from cache 1238).

[0121] In at least one embodiment, a set of registers 1245 stores context data for threads executed by the graphics processing engines 1231-1232, N, and context management circuitry 1248 manages thread contexts. For example, context management circuitry 1248 may perform save and restore operations to save and restore contexts for various threads during context switches (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1248 may store current register values ​​to a specified area in memory (e.g., identified by a context pointer) upon context switching. The register values ​​may then be restored when returning to context. In one embodiment, interrupt management circuitry 1247 receives and processes interrupts received from system devices.

[0122] In one implementation, the MMU 1239 converts virtual / effective addresses from the graphics processing engine 1231 to real / physical addresses in the system memory 1214. In at least one embodiment, the accelerator integrated circuit 1236 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1246 and / or other accelerator devices. The graphics accelerator module 1246 can be dedicated to a single application executed on the processor 1207, or can be shared between multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1231-1232, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with VMs and / or applications.

[0123] In at least one embodiment, the accelerator integrated circuit 1236 performs as a bridge to the system of graphics acceleration modules 1246 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 1236 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engines 1231-1232, N.

[0124] Since the hardware resources of the graphics processing engines 1231-1232, N are explicitly mapped to the real address space seen by the host processor 1207, any host processor can directly address these resources using effective address values. One function of the accelerator integrated circuit 1236 is to physically separate the graphics processing engines 1231-1232, N so that they appear to the system as independent units.

[0125] In at least one embodiment, one or more graphics memories 1233-1234, M are respectively coupled to each graphics processing engine 1231-1232, N. Graphics memories 1233-1234, M store instructions and data, which are processed by each graphics processing engine 1231-1232, N. In at least one embodiment, graphics memory 1233-1234, M may be a volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be a non-volatile memory, such as 3D XPoint or Nano-Ram.

[0126] In one embodiment, to reduce data traffic on link 1240, a biasing technique is used to ensure that the data stored in graphics memory 1233-1234, M is the data most frequently used by graphics processing engines 1231-1232, N, and preferably not used (at least not frequently) by cores 1260A-1260D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 1231-1232, N) in the core's cache 1262A-1262D, 1256 and system memory 1214.

[0127] Fig. 12C Another exemplary embodiment is shown in which an accelerator integrated circuit 1236 is integrated into the processor 1207. In this embodiment, the graphics processing engines 1231-1232, N communicate directly with the accelerator integrated circuit 1236 via the interface 1237 and the interface 1235 (which may also utilize any form of bus or interface protocol) through the high-speed link 1240. The accelerator integrated circuit 1236 can perform operations related to Fig. 12B The same operations as described above. However, due to its close proximity to the coherence bus 1264 and caches 1262A-1262D, 1256, it may have a higher throughput. At least one embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1236 and a programming model controlled by the graphics acceleration module 1246.

[0128] In at least one embodiment, the graphics processing engines 1231-1232, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to the graphics processing engines 1231-1232, N, thereby providing virtualization within a VM / partition.

[0129] In at least one embodiment, graphics processing engines 1231-1232, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can use a system hypervisor to virtualize graphics processing engines 1231-1232, N to allow each operating system to access. For a single partition system without a hypervisor, the operating system owns graphics processing engines 1231-1232, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1231-1232, N to provide access to each process or application.

[0130] In at least one embodiment, the graphics acceleration module 1246 or the individual graphics processing engines 1231-1232, N use a process handle to select a process element. In at least one embodiment, the process elements are stored in the system memory 1214 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1231-1232, N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0131] Fig.12D An exemplary accelerator integrated slice 1290 is shown. As used herein, a "slice" includes a specified portion of the processing resources of the accelerator integrated circuit 1236. The application effective address space 1282 in the system memory 1214 stores process elements 1283. In one embodiment, the process element 1283 is stored in response to a GPU call 1281 from an application 1280 executed on the processor 1207. The process element 1283 contains the process state of the corresponding application 1280. The work descriptor (WD) 1284 contained in the process element 1283 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, the WD 1284 is a pointer to a job request queue in the address space 1282 of the application.

[0132] Graphics acceleration module 1246 and / or each graphics processing engine 1231-1232, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1284 to graphics acceleration module 1246 to start a job in a virtualized environment can be included.

[0133] In at least one embodiment, the dedicated process programming model is implementation specific. In this model, a single process owns a graphics acceleration module 1246 or an individual graphics processing engine 1231. When the graphics acceleration module 1246 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1236 for the owned partition, and when the graphics acceleration module 1246 is assigned, the operating system initializes the accelerator integrated circuit 1236 for the owned process.

[0134] In operation, the WD acquisition unit 1291 in the accelerator integrated slice 1290 acquires the next WD 1284, which includes an indication of the work to be completed by one or more graphics processing engines of the graphics acceleration module 1246. The data from the WD 1284 can be stored in the register 1245 and used by the MMU 1239, the interrupt management circuit 1247 and / or the context management circuit 1248, as shown. For example, one embodiment of the MMU 1239 includes a segment / page roaming circuit for accessing the segment / page table 1286 within the OS virtual address space 1285. The interrupt management circuit 1247 can process the interrupt event 1292 received from the graphics acceleration module 1246. When performing graphics operations, the effective address 1293 generated by the graphics processing engine 1231-1232, N is converted into a real address by the MMU 1239.

[0135] In one embodiment, the same set of registers 1245 is replicated for each graphics processing engine 1231-1232, N and / or graphics acceleration module 1246, and the registers 1245 can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 1290. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0136]

[0137]

[0138] Example registers that may be initialized by the operating system are shown in Table 2.

[0139]

[0140] In at least one embodiment, each WD 1284 is specific to a particular graphics acceleration module 1246 and / or graphics processing engine 1231-1232, N. It contains all the information needed by the graphics processing engine 1231-1232, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0141] Fig.12EAdditional details of an exemplary embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 1298 in which a process element list 1299 is stored. The hypervisor real address space 1298 can be accessed via a hypervisor 1296 that virtualizes a graphics acceleration module engine for an operating system 1295.

[0142] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1246. There are two programming models where the graphics acceleration module 1246 is shared by multiple processes and partitions, namely, time-sliced ​​sharing and graphics-directed sharing.

[0143] In at least one embodiment, in this model, the hypervisor 1296 owns the graphics acceleration module 1246 and makes its functionality available to all operating systems 1295. For the graphics acceleration module 1246 to support virtualization through the hypervisor 1296, the graphics acceleration module 1246 may comply with the following requirements: 1) the application's job request must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1246 must provide a context save and restore mechanism, 2) the graphics acceleration module 1246 guarantees that the application's job request is completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1246 provides the ability to preempt job processing, and 3) fairness between the graphics acceleration module 1246 processes must be ensured when operating in a directed shared programming model.

[0144] In at least one embodiment, the application 1280 is required to make an operating system 1295 system call using a graphics acceleration module 1246 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1246 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1246 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1246 and can take the form of a graphics acceleration module 1246 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1246. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. If the implementation of the accelerator integrated circuit 1236 and the graphics acceleration module 1246 does not support the user authority mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. The hypervisor 1296 may selectively apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 1283. In at least one embodiment, the CSRP is one of the registers 1245 that contains the effective address of an area in the application's effective address space 1282 for the graphics acceleration module 1246 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area may be fixed system memory.

[0145] Upon receiving the system call, the operating system 1295 may verify that the application 1280 has been registered and granted permission to use the graphics acceleration module 1246. The operating system 1295 then calls the hypervisor 1296 using the information shown in Table 3.

[0146]

[0147]

[0148] Upon receiving the hypervisor call, the hypervisor 1296 verifies that the operating system 1295 has registered and been granted permission to use the graphics acceleration module 1246. The hypervisor 1296 then places the process element 1283 into a linked list of process elements of the corresponding graphics acceleration module 1246 type. The process element may include the information shown in Table 4.

[0149]

[0150] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1290 registers 1245 .

[0151] like Fig.12F As shown, in at least one embodiment, a unified memory is used, which can be addressed via a common virtual memory address space for accessing physical processor memories 1201-1202 and GPU memories 1220-1223. In this implementation, operations executed on GPUs 1210-1213 use the same virtual / effective memory address space to access processor memories 1201-1202, and vice versa, thereby simplifying programmability. In one embodiment, the first part of the virtual / effective address space is allocated to processor memory 1201, the second part is allocated to the second processor memory 1202, the third part is allocated to GPU memory 1220, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed in each of processor memories 1201-1202 and GPU memories 1220-1223, thereby allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0152] In one embodiment, bias / coherency management circuits 1294A-1294E within one or more MMUs 1239A-1239E ensure cache coherency between caches of one or more host processors (e.g., 1205) and GPUs 1210-1213 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Fig.12F Multiple instances of bias / consistency management circuits 1294A- 1294E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 1205 and / or within an accelerator integrated circuit 1236 .

[0153] One embodiment allows the GPU-attached memory 1220-1223 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology, but without suffering from the performance defects associated with full system cache coherence. In at least one embodiment, the ability to access the GPU-attached memory 1220-1223 as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows the host processor 1205 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies include driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU-attached memory 1220-1223 without cache coherence overhead may be critical to the execution time of the offloaded calculation. For example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1210-1213. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0154] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in GPUs 1210-1213 (e.g., to cache frequently / recently used entries of the bias table), the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1220-1223. Alternatively, the entire bias table can be maintained within the GPU.

[0155] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU-attached memory 1220-1223 is accessed, resulting in the following operations. First, local requests from GPUs 1210-1213 to find their pages in the GPU bias are forwarded directly to the corresponding GPU memory 1220-1223. Local requests from GPUs to find their pages in the host bias are forwarded to processors 1205 (e.g., via the high-speed link described herein). In one embodiment, the request from processor 1205 to find the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to GPUs 1210-1213. In at least one embodiment, if the GPU is not currently using the page, the GPU can then migrate the page to the host processor bias. In at least one embodiment, the bias state of the page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or in limited cases by a purely hardware-based mechanism.

[0156] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that then calls the GPU's device driver, which then sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1205 bias to GPU bias, but not for the reverse migration.

[0157] In one embodiment, cache coherency is maintained by temporarily rendering GPU biased pages that cannot be cached by host processor 1205. To access these pages, processor 1205 may request access from GPU 1210, which may or may not immediately grant access. Therefore, to reduce communication between processor 1205 and GPU 1210, it is beneficial to ensure that GPU biased pages are pages required by the GPU and not by the host processor 1205, and vice versa.

[0158] Reasoning and / or training logic 615 is used to implement one or more embodiments. Fig. 6A and / or Figure 6B Details regarding the inference and / or training logic 615 are provided.

[0159] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0160] Fig.13An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0161] Fig.13 1 is a block diagram illustrating an exemplary system on a chip integrated circuit 1300 that can be manufactured using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1300 includes one or more application processors 1305 (e.g., CPUs), at least one graphics processor 1310, and may additionally include an image processor 1315 and / or a video processor 1320, any of which may be modular IP cores. In at least one embodiment, the integrated circuit 1300 includes peripheral or bus logic, which includes a USB controller 1325, a UART controller 1330, a SPI / SDIO controller 1335, and an I22S / I22C controller 1340. In at least one embodiment, the integrated circuit 1300 may include a display device 1345 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1350 and a mobile industry processor interface (MIPI) display interface 1355. In at least one embodiment, storage may be provided by a flash subsystem 1360, including flash memory and a flash controller. In at least one embodiment, a memory interface may be provided via a memory controller 1365 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1370 .

[0162] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 1300 to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0163] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0164] Figures 14A-14BAn exemplary integrated circuit and associated graphics processor that can be manufactured using one or more IP cores according to various embodiments described herein are shown. In addition to what is shown, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0165] Figures 14A-14B is a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Fig.14A An exemplary graphics processor 1410 of a system-on-chip integrated circuit that may be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Fig. 14B An additional exemplary graphics processor 1440 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores according to at least one embodiment is shown. In at least one embodiment, Fig.14A The graphics processor 1410 is a low power graphics processor core. In at least one embodiment, Fig. 14B The graphics processor 1440 is a higher performance graphics processor core. In at least one embodiment, each of the graphics processors 1410 and 1440 may be Fig.13 A variant of graphics processor 1310 .

[0166] In at least one embodiment, the graphics processor 1410 includes a vertex processor 1405 and one or more fragment processors 1415A-1415N (e.g., 1415A, 1415B, 1415C, 1415D to 1415N-1 and 1415N). In at least one embodiment, the graphics processor 1410 can execute different shader programs via separate logic, so that the vertex processor 1405 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1415A-1415N perform fragment (e.g., pixel) shading operations for the fragment or pixel shader program. In at least one embodiment, the vertex processor 1405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1415A-1415N use the primitives and vertex data generated by the vertex processor 1405 to generate a frame buffer displayed on a display device. In at least one embodiment, fragment processors 1415A-1415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs as provided in the Direct 3D API.

[0167] In at least one embodiment, graphics processor 1410 additionally includes one or more memory management units (MMUs) 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, one or more MMUs 1420A-1420B provide virtual to physical address mapping for graphics processor 1410 (including for vertex processor 1405 and / or fragment processors 1415A through 1415N), which may reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more caches 1425A-1425B. In at least one embodiment, one or more MMUs 1420A-1420B may be synchronized with other MMUs within the system, including with one or more application processors 1305, image processor 1315, and / or Fig.13 One or more MMUs associated with the video processor 1320 of the SoC, so that each processor 1305-1320 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1430A-1430B enable the graphics processor 1410 to interface with other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0168] In at least one embodiment, graphics processor 1440 includes Fig.14A The graphics processor 1410 includes one or more MMUs 1420A-1420B, one or more caches 1425A-1425B, and one or more circuit interconnects 1430A-1430B. In at least one embodiment, the graphics processor 1440 includes one or more shader cores 1455A-1455N (e.g., 1455A, 1455B, 1455C, 1455D, 1455E, 1455F to 1455N-1 and 1455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, graphics processor 1440 includes an inter-core task manager 1445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1455A-1455N and tiling unit 1458 to accelerate tiling operations for tile-based rendering, in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0169] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in integrated circuit 14A and / or 14B to infer or predict operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0170] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0171] Figures 15A-15B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Fig.15A shows that it can be included in Fig.13 The graphics core 1500 within the graphics processor 1310 of FIG. 10 and, in at least one embodiment, may be as follows: Fig. 14B Unified shader cores 1455A-1455N are shown. Fig. 15B A highly parallel general purpose graphics processing unit 1530 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0172] In at least one embodiment, graphics core 1500 includes a shared instruction cache 1502, texture units 1518, and cache / shared memory 1520 that are common to execution resources within graphics core 1500. In at least one embodiment, graphics core 1500 may include multiple slices 1501A-1501N or partitions of each core, and the graphics processor may include multiple instances of graphics core 1500. Slices 1501A-1501N may include support logic including local instruction caches 1504A-1504N, thread schedulers 1506A-1506N, thread dispatchers 1508A-1508N, and a set of registers 1510A-1510N. In at least one embodiment, slices 1501A-1501N may include a set of additional function units (AFU1512A-1512N), floating point units (FPU 1514A-1514N), integer arithmetic logic units (ALU 1516A-1516N), address calculation units (ACU 1513A-1513N), double precision floating point units (DPFPU 1515A-1515N), and matrix processing units (MPU1517A-1517N).

[0173] In at least one embodiment, the FPU 1514A-1514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1515A-1515N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1516A-1516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1517A-1517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPU 1517-1517N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1512A-1512N can perform additional logical operations that are not supported by the floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0174] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics core 1500 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0175] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0176] Fig. 15BA general purpose processing unit (GPGPU) 1530 in at least one embodiment is shown, which can be configured to enable highly parallel computing operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1530 can be directly linked to other instances of GPGPU 1530 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1530 includes a host interface 1532 to enable connection with a host processor. In at least one embodiment, host interface 1532 is a PCI Express interface. In at least one embodiment, host interface 1532 can be a manufacturer-specific communication interface or communication structure. In at least one embodiment, GPGPU 1530 receives commands from a host processor and uses a global scheduler 1534 to assign execution threads associated with those commands to a group of computing clusters 1536A-1536H. In at least one embodiment, computing clusters 1536A-1536H share cache memory 1538. In at least one embodiment, cache memory 1538 may be used as a higher level cache for cache memory within computing clusters 1536A-1536H.

[0177] In at least one embodiment, GPGPU 1530 includes memory 1544A-1544B coupled to compute clusters 1536A-1536H via a set of memory controllers 1542A-1542B. In at least one embodiment, memory 1544A-1544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0178] In at least one embodiment, computing clusters 1536A-1536H each include a set of graphics cores, such as Fig.15A The graphics core 1500 may include multiple types of integer and floating point logic units that can perform computational operations at various precision ranges of the computer, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating point units in each computing cluster 1536A-1536H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of the floating point units may be configured to perform 64-bit floating point operations.

[0179] In at least one embodiment, multiple instances of GPGPU 1530 can be configured to function as a computing cluster. In at least one embodiment, the communications used by computing clusters 1536A-1536H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1530 communicate through host interface 1532. In at least one embodiment, GPGPU 1530 includes an I / O hub 1539 that couples GPGPU 1530 with GPU link 1540, enabling direct connection to other instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a dedicated GPU to GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1530. In at least one embodiment, GPU link 1540 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1530 are located in separate data processing systems and communicate through network devices accessible through host interface 1532. In at least one embodiment, GPU link 1540 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1532 .

[0180] In at least one embodiment, the GPGPU 1530 may be configured to train a neural network. In at least one embodiment, the GPGPU 1530 may be used within an inference platform. In at least one embodiment, in the case where the GPGPU 1530 is used for inference, the GPGPU 1530 may include fewer computing clusters 1536A-1536H relative to when the GPGPU 1530 is used to train a neural network. In at least one embodiment, the memory technology associated with the memory 1544A-1544B may differ between the inference and training configurations, with higher bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1530 may support inference specific instructions. For example, in at least one embodiment, the inference configuration may provide support for one or more 8-bit integer dot product instructions that may be used during inference operations of a deployed neural network.

[0181] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in GPGPU 1530 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0182] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0183] Fig.16 A block diagram of a computer system 1600 according to at least one embodiment is shown. In at least one embodiment, the computer system 1600 includes a processing subsystem 1601 having one or more processors 1602 and a system memory 1604, which communicates via an interconnect path that may include a memory hub 1605. In at least one embodiment, the memory hub 1605 may be a separate component within a chipset component, or may be integrated within one or more processors 1602. In at least one embodiment, the memory hub 1605 is coupled to an I / O subsystem 1611 via a communication link 1606. In one embodiment, the I / O subsystem 1611 includes an I / O hub 1607, which may enable the computer system 1600 to receive input from one or more input devices 1608. In at least one embodiment, the I / O hub 1607 may enable a display controller, which may be included in one or more processors 1602, to provide output to one or more display devices 1610A. In at least one embodiment, the one or more display devices 1610A coupled to the I / O hub 1607 may include local, internal, or embedded display devices.

[0184] In at least one embodiment, the processing subsystem 1601 includes one or more parallel processors 1612 coupled to the memory hub 1605 via a bus or other communication link 1613. In at least one embodiment, the communication link 1613 can use any of a number of standard-based communication link technologies or protocols, such as but not limited to PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1612 form a parallel or vector processing system in a computational concentration, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1612 form a graphics processing subsystem that can output pixels to one of the one or more display devices 1610A coupled via the I / O hub 1607. In at least one embodiment, the one or more parallel processors 1612 can also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1610B.

[0185] In at least one embodiment, system storage unit 1614 can be connected to I / O hub 1607 to provide a storage mechanism for computer system 1600. In at least one embodiment, I / O switch 1616 can be used to provide an interface mechanism to enable connection between I / O hub 1607 and other components, such as network adapter 1618 and / or wireless network adapter 1619 that can be integrated into the platform, as well as various other devices that can be added through one or more additional devices 1620. In at least one embodiment, network adapter 1618 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1619 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0186] In at least one embodiment, computer system 1600 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1607. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Fig.16 The communication paths between the various components in the NV-Link high-speed interconnect or interconnect protocol.

[0187] In at least one embodiment, one or more parallel processors 1612 include circuits optimized for graphics and video processing, including, for example, video output circuits, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1612 include circuits optimized for general processing. In at least one embodiment, the components of computer system 1600 can be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processors 1612, memory hub 1605, processor 1602, and I / O hub 1607 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1600 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1600 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computer system.

[0188] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding reasoning and / or training logic 615. In at least one embodiment, reasoning and / or training logic 615 can be used in system 1600 to reason or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0189] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0190] processor

[0191] Fig.17A 1700 according to at least one embodiment. In at least one embodiment, the various components of the parallel processor 1700 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1700 shown is a processor according to an exemplary embodiment. Fig.16 A variation of the one or more parallel processors 1612 shown.

[0192] In at least one embodiment, parallel processor 1700 includes parallel processing unit 1702. In at least one embodiment, parallel processing unit 1702 includes I / O unit 1704, which enables communication with other devices, including other instances of parallel processing unit 1702. In at least one embodiment, I / O unit 1704 can be directly connected to other devices. In at least one embodiment, I / O unit 1704 connects with other devices by using a hub or switch interface (e.g., memory hub 1605). In at least one embodiment, the connection between memory hub 1605 and I / O unit 1704 forms communication link 1613. In at least one embodiment, I / O unit 1704 is connected to host interface 1706 and memory crossbar switch 1716, wherein host interface 1706 receives commands for performing processing operations and memory crossbar switch 1716 receives commands for performing memory operations.

[0193] In at least one embodiment, when the host interface 1706 receives the command buffer via the I / O unit 1704, the host interface 1706 can direct the work operations to execute those commands to the front end 1708. In at least one embodiment, the front end 1708 is coupled with a scheduler 1710, which is configured to distribute commands or other work items to the processing cluster array 1712. In at least one embodiment, the scheduler 1710 ensures that the processing cluster array 1712 is properly configured and in a valid state before assigning tasks to the processing cluster array 1712. In at least one embodiment, the scheduler 1710 is implemented by firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1710 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby achieving fast preemption and context switching of threads executed on the processing array 1712. In at least one embodiment, the host software can prove the workload for scheduling on the processing array 1712 through one of a plurality of graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1712 by scheduler 1710 logic within a microcontroller that includes scheduler 1710 .

[0194] In at least one embodiment, processing cluster array 1712 may include up to "N" processing clusters (e.g., cluster 1714A, cluster 1714B, through cluster 1714N). In at least one embodiment, each cluster 1714A-1714N of processing cluster array 1712 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1710 may allocate work to clusters 1714A-1714N of processing cluster array 1712 using various scheduling and / or work allocation algorithms, which may vary depending on the workload generated by each program or type of computation. In at least one embodiment, scheduling may be handled dynamically by scheduler 1710, or may be partially assisted by compiler logic during compilation of program logic configured to be executed by processing cluster array 1712. In at least one embodiment, different clusters 1714A-1714N of processing cluster array 1712 may be allocated to process different types of programs or to perform different types of computations.

[0195] In at least one embodiment, processing cluster array 1712 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1712 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1712 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0196] In at least one embodiment, processing cluster array 1712 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1712 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1712 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1702 may transfer data from system memory via I / O units 1704 for processing. In at least one embodiment, during processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 1722) during processing and then written back to system memory.

[0197] In at least one embodiment, when parallel processing unit 1702 is used to perform graphics processing, scheduler 1710 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1714A-1714N of processing cluster array 1712. In at least one embodiment, portions of processing cluster array 1712 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1714A-1714N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1714A-1714N for further processing.

[0198] In at least one embodiment, processing cluster array 1712 may receive processing tasks to be performed via scheduler 1710, which receives commands defining processing tasks from front end 1708. In at least one embodiment, a processing task may include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1710 may be configured to obtain an index corresponding to a task, or may receive an index from front end 1708. In at least one embodiment, front end 1708 may be configured to ensure that processing cluster array 1712 is configured to a valid state before starting a workload specified by an incoming command buffer (e.g., a batch-buffer, a push buffer, etc.).

[0199] In at least one embodiment, each of the one or more instances of parallel processing unit 1702 can be coupled to parallel processor memory 1722. In at least one embodiment, parallel processor memory 1722 can be accessed via memory crossbar switch 1716, which can receive memory requests from processing cluster array 1712 and I / O unit 1704. In at least one embodiment, memory crossbar switch 1716 can access parallel processor memory 1722 via memory interface 1718. In at least one embodiment, memory interface 1718 can include multiple partition units (e.g., partition unit 1720A, partition unit 1720B to partition unit 1720N), which can each be coupled to a portion of parallel processor memory 1722 (e.g., memory units). In at least one embodiment, the plurality of partition units 1720A-1720N are configured to be equal to the number of memory cells, such that the first partition unit 1720A has a corresponding first memory cell 1724A, the second partition unit 1720B has a corresponding memory cell 1724B, and the Nth partition unit 1720N has a corresponding Nth memory cell 1724N. In at least one embodiment, the number of partition units 1720A-1720N may not be equal to the number of memory devices.

[0200] In at least one embodiment, memory units 1724A-1724N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1724A-1724N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory units 1724A-1724N, allowing partition units 1720A-1720N to write portions of each rendering target in parallel to efficiently use the available bandwidth of parallel processor memory 1722. In at least one embodiment, local instances of parallel processor memory 1722 may be excluded to facilitate a unified memory design that utilizes system memory in combination with local cache memory.

[0201] In at least one embodiment, any of the clusters 1714A-1714N of the processing cluster array 1712 can process data to be written to any memory unit 1724A-1724N within the parallel processor memory 1722. In at least one embodiment, the memory crossbar 1716 can be configured to transmit the output of each cluster 1714A-1714N to any partition unit 1720A-1720N or another cluster 1714A-1714N, and the cluster 1714A-1714N can perform other processing operations on the output. In at least one embodiment, each cluster 1714A-1714N can communicate with the memory interface 1718 through the memory crossbar 1716 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 1716 has connections to memory interface 1718 to communicate with I / O unit 1704, and connections to local instances of parallel processor memory 1722 to enable processing units within different processing clusters 1714A-1714N to communicate with system memory or other memory that is not local to parallel processing unit 1702. In at least one embodiment, memory crossbar switch 1716 may use virtual channels to separate traffic flows between clusters 1714A-1714N and partition units 1720A-1720N.

[0202] In at least one embodiment, multiple instances of parallel processing unit 1702 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 1702 may be configured to interoperate, even if different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1702 may include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1702 or parallel processor 1700 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0203] Fig. 17B is a block diagram of a partition unit 1720 according to at least one embodiment. In at least one embodiment, the partition unit 1720 is Fig.17A1720N. In at least one embodiment, partition unit 1720 includes L2 cache 1721, frame buffer interface 1725, and raster operation unit ("ROP") 1726. L2 cache 1721 is a read / write cache that is configured to perform load and store operations received from memory crossbar switch 1716 and ROP 1726. In at least one embodiment, L2 cache 1721 outputs read misses and urgent write-back requests to frame buffer interface 1725 for processing. In at least one embodiment, updates may also be sent to the frame buffer via frame buffer interface 1725 for processing. In at least one embodiment, frame buffer interface 1725 communicates with memory units (such as ROPs) in parallel processor memory. Fig.17A interacts with one of the memory units 1724A-1724N (e.g., within parallel processor memory 1722).

[0204] In at least one embodiment, ROP 1726 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1726 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1726 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The compression logic performed by ROP 1726 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0205] In at least one embodiment, ROP 1726 is included within each processing cluster (e.g., Fig.17A In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar switch 1716 rather than pixel fragment data transmission. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Fig.16 1610), routed by processor 1602 for further processing, or by Fig.17A One of the processing entities within parallel processor 1700 is routed for further processing.

[0206] Fig. 17C is a block diagram of a processing cluster 1714 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Fig.17AIn at least one embodiment, one or more of the processing clusters 1714 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a specific program executed on a specific set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0207] In at least one embodiment, the operation of the processing cluster 1714 can be controlled by a pipeline manager 1732 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1732 Fig.17A The scheduler 1710 receives instructions and manages the execution of these instructions through the graphics multiprocessor 1734 and / or the texture unit 1736. In at least one embodiment, the graphics multiprocessor 1734 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included in the processing cluster 1714. In at least one embodiment, one or more instances of the graphics multiprocessor 1734 may be included in the processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 may process data, and the data crossbar 1740 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). In at least one embodiment, the pipeline manager 1732 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 1740.

[0208] In at least one embodiment, each graphics multiprocessor 1734 within a processing cluster 1714 may include the same set of function execution logic (e.g., arithmetic logic units, load store units, etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions are completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0209] In at least one embodiment, the instructions transmitted to the processing cluster 1714 constitute threads. In at least one embodiment, a group of threads executed across a group of parallel processing engines is a thread group. In at least one embodiment, the thread group executes the program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 1734. In at least one embodiment, a thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during the cycle that is processing the thread group. In at least one embodiment, a thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1734. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 1734, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1734.

[0210] In at least one embodiment, graphics multiprocessor 1734 includes internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor 1734 can abandon the internal cache and use cache memory (e.g., L1 cache 1748) within processing cluster 1714. In at least one embodiment, each graphics multiprocessor 1734 can also access partition units (e.g., Fig.17A 1720A-1720N) that are shared between all processing clusters 1714 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1734 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1702 can be used as global memory. In at least one embodiment, processing cluster 1714 includes multiple instances of graphics multiprocessor 1734, which can share common instructions and data that can be stored in L1 cache 1748.

[0211] In at least one embodiment, each processing cluster 1714 may include a memory management unit ("MMU") 1745 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1745 may reside in Fig.17A1718. In at least one embodiment, the MMU 1745 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1745 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 1734 or L1 cache or processing cluster 1714. In at least one embodiment, the physical address is processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0212] In at least one embodiment, the processing clusters 1714 can be configured such that each graphics multiprocessor 1734 is coupled to a texture unit 1736 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1734, and the texture data is retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1734 outputs processed tasks to a data crossbar 1740 to provide the processed tasks to another processing cluster 1714 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 1716. In at least one embodiment, a preROP 1742 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1734, direct the data to a ROP unit, which can communicate with a partition unit (e.g., Fig.17A In at least one embodiment, the PreROP 1742 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0213] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processing cluster 1714 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0214] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0215] Fig.17D A graphics multiprocessor 1734 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1734 is coupled to a pipeline manager 1732 of a processing cluster 1714. In at least one embodiment, the graphics multiprocessor 1734 has an execution pipeline that includes, but is not limited to, an instruction cache 1752, an instruction unit 1754, an address mapping unit 1756, a register file 1758, one or more general purpose graphics processing unit (GPGPU) cores 1762, and one or more load / store units 1766. The GPGPU cores 1762 and the load / store units 1766 are coupled to a cache memory 1772 and a shared memory 1770 via a memory and cache interconnect 1768.

[0216] In at least one embodiment, the instruction cache 1752 receives a stream of instructions to be executed from the pipeline manager 1732. In at least one embodiment, the instructions are cached in the instruction cache 1752 and dispatched for execution by the instruction unit 1754. In one embodiment, the instruction unit 1754 can dispatch instructions as thread groups (e.g., warps), each thread group being assigned to a different execution unit within the GPGPU core 1762. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 1756 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the load / store unit 1766.

[0217] In at least one embodiment, register file 1758 provides a set of registers for the functional units of graphics multiprocessor 1734. In at least one embodiment, register file 1758 provides temporary storage for operands for data paths connected to the functional units (e.g., GPGPU core 1762, load / store unit 1766) of graphics multiprocessor 1734. In at least one embodiment, register file 1758 is divided between each functional unit such that a dedicated portion of register file 1758 is allocated to each functional unit. In at least one embodiment, register file 1758 is divided between different warps being executed by graphics multiprocessor 1734.

[0218] In at least one embodiment, the GPGPU cores 1762 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1734. The GPGPU cores 1762 may be similar in architecture or the architecture may be different. In at least one embodiment, the first portion of the GPGPU core 1762 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1734 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0219] In at least one embodiment, the GPGPU core 1762 includes SIMD logic capable of executing a single instruction to multiple sets of data. In one embodiment, the GPGPU core 1762 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0220] In at least one embodiment, the memory and cache interconnect 1768 is an interconnect network that connects each functional unit of the graphics multiprocessor 1734 to the register file 1758 and the shared memory 1770. In at least one embodiment, the memory and cache interconnect 1768 is a crossbar interconnect that allows the load / store unit 1766 to implement load and store operations between the shared memory 1770 and the register file 1758. In at least one embodiment, the register file 1758 can operate at the same frequency as the GPGPU core 1762, so that the latency of data transfer between the GPGPU core 1762 and the register file 1758 is very low. In at least one embodiment, the shared memory 1770 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1734. In at least one embodiment, the cache memory 1772 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 1736. In at least one embodiment, the shared memory 1770 can also be used as a program managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1772, threads executing on GPGPU core 1762 may programmatically store data in shared memory.

[0221] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated with the core on the same package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0222] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics multiprocessor 1734 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0223] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0224] Fig.18 A multi-GPU computing system 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the multi-GPU computing system 1800 may include a processor 1802 coupled to a plurality of general purpose graphics processing units (GPGPUs) 1806A-D via a host interface switch 1804. In at least one embodiment, the host interface switch 1804 is a PCI Express switch device that couples the processor 1802 to a PCI Express bus, over which the processor 1802 may communicate with the GPGPUs 1806A-D. The GPGPUs 1806A-D may be interconnected via a collection of high-speed point-to-point GPU-to-GPU links 1816. In at least one embodiment, the GPU-to-GPU links 1816 are connected to each of the GPGPUs 1806A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1816 enable direct communication between each of the GPGPUs 1806A-D without requiring communication over the host interface bus 1804 to which the processor 1802 is connected. In at least one embodiment, host interface bus 1804 remains available for system memory access or communication with other instances of multi-GPU computing system 1800, for example, via one or more network devices, through GPU-to-GPU traffic directed to P2PGPU link 1816. Although in at least one embodiment, GPGPUs 1806A-D are connected to processor 1802 via host interface switch 1804, in at least one embodiment, processor 1802 includes direct support for P2PGPU link 1816 and can connect directly to GPGPUs 1806A-D.

[0225] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in multi-GPU computing system 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0226] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0227] Fig.19 is a block diagram of a graphics processor 1900 according to at least one embodiment. In at least one embodiment, graphics processor 1900 includes ring interconnect 1902, pipeline front end 1904, media engine 1937, and graphics cores 1980A-1980N. In at least one embodiment, ring interconnect 1902 couples graphics processor 1900 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 1900 is one of many processors integrated within a multi-core processing system.

[0228] In at least one embodiment, the graphics processor 1900 receives batches of commands via a ring interconnect 1902. In at least one embodiment, the incoming commands are interpreted by a command streamer 1903 in a pipeline front end 1904. In at least one embodiment, the graphics processor 1900 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1980A-1980N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1903 provides the commands to a geometry pipeline 1936. In at least one embodiment, for at least some media processing commands, the command streamer 1903 provides the commands to a video front end 1934, which is coupled to a media engine 1937. In at least one embodiment, the media engine 1937 includes a video quality engine (VQE) 1930 for video and image post-processing, and a multi-format encoding / decoding (MFX) 1933 engine for providing hardware accelerated encoding and decoding of media data. In at least one embodiment, geometry pipeline 1936 and media engine 1937 each generate execution threads for thread execution resources provided by at least one graphics core 1980A.

[0229] In at least one embodiment, the graphics processor 1900 includes a scalable thread execution resource featuring modular cores 1980A-1980N (sometimes referred to as core slices), each graphics core having multiple sub-cores 1950A-1950N, 1960A-1960N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1900 can have any number of graphics cores 1980A to 1980N. In at least one embodiment, the graphics processor 1900 includes a graphics core 1980A having at least a first sub-core 1950A and a second sub-core 1960A. In at least one embodiment, the graphics processor 1900 is a low-power processor having a single sub-core (e.g., 1950A). In at least one embodiment, the graphics processor 1900 includes multiple graphics cores 1980A-1980N, each graphics core including a group of first sub-cores 1950A-1950N and a group of second sub-cores 1960A-1960N. In at least one embodiment, each of the first sub-cores 1950A-1950N includes at least a first set of execution units 1952A-1952N and media / texture samplers 1954A-1954N. In at least one embodiment, each of the second sub-cores 1960A-1960N includes at least a second set of execution units 1962A-1962N and samplers 1964A-1964N. In at least one embodiment, each of the sub-cores 1950A-1950N, 1960A-1960N shares a set of shared resources 1970A-1970N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0230] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, inference and / or training logic 615 may be used in graphics processor 1900 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0231] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0232] Fig. 20is a block diagram illustrating a microarchitecture for a processor 2000 that may include logic circuitry for executing instructions according to at least one embodiment. In at least one embodiment, the processor 2000 may execute instructions including x86 instructions, ARM instructions, special instructions for an application specific integrated circuit (ASIC), etc. In at least one embodiment, the processor 2000 may include registers for storing packed data, such as a 64-bit wide MMX 4800 in a microprocessor enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2000 can execute instructions to accelerate machine learning or deep learning algorithms, training, or reasoning.

[0233] In at least one embodiment, the processor 2000 includes an in-order front end ("front end") 2001 to extract instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, the front end 2001 may include several units. In at least one embodiment, an instruction prefetcher 2026 fetches instructions from memory and provides the instructions to an instruction decoder 2028, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2028 decodes the received instructions into one or more operations of so-called "microinstructions" or "microoperations" (also referred to as "micro-operations" or "microinstructions") that are executable by the machine. In at least one embodiment, the instruction decoder 2028 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2030 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2034 for execution. In at least one embodiment, when trace cache 2030 encounters a complex instruction, microcode ROM 2032 provides the microinstructions necessary to complete the operation.

[0234] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions may require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2028 may access the microcode ROM 2032 to execute the instruction. In at least one embodiment, the instruction may be decoded into a small number of micro-operations for processing at the instruction decoder 2028. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2032. In at least one embodiment, the trace cache 2030 references the entry point programmable logic array ("PLA") to determine the correct micro-instruction pointer for reading the microcode sequence from the microcode ROM 2032 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2032 completes the micro-operation sequencing of the instruction, the front end 2001 of the machine may resume fetching micro-operations from the trace cache 2030.

[0235] In at least one embodiment, an out-of-order execution engine ("out-of-order engine") 2003 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance when the instructions go down the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 2003 includes, but is not limited to, a distributor / register renamer 2040, a memory microinstruction queue 2042, an integer / floating point microinstruction queue 2044, a memory scheduler 2046, a fast scheduler 2002, a slow / general floating point scheduler ("slow / general FP scheduler") 2004, and a simple floating point scheduler ("simple FP scheduler") 2006. In at least one embodiment, the fast scheduler 2002, the slow / general floating point scheduler 2004, and the simple floating point scheduler 2006 are also collectively referred to as "microinstruction schedulers 2002, 2004, 2006". In at least one embodiment, the allocator / register renamer 2040 allocates machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2040 renames logical registers to entries in the register file. In at least one embodiment, the allocator / register renamer 2040 also allocates entries for each microinstruction in one of the two microinstruction queues, the memory microinstruction queue 2042 for memory operations and the integer / floating point microinstruction queue 2044 for non-memory operations, in front of the memory scheduler 2046 and the microinstruction schedulers 2002, 2004, 2006. In at least one embodiment, the microinstruction schedulers 2002, 2004, 2006 determine when the microinstructions are ready to execute based on the readiness of their slave input register operand sources and the availability of the execution resource microinstructions that need to be completed. In at least one embodiment, the fast scheduler 2002 of at least one embodiment can be scheduled on each half of the main clock cycle, while the slow / general floating point scheduler 2004 and the simple floating point scheduler 2006 can be scheduled once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 arbitrate dispatch ports to schedule microinstructions for execution.

[0236] In at least one embodiment, execution block 2011 includes, but is not limited to, integer register file / branch network 2008, floating point register file / branch network ("FP register file / branch network") 2010, address generation units ("AGU") 2012 and 2014, fast arithmetic logic units ("fast ALU") 2016 and 2018, slow arithmetic logic unit ("slow ALU") 2020, floating point ALU ("FP") 2022, and floating point move unit ("FP move") 2024. In at least one embodiment, integer register file / branch network 2008 and floating point register file / bypass network 2010 are also referred to herein as "register files 2008, 2010". In at least one embodiment, AGUs 2012 and 2014, fast ALUs 2016 and 2018, slow ALU 2020, floating point ALU 2022, and floating point move unit 2024 are also referred to herein as "execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024". In at least one embodiment, execution block 2011 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0237] In at least one embodiment, register files 2008, 2010 may be arranged between microinstruction schedulers 2002, 2004, 2006 and execution units 2012, 2014, 2016, 2018, 2020, 2022, and 2024. In at least one embodiment, integer register file / branch network 2008 performs integer operations. In at least one embodiment, floating point register file / branch network 2010 performs floating point operations. In at least one embodiment, each of register files 2008, 2010 may include but is not limited to a branch network that can bypass or forward the just completed result that has not yet been written to the register file to a new slave object. In at least one embodiment, register files 2008, 2010 can communicate data with each other. In at least one embodiment, integer register file / branch network 2008 may include but is not limited to two separate register files, one register file for low-order 32-bit data, and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2010 may include, but is not limited to, 128-bit wide entries, since floating point instructions typically have operands that are 64 to 128 bits wide.

[0238] In at least one embodiment, the execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 can execute instructions. In at least one embodiment, the register files 2008, 2010 store integer and floating point data operand values ​​that the microinstructions need to execute. In at least one embodiment, the processor 2000 may include, but is not limited to, any number of execution units 2012, 2014, 2016, 2018, 2020, 2022, 2024 and combinations thereof. In at least one embodiment, the floating point ALU 2022 and the floating point move unit 2024 can perform floating point, MMX, SIMD, AVX and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, the floating point ALU 2022 may include, but is not limited to, a 64-bit by 64-bit floating point divider to perform division, square root and remainder micro-operations. In at least one embodiment, floating point hardware may be used to process instructions involving floating point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2016, 2018. In at least one embodiment, fast ALUs 2016, 2018 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations enter slow ALUs 2020 because slow ALUs 2020 can include, but are not limited to, integer execution hardware for long-delay type operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by AGUs 2012, 2014. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALUs 2016, fast ALUs 2018, and slow ALUs 2020 can be implemented to support various data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, the floating point ALU 2022 and floating point move unit 2024 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2022 and floating point move unit 2024 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0239] In at least one embodiment, microinstruction schedulers 2002, 2004, 2006 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed in processor 2000, processor 2000 can also include logic for handling memory misses. In at least one embodiment, if the data load in the data cache misses, there may be dependent operations running in the pipeline, which temporarily prevents the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and independent operations can be allowed to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor can also be designed to capture instruction sequences for text string comparison operations.

[0240] In at least one embodiment, the term "register" may refer to an onboard processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. On the contrary, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques by circuits within the processor, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packaging data.

[0241] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the inference and / or training logic 615 may be incorporated into the execution block 2011 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in the execution block 2011. In addition, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the execution block 2011 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0242] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0243] Fig.21 A deep learning application processor 2100 is shown in accordance with at least one embodiment. In at least one embodiment, the deep learning application processor 2100 uses instructions that, if executed by the deep learning application processor 2100, cause the deep learning application processor 2100 to perform some or all of the processes and techniques described throughout this disclosure. In at least one embodiment, the deep learning application processor 2100 is an application specific integrated circuit (ASIC). In at least one embodiment, the application processor 2100 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions, or both. In at least one embodiment, the deep learning application processor 2100 includes, but is not limited to, processing clusters 2110(1)-2110(12), inter-chip links (“ICLs”) 2120(1)-2120(12), inter-chip controllers (“ICCs”) 2130(1)-2130(2), memory controllers (“Mem Ctrlr”) 2142(1)-2142(4), high bandwidth memory physical layer (“HBM PHY”) 2144(1)-2144(4), a management controller central processing unit (“management controller CPU”) 2150, serial peripheral interface, inter-integrated circuit and general purpose input / output modules (“SPI, I2C, GPIO”), peripheral component interconnect express controller and direct memory access block (“PCIe controller and DMA”) 2170, and sixteen-lane peripheral component interconnect express port (“PCI Express x 16”) 2180.

[0244] In at least one embodiment, the processing cluster 2110 may perform deep learning operations, including inference or prediction operations based on weight parameters calculated based on one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2110 may include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2100 may include any number and type of processing clusters 2100. In at least one embodiment, the inter-chip link 2120 is bidirectional. In at least one embodiment, the inter-chip link 2120 and the inter-chip controller 2130 enable multiple deep learning application processors 2100 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2100 may include any number (including zero) and type of ICL 2120 and ICC 2130.

[0245] In at least one embodiment, HBM2 2140 provides a total of 32GB of memory. HBM2 2140(i) is associated with both memory controller 2142(i) and HBM PHY 2144(i). In at least one embodiment, any number of HBM2 2140 can provide any type and total amount of high bandwidth memory and can be associated with any number (including zero) and type of memory controller 2142 and HBM PHY 2144. In at least one embodiment, SPI, I2C, GPIO 3360, PCIe controller 2160 and DMA 2170 and / or PCIe2180 can be replaced with any number and type of blocks to implement any number and type of communication standards in any technically feasible manner.

[0246] Reasoning and / or training logic 1015 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor 2100 is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2100. In at least one embodiment, the deep learning application processor 2100 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2100. In at least one embodiment, the processor 2100 can be used to perform one or more of the neural network use cases described herein.

[0247] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0248] Fig. 222 is a block diagram of a neuromorphic processor 2200 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2200 may receive one or more inputs from a source external to the neuromorphic processor 2200. In at least one embodiment, these inputs may be transmitted to one or more neurons 2202 within the neuromorphic processor 2200. In at least one embodiment, the neurons 2202 and their components may be implemented using circuits or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, thousands of instances of neurons 2202, although any suitable number of neurons 2202 may be used. In at least one embodiment, each instance of a neuron 2202 may include a neuron input 2204 and a neuron output 2206. In at least one embodiment, a neuron 2202 may generate an output that may be transmitted to the inputs of other instances of the neuron 2202. In at least one embodiment, the neuron input 2204 and the neuron output 2206 may be interconnected via a synapse 2208.

[0249] In at least one embodiment, the neurons 2202 and synapses 2208 may be interconnected such that the neuromorphic processor 2200 operates to process or analyze information received by the neuromorphic processor 2200. In at least one embodiment, the neuron 2202 may send an output pulse (or "trigger" or "spike") when the input received through the neuron input 2204 exceeds a threshold. In at least one embodiment, the neuron 2202 may sum or integrate the signal received at the neuron input 2204. For example, in at least one embodiment, the neuron 2202 may be implemented as a leaky integrate-trigger neuron, where if the sum (referred to as the "membrane potential") exceeds a threshold, the neuron 2202 may generate an output (or "trigger") using a transfer function such as a sigmoid or threshold function. In at least one embodiment, the leaky integrate-trigger neuron may sum the signal received at the neuron input 2204 into a membrane potential, and may apply an application attenuation factor (or leakage) to reduce the membrane potential. In at least one embodiment, a leaky integrate-and-trigger neuron may trigger if multiple input signals are received at the neuron input 2204 fast enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, the neuron 2202 may be implemented using circuitry or logic that receives inputs, integrates the inputs into a membrane potential, and decays the membrane potential. In at least one embodiment, the inputs may be averaged, or any other suitable transfer function may be used. In addition, in at least one embodiment, the neuron 2202 may include, but is not limited to, a comparator circuit or logic that generates an output spike at the neuron output 2206 when the result of applying the transfer function to the neuron input 2204 exceeds a threshold. In at least one embodiment, once the neuron 2202 triggers, it may ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, the neuron 2202 may resume normal operation after a suitable period of time (or repair period).

[0250] In at least one embodiment, neurons 2202 may be interconnected via synapses 2208. In at least one embodiment, synapses 2208 may be operable to transmit a signal from an output of a first neuron 2202 to an input of a second neuron 2202. In at least one embodiment, a neuron 2202 may transmit information over more than one instance of synapse 2208. In at least one embodiment, one or more instances of a neuron output 2206 may be connected to an instance of a neuron input 2204 in the same neuron 2202 via an instance of synapse 2208. In at least one embodiment, an instance of a neuron 2202 that produces an output to be transmitted over an instance of synapse 2208 may be referred to as a "pre-synaptic neuron" relative to that instance of synapse 2208. In at least one embodiment, an instance of a neuron 2202 that receives an input transmitted through an instance of synapse 2208 may be referred to as a "post-synaptic neuron" relative to an instance of synapse 2208. In at least one embodiment, with respect to various instances of synapses 2208, because an instance of neuron 2202 can receive input from one or more instances of synapses 2208 and can also transmit output through one or more instances of synapses 2208, a single instance of neuron 2202 can be both a "pre-synaptic neuron" and a "post-synaptic neuron."

[0251] Neurons 2202 may be organized into one or more layers. Each instance of a neuron 2202 may have a neuron output 2206 that may fan out to one or more neuron inputs 2204 through one or more synapses 2208. In at least one embodiment, a neuron output 2206 of a neuron 2202 in a first layer 2210 may be connected to a neuron input 2204 of a neuron 2202 in a second layer 2212. In at least one embodiment, a layer 2210 may be referred to as a "feed-forward layer". In at least one embodiment, each instance of a neuron 2202 in an instance of a first layer 2210 may fan out to each instance of a neuron 2202 in a second layer 2212. In at least one embodiment, a first layer 2210 may be referred to as a "fully connected feed-forward layer". In at least one embodiment, each instance of a neuron 2202 in each instance of a second layer 2212 may fan out to less than all instances of a neuron 2202 in a third layer 2214. In at least one embodiment, a second layer 2212 may be referred to as a "sparsely connected feed-forward layer". In at least one embodiment, neurons 2202 in a second layer 2212 may fan out to neurons 2202 in multiple other layers, including fanning out to neurons 2202 in the (same) second layer 2212. In at least one embodiment, the second layer 2212 may be referred to as a "recurrent layer". In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, any suitable combination of recurrent layers and feed-forward layers, including but not limited to sparsely connected feed-forward layers and fully connected feed-forward layers.

[0252] In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, a reconfigurable interconnect architecture or a dedicated hardwired interconnect to connect the synapses 2208 to the neurons 2202. In at least one embodiment, the neuromorphic processor 2200 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2202 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, the synapses 2208 may be connected to the neurons 2202 using an interconnect structure such as a network on a chip or through dedicated connections. In at least one embodiment, the synaptic interconnects and their components may be implemented using circuitry or logic.

[0253] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0254] Fig.23A processing system according to at least one embodiment is shown. In at least one embodiment, system 2300 includes one or more processors 2302 and one or more graphics processors 2308, and can be a single processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2302 or processor cores 2307. In at least one embodiment, system 2300 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0255] In at least one embodiment, the system 2300 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console for gaming and media consoles. In at least one embodiment, the system 2300 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, the processing system 2300 may also include a wearable device coupled to or integrated in a wearable device, such as a smart watch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2300 is a television or set-top box device having one or more processors 2302 and a graphical interface generated by one or more graphics processors 2308.

[0256] In at least one embodiment, one or more processors 2302 each include one or more processor cores 2307 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2307 is configured to process a specific instruction set 2309. In at least one embodiment, the instruction set 2309 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or calculate by very long instruction words (VLIW). In at least one embodiment, the processor cores 2307 can each process different instruction sets 2309, which can include instructions that help emulate other instruction sets. In at least one embodiment, the processor cores 2307 can also include other processing devices, such as digital signal processors (DSPs).

[0257] In at least one embodiment, the processor 2302 includes a cache memory 2304. In at least one embodiment, the processor 2302 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared between various components of the processor 2302. In at least one embodiment, the processor 2302 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared between the processor cores 2307 using known cache coherence techniques. In at least one embodiment, the processor 2302 additionally includes a register file 2306, and the processor may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. In at least one embodiment, the register file 2306 may include general registers or other registers.

[0258] In at least one embodiment, one or more processors 2302 are coupled to one or more interface buses 2310 to transmit communication signals, such as address, data, or control signals, between the processor 2302 and other components in the system 2300. In at least one embodiment, the interface bus 2310 can be a processor bus in one embodiment, such as a version of a direct media interface (DMI) bus. In at least one embodiment, the interface bus 2310 is not limited to a DMI bus, and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2302 includes an integrated memory controller 2316 and a platform controller hub 2330. In at least one embodiment, the memory controller 2316 facilitates communication between memory devices and other components of the processing system 2300, while the platform controller hub (PCH) 2330 provides connections to input / output (I / O) devices through a local I / O bus.

[0259] In at least one embodiment, the memory device 2320 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or have appropriate performance to be used as a processor memory. In at least one embodiment, the memory device 2320 may be used as a system memory of the processing system 2300 to store data 2322 and instructions 2321 for use when one or more processors 2302 execute an application or process. In at least one embodiment, the memory controller 2316 is also coupled to an optional external graphics processor 2312, which may communicate with one or more graphics processors 2308 in the processor 2302 to perform graphics and media operations. In at least one embodiment, a display device 2311 may be connected to the processor 2302. In at least one embodiment, the display device 2311 may include one or more of the internal display devices, such as in a mobile electronic device or laptop device or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, the display device 2311 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0260] In at least one embodiment, the platform controller hub 2330 enables peripheral devices to be connected to the storage device 2320 and the processor 2302 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2346, a network controller 2334, a firmware interface 2328, a wireless transceiver 2326, a touch sensor 2325, a data storage device 2324 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2324 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2325 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2326 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or long-term evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2328 enables communication with the system firmware and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, the network controller 2334 can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2310. In at least one embodiment, the audio controller 2346 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2300 includes an optional legacy I / O controller 2340 for coupling legacy (e.g., personal system 2 (PS / 2)) devices to the system. In at least one embodiment, the platform controller hub 2330 can also be connected to one or more universal serial bus (USB) controllers 2342, which connect input devices such as a keyboard and mouse 2343 combination, a camera 2344, or other USB input devices.

[0261] In at least one embodiment, instances of memory controller 2316 and platform controller hub 2330 may be integrated into a discrete external graphics processor, such as external graphics processor 2312. In at least one embodiment, platform controller hub 2330 and / or memory controller 2316 may be external to one or more processors 2302. For example, in at least one embodiment, system 2300 may include external memory controller 2316 and platform controller hub 2330, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with processor 2302.

[0262] Reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2300. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the graphics processor 2312. Additionally, in at least one embodiment, the inference and / or training operations described herein may use a number of ALUs other than the ALUs embodied in the graphics processor 2312. Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2300 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0263] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0264] Fig.24 is a block diagram of a processor 2400 having one or more processor cores 2402A-2402N, an integrated memory controller 2414, and an integrated graphics processor 2408, according to at least one embodiment. In at least one embodiment, the processor 2400 may include additional cores, up to and including the additional core 2402N represented by the dashed box. In at least one embodiment, each processor core 2402A-2402N includes one or more internal cache units 2404A-2404N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2406.

[0265] In at least one embodiment, the internal cache units 2404A-2404N and the shared cache unit 2406 represent a cache memory hierarchy within the processor 2400. In at least one embodiment, the cache memory units 2404A-2404N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2406 and 2404A-2404N.

[0266] In at least one embodiment, the processor 2400 may also include a set of one or more bus controller units 2416 and a system agent core 2410. In at least one embodiment, the one or more bus controller units 2416 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2410 provides management functions for various processor components. In at least one embodiment, the system agent core 2410 includes one or more integrated memory controllers 2414 to manage access to various external memory devices (not shown).

[0267] In at least one embodiment, one or more processor cores 2402A-2402N include support for multiple threads simultaneously. In at least one embodiment, system agent core 2410 includes components for coordinating and operating cores 2402A-2402N during multithreaded processing. In at least one embodiment, system agent core 2410 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 2402A-2402N and graphics processor 2408.

[0268] In at least one embodiment, the processor 2400 also includes a graphics processor 2408 for performing graphics processing operations. In at least one embodiment, the graphics processor 2408 is coupled to a shared cache unit 2406 and a system agent core 2410 including one or more integrated memory controllers 2414. In at least one embodiment, the system agent core 2410 also includes a display controller 2411 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2411 may also be a separate module coupled to the graphics processor 2408 via at least one interconnect, or may be integrated within the graphics processor 2408.

[0269] In at least one embodiment, a ring-based interconnect unit 2412 is used to couple the internal components of the processor 2400. In at least one embodiment, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, the graphics processor 2408 is coupled to the ring interconnect 2412 via an I / O link 2413.

[0270] In at least one embodiment, I / O link 2413 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory modules 2418 (e.g., eDRAM modules). In at least one embodiment, each of processor cores 2402A-2402N and graphics processor 2408 uses embedded memory modules 2418 as a shared last level cache.

[0271] In at least one embodiment, the processor cores 2402A-2402N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2402A-2402N execute a common instruction set, while one or more other processor cores 2402A-2402N execute a subset or a different instruction set of the common instruction set. In at least one embodiment, the processor cores 2402A-2402N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2400 can be implemented on one or more chips or implemented as a SoC integrated circuit.

[0272] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Detail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the processor 2400. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the graphics processor 2312, one or more graphics cores 2402A-2402N, or Fig.24 In addition, in at least one embodiment, the inference and / or training operations described herein may use other than Fig. 6A or Figure 6B In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0273] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0274] Fig.25 is a block diagram of the hardware logic of a graphics processor core 2500 according to at least one embodiment described herein. In at least one embodiment, the graphics processor core 2500 is included within a graphics core array. In at least one embodiment, the graphics processor core 2500 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, the graphics processor core 2500 is an example of a graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on a target power and performance envelope. In at least one embodiment, each graphics core 2500 may include a fixed function block 2530 coupled to a plurality of sub-cores 2501A-2501F (also referred to as sub-slices), the plurality of sub-cores including modular blocks having general purpose and fixed function logic.

[0275] In at least one embodiment, fixed function block 2530 includes geometry and fixed function pipelines 2536, which may be shared by all sub-cores in graphics processor 2500, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry and fixed function pipelines 2536 include a 3D fixed function pipeline, a video front end unit, a thread maker and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0276] In at least one fixed embodiment, the fixed function block 2530 also includes a graphics SoC interface 2537, a graphics microcontroller 2538, and a media pipeline 2539. In at least one embodiment, the graphics SoC interface 2537 provides an interface between the graphics core 2500 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, the graphics microcontroller 2538 is a programmable subprocessor that can be configured to manage various functions of the graphics processor 2500, including thread dispatching, scheduling, and preemption. In at least one embodiment, the media pipeline 2539 includes logic that helps decode, encode, pre-process, and / or post-process multimedia data including image and video data. In at least one embodiment, the media pipeline 2539 implements media operations via requests to calculation or sampling logic within the sub-cores 2501-2501F.

[0277] In at least one embodiment, the SoC interface 2537 enables the graphics core 2500 to communicate with a general application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2537 may also enable communication with fixed function devices within the SoC (e.g., a camera imaging pipeline), and enable the use and / or implementation of global memory atomics that may be shared between the graphics core 2500 and the CPU within the SoC. In at least one embodiment, the SoC interface 2537 may also implement power management controls for the graphics core 2500 and enable interfaces between the clock domain of the graphics core 2500 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2537 enables receiving command buffers from a command stream converter and a global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to media pipeline 2539 when media operations are to be performed, or may be assigned to geometry and fixed function pipelines (e.g., geometry and fixed function pipeline 2536, geometry and fixed function pipeline 2514) when graphics processing operations are to be performed.

[0278] In at least one embodiment, the graphics microcontroller 2538 can be configured to perform various scheduling and management tasks for the graphics core 2500. In at least one embodiment, the graphics microcontroller 2538 can perform graphics and / or computational workload scheduling on various graphics parallel engines within the execution unit (EU) arrays 2502A-2502F, 2504A-2504F in the sub-cores 2501A-2501F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2500 can submit a workload to one of a plurality of graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, the scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is completed. In at least one embodiment, graphics microcontroller 2538 may also facilitate low power or idle states for graphics core 2500, thereby providing graphics core 2500 with the ability to save and restore registers across low power state transitions within graphics core 2500 independent of an operating system and / or graphics driver software on the system.

[0279] In at least one embodiment, the graphics core 2500 may have up to N modular sub-cores more or less than the sub-cores 2501A-2501F shown. For each set of N sub-cores, in at least one embodiment, the graphics core 2500 may also include shared function logic 2510, shared and / or cache memory 2512, geometry / fixed function pipelines 2514, and additional fixed function logic 2516 to accelerate various graphics and compute processing operations. In at least one embodiment, the shared function logic 2510 may include logic units (e.g., samplers, math and / or inter-thread communication logic) that may be shared by each of the N sub-cores within the graphics core 2500. In at least one embodiment, the shared and / or cache memory 2512 may be the last level cache for the N sub-cores 2501A-2501F within the graphics core 2500, and may also be used as a shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2514 may be included in place of geometry / fixed function pipeline 2536 within fixed function block 2530 and may include the same or similar logic units.

[0280] In at least one embodiment, the graphics core 2500 includes additional fixed function logic 2516, which may include various fixed function acceleration logic for use by the graphics core 2500. In at least one embodiment, the additional fixed function logic 2516 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and in the full geometry pipeline and the culling pipeline within the geometry and fixed function pipelines 2514, 2536, it is an additional geometry pipeline that may be included in the additional fixed function logic 2516. In at least one embodiment, the culling pipeline is a trimmed version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate environment. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, so that shading can be completed earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2516 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether they are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0281] In at least one embodiment, the additional fixed function logic 2516 may also include machine learning acceleration logic, such as fixed function matrix multiplication logic, for implementing optimizations including for machine learning training or inference.

[0282] In at least one embodiment, a set of execution resources is included within each graphics sub-core 2501A-2501F, which can be used to perform graphics, media, and compute operations in response to requests from a graphics pipeline, a media pipeline, or a shader program. In at least one embodiment, the graphics sub-core 2501A-2501F includes multiple EU arrays 2502A-2502F, 2504A-2504F, thread dispatch and inter-thread communication (TD / IC) logic 2503A-2503F, 3D (e.g., texture) samplers 2505A-2505F, media samplers 2506A-2506F, shader processors 2507A-2507F, and shared local memory (SLM) 2508A-2508F. Each of the EU arrays 2502A-2502F, 2504A-2504F includes a plurality of execution units, which are general purpose graphics processing units capable of servicing graphics, media, or compute operations, performing floating point and integer / fixed point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, the TD / IC logic 2503A-2503F performs local thread dispatch and thread control operations for the execution units within the sub-core, and facilitates communication between threads executed on the execution units of the sub-core. In at least one embodiment, the 3D samplers 2505A-2505F can read data associated with textures or other 3D graphics into memory. In at least one embodiment, the 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, the media samplers 2506A-2506F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2501A-2501F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2501A-2501F may utilize shared local memory 2508A-2508F within each sub-core to enable threads executing within a thread group to execute using a common pool of on-chip memory.

[0283] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetail is provided regarding the inference and / or training logic 615. In at least one embodiment, some or all of the inference and / or training logic 615 may be incorporated into the graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may be used in the graphics processor 2312, the graphics microcontroller 2538, the geometry and fixed function pipelines 2514 and 2536, or Fig.25 In addition, in at least one embodiment, the inference and / or training operations described herein may use the addition Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALU of the graphics processor 2500 to execute one or more of the machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0284] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0285] Figures 26A-26B Thread execution logic 2600 is shown for an array of processing elements including a graphics processor core, according to at least one embodiment. Fig.26A At least one embodiment is shown in which thread execution logic 2600 is used. Fig.26B Exemplary internal details of an execution unit in accordance with at least one embodiment are shown.

[0286] like Fig.26AAs shown in , in at least one embodiment, thread execution logic 2600 includes a shader processor 2602, a thread dispatcher 2604, an instruction cache 2606, a scalable execution unit array including a plurality of execution units 2608A-2608N, a sampler 2610, a data cache 2612, and a data port 2614. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2608A, 2608B, 2608C, 2608D to 2608N-1 and 2608N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected by an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 2600 includes one or more connections to a memory (such as system memory or cache memory) through instruction cache 2606, data port 2614, sampler 2610, and one or more of execution units 2608A-2608N. In at least one embodiment, each execution unit (e.g., 2608A) is an independent programmable general-purpose computing unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2608A-2608N is scalable to include any number of separate execution units.

[0287] In at least one embodiment, execution units 2608A-2608N are primarily used to execute shader programs. In at least one embodiment, shader processor 2602 can process various shader programs and dispatch execution threads associated with shader programs via thread dispatcher 2604. In at least one embodiment, thread dispatcher 2604 includes logic for arbitrating thread initialization celebrations from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 2608A-2608N. For example, in at least one embodiment, a geometry pipeline can dispatch vertices, tessellation or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2604 can also process runtime thread generation requests from executing shader programs.

[0288] In at least one embodiment, the execution units 2608A-2608N support an instruction set that includes native support for many standard 3D graphics shader instructions, allowing shader programs in graphics libraries (such as Direct 3D and OpenGL) to execute with minimal conversion. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 2608A-2608N includes one or more arithmetic logic units (ALUs) capable of executing multiple-issue single instruction multiple data (SIMD), and multi-threaded operations enable an efficient execution environment despite higher latency memory access. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single-precision and double-precision floating-point operations, SIMD branch functions, logical operations, prior operations, and other other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, dependency logic within execution units 2608A-2608N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, an execution unit can perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0289] In at least one embodiment, each of the execution units 2608A-2608N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size" or number of lanes of an instruction. In at least one embodiment, an execution lane is a logical unit used for the execution of data element access, masking, and flow control within an instruction. In at least one embodiment, the multiple lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) for a particular graphics processor. In at least one embodiment, the execution units 2608A-2608N support integer and floating point data types.

[0290] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quadword (QW) size data elements), eight separate 32-bit packed data elements (doubleword (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements) or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0291] In at least one embodiment, one or more execution units may be combined into fused execution units 2609A-2609N having thread control logic (2607A-2607N) shared with fused EUs. In at least one embodiment, multiple EUs may be merged into one EU group. In at least one embodiment, the number of EUs in a fused EU group may be configured to execute separate SIMD hardware threads. The number of EUs in a fused EU group may vary according to various embodiments. In at least one embodiment, each EU may execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2609A-2609N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2609A includes a first EU 2608A, a second EU 2608B, and a thread control logic 2607A shared with the first EU 2608A and the second EU 2608B. In at least one embodiment, thread control logic 2607A controls threads executing on fused graphics execution unit 2609A, allowing each EU within fused execution units 2609A-2609N to execute using a common instruction pointer register.

[0292] In at least one embodiment, one or more internal instruction caches (e.g., 2606) are included in the thread execution logic 2600 to cache thread instructions for the execution unit. In at least one embodiment, one or more data caches (e.g., 2612) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2610 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, the sampler 2610 includes a specialized texture or media sampling function to process the texture or media data during the sampling process before providing the sampled data to the execution unit.

[0293] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to the thread execution logic 2600 through the thread generation and dispatch logic. In at least one embodiment, once a set of geometric objects have been processed and rasterized into pixel data, the pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 2602 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, template buffer, etc.). In at least one embodiment, the pixel shader or fragment shader calculates the values ​​of various vertex attributes to be interpolated on the rasterized object. In at least one embodiment, the pixel processor logic within the shader processor 2602 then executes the pixel or fragment shader program provided by the application program interface (API). In at least one embodiment, in order to execute the shader program, the shader processor 2602 dispatches the thread to the execution unit (e.g., 2608A) via the thread dispatcher 2604. In at least one embodiment, the shader processor 2602 uses the texture sampling logic in the sampler 2610 to access the texture data in the texture map stored in the memory. In at least one embodiment, arithmetic operations on texture data and input geometry data calculate pixel color data for each geometry fragment, or discard one or more pixels for further processing.

[0294] In at least one embodiment, data port 2614 provides a memory access mechanism for thread execution logic 2600 to output processed data to memory for further processing on the graphics processor output pipeline. In at least one embodiment, data port 2614 includes or is coupled to one or more cache memories (e.g., data cache 2612) to cache data for memory access via the data port.

[0295] like Fig.26BAs shown, in at least one embodiment, the graphics execution unit 2608 may include an instruction fetch unit 2637, a general register file array (GRF) 2624, an architectural register file array (ARF) 2626, a thread arbiter 2622, an issue unit 2630, a branch unit 2632, a set of SIMD floating point units (FPUs) 2634, and in at least one embodiment, a set of dedicated integer SIMD ALUs 2635. The GRF 2624 and ARF 2626 include a set of general register files and architectural register files associated with each simultaneous hardware thread that can be active in the graphics execution unit 2608. In at least one embodiment, the per-thread architectural state is maintained in the ARF 2626, while data used during thread execution is stored in the GRF 2624. In at least one embodiment, the execution state of each thread, including the instruction pointer of each thread, can be saved in thread-specific registers in the ARF 2626.

[0296] In at least one embodiment, graphics execution unit 2608 has an architecture that is a combination of simultaneous multithreading (SMT) and fine-grained interleaved multithreading (IMT). In at least one embodiment, the architecture has a modular configuration that can be fine-tuned at design time based on the target number of simultaneous threads and the number of registers per execution unit, where execution unit resources are logically allocated for executing multiple simultaneous threads.

[0297] In at least one embodiment, the graphics execution unit 2608 may issue multiple instructions together, each of which may be a different instruction. In at least one embodiment, the thread arbiter 2622 of the graphics execution unit thread 2608 may dispatch the instruction to one of the issue unit 2630, the branch unit 2632, or the SIMD FPU 2634 for execution. In at least one embodiment, each execution thread may access 128 general registers in the GRF 2624, each of which may store 32 bytes and may be accessed as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread may access 4KB in the GRF 2624, although the embodiment is not limited thereto, and more or less register resources may be provided in other embodiments. In at least one embodiment, although the number of threads per execution unit may also vary depending on the embodiment, up to seven threads may be executed simultaneously. In at least one embodiment in which seven threads may access 4KB, the GRF 2624 may store a total of 28KB. In at least one embodiment, flexible addressing modes may allow registers to be addressed together to efficiently build wider registers or rectangular block data structures representing strides.

[0298] In at least one embodiment, memory operations, sampler operations, and other longer latency system communications are scheduled via "send" instructions executed by message passing send unit 2630. In at least one embodiment, dispatching branch instructions to dedicated branch unit 2632 facilitates SIMD divergence and eventual convergence.

[0299] In at least one embodiment, the graphics execution unit 2608 includes one or more SIMD floating point units (FPUs) 2634 to perform floating point operations. In at least one embodiment, one or more FPUs 2634 also support integer calculations. In at least one embodiment, one or more FPUs 2634 can SIMD perform up to M 32-bit floating point (or integer) operations, or SIMD perform up to 2M 16-bit integer or 16-bit floating point operations. In at least one embodiment, at least one FPU provides extended math capabilities to support high throughput a priori math functions and double-precision 64-bit floating points. In at least one embodiment, there is also a set of 8-bit integer SIMD ALUs 2635, and can be specifically optimized to perform operations related to machine learning calculations.

[0300] In at least one embodiment, an array of multiple instances of graphics execution unit 2608 may be instantiated in graphics sub-core groupings (e.g., sub-slices). In at least one embodiment, execution unit 2608 may execute instructions across multiple execution lanes. In at least one embodiment, each thread executing on graphics execution unit 2608 executes on a different lane.

[0301] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Detailed information about the reasoning and / or training logic 615 is provided. In at least one embodiment, part or all of the reasoning and / or training logic 615 may be incorporated into the execution logic 2600. In addition, in at least one embodiment, other than Fig. 6A or Figure 6B In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution logic 2600 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0302] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0303] Fig. 27A parallel processing unit ("PPU") 2700 is shown in accordance with at least one embodiment. In at least one embodiment, the PPU 2700 is configured with machine-readable code that, if executed by the PPU 2700, causes the PPU 2700 to perform some or all of the processes and techniques described throughout the present disclosure. In at least one embodiment, the PPU 2700 is a multithreaded processor implemented on one or more integrated circuit devices, and utilizes multithreading as a latency hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) executed in parallel on multiple threads. In at least one embodiment, a thread refers to an execution thread and is an instance of a group of instructions configured to be executed by the PPU 2700. In at least one embodiment, the PPU 2700 is a graphics processing unit ("GPU") configured to implement a graphics rendering pipeline for processing three-dimensional ("3D") graphics data to generate two-dimensional ("2D") image data for display on a display device, such as a liquid crystal display ("LCD") device. In at least one embodiment, the PPU 2700 is used to perform computations such as linear algebra operations and machine learning operations. Fig. 27 The example parallel processor is shown for illustrative purposes only, and should be construed as a non-limiting example of a processor architecture contemplated within the scope of the present disclosure, and any suitable processor may be employed in addition and / or in place thereof.

[0304] In at least one embodiment, one or more PPUs 2700 are configured to accelerate high performance computing ("HPC"), data centers, and machine learning applications. In at least one embodiment, PPU 2700 is configured to accelerate deep learning systems and applications, including the following non-limiting examples: autonomous vehicle platforms, deep learning, high-precision speech, image, text recognition systems, intelligent video analysis, molecular simulation, drug discovery, disease diagnosis, weather forecasting, big data analysis, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimization, and personalized user recommendations, etc.

[0305] In at least one embodiment, the PPU 2700 includes, but is not limited to, an input / output ("I / O") unit 2706, a front end unit 2710, a scheduler unit 2712, a work distribution unit 2714, a hub 2716, a crossbar switch ("Xbar") 2720, one or more general processing clusters ("GPCs") 2718, and one or more partition units ("memory partition units") 2722. In at least one embodiment, the PPU 2700 is connected to a host processor or other PPUs 2700 via one or more high-speed GPU interconnects ("GPU interconnects") 2708. In at least one embodiment, the PPU 2700 is connected to a host processor or other peripheral devices via interconnect 2702. In an embodiment, the PPU 2700 is connected to a local memory including one or more memory devices ("memory") 2704. In at least one embodiment, the memory devices 2704 include, but are not limited to, one or more dynamic random access memory ("DRAM") devices. In at least one embodiment, one or more DRAM devices are configured and / or configurable as a high bandwidth memory ("HBM") subsystem with multiple DRAM dies stacked within each device.

[0306] In at least one embodiment, the high-speed GPU interconnect 2708 may refer to a wire-based multi-lane communication link that the system uses to scale and includes one or more PPUs 2700 in conjunction with one or more central processing units ("CPUs"), supporting cache coherence between the PPU 2700 and the CPU and CPU mastering. In at least one embodiment, the high-speed GPU interconnect 2708 transmits data and / or commands to other units of the PPU 2700, such as one or more copy engines, video encoders, video decoders, power management units, and / or other units in the PPU 2700 through the hub 2716. Fig. 27 Other components that may not be explicitly shown.

[0307] In at least one embodiment, I / O unit 2706 is configured to receive data from a host processor ( Fig. 27In at least one embodiment, the I / O unit 2706 communicates with the host processor directly through the system bus 2702 or through one or more intermediate devices (e.g., a memory bridge). In at least one embodiment, the I / O unit 2706 can communicate with one or more other processors (e.g., one or more PPUs 2700) via the system bus 2702. In at least one embodiment, the I / O unit 2706 implements a Peripheral Component Interconnect Express ("PCIe") interface for communicating over a PCIe bus. In at least one embodiment, the I / O unit 2706 implements an interface for communicating with external devices.

[0308] In at least one embodiment, the I / O unit 2706 decodes packets received via the system bus 2702. In at least one embodiment, at least some of the packets represent commands configured to cause the PPU 2700 to perform various operations. In at least one embodiment, the I / O unit 2706 sends the decoded commands to various other units of the PPU 2700 as specified by the commands. In at least one embodiment, the commands are sent to the front end unit 2710 and / or to the hub 2716 or other units of the PPU 2700, such as one or more replication engines, video encoders, video decoders, power management units, etc. ( Fig. 27 In at least one embodiment, I / O unit 2706 is configured to route communications between various logical units of PPU 2700.

[0309] In at least one embodiment, a program executed by a host processor encodes a command stream in a buffer that provides a workload to the PPU 2700 for processing. In at least one embodiment, the workload includes instructions and data to be processed by those instructions. In at least one embodiment, the buffer is an area in memory that is accessible (e.g., read / write) by both the host processor and the PPU 2700—the host interface unit can be configured to access the buffer in the system memory connected to the system bus 2702 via the memory request transmitted via the I / O unit 2706 through the system bus 2702. In at least one embodiment, the host processor writes the command stream to the buffer and then sends a pointer indicating the start of the command stream to the PPU 2700, so that the front end unit 2710 receives one or more command stream pointers and manages one or more command streams, reads commands from the command stream and forwards the commands to the various units of the PPU 2700.

[0310] In at least one embodiment, the front end unit 2710 is coupled to a scheduler unit 2712 that configures the various GPCs 2718 to process tasks defined by one or more command streams. In at least one embodiment, the scheduler unit 2712 is configured to track state information related to the various tasks managed by the scheduler unit 2712, where the state information may indicate which GPC 2718 the task is assigned to, whether the task is active or inactive, a priority associated with the task, etc. In at least one embodiment, the scheduler unit 2712 manages multiple tasks that are executed on one or more GPCs 2718.

[0311] In at least one embodiment, the scheduler unit 2712 is coupled to a work distribution unit 2714, which is configured to dispatch tasks for execution on the GPCs 2718. In at least one embodiment, the work distribution unit 2714 tracks a plurality of scheduled tasks received from the scheduler unit 2712 and the work distribution unit 2714 manages a pending task pool and an active task pool for each GPC 2718. In at least one embodiment, the pending task pool includes a plurality of time slots (e.g., 32 time slots) containing tasks assigned to be processed by a particular GPC 2718; the active task pool may include a plurality of time slots (e.g., 4 time slots) for tasks actively processed by the GPC 2718, such that as one of the tasks in the GPC 2718 completes execution, the task is evicted from the active task pool of the GPC 2718 and one of the other tasks is selected from the pending task pool and scheduled for execution on the GPC 2718. In at least one embodiment, if an active task is idle on GPC 2718, such as while waiting for data dependencies to be resolved, the active task is evicted from GPC 2718 and returned to the pending task pool, while another task in the pending task pool is selected and scheduled for execution on GPC 2718.

[0312] In at least one embodiment, work distribution unit 2714 communicates with one or more GPCs 2718 via XBar 2720. In at least one embodiment, XBar 2720 is an interconnect network that couples many units of PPU 2700 to other units of PPU 2700 and can be configured to couple work distribution unit 2714 to a specific GPC 2718. In at least one embodiment, other units of one or more PPU 2700 can also be connected to XBar 2720 through hub 2716.

[0313] In at least one embodiment, the tasks are managed by the scheduler unit 2712 and assigned to one of the GPCs 2718 by the work distribution unit 2714. The GPC 2718 is configured to process the tasks and produce results. In at least one embodiment, the results can be consumed by other tasks in the GPC 2718, routed to a different GPC 2718 via the XBar 2720, or stored in the memory 2704. In at least one embodiment, the results can be written to the memory 2704 via a partition unit 2722, which implements a memory interface for writing data to or reading data from the memory 2704. In at least one embodiment, the results can be transmitted to another PPU 2704 or a CPU via the high-speed GPU interconnect 2708. In at least one embodiment, the PPU 2700 includes, but is not limited to, U partition units 2722, which is equal to the number of separate and distinct memory devices 2704 coupled to the PPU 2700. In at least one embodiment, the partition unit 2722 will be described below in conjunction with Fig.29 Describe in more detail.

[0314] In at least one embodiment, the host processor executes a driver core that implements an application programming interface (API) that enables one or more applications executing on the host processor to schedule operations for execution on the PPU 2700. In one embodiment, multiple computing applications are executed simultaneously by the PPU 2700, and the PPU 2700 provides isolation, quality of service (“QoS”), and independent address spaces for the multiple computing applications. In at least one embodiment, the application generates instructions (e.g., in the form of API calls) that cause the driver core to generate one or more tasks for execution by the PPU 2700, and the driver core outputs the tasks to one or more streams processed by the PPU 2700. In at least one embodiment, each task includes one or more related thread groups, which may be referred to as warps. In at least one embodiment, a warp includes multiple related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, a cooperative thread may refer to multiple threads that include instructions for performing tasks and exchanging data through shared memory. In at least one embodiment, in combination Fig.29 Threads and cooperating threads are described in greater detail according to at least one embodiment.

[0315] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6BDetails are provided regarding the inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the PPU 2700. In at least one embodiment, the PPU 2700 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or the PPU 2700. In at least one embodiment, the PPU 2700 can be used to perform one or more of the neural network use cases described herein.

[0316] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0317] Fig.28 A general processing cluster ("GPC") 2800 is shown in accordance with at least one embodiment. In at least one embodiment, GPC 2800 is Fig. 27 2718. In at least one embodiment, each GPC 2800 includes, but is not limited to, multiple hardware units for processing tasks, and each GPC 2800 includes, but is not limited to, a pipeline manager 2802, a pre-raster operations unit ("preROP") 2804, a raster engine 2808, a work distribution crossbar ("WDX") 2816, a memory management unit ("MMU") 2818, one or more data processing clusters ("DPC") 2806, and any suitable combination of components.

[0318] In at least one embodiment, the operation of the GPC 2800 is controlled by a pipeline manager 2802. In at least one embodiment, the pipeline manager 2802 manages the configuration of one or more DPCs 2806 to process tasks assigned to the GPC 2800. In at least one embodiment, the pipeline manager 2802 configures at least one of the one or more DPCs 2806 to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, the DPC 2806 is configured to execute vertex shader programs on a programmable streaming multiprocessor (“SM”) 2814. In at least one embodiment, the pipeline manager 2802 is configured to route packets received from the work distribution unit to appropriate logic units within the GPC 2800, and in at least one embodiment, some packets may be routed to fixed function hardware units in the preROP 2804 and / or the raster engine 2808, while other packets may be routed to the DPC 2806 for processing by the primitive engine 2812 or the SM 2814. In at least one embodiment, pipeline manager 2802 configures at least one of DPCs 2806 to implement a neural network model and / or a computational pipeline.

[0319] In at least one embodiment, preROP unit 2804 is configured to route data generated by raster engine 2808 and DPC 2806 to a raster operations ("ROP") unit in partition unit 2722 in at least one embodiment, in conjunction with Fig. 27 Described in more detail. In at least one embodiment, the preROP unit 2804 is configured to perform optimizations for color blending, organize pixel data, perform address translation, and the like. In at least one embodiment, the raster engine 2808 includes, but is not limited to, a plurality of fixed-function hardware units configured to perform various raster operations, and in at least one embodiment, the raster engine 2808 includes, but is not limited to, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile aggregation engine, and any suitable combination thereof. In at least one embodiment, the setup engine receives the transformed vertices and generates plane equations associated with the geometric primitives defined by the vertices; the plane equations are transmitted to the coarse raster engine to generate coverage information for the base primitives (e.g., an x, y coverage mask for the tile); the output of the coarse raster engine is transmitted to the culling engine, where fragments associated with primitives that fail the z test are culled, and to the clipping engine, where the fragments that are outside the frustum are clipped. In at least one embodiment, the clipped and culled fragments are passed to the fine raster engine to generate attributes for the pixel fragments based on the plane equations generated by the setup engine. In at least one embodiment, the output of the raster engine 2808 includes fragments to be processed by any appropriate entity (e.g., by a fragment shader implemented within the DPC 2806).

[0320] In at least one embodiment, each DPC 2806 included in GPC 2800 includes, but is not limited to, an M-pipeline controller ("MPC") 2810; a primitive engine 2812; one or more SMs 2814; and any suitable combination thereof. In at least one embodiment, MPC 2810 controls the operation of DPC 2806, routing packets received from pipeline manager 2802 to appropriate units in DPC 2806. In at least one embodiment, packets associated with vertices are routed to primitive engine 2812, which is configured to fetch vertex attributes associated with the vertices from memory; conversely, packets associated with shader programs may be sent to SM 2814.

[0321] In at least one embodiment, SM 2814 includes, but is not limited to, a programmable stream processor configured to process tasks represented by multiple threads. In at least one embodiment, SM 2814 is multithreaded and configured to execute multiple threads (e.g., 32 threads) from a specific thread group simultaneously, and implements a single instruction, multiple data ("SIMD") architecture, wherein each thread in a group of threads (e.g., a warp) is configured to process different data sets based on the same instruction set. In at least one embodiment, all threads in a thread group execute the same instruction. In at least one embodiment, SM 2814 implements a single instruction, multiple thread ("SIMT") architecture, wherein each thread in a group of threads is configured to process different data sets based on the same instruction, but wherein individual threads in a thread group are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state are maintained for each warp, thereby achieving concurrency between warps and serial execution within the warp when threads in the warp diverge. In another embodiment, a program counter, call stack, and execution state are maintained for each individual thread, thereby enabling equal concurrency between all threads within and between warps. In at least one embodiment, execution state is maintained for each individual thread, and threads executing the same instructions can be converged and executed in parallel to improve efficiency. At least one embodiment of SM 2814 is described in more detail below.

[0322] In at least one embodiment, MMU 2818 is used between GPC 2800 and memory partition unit (e.g., Fig. 27 The MMU 2818 provides an interface between the partition unit 2722 of the memory, and provides virtual address to physical address translation, memory protection, and arbitration of memory requests. In at least one embodiment, the MMU 2818 provides one or more translation lookaside buffers ("TLBs") for performing translation of virtual addresses to physical addresses in memory.

[0323] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations associated with one or more embodiments. Fig. 6A and / or Figure 6B Details are provided regarding inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the GPC 2800. In at least one embodiment, the GPC 2800 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or the GPC 2800. In at least one embodiment, the GPC 2800 can be used to perform one or more of the neural network use cases described herein.

[0324] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0325] Fig.29 A memory partition unit 2900 of a parallel processing unit ("PPU") according to at least one embodiment is shown. In at least one embodiment, the memory partition unit 2900 includes, but is not limited to, a raster operation ("ROP") unit 2902; a level 2 ("L2") cache 2904; a memory interface 2906; and any suitable combination thereof. In at least one embodiment, the memory interface 2906 is coupled to a memory. In at least one embodiment, the memory interface 2906 may implement a 32, 64, 128, 1024 bit data bus, or a similar implementation for high speed data transfer. In at least one embodiment, the PPU includes U memory interfaces 2906, one memory interface 2906 for each pair of partition units 2900, wherein each pair of partition units 2900 is connected to a corresponding memory device. For example, in at least one embodiment, the PPU may be connected to up to Y memory devices, such as a high bandwidth memory stack or a graphics double data rate version 5 synchronous dynamic random access memory ("GDDR5 SDRAM").

[0326] In at least one embodiment, the memory interface 2906 implements a high bandwidth memory second generation ("HBM2") memory interface, and Y is equal to half of U. In at least one embodiment, the HBM2 memory stack is located on the same physical package as the PPU, providing significant power and area savings compared to traditional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, but is not limited to, four memory dies, and Y is equal to 4, each HBM2 stack includes two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, the memory supports single error correction double error detection ("SECDED") error correction code ("ECC") to protect data. In at least one embodiment, ECC provides higher reliability for computing applications that are sensitive to data corruption.

[0327] In at least one embodiment, the PPU implements a multi-level memory hierarchy. In at least one embodiment, the memory partition unit 2900 supports unified memory to provide a single unified virtual address space for the central processing unit ("CPU") and the PPU memory, thereby enabling data sharing between virtual memory systems. In at least one embodiment, the frequency of PPU accesses to memory located on other processors is tracked to ensure that memory pages are moved to the physical memory of the PPU that accesses the page more frequently. In at least one embodiment, the high-speed GPU interconnect 2708 supports address translation services that allow the PPU to directly access the CPU's page tables and provide full access to the CPU memory through the PPU.

[0328] In at least one embodiment, the copy engine transfers data between multiple PPUs or between a PPU and a CPU. In at least one embodiment, the copy engine can generate a page fault for an address that is not mapped in a page table, and the memory partition unit 2900 then services the page fault, maps the address into a page table, and then the copy engine performs the transfer. In at least one embodiment, fixed (i.e., non-pageable) memory is operated for multiple copy engines between multiple processors, thereby substantially reducing the available memory. In at least one embodiment, in the event of a hardware page fault, the address can be passed to the copy engine without regard to whether it resides in a memory page, and the copy process is transparent.

[0329] According to at least one embodiment, from Fig. 27 Data from memory 2704 or other system memory is retrieved by the memory partition unit 2900 and stored in an L2 cache 2904, which is located on the chip and shared between the various GPCs. In at least one embodiment, each memory partition unit 2900 includes, but is not limited to, at least a portion of an L2 cache associated with a corresponding memory device. In at least one embodiment, lower levels of cache are implemented in various units within a GPC. In at least one embodiment, each SM 2814 may implement a level 1 ("L1") cache, where the L1 cache is private memory dedicated to a particular SM 2814, and data is retrieved from the L2 cache 2904 and stored in each L1 cache for processing in the functional units of the SM 2814. In at least one embodiment, the L2 cache 2904 is coupled to the memory interface 2906 and the XBar 2720.

[0330] In at least one embodiment, the ROP unit 2902 performs graphics raster operations related to pixel color, such as color compression, pixel blending, etc. In at least one embodiment, the ROP unit 2902 performs depth testing in conjunction with the raster engine 2808, receiving the depth of the sample position associated with the pixel fragment from the culling engine of the raster engine 2808. In at least one embodiment, the depth is tested against the corresponding depth in the depth buffer of the sample position associated with the fragment. In at least one embodiment, if the fragment passes the depth test for the sample position, the ROP unit 2902 updates the depth buffer and sends the result of the depth test to the raster engine 2808. It will be appreciated that the number of partition units 2900 can be different than the number of GPCs, and therefore, each ROP unit 2902 can be coupled to each GPC in at least one embodiment. In at least one embodiment, the ROP unit 2902 tracks packets received from different GPCs and determines to which the results generated by the ROP unit 2902 are routed through the XBar 2720.

[0331] Fig.30 Streaming multiprocessor ("SM") 3000 is shown in accordance with at least one embodiment. In at least one embodiment, SM 3000 is Fig.28SM 2814. In at least one embodiment, SM 3000 includes, but is not limited to, instruction cache 3002; one or more scheduler units 3004; register file 3008; one or more processing cores ("cores") 3010; one or more special function units ("SFUs") 3012; one or more load / store units ("LSUs") 3014; interconnect network 3016; shared memory / level 1 ("L1") cache 3018; and any suitable combination thereof. In at least one embodiment, a work distribution unit schedules tasks for execution on a general processing cluster ("GPC") of a parallel processing unit ("PPU"), and each task is assigned to a specific data processing cluster ("DPC") within a GPC, and if the task is associated with a shader program, the task is assigned to one of SM 3000. In at least one embodiment, scheduler unit 3004 receives tasks from the work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM 3000. In at least one embodiment, the scheduler unit 3004 schedules thread blocks to execute as warps of parallel threads, where each thread block is assigned at least one warp. In at least one embodiment, each warp executes a thread. In at least one embodiment, the scheduler unit 3004 manages a plurality of different thread blocks, assigns warps to different thread blocks, and then dispatches instructions from a plurality of different cooperative groups to various functional units (e.g., processing core 3010, SFU 3012, and LSU 3014) in each clock cycle.

[0332] In at least one embodiment, a cooperative group may refer to a programming model for organizing groups of communicating threads that allows developers to express the granularity at which threads are communicating, thereby enabling the expression of richer and more efficient parallel decompositions. In at least one embodiment, a cooperative launch API supports synchronization between thread blocks to execute parallel algorithms. In at least one embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperative threads: a barrier across all threads of a thread block (e.g., a syncthreads() function). However, in at least one embodiment, programmers can define thread groups at a granularity smaller than a thread block and synchronize within the defined group to achieve higher performance, design flexibility, and software reuse in the form of a collective group-wide functional interface. In at least one embodiment, cooperative groups enable programmers to explicitly define thread groups at sub-block (i.e., as small as a single thread) and multi-block granularity, and perform collective operations, such as synchronizing threads in a cooperative group. In at least one embodiment, the programming model supports clean composition across software boundaries, so that library and utility functions can be safely synchronized in their local environment without having to make assumptions about convergence. In at least one embodiment, the cooperation group primitives enable new patterns of cooperative parallelism, including but not limited to producer-consumer parallelism, opportunistic parallelism, and global synchronization over an entire grid of thread blocks.

[0333] In at least one embodiment, the scheduling unit 3006 is configured to send instructions to one or more of the functional units, and the scheduler unit 3004 includes but is not limited to two scheduling units 3006, which enable two different instructions from the same thread warp to be scheduled in each clock cycle. In at least one embodiment, each scheduler unit 3004 includes a single scheduling unit 3006 or additional scheduling units 3006.

[0334] In at least one embodiment, each SM 3000 includes, in at least one embodiment, but is not limited to, a register file 3008 that provides a set of registers for the functional units of the SM 3000. In at least one embodiment, the register file 3008 is divided between each functional unit, so that a dedicated portion of the register file 3008 is allocated to each functional unit. In at least one embodiment, the register file 3008 is divided between different thread warps executed by the SM 3000, and the register file 3008 provides temporary storage for operands of the data paths connected to the functional units. In at least one embodiment, each SM 3000 includes, but is not limited to, a plurality of L processing cores 3010. In at least one embodiment, the SM 3000 includes, but is not limited to, a large number (e.g., 128 or more) of different processing cores 3010. In at least one embodiment, each processing core 3010 includes, in at least one embodiment, but is not limited to, a full pipeline, single-precision, double-precision, and / or mixed-precision processing unit, including, but not limited to, a floating-point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, the floating-point arithmetic logic unit implements the IEEE 754-2008 standard for floating-point arithmetic. In at least one embodiment, the processing core 3010 includes, but is not limited to, 64 single precision (32-bit) floating point cores, 64 integer cores, 32 double precision (64-bit) floating point cores, and 8 tensor cores.

[0335] According to at least one embodiment, the tensor core is configured to perform matrix operations. In at least one embodiment, one or more tensor cores are included in the processing core 3010. In at least one embodiment, the tensor core is configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and reasoning. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiplication and accumulation operation D=A×B+C, where A, B, C, and D are 4×4 matrices.

[0336] In at least one embodiment, the matrix multiplication inputs A and B are 16-bit floating point matrices, and the accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, the tensor core performs a 32-bit floating point accumulation operation on the 16-bit floating point input data. In at least one embodiment, the 16-bit floating point multiplication uses 64 operations and obtains a full-precision product, which is then accumulated with other intermediate products using 32-bit floating point addition to perform a 4x4x4 matrix multiplication. In at least one embodiment, the tensor core is used to perform larger two-dimensional or higher-dimensional matrix operations composed of these smaller elements. In at least one embodiment, an API (such as the CUDA9 C++ API) exposes specialized matrix loads, matrix multiplications and accumulations, and matrix storage operations to efficiently use tensor cores from CUDA-C++ programs. In at least one embodiment, at the CUDA level, the warp level interface assumes a 16×16 size matrix across all 32 warp threads.

[0337] In at least one embodiment, each SM 3000 includes, but is not limited to, M SFUs 3012 that perform special functions (e.g., attribute evaluation, reciprocal square root, etc.). In at least one embodiment, the SFUs 3012 include, but are not limited to, tree traversal units configured to traverse a hierarchical tree data structure. In at least one embodiment, the SFUs 3012 include, but are not limited to, texture units configured to perform texture map filtering operations. In at least one embodiment, the texture units are configured to load texture maps (e.g., 2D arrays of texture pixels) from memory and sample the texture maps to produce sampled texture values ​​for use by shader programs executed by the SM 3000. In at least one embodiment, the texture maps are stored in a shared memory / L1 cache 3018. In at least one embodiment, the texture units implement texture operations (such as filtering operations) using mip-maps (e.g., texture maps with different levels of detail) in accordance with at least one embodiment. In at least one embodiment, each SM 3000 includes, but is not limited to, two texture units.

[0338] In at least one embodiment, each SM 3000 includes, but is not limited to, N LSUs 3014 that implement load and store operations between the shared memory / L1 cache 3018 and the register file 3008. In at least one embodiment, each SM 3000 includes, but is not limited to, an interconnect network 3016 that connects each functional unit to the register file 3008, and connects the LSUs 3014 to the register file 3008 and the shared memory / L1 cache 3018. In at least one embodiment, the interconnect network 3016 is a crossbar switch that can be configured to connect any functional unit to any register in the register file 3008, and to connect the LSUs 3014 to memory locations in the register file 3008 and the shared memory / L1 cache 3018.

[0339] In at least one embodiment, shared memory / L1 cache 3018 is an array of on-chip memory that allows data storage and communication between SM 3000 and primitive engines and between threads in SM 3000 in at least one embodiment. In at least one embodiment, shared memory / L1 cache 3018 includes, but is not limited to, 128KB of storage capacity and is located in the path from SM 3000 to the partition unit. In at least one embodiment, shared memory / L1 cache 3018 is used in at least one embodiment for caching reads and writes. In at least one embodiment, one or more of shared memory / L1 cache 3018, L2 cache, and memory is a backing store.

[0340] In at least one embodiment, data cache and shared memory functions are combined into a single memory block, providing improved performance for both types of memory access. In at least one embodiment, the capacity is used by programs that do not use the shared memory or use it as a cache, for example, if the shared memory is configured to use half of the capacity, and texture and load / store operations can use the remaining capacity. According to at least one embodiment, the integration within the shared memory / L1 cache 3018 enables the shared memory / L1 cache 3018 to be used as a high throughput pipeline for streaming data, while providing high bandwidth and low latency access to frequently reused data. In at least one embodiment, when configured for general parallel computing, a simpler configuration can be used compared to graphics processing. In at least one embodiment, the fixed-function graphics processing unit is bypassed, thereby creating a simpler programming model. In at least one embodiment, in a general parallel computing configuration, the work distribution unit directly allocates and distributes blocks of threads to DPCs. In at least one embodiment, threads in a block execute the same program, use unique thread IDs in computations to ensure that each thread generates unique results, use SM 3000 to execute the program and perform computations, use shared memory / L1 cache 3018 to communicate between threads, and use LSU 3014 to read and write global memory through shared memory / L1 cache 3018 and memory partitioning units. In at least one embodiment, when configured for general parallel computing, SM 3000 writes commands to scheduler unit 3004 that can be used to start new work on a DPC.

[0341] In at least one embodiment, the PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant ("PDA"), a digital camera, a vehicle, a head mounted display, a handheld electronic device, etc. In at least one embodiment, the PPU is implemented on a single semiconductor substrate. In at least one embodiment, the PPU is included in a system on a chip ("SoC") along with one or more other devices (e.g., additional PPUs, memory, a reduced instruction set computer ("RISC") CPU, one or more memory management units ("MMU"), a digital-to-analog converter ("DAC"), etc.).

[0342] In at least one embodiment, the PPU may be included on a graphics card that includes one or more storage devices. The graphics card may be configured to connect to a PCIe slot on a desktop computer motherboard. In at least one embodiment, the PPU may be an integrated graphics processing unit ("iGPU") included in a chipset of the motherboard.

[0343] The reasoning and / or training logic 615 is used to perform reasoning and / or training operations related to one or more embodiments. Fig. 6A and / or Figure 6B Provides details about the inference and / or training logic 615. In at least one embodiment, the deep learning application processor is used to train a machine learning model (such as a neural network) to predict or infer information provided to the SM 3000. In at least one embodiment, the SM 3000 is used to infer or predict information based on a machine learning model (e.g., a neural network) that has been trained by another processor or system or by the SM 3000. In at least one embodiment, the SM 3000 can be used to perform one or more of the neural network use cases described herein.

[0344] In at least one embodiment, such a component may be used to compile compute-bound operations that are fused with user-provided functions.

[0345] In at least one embodiment, a single semiconductor platform may refer to a unique single semiconductor-based integrated circuit or chip. In at least one embodiment, a multi-chip module with increased connectivity may be used that emulates on-chip operations and provides substantial improvements over utilizing a traditional central processing unit ("CPU") and bus implementation. In at least one embodiment, the various modules may also be placed separately or in various combinations of semiconductor platforms, depending on the needs of the user.

[0346] In at least one embodiment, a computer program in the form of a machine-readable executable code or a computer control logic algorithm is stored in the main memory 1004 and / or the auxiliary storage. According to at least one embodiment, if executed by one or more processors, the computer program enables the system 1000 to perform various functions. In at least one embodiment, the memory 1004, storage and / or any other storage are possible examples of computer-readable media. In at least one embodiment, the auxiliary storage can refer to any suitable storage device or system, such as a hard disk drive and / or a removable storage drive, which represents a floppy disk drive, a tape drive, an optical disk drive, a digital versatile disk ("DVD") drive, a recording device, a universal serial bus ("USB") flash memory, etc. In at least one embodiment, the architecture and / or functions of each of the previous figures are implemented in the environment of any suitable combination of CPU 1002; parallel processing system 1012; integrated circuits capable of having at least part of the capabilities of two CPUs 1002; parallel processing system 1012; chipsets (e.g., a group of integrated circuits designed to work and sell as a unit that performs related functions, etc.); and integrated circuits.

[0347] In at least one embodiment, the architecture and / or functionality of the various previous figures are implemented in the context of a general purpose computer system, a circuit board system, a game console system dedicated to entertainment purposes, a dedicated system, etc. In at least one embodiment, the computer system 1000 can take the form of a desktop computer, a laptop computer, a tablet computer, a server, a supercomputer, a smartphone (e.g., wireless, handheld device), a personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a handheld electronic device, a mobile telephone device, a television, a workstation, a game console, an embedded system, and / or any other type of logic.

[0348] In at least one embodiment, the parallel processing system 1012 includes, but is not limited to, a plurality of parallel processing units ("PPUs") 1014 and associated memory 1016. In at least one embodiment, the PPUs 1014 are connected to a host processor or other peripheral device via an interconnect 1018 and a switch 1020 or multiplexer. In at least one embodiment, the parallel processing system 1012 distributes computational tasks across parallelizable PPUs 1014, for example, as part of a distribution of computational tasks across multiple graphics processing unit ("GPU") thread blocks. In at least one embodiment, memory is shared and accessed (e.g., for read and / or write access) between some or all of the PPUs 1014, although such shared memory may incur a performance penalty relative to using local memory and registers resident on the PPUs 1014. In at least one embodiment, the operation of the PPUs 1014 is synchronized by using a command (such as __syncthreads()) where all threads in a block (e.g., executing across multiple PPUs 1014) reach a certain code execution point before proceeding.

[0349] Other variations are within the spirit of the present disclosure. Thus, while the disclosed technology is susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described in detail above. However, it should be understood that it is not intended to limit the present disclosure to the specific form or forms disclosed, but on the contrary, it is intended to cover all modifications, alternative constructions, and equivalents that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0350] In the context of describing the disclosed embodiments (especially in the context of the following claims), the use of the terms "a / an" and "the" and similar designations should be interpreted as covering both the singular and the plural, unless otherwise specified herein or clearly contradicted by the context, and not as a definition of the term. Unless otherwise specified, the terms "comprise", "have", "include" and "contain" should be interpreted as open terms (meaning "including but not limited to") unless otherwise specified. The term "connected" should be interpreted as partially or completely contained together, attached thereto, or connected together when not modified and referring to a physical connection, even if there is something intervening. Unless otherwise specified herein, the numerical ranges listed herein are intended only to be used as a shorthand method of individually referring to each individual value falling within the range, and each individual value is incorporated into the specification as if it were individually listed herein. Unless otherwise specified or contradictory by the context, the use of the term "set" (e.g., "set of items") or "subset" should be interpreted as a non-empty set including one or more members. Further, unless otherwise indicated or contradicted by context, the term "subset" of a corresponding set does not necessarily mean a proper subset of the corresponding set, but a subset and a corresponding set may be equivalent.

[0351] Connective language, such as phrases of the form "at least one of A, B, and C," or "at least one of A, B, and C," unless expressly stated otherwise or clearly contradicted by context, is to be understood otherwise by context, which context is generally used to present an item, term, or the like as being A or B or C, or any non-empty subset of the set of A and B and C. For example, in the illustrative example of a set having three members, the connective phrases "at least one of A, B, and C" and "at least one of A, B, and C" refer to any of the following sets: {A}, {B}, {C}, {A, B}, { A, C}, {B, C}, {A, B, C}. Thus, such connective language is generally not intended to imply that certain embodiments require the presence of at least one of A, at least one of B, and at least one of C, respectively. Furthermore, unless otherwise indicated or contradicted by context, the term "plurality" indicates plural status (e.g., "plurality of items" indicates a plurality of items). A plurality is at least two items, but may be more when so indicated, either explicitly or by context. Further, unless otherwise indicated or otherwise clear from context, the phrase "based on" means "based at least in part on" rather than "based solely on."

[0352] The operations of the processes described herein may be performed in any suitable order, unless otherwise specified herein or otherwise clearly contradictory to the context. In at least one embodiment, processes such as those described herein (or variations and / or combinations thereof) are performed under the control of one or more computer systems configured with executable instructions, and are implemented as codes (e.g., executable instructions, one or more computer programs, or one or more applications) that are executed together on one or more processors, by hardware or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium, for example, in the form of a computer program including a plurality of instructions that can be executed by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transient computer-readable storage medium that excludes transient signals (e.g., transient electrical or electromagnetic transmissions of propagation) but includes non-transient data storage circuits (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a collection of one or more non-transitory computer-readable storage media on which executable instructions (or other memory for storing executable instructions) are stored, and when executed by one or more processors of a computer system (i.e., due to being executed), the computer system is caused to perform the operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media includes a plurality of non-transitory computer-readable storage media and one or more of the non-transitory computer-readable storage media in the plurality of non-transitory computer-readable storage media lack all codes, while the plurality of non-transitory computer-readable storage media collectively store all codes. In at least one embodiment, executable instructions are executed so that different instructions are executed by different processors. For example, a non-transitory computer-readable storage medium stores instructions, and a main central processing unit ("CPU") executes some of the instructions, while a graphics processing unit ("GPU") executes other instructions. In at least one embodiment, different components of the computer system have separate processors, and different processors execute different subsets of instructions.

[0353] Thus, in at least one embodiment, a computer system is configured to implement one or more services that individually or collectively perform the operations of the processes described herein, and such a computer system is configured with applicable hardware and / or software that can enable the execution of the operations. Further, a computer system that implements at least one embodiment of the present disclosure is a single device, and in another embodiment, is a distributed computer system comprising multiple devices that operate differently, such that the distributed computer system performs the operations described herein and such that a single device does not perform all operations.

[0354] The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended only to better illustrate embodiments of the present disclosure and does not limit the scope of the present disclosure unless otherwise required. No language in the specification should be construed as indicating any non-claimed element is essential to the practice of the present disclosure.

[0355] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0356] In the specification and claims, the terms "coupled" and "connected" and their derivatives may be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in specific examples, "connected" or "coupled" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. "Coupled" may also refer to two or more elements that are not in direct contact with each other, but still cooperate or interact with each other.

[0357] Unless expressly stated otherwise, it is to be understood that throughout the specification terms such as “processing,” “computing,” “calculating,” “determining,” etc. refer to the action and / or process of a computer or computing system, or similar electronic computing device, that manipulates and / or transforms data represented as physical (such as electronic) quantities within registers and / or memories of a computing system into other data similarly represented as physical quantities within a computing system memory, registers or other such information storage, transmission or display device.

[0358] In a similar manner, the term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. As a non-limiting example, a "processor" may be a CPU or a GPU. A "computing platform" may include one or more processors. As used herein, a "software" process may include, for example, software and / or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Moreover, each process may refer to multiple processes for executing instructions sequentially or in parallel, continuously or intermittently. The terms "system" and "method" are used interchangeably herein, as long as a system can embody one or more methods and a method can be considered a system.

[0359] In this document, reference may be made to obtaining, acquiring, receiving or inputting analog or digital data into a subsystem, a computer system or a computer-implemented machine. Obtaining, acquiring, receiving or inputting analog and digital data may be accomplished in various ways, such as by receiving the data of a parameter as a function call or a call to an application programming interface. In some implementations, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data via a serial or parallel interface. In another implementation, the process of obtaining, acquiring, receiving or inputting analog or digital data may be accomplished by transmitting data from providing an entity to acquiring an entity via a computer network. Reference may also be made to providing, outputting, transmitting, sending or presenting analog or digital data. In different examples, the process of providing, outputting, transmitting, sending or presenting analog or digital data may be accomplished by transmitting data as an input or output parameter of a function call, a parameter of an application programming interface or an interprocess communication mechanism.

[0360] Although the above discussion sets forth exemplary embodiments of the described technology, other architectures may be used to implement the described functionality and are intended to be within the scope of the present invention. In addition, although a specific distribution of responsibilities is defined above for discussion purposes, the various functions and responsibilities may be distributed and divided in different ways depending on the circumstances.

[0361] Furthermore, although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter claimed in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

1. A processor, comprising: One or more circuits for executing a compiler to compile one or more source code software programs and one or more object code software programs to generate a single object code software program.

2. The processor of claim 1, wherein the one or more source code software programs include: An intermediate representation comprising one or more separately compiled representations of one or more convolution kernels or matrix multiplications.

3. The processor of claim 1 , wherein the one or more source code software programs include: One or more intermediate representations, the one or more intermediate representations corresponding to the one or more application-specific function objects.

4. The processor of claim 3, wherein the application specific function object is received from an application via an application programming interface (API).

5. The processor of claim 3, wherein at least one intermediate representation corresponding to the one or more application specific function objects is inserted into one or more callback locations.

6. The processor of claim 1, wherein the one or more circuits are further for compiling into bitcode for distribution in one or more libraries.

7. The processor of claim 1, wherein the one or more circuits are further configured to perform one or more optimizations prior to compiling using one or more just-in-time code generation processes.

8. A system comprising: one or more processors for executing a compiler to compile one or more source code software programs and one or more object code software programs to generate a single object code software program; as well as Memory for storing compiled code software programs.

9. The system of claim 8, wherein the one or more source code software programs include: An intermediate representation comprising one or more separately compiled representations of one or more convolution kernels or matrix multiplications.

10. The system of claim 8, wherein the one or more source code software programs include: One or more intermediate representations, the one or more intermediate representations corresponding to the one or more application-specific function objects.

11. The system of claim 10, wherein the application specific function object is received from an application via an application programming interface (API).

12. The system of claim 10, wherein at least one intermediate representation corresponding to the one or more application specific function objects is inserted into one or more callback locations.

13. The system of claim 8, wherein the one or more circuits are further for compiling into bitcode for distribution in one or more libraries.

14. The system of claim 8, wherein the one or more processors are further configured to perform one or more optimizations prior to compiling using one or more just-in-time code generation processes.

15. A non-transitory machine-readable medium having stored thereon a set of instructions that, if executed by one or more processors, cause the one or more processors to at least: The compiler is executed to compile the one or more source code software programs and the one or more object code software programs to generate a single object code software program.

16. The non-transitory machine-readable medium of claim 15, wherein the one or more source code software programs include: An intermediate representation comprising one or more separately compiled representations of one or more convolution kernels or matrix multiplications.

17. The non-transitory machine-readable medium of claim 15, wherein the one or more source code software programs include: One or more intermediate representations, the one or more intermediate representations corresponding to the one or more application-specific function objects.

18. The non-transitory machine-readable medium of claim 17, wherein the application specific function object is received from an application via an application programming interface (API).

19. The non-transitory machine-readable medium of claim 17, wherein at least one intermediate representation corresponding to the one or more application specific function objects is inserted into one or more callback locations.

20. The non-transitory machine-readable medium of claim 15, wherein the one or more processors are further configured to compile into bitcode for distribution in one or more libraries.

21. The non-transitory machine-readable medium of claim 15, wherein the one or more processors are further configured to perform one or more optimizations prior to compiling using one or more just-in-time code generation processes.

22. A method comprising: The compiler is executed to compile the one or more source code software programs and the one or more object code software programs to generate a single object code software program.

23. The method of claim 22, wherein the one or more source code software programs include: An intermediate representation comprising one or more separately compiled representations of one or more convolution kernels or matrix multiplications.

24. The method of claim 22, wherein the one or more source code software programs include: One or more intermediate representations, the one or more intermediate representations corresponding to the one or more application-specific function objects.

25. The method of claim 24, wherein the application specific function object is received from an application via an application programming interface (API).

26. The method of claim 24, wherein at least one intermediate representation corresponding to the one or more application specific function objects is inserted into one or more callback locations.

27. The method of claim 22, wherein the one or more circuits are further configured to compile into bitcode for distribution in one or more libraries.

28. The method of claim 22, wherein the one or more circuits are further configured to perform one or more optimizations prior to compiling using one or more just-in-time code generation processes.

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