Simulation Method, Device and Electronic Device for Multicore Mechanism

Abstract

The present application provides a simulation method, apparatus, and electronic device for a multi-core mechanism, including: during the running of a test case, identifying whether there are multiple target test sequences that can be parallelized; in response to the existence of multiple target test sequences that can be parallelized, configuring a matching target simulation core for each target test sequence; running each target test sequence in parallel based on the target simulation core until the end; continuing to run the next test sequence in the test case until the test case runs to completion. In the present application, the parallel running of test sequences is realized based on the multi-core mechanism, shortening the running time of the test case and improving the efficiency of chip verification.

Description

Technical Field

[0001] This application relates to the field of chip verification, and particularly to a simulation method, apparatus, and electronic device for a multi-core mechanism. Background Art

[0002] With the increase in the complexity of chip design, the verification time for each module of the chip also increases accordingly, which has affected the verification efficiency of the chip to a certain extent.

[0003] Therefore, how to improve the verification efficiency of the chip has become a problem to be solved currently. Summary of the Invention

[0004] The purpose of this application aims to solve at least one of the technical problems in the above technologies to some extent.

[0005] The first aspect of this application provides a simulation method for a multi-core mechanism, including: during the running of a test case, identifying whether there are multiple target test sequences that can be parallelized; in response to the existence of the multiple target test sequences that can be parallelized, configuring a matching target simulation core for each target test sequence; running each target test sequence in parallel based on the target simulation core until the end; and continuing to run the next test sequence in the test case until the test case runs to the end.

[0006] The simulation method for a multi-core mechanism provided by the first aspect of this application further has the following technical features, including:

[0007] According to an embodiment of this application, during the running of the test case, identifying whether there are multiple target test sequences that can be parallelized includes: in response to the test case meeting the parallel condition, determining that the test case has the multiple target test sequences that can be parallelized, where each target test sequence includes at least one test sequence to be run.

[0008] According to an embodiment of this application, the method further includes: identifying that there are multiple test sequences to be run in the test case that have no dependencies and can continue to run the next test sequence after running to the end, and determining that the test case meets the parallel condition.

[0009] According to an embodiment of this application, the target test sequences are the multiple test sequences to be run that have no dependencies and can continue to run the next test sequence after running to the end.

[0010] According to an embodiment of the present application, the step of configuring a matching target simulation core for each target test sequence in response to the existence of multiple target test sequences that can be parallelized includes: in response to the existence of available simulation cores, configuring the matching target simulation core for the target test sequence based on the available simulation cores; in response to the non-existence of available simulation cores, placing the target test sequence in a queue to be run until a matching target simulation core is configured.

[0011] According to an embodiment of the present application, the step of configuring the matching target simulation core for the target test sequence based on the available simulation cores in response to the existence of available simulation cores includes: identifying that the unoccupied space of the simulation core is greater than or equal to the running space of the target test sequence, and then using the simulation core as the available simulation core; in response to the simulation environment provided by the available simulation core matching the to-be-run function corresponding to the target test sequence, determining the available simulation core as the target simulation core.

[0012] According to an embodiment of the present application, the method further includes: in response to the test case not meeting the parallel condition, performing simulation on the test case based on the running simulation core until the simulation ends.

[0013] A second aspect of the present application provides a simulation device with a multi-core mechanism, including: an identification module, configured to identify whether there are multiple target test sequences that can be parallelized during the running process of a test case; a configuration module, configured to configure a matching target simulation core for each target test sequence in response to the existence of the multiple target test sequences that can be parallelized; a parallel module, configured to run each target test sequence in parallel based on the target simulation core until the end; a simulation module, configured to continue running the next test sequence in the test sequence until the test case runs to the end.

[0014] The simulation device with a multi-core mechanism provided in the second aspect of the present application further has the following technical features, including:

[0015] According to an embodiment of the present application, the identification module is further configured to: in response to the test case meeting the parallel condition, determine that the test case has the multiple target test sequences that can be parallelized, where each target test sequence includes at least one to-be-run test sequence.

[0016] According to an embodiment of the present application, the identification module is further configured to: identify that in the test case, there are multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to the end, and determine that the test case meets the parallel condition.

[0017] According to an embodiment of the present application, the target test sequence is the plurality of to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after the operation ends.

[0018] According to an embodiment of the present application, the configuration module is further configured to: in response to the existence of available simulation cores, configure the matching target simulation core for the target test sequence based on the available simulation cores; in response to the non-existence of available simulation cores, place the target test sequence in the to-be-run queue until the matching target simulation core is configured.

[0019] According to an embodiment of the present application, the configuration module is further configured to: identify that the unoccupied space of the simulation core is greater than or equal to the running space of the target test sequence, and then use the simulation core as the available simulation core; in response to the simulation environment provided by the available simulation core matching the to-be-run function corresponding to the target test sequence, determine the available simulation core as the target simulation core.

[0020] According to an embodiment of the present application, the simulation module is further configured to: in response to the test case not meeting the parallel condition, perform simulation on the test case based on the running simulation core until the simulation ends.

[0021] An embodiment of the third aspect of the present application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the simulation method of the multi-core mechanism provided in the first aspect of the present application.

[0022] An embodiment of the fourth aspect of the present application provides a readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the simulation method of the multi-core mechanism provided in the first aspect of the present application.

[0023] An embodiment of the fifth aspect of the present application provides a computer program product, and when the instruction processor in the computer program product executes, it executes the simulation method of the multi-core mechanism provided in the first aspect of the present application.

[0024] The simulation method and device based on the multi-core mechanism provided by this application identify whether there are multiple target test sequences that can be parallelized in the test sequence to be run during the running process of the test case. If there are multiple target test sequences that can be parallelized, a matching target simulation core is configured for each target test sequence. Each target test sequence can run in its corresponding target simulation core. After the target test sequence finishes running, the next test sequence in the test case can continue to run until the test case finishes running. In this application, the parallel running of the test sequences is realized based on the multi-core mechanism, which shortens the running time of the test case and improves the efficiency of chip verification.

[0025] Additional aspects and advantages of this application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of this application. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of this application will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a schematic flowchart of the simulation method of the multi-core mechanism according to an embodiment of this application;

[0028] Figure 2 is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application;

[0029] Figure 3 is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application;

[0030] Figure 4 is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application;

[0031] Figure 5 is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application;

[0032] Figure 6 is a schematic structural diagram of the simulation device of the multi-core mechanism according to an embodiment of this application;

[0033] Figure 7 is a schematic structural diagram of the simulation device of the multi-core mechanism according to another embodiment of this application;

[0034] Figure 8 is a block diagram of an electronic device according to an embodiment of this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] Embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, but should not be construed as limiting the present application.

[0036] The simulation method, device, electronic device, and storage medium of the multi-core mechanism of the embodiments of the present application will be described below with reference to the accompanying drawings.

[0037] Figure 1 It is a schematic flowchart of the simulation method of the multi-core mechanism according to an embodiment of the present application. As Figure 1 shown, the method includes:

[0038] S101, during the running of the test case, identify whether there are multiple target test sequences that can be parallelized.

[0039] In implementation, the functions of the chip need to be realized based on the running of multiple steps. Among them, there is a set order for the running of the steps, and the steps need to be run sequentially according to the set order to realize the corresponding chip functions.

[0040] Among the running steps for realizing the chip functions, there may be some running steps that can be run simultaneously without affecting the running of subsequent other steps and without affecting the realization of the corresponding chip functions. Further, these steps can be determined as the running steps that can be parallelized.

[0041] In implementation, a corresponding test case can be constructed based on the function to be verified of the chip, and a corresponding test sequence can be constructed based on the steps to be run for realizing the function to be verified. In the scenario where there are running steps that can be parallelized among the steps for realizing the function to be verified of the chip, in its corresponding test case, the test sequences corresponding to the running steps that can be parallelized can be determined as the test sequences that can be simulated side by side.

[0042] Optionally, during the running of the test case, the test sequences to be run can be judged, and it can be identified whether there are test sequences that can be simulated side by side among them, and they can be determined as test sequences.

[0043] In the embodiments of the present application, there is a set parallel determination criterion for the parallelizable test sequences. During the running of the test case, the relevant parameter information of the test sequences to be run can be obtained, and it can be judged whether there are test sequences that meet the parallel determination criterion in the test sequences to be run according to the obtained parameter information.

[0044] Optionally, there is a set quantity criterion in the parallel determination criterion, which may include that the number of parallelizable test sequences in the test case is at least two or more.

[0045] Furthermore, based on the set parallel determination criteria, multiple parallelizable test sequences can be identified from the to-be-run test sequences, and then multiple target test sequences that can be parallelized in the to-be-run test sequences can be determined.

[0046] S102. In response to the existence of multiple target test sequences that can be parallelized, configure a matching target simulation core for each target test sequence.

[0047] In implementation, the simulation core can provide a simulation environment for test cases in chip verification. In this simulation environment, the test cases can simulate the to-be-verified functions of the chip, so as to achieve the purpose of verifying the functions of the chip.

[0048] Among them, different simulation cores with configuration parameters can provide different simulation environments for test cases. Therefore, the corresponding simulation core can be configured for the test cases according to the required conditions for implementing the to-be-verified functions of the chip corresponding to the test cases.

[0049] In the embodiments of the present application, in order to achieve the parallel running of multiple target test sequences, a matching simulation core can be configured for each target test sequence. Among them, each target test sequence has corresponding to-be-run steps. The corresponding simulation core can be configured for it according to the running environment required by the to-be-run steps corresponding to each target test sequence, and it is determined as the target simulation core corresponding to each target test sequence.

[0050] Furthermore, each target test sequence can run in the simulation environment provided by the corresponding target simulation core to achieve the parallel running of multiple target test sequences.

[0051] S103. Based on the target simulation cores, run each target test sequence in parallel until the end.

[0052] In implementation, each target test sequence can run separately in the simulation environment provided by its matching target simulation core, thereby achieving the parallel running of multiple target test sequences.

[0053] In the embodiments of the present application, there may be multiple batches of target test sequences in the test cases, and multiple target test sequences in the same time batch can run in parallel. For different target test sequences, their running times are different. After all the multiple target test sequences in the same time batch have finished running, the next test sequence of the multiple target test sequences can be run.

[0054] In some implementations, the same running time can be set for each target test sequence within the same time batch. Each target test sequence can start running at the set same running time in the simulation environment provided by its matched target simulation core, so as to achieve the simultaneous parallel running of multiple target test sequences.

[0055] In other implementations, the corresponding running time can be set for the target test sequence based on the usage of the target simulation core matched by each target test sequence within the same time batch. Among them, the running time of each target test sequence may be different. Further, each target test sequence runs in the simulation environment provided by its matched target simulation core based on its set running time, thereby achieving the non-simultaneous parallel running of multiple target test sequences that can be parallelized.

[0056] S104, continue to run the next test sequence in the test case until the test case runs to completion.

[0057] In the embodiments of the present application, when the target test sequence with the longest running time within the same time batch runs to completion, it can be determined that all the target test sequences within this time batch have run to completion.

[0058] Further, the running of the next test sequence in the test case can be continued.

[0059] Among them, the next test sequence after all the target test sequences within the current time batch can be continued to run, or the multiple target test sequences that can be parallelized within the next time batch adjacent to the current time batch can be continued to run.

[0060] It can be understood that during the running of the test case, the identification of the target test sequences that can be parallelized is carried out. When the target test sequences that can be parallelized within the same time batch are identified, the corresponding target simulation cores are respectively configured for them. After the target test sequences within each time batch run to completion, the running of the subsequent test sequences is continued until all the test sequences run to completion, thereby achieving the running to completion of the test case.

[0061] The simulation method of the multi-core mechanism provided by the present application identifies whether there are multiple target test sequences that can be parallelized among the test sequences to be run during the running of the test case. If there are multiple target test sequences that can be parallelized, the corresponding target simulation cores are respectively configured for each target test sequence. Each target test sequence can run in its corresponding target simulation core. When the target test sequence runs to completion, the next test sequence in the test case can be continued to run until the test case runs to completion. In the present application, the parallel running of the test sequences is achieved based on the multi-core mechanism, shortening the running time of the test case and improving the efficiency of chip verification.

[0062] In the above embodiments, for the determination of multiple target test sequences that can be parallelized, it can be combined with Figure 2 to further understand that Figure 2 is a schematic flowchart of a simulation method for a multi-core mechanism according to another embodiment of the present application. As Figure 2 shown, the method includes:

[0063] S201, in response to the test case satisfying the parallel condition, determine that there are multiple target test sequences that can be parallelized in the test case, where each target test sequence includes at least one test sequence to be run.

[0064] In the embodiments of the present application, based on the set parallel condition, it can be identified whether there are multiple target test sequences that can be parallelized in the test sequences to be run.

[0065] In implementation, the function to be verified of the chip is realized based on the execution of several steps to be run. Among them, there are some steps to be run that can be independently executed in the same time batch, and after the execution ends, the execution of other subsequent steps can continue.

[0066] Correspondingly, the test case is realized by simulating the execution of several test sequences. Among them, there are some test sequences that can be independently executed in the same time batch, and after the execution ends, the execution of the next test sequence in the test case can continue.

[0067] Optionally, corresponding parallel conditions can be set based on the above content, and multiple target test sequences that can be parallelized are identified and obtained from the test sequences to be run according to the parallel conditions.

[0068] Among them, the target test sequences are multiple test sequences to be run that have no dependency relationship and can continue to run the next test sequence after the execution ends.

[0069] Further, the relevant attribute information of the test sequences to be run can be read during the execution of the test case, and it is determined whether it meets the corresponding parallel conditions. If there is no dependency relationship among multiple test sequences to be run and the next test sequence can continue to be run after the execution ends, then these multiple test sequences to be run can be determined as multiple target test sequences that can be parallelized.

[0070] Correspondingly, it is recognized that in the test case, there are multiple test sequences to be run that have no dependency relationship and can continue to run the next test sequence after the execution ends, and it is determined that the test case meets the parallel condition.

[0071] In some implementations, it is possible to determine whether a test case meets the parallel condition before the test case runs. If it is determined that the test case meets the parallel condition, corresponding recognition resources can be configured for it before the test case runs. Among them, based on the configuration of the recognition resources, the recognition of multiple target test sequences that can be parallelized during the running of the test case can be achieved.

[0072] Optionally, all the running steps of the function to be verified corresponding to the test case can be analyzed, the running modes achievable by all the running steps can be classified, and digitized presentation can be performed. Among them, the to-be-run steps that meet the parallel condition can be marked as events-per-cycle. If there is a numerical display after events-per-cycle in the result of the digitized presentation, it can be determined that there are multiple target test sequences that can be parallelized in the test case, and thus it can be determined that the test case meets the parallel condition.

[0073] Furthermore, the analysis of the test case can be achieved through the running of relevant setting codes. Based on the running of the setting codes, the analysis of whether the test case meets the parallel condition can be achieved.

[0074] Furthermore, based on the configuration of the recognition resources, among the test cases that meet the parallel condition, multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to completion are recognized, and they are determined as the multiple target test sequences that can be parallelized in the test case.

[0075] Among them, each target test sequence has corresponding to-be-run steps, and each to-be-run step can be achieved based on the running of at least one test sequence. Therefore, each target test sequence includes at least one to-be-run test sequence.

[0076] The simulation method of the multi-core mechanism provided by this application determines whether a test case meets the parallel condition, and for the test cases that meet the parallel condition, the to-be-run test sequences therein are recognized during their running process, and multiple target test sequences that can be parallelized are obtained. In this application, through the recognition of the target test sequences, a basis is provided for realizing the parallelism of multiple test sequences in the test case, thereby improving the running efficiency of the test case.

[0077] Correspondingly, there may be test cases that do not meet the parallel condition, which can be combined Figure 3 Understand, Figure 3 is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application. As Figure 3 shown, the method includes:

[0078] S301, in response to the test case not meeting the parallel condition, perform simulation on the test case based on the running simulation until the simulation ends.

[0079] In the embodiments of the present application, there are multiple functions to be verified in the chip. Therefore, multiple test cases need to be constructed during the verification of the chip. Among them, if some test cases meet the set parallel conditions, multiple target test sequences that can be parallelized can be identified during the running process of these test cases.

[0080] Correspondingly, there are some test cases that do not meet the set parallel conditions.

[0081] It can be understood that there is a dependency relationship between the running steps for implementing the functions to be verified corresponding to these test cases, and they cannot run independently. Based on this situation, it can be determined that these test cases do not meet the set parallel conditions.

[0082] Furthermore, for these test cases that do not meet the parallel conditions, they can be run based on the simulation environment provided by the simulation core matched for them, and other simulation cores are not allocated to some of the test sequences among them. When all the test sequences have finished running, the simulation of this test case ends.

[0083] For the simulation method of the multi-core mechanism provided by the present application, for test cases that do not meet the parallel conditions, they can be run in the simulation core matched for them until the simulation of the test case ends. In the simulation method of the multi-core mechanism provided by the present application, a running method is provided for test cases that do not meet the parallel conditions, ensuring the integrity of the chip verification process and the verification coverage of the functions to be verified of the chip.

[0084] In the above embodiments, regarding the configuration of the simulation core, it can be combined with Figure 4 For further understanding, Figure 4 is a schematic flowchart of the simulation method of the multi-core mechanism for another embodiment of the present application. As Figure 4 shown, this method includes:

[0085] S401, in response to the existence of available simulation cores, configure a matching target simulation core for the target test sequence based on the available simulation cores.

[0086] In implementation, the functions to be verified of the chip can be simulated through the simulation environment provided by the simulation core, so as to realize the verification of the chip. Among them, there is a set number of simulation cores.

[0087] In the embodiments of the present application, when there are multiple target test sequences that can be parallelized in a test case, a matching target simulation core needs to be configured for each target test sequence. Furthermore, before determining the target simulation core corresponding to each target test sequence, it is necessary to judge it based on the relevant status of the simulation core, so as to determine whether it can be used as the target simulation core of the target test sequence.

[0088] Further, if the unoccupied space of the simulation core is greater than or equal to the running space of the target test sequence, the simulation core is regarded as an available simulation core.

[0089] In the embodiments of the present application, the running of the test sequence needs to occupy the running space of its corresponding simulation core. Therefore, a preliminary judgment can be made based on the running space of the simulation core. Among them, if the unoccupied space of the simulation core is greater than or equal to the space required for the target test sequence to run, the simulation core can be determined as an available simulation core.

[0090] Further, in response to the simulation environment provided by the available simulation core matching the to-be-run function corresponding to the target test sequence, the available simulation core is determined as the target simulation core.

[0091] In the embodiments of the present application, the to-be-run function corresponding to the target test sequence requires a matching simulation environment. Therefore, from the simulation environments provided by the available simulation cores, a simulation environment that can realize the running of the target test sequence can be selected, and the simulation core corresponding to this simulation environment is determined as the target simulation core matching the target test sequence.

[0092] S402, in response to the non-existence of an available simulation core, place the target test sequence in the to-be-run queue until a matching target simulation core is configured.

[0093] In the embodiments of the present application, there is a to-be-run queue for the target test sequence. When a matching target simulation core cannot be configured for the target test sequence, it can be placed in the to-be-run queue.

[0094] In some implementations, if the current simulation core cannot provide a running space for the running of the target test sequence, it can be determined that there is no available simulation core currently.

[0095] In this scenario, any simulation core that can provide a simulation environment for the target test sequence can be selected, and the target test sequence is placed in the to-be-run queue corresponding to this simulation core until this simulation core can provide a running space for it, and then this simulation core is determined as the target simulation core matching the target test sequence.

[0096] In other implementations, if the current simulation core can provide a running space for the target test sequence, but cannot provide a matching simulation environment for the target test sequence, it can be determined that there is no available simulation core currently.

[0097] In this scenario, any simulation core that can provide a running environment for the target test sequence can be selected, and it is determined whether the simulation environment can be modified by modifying its parameter configuration. If the parameter of the simulation core can provide a simulation environment for the target test sequence after modification, the target test sequence can be placed in the pending execution queue corresponding to the simulation core. After all the test sequences before the target test sequence have finished running, the relevant parameters of the simulation core can be modified, and it is determined as the target simulation core matching the target test sequence.

[0098] The simulation method of the multi-core mechanism provided by this application configures a target simulation core that matches the target test sequence based on the relevant information of the simulation core, thereby realizing the parallel running of multiple target test sequences, so as to effectively improve the running efficiency of test cases.

[0099] For a better understanding of the above embodiments, it can be combined with Figure 5 , Figure 5 which is a schematic flowchart of the simulation method of the multi-core mechanism according to another embodiment of this application. As Figure 5 shown, the method includes:

[0100] As Figure 5 shown, Test Case 1, Test Case 2, and Test Case 3 are test cases that meet the parallel conditions.

[0101] Among them, Test Case 1 runs in the simulation environment provided by Simulation Core 1. Test Case 1 includes two target test sequences 11 and 12 that can be parallel. Simulation Core 2 is configured as the target simulation core matching the target test sequence 11, and Simulation Core 3 is configured as the target simulation core matching the target test sequence 12.

[0102] Test Case 2 runs in the simulation environment provided by Simulation Core 7. Test Case 2 includes three target test sequences 21, 22, and 23 that can be parallel. Simulation Core 3 is configured as the target simulation core matching the target test sequence 21, Simulation Core 4 is configured as the target simulation core matching the target test sequence 22, and Simulation Core 5 is configured as the target simulation core matching the target test sequence 23.

[0103] Test Case 3 runs in the simulation environment provided by Simulation Core 5. Test Case 3 includes two target test sequences 31 and 32 that can be parallel. Simulation Core 6 is configured as the target simulation core matching the target test sequence 31, and Simulation Core 8 is configured as the target simulation core matching the target test sequence 32.

[0104] Each target test sequence can run in the simulation environment provided by its matching target simulation core, thereby realizing the parallel running of multiple target test sequences.

[0105] In the simulation method of the multi-core mechanism provided by this application, during the running process of a test case, it is identified whether there are multiple target test sequences that can be run in parallel in the test sequence to be run. If there are multiple target test sequences that can be run in parallel, a matching target simulation core is configured for each target test sequence. Each target test sequence can be run in its corresponding target simulation core. After the target test sequence finishes running, the next test sequence in the test case can be continued until the test case finishes running. In this application, the parallel running of test sequences is realized based on the multi-core mechanism, shortening the running time of the test case and improving the efficiency of chip verification.

[0106] Corresponding to the simulation method of the multi-core mechanism provided in the above several embodiments, an embodiment of this application also provides a simulation device of the multi-core mechanism. Since the simulation device of the multi-core mechanism provided in the embodiment of this application corresponds to the simulation method of the multi-core mechanism provided in the above several embodiments, the implementation manners of the above simulation method of the multi-core mechanism are also applicable to the simulation device of the multi-core mechanism provided in the embodiment of this application and will not be described in detail in the following embodiments.

[0107] Figure 6 It is a schematic structural diagram of a simulation device of the multi-core mechanism according to an embodiment of this application. As Figure 6 shown, the simulation device 600 of the multi-core mechanism includes an identification module 61, a configuration module 62, a parallel module 63, and a simulation module 64, where:

[0108] The identification module 61 is used to identify whether there are multiple target test sequences that can be run in parallel during the running process of a test case;

[0109] The configuration module 62 is used to, in response to the existence of multiple target test sequences that can be run in parallel, configure a matching target simulation core for each target test sequence;

[0110] The parallel module 63 is used to run each target test sequence in parallel based on the target simulation core until the end;

[0111] The simulation module 64 is used to continue running the next test sequence in the test case until the test case finishes running.

[0112] Figure 7 It is a schematic structural diagram of a simulation device of the multi-core mechanism according to an embodiment of this application. As Figure 7 shown, the simulation device 700 of the multi-core mechanism includes an identification module 71, a configuration module 72, a parallel module 73, and a simulation module 74, where:

[0113] It should be noted that the recognition module 61, configuration module 62, parallel module 63, and simulation module 64 have the same structure and functions as the recognition module 71, configuration module 72, parallel module 73, and simulation module 74.

[0114] In the embodiment of the present application, the recognition module 71 is further configured to: in response to the test case meeting the parallel condition, determine that there are multiple target test sequences that can be parallelized in the test case, where each target test sequence includes at least one test sequence to be run.

[0115] In the embodiment of the present application, the recognition module 71 is further configured to: recognize that there are multiple test sequences to be run in the test case that have no dependencies and can continue to run the next test sequence after running to completion, and determine that the test case meets the parallel condition.

[0116] In the embodiment of the present application, the target test sequence is multiple test sequences to be run that have no dependencies and can continue to run the next test sequence after running to completion.

[0117] In the embodiment of the present application, the configuration module 72 is further configured to: in response to the existence of available simulation cores, configure a matching target simulation core for the target test sequence based on the available simulation cores; in response to the non-existence of available simulation cores, place the target test sequence in the queue to be run until a matching target simulation core is configured.

[0118] In the embodiment of the present application, the configuration module 72 is further configured to: recognize that the unoccupied space of the simulation core is greater than or equal to the running space of the target test sequence, and then regard the simulation core as an available simulation core; in response to the simulation environment provided by the available simulation core matching the function to be run corresponding to the target test sequence, determine the available simulation core as the target simulation core.

[0119] In the embodiment of the present application, the simulation module 74 is further configured to: in response to the test case not meeting the parallel condition, perform simulation on the test case based on the running simulation core until the simulation ends.

[0120] The simulation device with a multi-core mechanism provided by the present application identifies whether there are multiple target test sequences that can be parallelized in the test sequences to be run during the running process of the test case. If there are multiple target test sequences that can be parallelized, a matching target simulation core is configured for each target test sequence. Each target test sequence can run in its corresponding target simulation core. When the target test sequence runs to completion, the next test sequence in the test case can continue to run until the test case runs to completion. In the present application, the parallel running of the test sequences is realized based on the multi-core mechanism, shortening the running time of the test case and improving the efficiency of chip verification.

[0121] To achieve the above embodiments, the present application further provides an electronic device, a computer-readable storage medium, and a computer program product.

[0122] Figure 8 It is a block diagram of an electronic device according to an embodiment of the present application. According to the Figure 8 electronic device shown, the simulation method of the multi-core mechanism of the Figures 1 to 5 embodiment can be implemented.

[0123] To achieve the above embodiments, the present application further provides a readable storage medium storing computer instructions, and the computer instructions are used to cause a computer to execute the Figures 1 to 5 simulation method of the multi-core mechanism of the embodiment.

[0124] To achieve the above embodiments, the present application further provides a computer program product. When the instruction processor in the computer program product executes, it executes the Figures 1 to 5 simulation method of the multi-core mechanism of the embodiment.

[0125] In the description of this specification, the descriptions referring to terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0126] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0127] Any process or method description in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process. And the scope of the preferred embodiments of the present application includes additional implementations, where the functions can be executed in a way that is not shown or discussed, including in a substantially simultaneous manner according to the involved functions or in a reverse order, which should be understood by those skilled in the art of the embodiments of the present application.

[0128] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a definite sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch instructions from the instruction execution system, apparatus, or device and execute the instructions), or used in combination with these instruction execution systems, apparatuses, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other suitable processing as necessary, and then stored in a computer memory.

[0129] It should be understood that various parts of the present application can be implemented using hardware, software, firmware, or combinations thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0130] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0131] In addition, each functional unit in various embodiments of the present application may be integrated into one processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0132] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A simulation method for a multi-core mechanism, characterized in that, Including: During the running process of a test case, if it is identified that in the test case, there are multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to completion, then it is determined that the test case meets the parallel condition; In response to the test case meeting the parallel condition, it is determined that the test case has multiple target test sequences that can be parallelized in the same time batch; Configure a matching target simulation core for each target test sequence; Based on the target simulation cores, run each target test sequence in parallel until all the multiple target test sequences in the same time batch are run to completion; Continue to run the next test sequence in the test case until the test case is run to completion. The next test sequence refers to a test sequence that cannot be parallelized with other to-be-run test sequences, or multiple parallelizable test sequences in the next time batch adjacent to the current time batch.

2. The method according to claim 1, wherein The multiple target test sequences are the multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to completion.

3. The method according to claim 2, wherein The configuring a matching target simulation core for each target test sequence includes: In response to the existence of an available simulation core, configure the matching target simulation core for the target test sequence based on the available simulation core; In response to the non-existence of an available simulation core, place the target test sequence in the to-be-run queue until a matching target simulation core is configured.

4. The method according to claim 3, characterized in that, The in response to the existence of an available simulation core, configure the matching target simulation core for the target test sequence based on the available simulation core includes: Identify that the unoccupied space of the running simulation core is greater than or equal to the running space of the target test sequence, then use the running simulation core as the available simulation core; In response to the simulation environment provided by the available simulation core matching the to-be-run function corresponding to the target test sequence, determine the available simulation core as the target simulation core.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: In response to the test case not meeting the parallel condition, perform simulation on the test case based on the running simulation core until the simulation is completed.

6. A simulation device with a multi-core mechanism, characterized in that, Including: An identification module, used during the running process of a test case, to identify that in the test case, there are multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to completion, then determine that the test case meets the parallel condition; in response to the test case meeting the parallel condition, determine that the test case has multiple target test sequences that can be parallelized in the same time batch; A configuration module, used to configure a matching target simulation core for each target test sequence; A parallel module, used to run each target test sequence in parallel based on the target simulation cores until all the multiple target test sequences in the same time batch are run to completion; A simulation module, used to continue to run the next test sequence in the test sequence until the test case is run to completion. The next test sequence refers to a test sequence that cannot be parallelized with other to-be-run test sequences, or multiple parallelizable test sequences in the next time batch adjacent to the current time batch.

7. The device according to claim 6, characterized in that, The multiple target test sequences are the multiple to-be-run test sequences that have no dependency relationship and can continue to run the next test sequence after running to completion.

8. The device according to claim 7, characterized in that, The configuration module is further configured to: In response to the existence of available simulation cores, configure the matching target simulation cores for the target test sequences based on the available simulation cores; In response to the non-existence of available simulation cores, place the target test sequences in a to-be-run queue until the matching target simulation cores are configured.

9. The device according to claim 8, wherein The configuration module is further configured to: Identify that the unoccupied space of the running simulation core is greater than or equal to the running space of the target test sequence, and then use the running simulation core as the available simulation core; In response to the simulation environment provided by the available simulation core matching the to-be-run function corresponding to the target test sequence, determine the available simulation core as the target simulation core.

10. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-5.

11. A readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the method according to any one of claims 1-5.

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