Non-volatile memory and data reading method thereof and storage system

Abstract

The application discloses a nonvolatile memory, a data reading method and a storage system. The memory comprises storage units and word lines, and the storage units in the same row are connected to the same word line. The method comprises a pre-activation stage and a reading stage. In the pre-activation stage, the voltage of the word line adjacent to the word line of the selected storage unit is raised to a first level; in the reading stage, the voltage of the word line of the selected storage unit is raised to an initial reading level, and the voltage of the adjacent word line is raised to a second level. The method comprises at least one reading operation for reading the storage unit in a low programming state, a medium programming state and a high programming state. The initial reading level is a reading level for reading any one of the low programming state and the medium programming state, and the first level is greater than a reading level for reading the high programming state. The method can slow down the coupling effect between the word lines, reduce the reading interference related to the potential difference in the data reading, and compress the reading period.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a non-volatile memory, a data reading method for the non-volatile memory, and a storage system. Background Technology

[0002] During the reading process of non-volatile memory, it is usually necessary to raise the voltage of the word line outside the storage row where the selected memory cell is located in the selected memory cell string to the on level, and raise the voltage of the word line of the selected memory cell to the read level, so as to turn on the channel of the selected memory cell string, thereby realizing the reading of the information in the selected memory cell.

[0003] However, with the increasing demand for higher storage density in non-volatile memory, the number of stacked layers in non-volatile memory, such as 3D NMR, is constantly increasing. The length of the channels in their structure is also increasing in the vertical direction. Furthermore, the gate-to-gate spacing of memory cells is continuously decreasing in order to achieve even higher storage density. Therefore, the increase in storage density of non-volatile memory leads to more data retrieval problems.

[0004] Therefore, how to achieve efficient data reading from non-volatile memory is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In order to solve or partially solve the above-mentioned or other problems existing in the related art, various embodiments are proposed, which will be further described below in this application.

[0006] One aspect of this application provides a data reading method for a non-volatile memory. The method includes a pre-conduction phase and a read phase performed sequentially. The memory includes memory cells and word lines, wherein memory cells in the same row are connected to the same word line. The method includes: in the pre-conduction phase, raising the voltage of an adjacent word line adjacent to a selected memory cell word line to a first level; and in the read phase, raising the voltage of the selected memory cell word line to its initial read level and raising the voltage of the adjacent word lines to a second level. The method includes at least one read operation performed according to a low programming state, a medium programming state, and a high programming state of the memory cell; the initial read level is a read level for reading either the low programming state or the medium programming state; and the first level is greater than the read level for reading the high programming state.

[0007] According to one embodiment of this application, the memory includes a memory cell string, a common source terminal, and a bit line, wherein the memory cell string includes a bottom select gate transistor, the memory cell, and a top select gate transistor connected in series, the bit line is connected to the top select gate transistor, and the common source terminal is connected to the bottom select gate transistor. The method further includes: during the pre-conduction phase, increasing the voltage of at least one of the bit line and the common source terminal to a pre-charge level.

[0008] According to one embodiment of this application, during the period when the voltage of at least one of the bit line and the common source terminal rises to the precharge level, the voltage of the adjacent word line is raised to the first level.

[0009] According to one embodiment of this application, the word lines include the selected memory cell word lines and the unselected memory cell word lines, the unselected memory cell word lines include the adjacent word lines and other memory cell word lines, and the method further includes: during the period when the voltage of the adjacent word lines rises to the first level, raising the voltage of the other memory cell word lines to a pass level, wherein the pass level is greater than the read level for reading the high programming state.

[0010] According to one embodiment of this application, the first level is greater than or equal to the pass level.

[0011] According to one embodiment of this application, raising the voltage of the adjacent word line to a second level includes: during the pre-conduction phase, continuously raising the voltage of the adjacent word line to the first level and then maintaining it at the first level; and during the read phase, continuously raising the voltage of the adjacent word line from the first level to the second level.

[0012] According to one embodiment of this application, raising the voltage of the adjacent word line to a second level includes: raising the voltage of the adjacent word line to the first level with a first slope; and raising the voltage of the adjacent word line from the first level to the second level with a second slope, wherein the first slope is greater than the second slope.

[0013] According to one embodiment of this application, the adjacent word lines include one or more word lines located on either side of the selected memory cell word line and adjacent to the selected memory cell word line, wherein the number of adjacent word lines is less than or equal to 5.

[0014] According to one embodiment of this application, the memory cell is a floating gate transistor or a charge trapping transistor, and the memory cell is any one of a single-level cell type, a multi-level cell type, a three-level cell type, a four-level cell type, and a five-level cell type.

[0015] Another aspect of this application provides a non-volatile memory, the non-volatile memory comprising: a memory cell array including memory cells and word lines, wherein memory cells in the same row are connected to the same word line; and a control circuit coupled to the memory cell array and configured to perform a data read operation on selected memory cells in the memory cell array as described in any one of the data read methods for non-volatile memory provided in this application.

[0016] According to one embodiment of this application, the storage cell array is a three-dimensional NAND storage cell array, and the non-volatile memory is a three-dimensional NAND memory.

[0017] Another aspect of this application provides a storage system comprising: at least one processor; and a non-volatile memory communicatively connected to the at least one processor, wherein the non-volatile memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform a data read operation as described in any one of the data read methods for non-volatile memory provided in this application. According to at least one embodiment of the non-volatile memory, data read method, and storage system provided in this application, while ensuring that the conduction level applied to the channels on adjacent word lines for turning on selected memory cell strings has a relatively high voltage value to mitigate the coupling effect between word lines affecting data read reliability, the conduction level on the adjacent word lines is formed in stages, thereby reducing read interference related to potential difference during data read and compressing the read time period of the non-volatile memory.

[0018] Furthermore, in at least one embodiment of this application, during the formation of the initial read level on the selected word line to be read, a coupling voltage can be generated on the selected word line through a voltage ramp on adjacent word lines, thereby accelerating the voltage change on the selected word line and reducing the time required to reach the initial read level, thus compressing the read period of the non-volatile memory.

[0019] In at least one embodiment of this application, during the pre-conduction phase, increasing the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to the pre-charge level can increase the channel potential of the unselected memory string, making the channel potential equal to the pre-charge level, thereby reducing the potential difference between the channel potential of the unselected memory cell and its conduction level (which can be understood as the second level) during the read phase, thereby reducing read interference during the data read process.

[0020] Furthermore, simply increasing the channel potential of the unselected memory string by raising the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to a pre-charge level may result in insufficient channel potential pre-charge. Therefore, according to the data read method provided in at least one embodiment of this application, during the period of raising the voltage of at least one of the bit lines and common source terminals to the pre-charge level, only the voltage of the adjacent word lines is raised to a first level. This can alleviate the potential difference between the voltage applied to the adjacent word lines (which can be understood as the first level) and the channel potential, thereby reducing read interference caused by the potential difference. At the same time, it can also reduce the time for pre-charging the channel potential of the unselected memory string and compress the read period of the non-volatile memory. Attached Figure Description

[0021] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0022] Figure 1 A block diagram of a non-volatile memory according to one embodiment of this application is shown;

[0023] Figure 2 A circuit diagram of a non-volatile memory according to one embodiment of this application is shown;

[0024] Figure 3 The threshold voltage distribution of eight states of a TLC-type memory cell according to one embodiment of this application is shown.

[0025] Figure 4 A partial three-dimensional schematic diagram of a non-volatile memory according to one embodiment of this application is shown;

[0026] Figure 5 This is a flowchart of a data reading method for a non-volatile memory according to one embodiment of this application;

[0027] Figure 6 This application illustrates one embodiment of the method for... Figure 4 The timing diagram for reading from the memory cells shown;

[0028] Figure 7 This application illustrates another embodiment of the method for... Figure 4 The timing diagram for reading from the memory cell shown; and

[0029] Figure 8 This is a schematic diagram of a storage system according to one embodiment of this application. Detailed Implementation

[0030] Exemplary embodiments of the invention will now be described more fully below with reference to the accompanying drawings, in which preferred embodiments of the invention are illustrated. However, the invention may be embodied in various forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0031] It should also be understood that when a component or layer is referred to as being "on" another component or layer, "connected to," or "attached to" another component or layer, it may be directly on or directly connected to the other component or layer, or there may be a component or layer between them. However, when a component or layer is referred to as being "directly on" another component or layer, "directly connected to," or "directly attached to" another component or layer, there is no intermediate component or layer. Therefore, the term "connection" can refer to a physical connection, electrical connection, and / or fluid connection, with or without an intermediary element.

[0032] Throughout the specification, the same reference numerals denote the same components. In the accompanying drawings, the thickness of layers and regions is exaggerated for clarity.

[0033] While the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of one or more embodiments, the first level discussed below may be referred to as the second level. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," etc., may also be used herein to distinguish elements of different classes or groups. For the sake of brevity, the terms "first," "second," etc., may respectively represent "first class (or first group)," "second class (or second group)," etc.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the term "comprising" specifies the presence of the described features, areas, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, steps, operations, elements, components, and / or groups thereof.

[0035] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that, in addition to the orientations depicted in the figures, relative terms are intended to encompass different orientations of the device. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the exemplary term “down” can encompass both “down” and “up” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “up” and “down” orientations.

[0036] Figure 1 A block diagram of a non-volatile memory 100 according to one embodiment of this application is shown.

[0037] like Figure 1 As shown, the non-volatile memory 100 includes a memory cell array 110 coupled together with a control circuit 101 (such as...). Figure 1 (As shown in the dashed box). In some embodiments, the memory cell array 110 and the control circuitry 101 may be arranged on the same chip. In other embodiments, the memory cell array 110 may be arranged on an array chip, and the control circuitry 101 may be arranged on another chip (e.g., implemented using complementary metal-oxide-semiconductor (CMOS) technology, and referred to as a CMOS chip). The array chip and the CMOS chip may be electrically coupled together by processes such as bonding. In some embodiments, the non-volatile memory 100 is an integrated circuit (IC) package that encapsulates one or more array chips and CMOS chips.

[0038] The non-volatile memory 100 can be configured to store data in the memory cell array 110 and perform operations in response to received commands (CMDs). In some embodiments, the non-volatile memory 100 can receive write commands, read commands, erase commands, etc., and can perform operations accordingly.

[0039] In some implementations, the storage cell array 110 is a flash memory array and can be implemented using technologies such as 3D NAND flash memory. In some implementations, the peripheral circuitry 101 may include an address decoder 120, input / output circuitry 130, and control logic 140.

[0040] Furthermore, the memory cell array 110 can be connected to the address decoder 120 via word line WL, at least one serial select line SSL, and at least one ground select line GSL. The memory cell array 110 can be connected to the input / output circuitry 130 via bit line BL.

[0041] The memory cell array 110 may include multiple memory blocks BLK1 to BLKz. Alternatively, each of the memory blocks BLK1 to BLKz may include multiple memory cell strings (not shown), arranged along an x-direction, a y-direction other than the x-direction, and a z-direction (e.g., the z-direction can be understood as a direction perpendicular to the plane formed by the x-direction and the y-direction) to have a three-dimensional structure. Furthermore, each memory cell string may include at least one top select transistor (not shown), multiple memory cells (not shown), and at least one bottom select transistor (not shown) stacked on a substrate (not shown) and connected in series. Each memory cell may store at least one data bit.

[0042] Address decoder 120 can be connected to memory cell array 110 via word line WL, serial select line SSL, and ground select line GSL. Address decoder 120 can use the decoded row address to select word line WL, serial select line SSL, and ground select line GSL. Address decoder 120 can decode the column address of input address ADDR. The decoded column address DCA can be provided to input / output circuitry 130. Alternatively, address decoder 120 may include row decoder, column decoder, address buffer, etc.

[0043] Input / output circuitry 130 can be connected to memory cell array 110 via bit line BL. Input / output circuitry 130 can be configured to receive decoded column address DCA from address decoder 120. Input / output circuitry 130 can use the decoded column address DCA to select bit line BL. Input / output circuitry 130 can receive data from an external device to store it at memory cell array 110. Input / output circuitry 130 can read data from memory cell array 110 to output it to an external device; alternatively, input / output circuitry 130 can read data from a first region of memory cell array 110 to store it at a second region of memory cell array 110.

[0044] Control logic 140 controls the overall operation of non-volatile memory 100, including programming, reading, and erasing operations. Control logic 140 can operate in response to control signals or commands provided from external devices. Control logic 140 can provide a interference-free read mode 142 to control the channel charge of the memory cell string to mitigate read interference.

[0045] For example, the control logic 140 in the control circuit 101 can control the address decoder 120 and the input / output circuit 130 to perform data reading operations on selected memory cells in the memory array 110 according to the data reading method provided in at least one embodiment of this application. While ensuring that the conduction level applied to the word line adjacent to the selected memory cell and used to turn on the channel of the selected memory cell string has a relatively high voltage value to mitigate the coupling effect between word lines affecting the reliability of data reading, the conduction level on the adjacent word lines can also be formed in stages, thereby reducing read interference related to potential difference during data reading and compressing the read time period for non-volatile memory.

[0046] Figure 2 A circuit diagram of a non-volatile memory 100 according to one embodiment of this application is shown.

[0047] like Figure 2 As shown, taking a NAND flash memory circuit as an example, the circuit of the non-volatile memory 100 may include memory cells C(1,1) to C(P,N), top select cells Tss(1) to Tss(P), and bottom select cells Tgs(1) to Tgs(P). The memory cells C(1,1) to C(P,N) may be arranged into N rows R(1) to R(N) coupled to each word line WL(1) to WL(N). In a read operation, data may be read from memory cells C(1,1) to C(P,N) row by row from R(1) to R(N) or from R(N) to R(1), which is not limited in this application.

[0048] Each of the memory cells C(1,1) to C(P,N), the top selection cells Tss(1) to Tss(P) and the bottom selection cells Tgs(1) to Tgs(P) can be considered as a transistor (e.g., each of the top selection cells Tss(1) to Tss(P) can be understood as a top selection transistor; each of the bottom selection cells Tgs(1) to Tgs(P) can be understood as a bottom selection transistor), and may include a control terminal, a first terminal and a second terminal.

[0049] Furthermore, the serial select line SSL can be coupled to the control terminals of the top select units Tss(1) to Tss(P), and the bit lines BL(1) to BL(P) can be coupled to the first terminals of the top select units Tss(1) to Tss(P), respectively. The word lines WL(1) to WL(N) can be coupled to the control terminals of the memory cells C(1,1) to C(P,1) of the first row, up to the control terminals of the memory cells C(1,N) to C(P,N) of the Nth row, and the first terminals of the memory cells C(1,1) to C(P,1) can be coupled to the second terminals of the top select units Tss(1) to Tss(P), respectively. The ground selection line GSL can be coupled to the control terminals of the bottom selection units Tgs(1) to Tgs(P), the first terminals of the bottom selection units Tgs(1) to Tgs(P) can be coupled to the second terminals of the storage units C(1,N) to C(P,N) respectively, and the second terminals of the bottom selection units Tgs(1) to Tgs(P) can be coupled to the common source terminal.

[0050] The memory cells C(1,1) to C(P,N) can be floating gate transistors or charge trapping transistors, and the memory cells C(1,1) to C(P,N) can be single-level cell (SLC), multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), five-level cell (PLC) or higher-level types. This application does not limit the specific type of memory cell.

[0051] Each of the memory cells C(1,1) to C(P,N) can hold one of Q possible states, where Q is a positive integer equal to or greater than 2. For example, for a QLC type memory cell, Q = 2; for an MLC type memory cell, Q = 4; for a TLC type memory cell, Q = 8; for a QLC type memory cell, Q = 16; and for a PLC type memory cell, Q = 32. The Q possible states may include erase state S(0) and programming states S(1) to S(Q-1). For example, the eight possible states of a TLC type memory cell may include erase state S(0) and programming states S(1) to S(7).

[0052] Figure 3 The threshold voltage distribution of eight states of a TLC-type memory cell according to one embodiment of this application is shown.

[0053] like Figure 3As shown, taking a TLC type memory cell as an example, its eight possible states include erase state S(0) and programming states S(1) to S(7), where the threshold voltage distributions corresponding to erase state S(0) and programming states S(1) to S(7) are distributions of 30 to 37, respectively. Programming state S(1) is a low programming state, while programming state S(7) is a high programming state. In the read operation, the read levels Vr(1) to Vr(7) can be used to read the holding state of any one of the memory cells C(1,1) to C(P,N). Each read level Vr(q) can be set between the maximum threshold voltage of the threshold voltage distribution of state S(q-1) and the minimum threshold voltage of the threshold voltage distribution of state S(q) to distinguish the state of any one of the memory cells C(1,1) to C(P,N), where q is an integer and 1≤q≤7. For example, the read level Vr(1) can be set between the maximum threshold voltage of distribution 30 of the erase state S(0) and the minimum threshold voltage of distribution 31 of the programming state S(1). The read level Vr(1) (which can be understood as the low programming state of the memory cell) or any of the read levels Vr(2) to Vr(6) (which can be understood as the medium programming state of the memory cell) can be the initial read level to be applied to the word line of the selected memory cell.

[0054] Figure 4 A partial three-dimensional schematic diagram of a non-volatile memory 100 according to one embodiment of this application is shown.

[0055] like Figure 4 As shown, taking a local structure of a 3D NAND type memory with a vertical channel structure as an example, the non-volatile memory 100 may include a plurality of approximately vertically arranged memory cell strings 211 and 212, wherein each memory cell string 211 and 212 may include at least one bottom select gate transistor, a plurality of memory cells (black dots in the figure represent memory cells) connected in series and at least one top select gate transistor, wherein the bit line is connected to the top select gate transistor and the common source terminal is connected to the bottom select gate transistor.

[0056] For example, a memory cell string 211 may include three memory cells 201. One end of the memory cell string 211 is connected in series with a top select gate transistor 241, and the other end is connected in series with a bottom select gate transistor 231. A first string select word line 251 is connected to the gates of multiple bottom select gate transistors 231. Therefore, multiple memory cell strings 211 connected to multiple bottom select gate transistors 231 belong to the same memory string group, which can be called the first memory string group; similarly, multiple memory cell strings 212 connected to multiple bottom select gate transistors 232 belong to another memory string group, which can be called the second memory string group. One end of the memory cell string 211 in the first memory string group is connected to the common source terminal 220 through the bottom select gate transistor 231. Similarly, one end of the memory cell string 212 in the second memory string group is connected to the common source terminal 220 through the bottom select gate transistor 232. In other words, the bottom select gate transistors 231 and 232 of different memory string groups are all connected to the common source terminal 220. The non-volatile memory 100 also includes multiple bit lines 271 and 272, which are connected to one end of multiple memory cell strings 211 via top select gate transistor 241; or bit lines 271 and 272 are connected to one end of multiple memory cell strings 212 via top select gate transistor 242. Furthermore, a second string select word line 261 is connected to the gate of the top select gate transistor 241 belonging to the first memory string group; and a second string select word line 262 is connected to the gate of the top select gate transistor 242 belonging to the second memory string group.

[0057] Although the above embodiments of this application show a device including two memory string groups, it is understood that the embodiments are only partial structural schematic diagrams of the non-volatile memory of this application, and are not intended to limit the number of memory string groups, the number of memory cells in the memory string, the number of bottom select gate transistors and top select gate transistors, etc. in the non-volatile memory of this application.

[0058] exist Figure 4 In the partial structure of the non-volatile memory 100 shown, the memory cells are arranged in an array in three-dimensional space. Multiple memory cells located in the same layer form a memory row. The gates of memory cells located in different memory cell strings but in the same memory row are physically connected and are all connected to the same word line. For example, word line 281, word line 282 and word line 283 connect memory cells located in different memory rows.

[0059] When performing a read operation on a specific memory cell in the non-volatile memory 100, it is necessary to determine the memory string and memory row containing the selected memory cell. This memory row can be determined by the word line connected to the selected memory cell. For example, with Figure 4The storage cell 201 circled in the middle is the selected storage cell to be read. The storage cell string 211 where the selected storage cell 201 is located is the selected storage cell string. The word line connected to the selected storage row where the selected storage cell 201 is located is the word line 282, which is called the selected storage cell word line 282.

[0060] Figure 5 A flowchart of a data reading method 1000 for a non-volatile memory according to one embodiment of this application is shown. Figure 6 This application illustrates one embodiment of the method for... Figure 4 The timing diagram shows the reading of the memory cell shown. Figure 7 This application illustrates another embodiment of the method for... Figure 4 The timing diagram shows the reading of the memory cell shown.

[0061] like Figures 4 to 7 As shown, a data read method for non-volatile memory may include a pre-on phase 01, a read phase 02, and a pre-off phase performed sequentially. At least one embodiment of this application provides a data read method including at least one read operation performed according to the low programming state, medium programming state, and high programming state of the selected memory cell 201. The non-volatile memory data read method 1000 may include:

[0062] In step S1, during the pre-conduction phase 01 (time t0 to t2), the voltages of adjacent word lines 281 and 283 adjacent to the selected memory cell word line 282 are raised to a first level, wherein the first level is greater than the read level of the high programming state used to read the selected memory cell 201.

[0063] In step S2, during the read phase 02 (times t2 to t5), the voltage of the selected memory cell word line 282 is increased to its initial read level, and the voltages of adjacent word lines 281 and 283 are increased to a second level, wherein the initial read level is the read level used to read either the low programming state or the medium programming state of the selected memory cell 201.

[0064] Specifically, refer to Figure 4 , Figure 6 and Figure 7During the read phase 02, a drive voltage can be applied to bit lines 271 and 272, and an on-state voltage can be applied to the first string select word line 251 and the second string select word line 261 of the selected memory cell string, turning on the bottom select gate transistor 231 and the top select gate transistor 241 of the selected memory cell string containing the selected memory cell 201. Furthermore, an off-state voltage can be applied to the bottom select gate transistor 232 and the top select gate transistor 242 of the non-selected memory cell string, turning off the bottom select gate transistor 232 and the top select gate transistor 242 of the non-selected memory cell string, disconnecting the channel of the non-selected memory cell string from the bit lines. The channel potential of the non-selected memory cell string is locked at a low potential, preventing the channel of the non-selected memory cell string from being turned on.

[0065] The word lines of the non-volatile memory 100 include selected memory cell word line 282 and unselected memory cell word lines (not shown). The unselected memory cell word lines include adjacent word lines 281, 283 and other memory cell word lines (not shown). During the read phase 02, the voltages of adjacent word lines 281 and 283 outside the memory row containing the selected memory cell 201 in the selected memory cell string can be increased to, for example, a second level, and the voltages of other memory cell word lines outside the memory row containing the selected memory cell 201 in the selected memory cell string can be increased to, for example, a pass level. Both the second level and the pass level are used to turn on the channel of the selected memory cell string, and therefore their voltage values ​​are both greater than the read level of the high-programmed state used to read the selected memory cell 201. The voltage of the selected memory cell word line 282 is increased to the initial read level, thereby allowing the information within the selected memory cell 201 to be read.

[0066] The inventors of this application have discovered that for memory cells located in non-selected rows on non-selected memory cell strings (e.g., memory cell 202), since the channel potential of this type of memory cell is originally low, it is affected by the second level on its word line 283 during the read phase 02, resulting in a potential difference between the channel potential and the second level, thereby causing HCI (Hot Carrier Injection) read interference (hereinafter referred to as read interference); for memory cells located in selected rows on non-selected memory cell strings (e.g., memory cell 203), since the channel potential of this type of memory cell is originally low, it is affected by the initial read level on its word line 282 during the read phase 02, resulting in a potential difference between the channel potential and the initial read level, thereby causing read interference; for non-selected memory cells located on selected memory cell strings (e.g., memory cell 204), during the read phase 02, read interference is caused by the potential difference between the second level and the driving voltage.

[0067] Furthermore, the inventors of this application have discovered that the aforementioned read interference is related to the potential difference that causes it; the larger the potential difference, the stronger the read interference. Therefore, the greater the second level (the level used to turn on the channel of the selected memory cell string) applied to adjacent word lines during the read phase, or the greater the pass level (the level used to turn on the channel of the selected memory cell string) applied to other memory cell word lines, the greater the read interference caused to the memory cell. For example, for the three types of non-selected memory cells 202, 203, and 204 described above, the read interference experienced by the non-selected memory cell 204 located on the selected memory cell string is less than that experienced by the other two types of memory cells 202 and 203.

[0068] Furthermore, with the increasing demand for higher storage density in non-volatile memory, the number of stacked layers in non-volatile memory such as 3D memory is constantly increasing, and the length of the channel in its structure is also constantly increasing in the vertical direction. In addition, the gate-to-gate spacing of memory cells is also constantly decreasing in order to achieve higher storage density. However, this situation will lead to the need to increase the conduction level applied to adjacent word lines (which can be understood as a second level) to mitigate the coupling effect between word lines that affects the reliability of data read.

[0069] Therefore, according to at least one embodiment of the non-volatile memory data reading method provided in this application, while ensuring that the conduction level (which can be understood as the second level) applied to the adjacent word lines for conducting the selected memory cell string has a relatively high voltage value to reduce the coupling effect between word lines that affects the reliability of data reading, the conduction level on the adjacent word lines is formed in stages to reduce the read interference related to the potential difference.

[0070] Specifically, as an option, such as Figure 4 and Figure 6 As shown, in one embodiment of this application, during the pre-conduction phase 01, the voltages of adjacent word lines 281 and 283 adjacent to the selected memory cell word line 282 can be increased to a first level, which can be greater than the read level of the high programming state used to read the selected memory cell 201. After the voltages of adjacent word lines 281 and 283 are increased to the first level, the voltages of adjacent word lines 281 and 283 can be maintained at the first level.

[0071] During read phase 02, the voltage of the selected memory cell word line 282 can be increased to its initial read level, which is the read level used for reading either the low programming state or the medium programming state of the selected memory cell 201. Furthermore, while the voltage of the selected memory cell word line 282 is increasing to its initial read level, the voltages of adjacent word lines 281 and 283 can be continuously increased from a first level to a second level. Therefore, during times t2 to t3, a coupling voltage can be generated on the selected word line 282 through the voltage ramps on adjacent word lines 281 and 283, thereby accelerating the voltage change on the selected word line 282 and reducing the time required to reach the initial read level, thus compressing the read period of the non-volatile memory.

[0072] Additionally, during the pre-conduction phase 01, while the voltages of adjacent word lines 281 and 283 rise to a first level, the voltages of other memory cell word lines (not shown) can also be raised to a pass level, wherein the pass level is greater than the read level of the high programming state used to read the selected memory cell 201, so that the channel of the selected memory cell string can be turned on.

[0073] In one embodiment of this application, the first level applied to adjacent word lines 281 and 283 can be set to be greater than or equal to the pass level applied to other memory cell word lines in order to mitigate the coupling effect between word lines that affects the reliability of data reading.

[0074] Refer again Figure 4 In one embodiment of this application, the adjacent word lines of the selected memory cell word line 282 include word lines 281 and 283 located on either side of the selected memory cell word line 282 and adjacent to the selected memory cell word line 282. Alternatively, the adjacent word lines of the selected memory cell word line can be one or more word lines, and the number of adjacent word lines can be, for example, less than or equal to 5. In other words, adjacent word lines can include one or more word lines located on either side of the selected memory cell word line and adjacent to the selected memory cell word line.

[0075] Refer again Figure 4 and Figure 6 In one embodiment of this application, in order to further mitigate the readout interference related to the potential difference, the voltage of at least one of the bit lines 271, 272 and the common source terminal 220 may be increased to the pre-charge level during the pre-conduction phase 01.

[0076] Alternatively, the precharge level applied to bit lines 271, 272 can be the same as or different from the precharge level applied to the common source terminal 220. Alternatively, during the pre-on phase 01, the voltages of bit lines 271, 272 and the common source terminal 220 can be simultaneously increased to the precharge level.

[0077] Additionally, the voltages of adjacent word lines 281 and 283 can be raised to a first level during the period when the voltages of at least one of bit lines 271, 272 and common source terminal 220 are raised to a precharge level.

[0078] By raising the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to the pre-charge level during the pre-conduction phase, the channel potential of the unselected memory string can be increased to make the channel potential equal to the pre-charge level. This reduces the potential difference between the channel potential of the unselected memory cell and its on-state voltage (which can be understood as the second level or pass level) during the read phase, thereby reducing read interference during the data read process.

[0079] Furthermore, simply increasing the channel potential of the unselected memory string by raising the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to a pre-charge level may result in insufficient channel potential pre-charge. Therefore, according to the data read method provided in at least one embodiment of this application, raising the voltage of adjacent word lines to a first level only during the period of raising the voltage of at least one of the bit lines and common source terminals to the pre-charge level can mitigate the potential difference between the voltage applied to adjacent word lines and the channel potential, thereby reducing read interference caused by the potential difference. At the same time, it can also reduce the time of pre-charging the channel potential of the unselected memory string and compress the read period of the non-volatile memory.

[0080] As another option, such as Figure 4 and Figure 7 As shown, in another embodiment of this application, during the pre-conduction phase 01, the voltages of adjacent word lines 281 and 283 adjacent to the selected memory cell word line 282 are increased to a first level with a first slope. The first level may be greater than the read level of the high programming state used to read the selected memory cell 201. Furthermore, the first level in this embodiment may be equal to the first level in the previous embodiment; or, the first level in this embodiment may not be equal to the first level in the previous embodiment.

[0081] After the voltages of adjacent word lines 281 and 283 are raised to the first level, the voltages of adjacent word lines 281 and 283 can be further raised to the second level with a second slope, wherein the first slope is greater than the second slope. Setting the first slope to be relatively large can reduce the time required to set the conduction voltage (which can be understood as the second voltage) of adjacent word lines.

[0082] In read phase 02, the voltage of the selected memory cell word line 282 can be increased to its initial read level, which is the read level used to read either the low programming state or the medium programming state of the selected memory cell 201. Between times t2 and t3, a coupling voltage can be generated on the selected word line 282 through voltage ramps on adjacent word lines 281 and 283, thereby accelerating the voltage change on the selected word line 282 and reducing the time required to reach the initial read level, thus compressing the read period for the non-volatile memory.

[0083] Additionally, during the pre-conduction phase 01, while the voltages of adjacent word lines 281 and 283 rise to a first level, the voltages of other memory cell word lines (not shown) can also be raised to a pass level, wherein the pass level is greater than the read level of the high programming state used to read the selected memory cell 201, so that the channel of the selected memory cell string can be turned on.

[0084] In one embodiment of this application, the first level applied to adjacent word lines 281 and 283 can be set to be greater than the pass level applied to other memory cell word lines in order to mitigate the coupling effect between word lines that affects the reliability of data reading.

[0085] Refer again Figure 4 In one embodiment of this application, the adjacent word lines of the selected memory cell word line 282 include word lines 281 and 283 located on either side of the selected memory cell word line 282 and adjacent to the selected memory cell word line 282. Alternatively, the adjacent word lines of the selected memory cell word line can be one or more word lines, and the number of adjacent word lines can be, for example, less than or equal to 5. In other words, adjacent word lines can include one or more word lines located on either side of the selected memory cell word line and adjacent to the selected memory cell word line.

[0086] Refer again Figure 4 and Figure 7 In one embodiment of this application, in order to further mitigate the readout interference related to the potential difference, the voltage of at least one of the bit lines 271, 272 and the common source terminal 220 may be increased to the pre-charge level during the pre-conduction phase 01.

[0087] Alternatively, the precharge level applied to bit lines 271, 272 can be the same as or different from the precharge level applied to the common source terminal 220. Alternatively, during the pre-on phase 01, the voltages of bit lines 271, 272 and the common source terminal 220 can be simultaneously increased to the precharge level.

[0088] In addition, the voltages of adjacent word lines 281 and 283 can be raised to a first level during the period when the voltages of at least one of the bit lines 271, 272 and the common source terminal 220 are raised to the precharge level.

[0089] By raising the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to the pre-charge level during the pre-conduction phase, the channel potential of the unselected memory string can be increased to make the channel potential equal to the pre-charge level. This reduces the potential difference between the channel potential of the unselected memory cell and its on-state voltage (which can be understood as the second level or pass level) during the read phase, thereby reducing read interference during the data read process.

[0090] Furthermore, simply increasing the channel potential of the unselected memory string by raising the voltage of at least one of the bit lines and common source terminals of the non-volatile memory to a pre-charge level may result in insufficient channel potential pre-charge. Therefore, during the period of raising the voltage of at least one of the bit lines and common source terminals to the pre-charge level, the data read method provided in at least one embodiment of this application only raises the voltage of adjacent word lines to a first level, which can reduce the potential difference between the voltage applied to adjacent word lines and the channel potential, thereby reducing read interference caused by the potential difference. At the same time, it can also reduce the time of pre-charging the channel potential of the unselected memory string and compress the read period of the non-volatile memory.

[0091] Figure 8 This is a schematic diagram of a storage system 3000 according to one embodiment of this application.

[0092] like Figure 8 As shown, this application also provides a storage system 3000. The storage system 3000 includes at least one processor 3100 and a non-volatile memory 3200 (e.g., memory connected in communication with the at least one processor 3100) that is also in communication with the processor 3100. Figure 8 The memory shown (hereinafter referred to as memory 3200) and the interfaces for connecting the various components, including but not limited to high-speed interfaces and low-speed interfaces.

[0093] Processor 3100 can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to an interface). In other embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take the 3100 processor as an example.

[0094] The memory 3200 is the non-volatile memory provided in this application. The memory stores instructions executable by at least one processor to cause the at least one processor to perform any one of the data read operations described in the data read method for the non-volatile memory provided in this application.

[0095] The memory 3200, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules. The processor 3100 executes various functional applications and data processing of the server by running the non-transitory software programs, instructions, and modules stored in the memory 3200, thereby implementing the data reading method of the non-volatile memory in the above method embodiment.

[0096] The memory 3200 may include high-speed random access memory, and may also include non-transient memory, such as at least one disk storage device, flash memory device, or other non-transient solid-state storage device.

[0097] In addition, the storage system 3000 may also include an input device 3300 and an output device 3400. The processor 3100, memory 3200, input device 3300, and output device 3400 can be connected via a bus or other means. Figure 8 The example given is a bus connection. The above description is merely an illustration of the embodiments of this application and the principles of the applied technology. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-mentioned technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-mentioned technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for reading data from a non-volatile memory, characterized in that, The method includes a pre-conduction phase and a read phase performed sequentially. The memory includes a memory cell string, a common-source terminal, a bit line, and a word line. The memory cell string includes a bottom select-gate transistor, a memory cell, and a top select-gate transistor connected in series. The bit line is connected to the top select-gate transistor, and the common-source terminal is connected to the bottom select-gate transistor. Multiple memory cells located in different memory cell strings but within the same layer form a memory row. Memory cells in the same memory row are connected to the same word line. The method includes: During the pre-conduction phase, the voltage of at least one of the bit lines and the common-source terminal is increased to a pre-charge level, and the voltage of the adjacent word line adjacent to the selected memory cell word line is increased to a first level; and During the read phase, the voltage of the selected memory cell word line is increased to its initial read level, and the voltage of the adjacent word line is increased to a second level. The method includes at least one read operation that reads the memory cell according to its low programming state, medium programming state, and high programming state. The initial read level is a read level used to read either the low programming state or the medium programming state; and The first level is greater than the read level used to read the high programming state.

2. The method according to claim 1, characterized in that, During the voltage rise to the pre-charge level of at least one of the bit line and the common source terminal, Increase the voltage of the adjacent word line to the first level.

3. The method according to any one of claims 1 to 2, characterized in that, The word lines include the selected memory cell word lines and the unselected memory cell word lines, the unselected memory cell word lines include the adjacent word lines and other memory cell word lines, and the method further includes: During the period when the voltage of the adjacent word line rises to the first level, the voltage of the other memory cell word lines is raised to the pass level. Wherein, the pass level is greater than the read level used to read the high programming state.

4. The method according to claim 3, characterized in that, The first level is greater than or equal to the pass level.

5. The method according to any one of claims 1 to 2, characterized in that, During the pre-conduction phase, the voltage of the adjacent word lines is continuously increased to the first level and then maintained at the first level. as well as During the reading phase, the voltage of the adjacent word lines is continuously increased from the first level to the second level.

6. The method according to any one of claims 1 to 2, characterized in that, Increase the voltage of the adjacent word lines to the first level with a first slope; as well as The voltage of the adjacent word lines is increased from the first level to the second level with a second slope. Wherein, the first slope is greater than the second slope.

7. The method according to any one of claims 1 to 2, characterized in that, The adjacent word lines include one or more word lines located on either side of the selected memory cell word line and adjacent to the selected memory cell word line. The number of adjacent character lines is less than or equal to 5.

8. The method according to any one of claims 1 to 2, characterized in that, The memory cell is a floating gate transistor or a charge trapping transistor, and the memory cell is any one of the following types: single-level cell, multi-level cell, three-level cell, four-level cell, and five-level cell.

9. A non-volatile memory, characterized in that, The non-volatile memory includes: A storage array includes storage cells and word lines, wherein storage cells in the same row are connected to the same word line. A control circuit, coupled to the storage array, is configured to perform a data read operation on a selected storage cell in the storage array using the data read method for a non-volatile memory according to any one of claims 1-8.

10. The non-volatile memory according to claim 9, characterized in that, The storage array is a three-dimensional NAND storage array, and the non-volatile memory is a three-dimensional NAND memory.

11. A storage system, characterized in that, The storage system includes: At least one processor; and Non-volatile memory communicatively connected to the at least one processor The non-volatile memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method according to any one of claims 1-8.

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