Display panel, its manufacturing method, and display device

Abstract

An embodiment of the present application provides a display panel, a manufacturing method thereof, and a display device. The display panel includes a display area and a non-display area surrounding the display area, and the non-display area includes a public area; the part of the display panel located in the public area includes: a substrate, a common electrode, an insulating layer, and a dam layer stacked in sequence, the insulating layer has a first trench, and the first trench is located on the side of the dam layer away from the display area; the orthographic projection of the common electrode on the substrate is a first projection, and the orthographic projections of the first trench and the dam layer on the substrate are a second projection, and at least part of the first projection coincides with the second projection. The embodiment of the present application can increase the length of the common electrode, reduce its resistance, reduce the voltage drop difference, improve the display uniformity, shorten the encapsulation distance, anchor the inorganic encapsulation layer, prevent cracks from growing along the inorganic layer, block the growth path of cracks, and improve the product information reliability. The non-display area of the display panel is reduced, and the area of the display area is expanded, improving the screen-to-body ratio of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technologies. Specifically, the present application relates to a display panel, a preparation method thereof, and a display device. Background Art

[0002] The applications of display panels are becoming increasingly diverse, and the requirements for the form of display panels are also getting higher and higher. Especially for the border area without display, with the pursuit of the ultimate screen-to-body ratio, the border is further compressed. The border generally consists of a gate driver on array (GOA) of the array substrate, a cathode connection, a common power line, and a packaging structure. Organic electroluminescence display (OLED) generally adopts a thin-film packaging structure to ensure the water and oxygen barrier performance of OLED devices. The thin-film packaging structure is generally an inorganic / organic laminated structure. At the edge of the device, the inorganic layer requires a certain length to ensure the packaging characteristics of the device. This is disadvantageous for display devices pursuing an extremely narrow border.

[0003] In summary, in the display panel of the prior art, there are technical problems that the length of the thin-film packaging structure at the panel edge is too long and the border of the display panel is too wide. Summary of the Invention

[0004] Aiming at the disadvantages of the existing methods, the present application provides a display panel, a preparation method thereof, and a display device to solve the technical problems existing in the display panel of the prior art that the length of the thin-film packaging structure at the panel edge is too long and the border of the display panel is too wide.

[0005] In a first aspect, an embodiment of the present application provides a display panel, including a display area and a non-display area surrounding the display area. The non-display area includes an opening area;

[0006] The part of the display panel located in the opening area includes: a substrate, a common electrode, an insulating layer, and a dam layer stacked in sequence. The insulating layer has a first trench, and the first trench is located on the side of the dam layer away from the display area;

[0007] The orthographic projection of the common electrode on the substrate is a first projection, and the orthographic projections of the first trench and the dam layer on the substrate are a second projection. At least part of the first projection coincides with the second projection.

[0008] In some embodiments of the present application, the insulating layer includes a planarization layer and a passivation layer;

[0009] The first trench is formed in the planarization layer;

[0010] The passivation layer is located on the side of the planarization layer away from the substrate and exposes the first trench. Part of the passivation layer covers part of the opening of the first trench.

[0011] In some embodiments of the present application, the common electrode includes: a first source-drain electrode, a second source-drain layer, and a first conductive layer. The first conductive layer covers the side of the passivation layer away from the substrate and covers the sidewall and bottom of the first trench.

[0012] The second source-drain layer is disposed on the side of the flat layer close to the substrate and contacts the first conductive layer at the bottom of the first trench. The first source-drain layer is disposed on the side of the second source-drain layer close to the substrate and contacts the second source-drain layer.

[0013] In some embodiments of the present application, the common electrode includes: a first source-drain layer, a second source-drain layer, and a first conductive layer. The first conductive layer is disposed on the side of the flat layer close to the substrate. The second source-drain layer is disposed on the side of the first conductive layer close to the substrate and contacts the first conductive layer. The first source-drain layer is disposed on the side of the second source-drain layer close to the substrate and contacts the second source-drain layer.

[0014] In some embodiments of the present application, the common electrode further includes a first gate layer and a second gate layer. The second gate layer is disposed on the side of the first source-drain layer close to the substrate and contacts the first source-drain layer. The first gate layer is disposed on the side of the second gate layer close to the substrate and contacts the second gate layer.

[0015] In some embodiments of the present application, the common electrode further includes a first gate layer and a second gate layer. The second gate layer is disposed on the side of the first source-drain layer close to the substrate and contacts the first source-drain layer. A plurality of through holes are formed in the second gate layer. The first gate layer is disposed on the side of the second gate layer close to the substrate and contacts the second gate layer. The first gate layer is connected to the first source-drain layer through the through holes.

[0016] In some embodiments of the present application, the non-display area further includes an overlapping area located between the display area and the public area.

[0017] The part of the display panel located in the overlapping area includes: a substrate, an insulating layer, a first conductive layer, and a second conductive layer stacked in sequence.

[0018] The insulating layer has a second trench, and at least a part of the first conductive layer overlaps with at least a part of the second conductive layer in the second trench.

[0019] In some embodiments of the present application, the insulating layer has a third trench. The insulating layer includes a flat layer and a passivation layer.

[0020] The third trench is formed in the flat layer.

[0021] The passivation layer is located on the side of the flat layer away from the substrate and exposes the third trench. A part of the passivation layer shields a part of the opening of the third trench.

[0022] In some embodiments of the present application, the first conductive layer covers the side of the passivation layer away from the substrate, as well as the sidewalls and bottom of the third trench, and the second conductive layer is disconnected at the third trench.

[0023] In some embodiments of the present application, the portion of the display panel located in the overlapping region further includes: a first source-drain layer and a second source-drain layer. The second source-drain layer is disposed on the side of the third trench close to the substrate and is overlapped with the first conductive layer through the second trench. The first source-drain layer is disposed on the side of the second source-drain layer close to the substrate and is overlapped with the second source-drain layer.

[0024] In some embodiments of the present application, the display panel further includes a gate driving electrode. The orthographic projection of the overlapping portion of the first conductive layer and the second conductive layer on the substrate is a third projection, and the orthographic projection of the gate driving electrode on the substrate is a fourth projection. At least a part of the third projection and the fourth projection coincide.

[0025] In a second aspect, an embodiment of the present application provides a display device, including: the display panel according to any one of the first aspects above.

[0026] In a third aspect, an embodiment of the present application provides a method for manufacturing a display panel, which is used to manufacture the display panel according to the first aspect above. The method for manufacturing the display panel includes the following steps:

[0027] Provide a substrate;

[0028] Prepare a common electrode and an insulating layer on one side of the substrate, and prepare a first trench in the portion of the insulating layer corresponding to the open area in the non-display area;

[0029] Prepare a barrier rib on the side of the insulating layer away from the substrate;

[0030] Wherein, the orthographic projection of the common electrode on the substrate is a first projection, the orthographic projections of the first trench and the barrier rib on the substrate are a second projection, and at least a part of the first projection and the second projection coincide.

[0031] In some embodiments of the present application, preparing a second trench on the insulating layer and preparing a second trench in the portion of the insulating layer corresponding to the overlapping region in the non-display area includes:

[0032] Preparing a common electrode and an insulating layer on one side of the substrate, and preparing a first trench in the portion of the insulating layer corresponding to the open area in the non-display area includes:

[0033] Successively prepare a planarization layer and a passivation layer on one side of the substrate. The etching selectivity of the passivation layer is less than that of the planarization layer;

[0034] Etch the portion of the passivation layer corresponding to the open area in the non-display area so that the passivation layer forms a first recess exposing the planarization layer;

[0035] Contact the etching fluid with the flat layer through the first recess to form a second recess communicating with the first recess.

[0036] The beneficial technical effects brought by the technical solutions provided in the embodiments of the present application include: by laminating the first trench and the isolation dam with the common electrode, on the one hand, the length of the common electrode can be increased on the same non-display area length, reducing its resistance, decreasing the voltage drop difference, and improving display uniformity; on the other hand, the first trench and the isolation dam participate in packaging, which can shorten the packaging distance, anchor the inorganic packaging layer, prevent cracks from growing along the inorganic layer, block the growth path of cracks, and improve the product information reliability. As a result, the non-display area of the display panel is reduced, the area of the display area is expanded, and the screen-to-body ratio of the display panel is improved. The additional aspects and advantages of the present application will be partially given in the following description, and these will become obvious from the following description or be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, in which:

[0038] Figure 1 is a schematic structural diagram of a display panel in an embodiment of the present application;

[0039] Figure 2 is a schematic structural diagram of a display panel in another embodiment of the present application;

[0040] Figure 3 is a schematic structural diagram of a display panel in yet another embodiment of the present application.

[0041] In the figure:

[0042] 1 - Substrate; 2 - Insulating layer (21 - Flat layer, 22 - Passivation layer); 3 - First conductive layer; 4 - Second conductive layer; 5 - First source-drain layer; 6 - Second source-drain layer; 7 - Isolation dam; 8 - First gate layer; 9 - Second gate layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The present application will be described in detail below. Examples of the embodiments of the present application are shown in the drawings, where the same or similar reference numerals denote the same or similar components or components with the same or similar functions throughout. In addition, if the detailed description of the known technology is unnecessary for showing the features of the present application, it will be omitted. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as limiting the present application.

[0044] Those skilled in the art of the present technology can understand that, unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the general understanding of those of ordinary skill in the art to which this application belongs. It should also be understood that terms such as those defined in a general dictionary should be understood to have a meaning consistent with the meaning in the context of the prior art, and will not be interpreted with an idealized or overly formal meaning unless specifically defined as here.

[0045] Those skilled in the art of the present technology can understand that, unless specifically stated, the singular forms "a", "an", "the" and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the specification of this application means the presence of features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or their groups. It should be understood that when we say that an element is "connected" or "coupled" to another element, it can be directly connected or coupled to other elements, or there may also be intermediate elements. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The phrase "and / or" used herein includes all or any unit and all combinations of one or more of the associated listed items.

[0046] Through research, it is found in this application that in the display panel of the prior art, there are technical problems that the length of the thin film encapsulation structure at the panel edge is too long and the border of the display panel is too wide.

[0047] A display panel, a preparation method thereof, and a display device provided in this application are intended to solve the above technical problems of the prior art. The technical solutions of this application and how the technical solutions of this application solve the above technical problems will be described in detail below with specific embodiments.

[0048] In a first aspect, an embodiment of this application provides a display panel. As Figure 1 shown, Figure 1 is a schematic structural diagram of a display panel in an embodiment of this application. The display panel includes a display area and a non-display area surrounding the display area, and the non-display area includes an opening area; the part of the display panel located in the opening area includes: a substrate 1, a common electrode, an insulating layer 2, and a dam 7 stacked in sequence. The insulating layer has a first trench, and the first trench is located on the side of the dam away from the display area; the orthographic projection of the common electrode on the substrate 1 is a first projection, and the orthographic projections of the first trench and the dam 7 on the substrate 1 are a second projection, and at least part of the first projection coincides with the second projection.

[0049] By designing the first trench and the isolation dam in a stacked manner with the common electrode, on the one hand, it is possible to increase the length of the common electrode on the same non-display area length, reduce its resistance, decrease the voltage drop difference, and improve the display uniformity; on the other hand, the first trench and the isolation dam participate in the encapsulation, which can shorten the encapsulation distance, anchor the inorganic encapsulation layer, prevent cracks from growing along the inorganic layer, block the growth path of the cracks, and improve the product information reliability. As a result, the non-display area of the display panel is reduced, and the area of the display area is expanded, improving the screen-to-body ratio of the display panel.

[0050] In some embodiments of the present application, the non-display area further includes an overlapping area located between the display area and the public area; the part of the display panel located in the overlapping area includes: a substrate 1, an insulating layer 2, a first conductive layer 3, and a second conductive layer 4 stacked in sequence;

[0051] The insulating layer 2 has a second trench, and at least part of the first conductive layer 3 overlaps with at least part of the second conductive layer 4 in the second trench.

[0052] By forming a second trench on the insulating layer 2 in the overlapping area and overlapping the first conductive layer 3 and the second conductive layer 4 in the second trench, compared with the overlapping of the first conductive layer 3 and the second conductive layer 4 on a plane, this embodiment can increase the contact area between the first conductive layer 3 and the second conductive layer 4 on the same non-display area length; thus, while ensuring the contact area between the first conductive layer 3 and the second conductive layer 4, the width of the non-display area can be reduced, the area of the display area is expanded, and the screen-to-body ratio of the display panel is improved.

[0053] In some embodiments of the present application, the insulating layer 2 has a third trench, and the insulating layer 2 includes a planar layer 21 and a passivation layer 22; the third trench is formed in the planar layer 21; the passivation layer 22 is located on the side of the planar layer 21 away from the substrate 1 and exposes the third trench, and part of the passivation layer 22 covers part of the opening of the third trench.

[0054] In this embodiment, the first conductive layer 3 is an anode layer, and the second conductive layer 4 is a cathode layer. The first conductive layer 3 is disposed on the surface of the planar layer 21 away from the substrate 1, the second conductive layer 4 is disposed on the side of the first conductive layer 3 away from the substrate 1, and a pixel definition layer 5 is disposed between the first conductive layer 3 and the second conductive layer 4. The first conductive layer 3 overlaps with the second conductive layer 4, and at least part of the overlapping portion is located in the second trench.

[0055] In some embodiments, the flat layer 21 is provided with a plurality of second grooves in the overlapping region. At least part of the second grooves are overlapping grooves. At least part of the first conductive layer 3 covers the side walls and the bottom of the overlapping grooves. At least part of the second conductive layer 4 conformally covers the side of the first conductive layer 3 away from the substrate 1 in the overlapping grooves, that is, the first conductive layer 3 and the second conductive layer 4 are in direct contact to complete the overlap. Among them, in some regions, air holes are provided in the first conductive layer 3, and the second conductive layer 4 does not directly contact the first conductive layer 3 around the air holes, forming an accommodating space, and a pixel definition layer is filled in the accommodating space.

[0056] The third groove is an isolation groove. The flat layer 21 forms the isolation groove, and the passivation layer 22 is disposed on the side of the flat layer 21 away from the substrate 1 and exposes the isolation groove. Part of the passivation layer 22 shields part of the opening of the isolation groove, that is, the orthographic projection of the passivation layer 22 on the substrate 1 partially coincides with the orthographic projection of the opening of the isolation groove on the substrate 1.

[0057] Similar to the overlapping groove, the isolation groove can increase the contact area between the encapsulation layer and the first conductive layer 3 or the second conductive layer 4, reduce the width occupied by the encapsulation structure, thereby reducing the width of the non-display area, anchor the inorganic encapsulation layer, prevent cracks from growing along the inorganic layer, block the growth path of the cracks, and improve the product information reliability.

[0058] In some embodiments of the present application, the first conductive layer 3 covers the side of the passivation layer 22 away from the substrate 1, as well as the side walls and the bottom of the third groove, and the second conductive layer 4 is disconnected at the third groove.

[0059] In this embodiment, different from the overlapping groove, in the isolation groove, the first conductive layer 3 still covers the side walls and the bottom of the isolation groove, but at the opening of the isolation groove, the first conductive layer 3 covers the passivation layer 22 and shields part of the opening of the isolation groove. And the second conductive layer 4 overlapping with the first conductive layer 3 is disconnected at the isolation groove due to the verticality of thermal evaporation. The second conductive layer 4 only covers the surface of the first conductive layer 3 away from the substrate 1 at the isolation groove and does not contact the side surface of the first conductive layer 3.

[0060] In some embodiments of the present application, the part of the display panel located in the overlapping region further includes: a second source-drain layer 6 and a first source-drain layer 5. The second source-drain layer 6 is disposed on the side of the third groove close to the substrate 1 and overlaps with the first conductive layer 3 through the second groove. The first source-drain layer 5 is disposed on the side of the second source-drain layer 6 close to the substrate 1 and overlaps with the second source-drain layer 6.

[0061] In this embodiment, the flat layer 21 includes a first flat layer and a second flat layer on a side of the first flat layer away from the substrate 1, and the second source-drain layer 6 is disposed on a side of the first flat layer away from the substrate 1. The sum of the depth of at least one overlapping groove and the thickness of the second source-drain layer 6 is greater than the thickness of the second flat layer, and the first conductive layer 3 overlaps with the second source-drain layer 6 through the overlapping groove. The sum of the depth of at least one isolation groove and the thickness of the second source-drain layer 6 is less than the thickness of the second flat layer. The isolation groove and the second source-drain layer 6 can be designed in a stacked manner, and there is still a second flat layer with a reduced thickness between the isolation groove and the second source-drain layer 6. The first conductive layer 3 in the isolation groove extends out of the isolation groove and overlaps with the second source-drain layer 6 through the overlapping groove. The orthographic projection of the opening of the isolation groove on the substrate 1 and the orthographic projection of the second source-drain layer 6 on the substrate at least partially overlap. The above stacked design can reduce the width of the overlapping area and thus reduce the overall width of the non-display area.

[0062] In some embodiments of the present application, the display panel further includes a gate driving electrode 6. The orthographic projection of the overlapping portion of the first conductive layer 3 and the second conductive layer 4 on the substrate 1 is a third projection, and the orthographic projection of the gate driving electrode 6 on the substrate 1 is a fourth projection. The third projection and the fourth projection at least partially overlap.

[0063] In this embodiment, the overlapping portion refers to the position where the first conductive layer 3 and the second conductive layer 4 are in direct contact, and the overlapping area refers to one of the sub-regions of the non-display area. The gate driving electrode 6 is located between the insulating layer 2 and the substrate 1. The orthographic projection of the gate driving electrode 6 on the substrate 1 and the orthographic projection of the overlapping portion on the substrate at least partially overlap, which can reduce the width of the overlapping area and thus reduce the width of the non-display area.

[0064] In some embodiments of the present application, the non-display area further includes a common area on a side of the overlapping area away from the display area. The portion of the display panel located in the common area includes: the substrate 1, the common electrode, the insulating layer 2, and the isolation dam 7 stacked in sequence. The insulating layer 2 has a first trench, and the first trench is disposed on a side of the second trench away from the display area. The isolation dam 7 is disposed between the second trench and the first trench.

[0065] In this embodiment, a common area is further included on a side of the overlapping area away from the display area. The common area is provided with an isolation dam 7, and the insulating layer 2 is provided with a first trench. The first trench is located on a side of the isolation dam 7 away from the second trench.

[0066] In some embodiments of the present application, the insulating layer 2 includes a flat layer 21 and a passivation layer 22;

[0067] The first trench is formed in the flat layer 21;

[0068] The passivation layer 22 is located on a side of the flat layer 21 away from the substrate 1 and exposes the first trench. Part of the passivation layer 22 covers part of the opening of the first trench.

[0069] In this embodiment, different from the overlapping region, the second conductive layer 4 is not provided in the exposed region. The first conductive layer 3 and the second conductive layer 4 do not need to overlap in the exposed region, and no overlapping groove is provided in the exposed region. Compared with the thickness of the flat layer in the overlapping region, the thickness of the flat layer is smaller, and the depth of the first trench is not less than the thickness of the flat layer, so that the first trench exposes other film layers. Part or all of the first trenches are isolation trenches, the flat layer 21 forms the isolation trenches, and the passivation layer 22 is disposed on the side of the flat layer 21 away from the substrate 1 and exposes the isolation trenches. Part of the passivation layer 22 shields part of the opening of the isolation trench, that is, the orthographic projection of the passivation layer 22 on the substrate 1 coincides with part of the orthographic projection of the opening of the isolation trench on the substrate 1.

[0070] The isolation trenches can increase the contact area between the encapsulation layer and the first conductive layer 3 or the flat layer, reduce the width occupied by the encapsulation structure, thereby reducing the width of the non-display area, anchor the inorganic encapsulation layer, prevent cracks from growing along the inorganic layer, block the growth path of the cracks, and improve the reliability of product information.

[0071] In some embodiments of the present application, the common electrode at least includes: a first source-drain layer 5, a second source-drain layer 6, and a first conductive layer 3. The first conductive layer 3 covers the side of the passivation layer 22 away from the substrate 1, as well as covers the sidewalls and bottom of the first trench;

[0072] The second source-drain layer 6 is disposed on the side of the flat layer 21 close to the substrate 1 and contacts the first conductive layer 3 at the bottom of the first trench. The first source-drain layer 5 is disposed on the side of the second source-drain layer 6 close to the substrate 1 and contacts the second source-drain layer 6.

[0073] In this embodiment, the first source-drain layer 5, the second source-drain layer 6, and the first conductive layer 3 are stacked in the exposed region to form a common electrode. Similar to the overlapping region, the first conductive layer 3 covers the side of the passivation layer 22 away from the substrate 1 and covers the sidewalls and bottom of the first trench. The second source-drain layer 6 is flatly laid on the side of the flat layer close to the substrate 1. At the bottom of the first trench, the second source-drain layer 6 overlaps with the first conductive layer 3. The first source-drain layer 5 is flatly laid on the side of the second source-drain layer 6 close to the substrate 1, and full contact is made between the first source-drain layer 5 and the second source-drain layer 6. Since the three conductive layers form a common electrode, the resistance of the common electrode is reduced, thereby reducing the power consumption of the display panel.

[0074] In some embodiments of the present application, the common electrode at least includes: a first source-drain layer 5, a second source-drain layer 6, and a first conductive layer 3. The first conductive layer 3 is disposed on the side of the flat layer 21 close to the substrate 1. The second source-drain layer 6 is disposed on the side of the first conductive layer 3 close to the substrate 1 and contacts the first conductive layer 3. The first source-drain layer 5 is disposed on the side of the second source-drain layer 6 close to the substrate 1 and contacts the second source-drain layer 6.

[0075] As Figure 2 shown Figure 2 is a schematic structural diagram of a display panel in another embodiment of the present application. In this embodiment, the first source-drain layer 5, the second source-drain layer 6, and the first conductive layer 3 are stacked in the open area to form a common electrode. Different from the overlapping area, the first conductive layer 3 is flatly laid on the side of the flat layer close to the substrate 1. The encapsulation layer in the first trench directly covers the side of the passivation layer 22 away from the substrate 1 and covers the side wall and bottom of the first trench. The second source-drain layer 6 is flatly laid on the side of the first conductive layer 3 close to the substrate 1. The second source-drain layer 6 is in full contact with the first conductive layer 3. The first source-drain layer 5 is flatly laid on the side of the second source-drain layer 6 close to the substrate 1. The first source-drain layer 5 is in full contact with the second source-drain layer 6. Since the contact surfaces between the three conductive layers forming the common electrode become larger, the resistance of the common electrode is further reduced, thereby further reducing the power consumption of the display panel.

[0076] In some embodiments of the present application, the positive projection of the common electrode on the substrate 1 is the first projection, and the positive projections of the first trench and the isolation dam 7 on the substrate are the second projection. The first projection and the second projection at least partially overlap.

[0077] In this embodiment, at least one of the first trench and the isolation dam 7 is designed to be laminated with the common electrode, and the first projection and the second projection at least partially overlap, thereby reducing the width of the common area and reducing the overall width of the non-display area.

[0078] In some embodiments of the present application, the common electrode further includes a first gate layer 8 and a second gate layer 9. The second gate layer 9 is disposed on the side of the first source-drain layer 5 close to the substrate 1 and is in contact with the first source-drain layer 5. The first gate layer 8 is disposed on the side of the second gate layer 9 close to the substrate 1 and is in contact with the second gate layer 9.

[0079] In this embodiment, the first gate layer 8, the second gate layer 9, the first source-drain layer 5, the second source-drain layer 6, and the first conductive layer 3 are stacked in the open area to form a common electrode. The second gate layer 9 is flatly laid on the side of the first source-drain layer 5 close to the substrate 1. The first source-drain layer 5 is in full contact with the second gate layer 9. The first gate layer 8 is flatly laid on the side of the second gate layer 9 close to the substrate 1. The first gate layer 8 is in full contact with the second gate layer 9. Since the number of conductive layers forming the common electrode increases, the resistance of the common electrode is further reduced, thereby further reducing the power consumption of the display panel.

[0080] In some embodiments of the present application, the common electrode further includes a first gate layer 8 and a second gate layer 9. The second gate layer 9 is disposed on a side of the first source-drain layer 5 close to the substrate 1 and contacts the first source-drain layer 5. A plurality of through holes are formed in the second gate layer 9. The first gate layer 8 is disposed on a side of the second gate layer 9 close to the substrate 1 and contacts the second gate layer 9. The first gate layer 8 is connected to the first source-drain layer 5 through the through holes.

[0081] As Figure 3 shown, Figure 3 FIG. is a schematic structural diagram of a display panel in another embodiment of the present application. In this embodiment, the first gate layer 8, the second gate layer 9, the first source-drain layer 5, the second source-drain layer 6, and the first conductive layer 3 are stacked in the open area to form a common electrode. The second gate layer 9 is disposed on a side of the first source-drain layer 5 close to the substrate 1 and includes a plurality of through holes. The first source-drain layer 5 is in contact with the second gate layer 9. The first gate layer 8 is flatly disposed on a side of the second gate layer 9 close to the substrate 1. The first gate layer 8 is in contact with the second gate layer 9. The plurality of through holes are filled with the first gate layer 8 or the first source-drain layer 5. The first gate layer 8 is electrically connected to the first source-drain layer 5 through the through holes.

[0082] In another embodiment, the first gate layer 8, the second gate layer 9, the first source-drain layer 5, the second source-drain layer 6, and the first conductive layer 3 are stacked in the open area to form a common electrode. The second gate layer 9 includes a plurality of columnar structures and is disposed on a side of the first source-drain layer 5 close to the substrate 1. The first source-drain layer 5 is in contact with the second gate layer 9. The first gate layer 8 is flatly disposed on a side of the second gate layer 9 close to the substrate 1. The first gate layer 8 is in contact with the second gate layer 9. The gaps between the plurality of columnar structures are filled with the first gate layer 8 or the first source-drain layer 5. The first gate layer 8 is electrically connected to the first source-drain layer 5 through the above-mentioned filling material. In the above embodiments, not only the embodiment of the front laying of the second gate layer 9 is introduced, but also the patterning of the second gate layer 9 is included. After the second gate layer 9 is patterned, without affecting the conductive performance of the common electrode, the stress on the common electrode can be relieved, and the structural stability of the display panel can be improved.

[0083] Based on the same inventive concept, in a second aspect, an embodiment of the present application provides a display device, including a display panel including the display panel in any one of the above embodiments in the first aspect.

[0084] Based on the same inventive concept, in a third aspect, an embodiment of the present application provides a method for manufacturing a display device for the display panel in any one of the above embodiments in the first aspect. The method for manufacturing a display panel includes:

[0085] Providing a substrate 1;

[0086] Prepare a common electrode and an insulating layer 2 on one side of the substrate 1, and prepare a first trench in the part of the insulating layer 2 corresponding to the exposed area in the non-display area;

[0087] Prepare a dam 7 on the side of the insulating layer 2 away from the substrate;

[0088] Wherein, the orthographic projection of the common electrode on the substrate is a first projection, and the orthographic projections of the first trench and the dam on the substrate are second projections, and at least part of the first projection coincides with the second projection.

[0089] In some embodiments of the present application, another method for manufacturing a display panel or a method for unfolding / expanding the manufacture of a display panel is provided. The method includes the following steps:

[0090] When preparing a common electrode and an insulating layer 2 on one side of the substrate 1 and preparing a first trench in the part of the insulating layer 2 corresponding to the exposed area in the non-display area, it includes:

[0091] Prepare a planarization layer 21 and a passivation layer 22 in sequence on one side of the substrate 1, and the etching selectivity of the passivation layer 22 is less than that of the planarization layer 21;

[0092] Etch the part of the passivation layer 22 corresponding to the exposed area in the non-display area so that the passivation layer 22 forms a first recess exposing the planarization layer 21;

[0093] Contact the etching fluid with the planarization layer 21 through the first recess to form a second recess communicating with the first recess.

[0094] In some embodiments, the first recess and the second recess communicate to form a first trench. The structure of the first recess can be formed by etching or laser, such as dry etching; the structure of the second recess can be formed by an etching fluid. In this embodiment, by controlling the flow rates of different etching gases, a groove with an undercut structure can be obtained. The structure of the first trench generally consists of two or more film layers. The upper layer forms an eaves, and the lower layer forms an undercut concave shape. Generally, the upper layer structure is an inorganic layer or a metal, alloy or organic layer, and the lower layer is an organic layer or an inorganic layer, etc.

[0095] In another embodiment, the first recess and the second recess can be made of the same etching fluid. Since the etching selectivity of the passivation layer 22 is less than that of the planarization layer 21, a groove with an undercut structure can still be etched.

[0096] In this embodiment, the upper layer structure of the second trench is a passivation layer 22, and the lower layer structure is a planarization layer 21. The gas for etching the passivation layer 22 is a gas such as trifluoromethane (CHF3). When etching the lower planarization layer 21, the etching gas is mainly oxygen (O2). At this time, the passivation layer 22 can be used as a hard mask to etch the planarization layer 21 to form an undercut structure. The side etch amount of this undercut structure is 0.2 - 2 μm, preferably 0.3 - 0.5 μm, and the depth is 1 - 3 μm, preferably 1.2 - 2 μm. The opening size of the undercut structure is 3 - 20 μm, preferably 5 - 10 μm.

[0097] The preparation method of the third trench is the same as that of the first trench, and will not be repeated here.

[0098] Applying the embodiments of the present application can at least achieve the following beneficial effects: 1. By laminating the first trench and the isolation dam with the common electrode, on the one hand, it can increase the length of the common electrode on the same non-display area length, reduce its resistance, reduce the voltage drop difference, and improve the display uniformity; on the other hand, the first trench and the isolation dam participate in the encapsulation, which can shorten the encapsulation distance, anchor the inorganic encapsulation layer, prevent cracks from growing along the inorganic layer, block the growth path of cracks, and improve the product information reliability. As a result, the non-display area of the display panel is reduced, and the area of the display area is expanded, improving the screen-to-body ratio of the display panel.

[0099] 2. By opening a second trench in the insulating layer 2 in the overlapping area and overlapping the first conductive layer 3 and the second conductive layer 4 in the second trench, compared with the overlapping of the first conductive layer 3 and the second conductive layer 4 on the plane, this embodiment can increase the contact area between the first conductive layer 3 and the second conductive layer 4 on the same non-display area length; thus, while ensuring the contact area between the first conductive layer 3 and the second conductive layer 4, the width of the non-display area can be reduced, and the area of the display area is expanded, improving the screen-to-body ratio of the display panel.

[0100] 3. The laminated design can reduce the width of the overlapping area, thereby reducing the overall width of the non-display area.

[0101] 4. Multiple conductive layers form a common electrode, reducing the resistance of the common electrode, thereby reducing the power consumption of the display panel.

[0102] 5. Pattern at least one conductive layer. Without affecting the conductivity of the common electrode, it can relieve the stress on the common electrode and improve the structural stability of the display panel.

[0103] Those skilled in the art of the present application can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, those in the prior art that have steps, measures, and solutions in the various operations, methods, and processes disclosed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0104] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0105] The terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0106] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0107] In the description of this specification, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0108] It should be understood that although the steps in the flowchart of the accompanying drawings are shown sequentially according to the indication of the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this document, there is no strict order restriction for the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or sub-steps or stages of other steps.

[0109] The above are only some embodiments of the present application. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present application, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present application.

Claims

1. A display panel, characterized in that, It includes a display area and a non-display area surrounding the display area, and the non-display area includes a disclosure area; The part of the display panel located in the disclosure area includes: a substrate, a common electrode, an insulating layer, and a dam, which are stacked in sequence. The insulating layer has a first trench, and the first trench is located on the side of the dam away from the display area; The orthographic projection of the common electrode on the substrate is a first projection, and the orthographic projections of the first trench and the dam on the substrate are a second projection. At least part of the first projection coincides with at least part of the second projection.

2. The display panel according to claim 1, wherein The insulating layer includes a planarization layer and a passivation layer; The first trench is formed in the planarization layer; The passivation layer is located on the side of the planarization layer away from the substrate and exposes the first trench. Part of the passivation layer shields part of the opening of the first trench.

3. The display panel according to claim 2, wherein The common electrode includes: a first source-drain electrode, a second source-drain layer, and a first conductive layer. The first conductive layer covers the side of the passivation layer away from the substrate and covers the sidewall and bottom of the first trench; The second source-drain layer is disposed on the side of the planarization layer close to the substrate and contacts the first conductive layer at the bottom of the first trench. The first source-drain layer is disposed on the side of the second source-drain layer close to the substrate and contacts the second source-drain layer.

4. The display panel according to claim 2, wherein The common electrode includes: a first source-drain layer, a second source-drain layer, and a first conductive layer. The first conductive layer is disposed on the side of the planarization layer close to the substrate. The second source-drain layer is disposed on the side of the first conductive layer close to the substrate and contacts the first conductive layer. The first source-drain layer is disposed on the side of the second source-drain layer close to the substrate and contacts the second source-drain layer.

5. The display panel according to claim 3 or 4, wherein The common electrode further includes a first gate layer and a second gate layer. The second gate layer is disposed on the side of the first source-drain layer close to the substrate and contacts the first source-drain layer. The first gate layer is disposed on the side of the second gate layer close to the substrate and contacts the second gate layer.

6. The display panel according to claim 3 or 4, characterized in that, The common electrode further includes a first gate layer and a second gate layer. The second gate layer is disposed on the side of the first source-drain layer close to the substrate and contacts the first source-drain layer. A plurality of through holes are formed in the second gate layer. The first gate layer is disposed on the side of the second gate layer close to the substrate and contacts the second gate layer. The first gate layer is connected to the first source-drain layer through the through holes.

7. The display panel according to claim 1, wherein The non-display area further includes an overlapping area located between the display area and the disclosure area; The part of the display panel located in the overlapping area includes: a substrate, an insulating layer, a first conductive layer, and a second conductive layer, which are stacked in sequence; The insulating layer has a second trench, and at least part of the first conductive layer overlaps with at least part of the second conductive layer in the second trench.

8. The display panel according to claim 7, wherein The insulating layer has a third trench. The insulating layer includes a planarization layer and a passivation layer; The third trench is formed in the planarization layer; The passivation layer is located on a side of the flat layer away from the substrate and exposes the third trench, and a part of the passivation layer shields a part of the opening of the third trench.

9. The display panel according to claim 8, characterized in that, The first conductive layer covers a side of the passivation layer away from the substrate, and the sidewalls and bottom of the third trench, and the second conductive layer is disconnected at the third trench.

10. The display panel according to claim 8, characterized in that, The portion of the display panel located in the overlapping region further includes: a first source-drain layer and a second source-drain layer. The second source-drain layer is disposed on a side of the third trench close to the substrate and is overlapped with the first conductive layer through the second trench. The first source-drain layer is disposed on a side of the second source-drain layer close to the substrate and is overlapped with the second source-drain layer.

11. The display panel according to claim 7, wherein, The display panel further includes a gate driving electrode. A positive projection of the overlapping portion of the first conductive layer and the second conductive layer on the substrate is a third projection, and a positive projection of the gate driving electrode on the substrate is a fourth projection. At least a part of the third projection coincides with the fourth projection.

12. A display device, characterized in that, Including the display panel according to any one of claims 1-11.

13. A method for manufacturing a display panel, characterized in that, Including: Providing a substrate; Preparing a common electrode and an insulating layer on one side of the substrate, and preparing a first trench in a portion of the insulating layer corresponding to an open area in the non-display area; Preparing a dam on a side of the insulating layer away from the substrate; Wherein, a positive projection of the common electrode on the substrate is a first projection, a positive projection of the first trench and the dam on the substrate is a second projection, and at least a part of the first projection coincides with the second projection.

14. The preparation method according to claim 13, characterized in that, Preparing a common electrode and an insulating layer on one side of the substrate, and preparing a first trench in a portion of the insulating layer corresponding to an open area in the non-display area, including: Sequentially preparing a flat layer and a passivation layer on one side of the substrate, and an etching selectivity of the passivation layer is less than an etching selectivity of the flat layer; Etching a portion of the passivation layer corresponding to the open area in the non-display area, such that the passivation layer forms a first recess exposing the flat layer; Bringing an etching fluid into contact with the flat layer through the first recess to form a second recess communicating with the first recess.

Images