Dual-loop Phase Locked Loop and Its Charge Pump

Abstract

The present disclosure provides a dual-loop phase-locked loop and its charge pump. In this dual-loop phase-locked loop, a charge pump and a loop filter with a proportional path and an integral path are coupled between a frequency discriminator and a voltage-controlled oscillator. Among them, the charge pump located on the proportional path can not only control the charging current provided by the upper current source / the discharging current provided by the lower current source through a gating switch to change the potential of the output node between the upper current source and the lower current source. At the same time, since the bias current provided by the bias current source is a preset desired current according to the sweep slope and the characteristics of this dual-loop phase-locked loop, it can also adaptively adjust the current flowing through the output node following the change of the sweep slope to maintain the potential of the output node. Thereby, it can effectively compensate for the voltage deviation problem generated when the dual-loop phase-locked loop works in the sweep mode, enabling the system parameters of the dual-loop phase-locked loop to be accurately controlled and greatly improving the stability and reliability of this dual-loop phase-locked loop.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and particularly to a dual-loop phase-locked loop and its charge pump. Background Art

[0002] In the application of integrated circuits, the clock system is an important module in chip design. To meet the different clock requirements of the system, a phase-locked loop circuit is adopted.

[0003] In the frequency synthesis phase-locked loop of the related art, its frequency locking is achieved through a single loop, which is sequentially connected by a frequency discriminator and phase detector, a charge pump, a loop filter, a voltage-controlled oscillator, a prescaler, and a frequency divider; first, the voltage-controlled oscillator generates an oscillation signal with a certain frequency through self-excited oscillation. After passing through the prescaler and the frequency divider, this signal enters the frequency discriminator and phase detector, where it is compared with the reference frequency and generates a frequency difference and a phase difference signal that enter the charge pump; the charge pump determines the intake current or the pump-out current according to this frequency difference value and phase difference value, and converts this current into a voltage value; the output voltage of the charge pump is filtered by the loop filter and then enters the voltage-controlled oscillator. By adjusting the value of the variable capacitor in the voltage-controlled oscillator, the oscillation frequency of the oscillator is changed; in fact, the entire loop first locks the frequency of the signal generated by the voltage-controlled oscillator within the required frequency band according to the frequency difference, and then locks the oscillation frequency at the required frequency point by gradually approaching the reference frequency of the output signal of the frequency divider in a fine-tuning manner.

[0004] In such a traditional phase-locked loop, the frequency range covered by the variable capacitor of the voltage-controlled oscillator is very limited and is completely inapplicable to wide-band applications such as the ZigBee system; if a variable capacitor array is used for frequency band selection, the control signal of the capacitor array and the frequency band need to be set in a one-to-one correspondence relationship, that is, a certain digital control value is preset to correspond to a certain frequency band. When an oscillation signal of this frequency band is required, the preset digital code control word is manually input to make its oscillation frequency within this frequency band, and then through loop frequency fine-tuning, the signal is finally locked at a certain oscillation frequency within this frequency band; however, due to process deviations, voltage changes, and temperature drift effects, the frequency signal generated by the actual voltage-controlled oscillator circuit is very different from the predetermined value, and there will be a large deviation in the one-to-one correspondence relationship between the variable capacitor array control word and the frequency band. To lock the required oscillation frequency, more loop cycles are required for frequency approximation, which greatly prolongs the phase-locked loop frequency locking time.

[0005] On this basis, an improved dual-loop phase-locked loop is proposed as Figure 1As shown, the dual-loop phase-locked loop 100 including an integration path 120 and a proportional path 130, when performing frequency sweeping, the output voltage of the loop filter 122 on the integration path 120 will change according to the output frequency. The output voltage of the loop filter 132 on the proportional path 130 remains unchanged ideally. However, in an actual circuit, on the one hand, since the input phase difference of the frequency discriminator and phase detector 110 is not 0 during the frequency sweeping process, the output voltage of the loop filter 132 on the proportional path 130 will change and deviate from its expected value. This deviation will cause the loop parameters of the dual-loop phase-locked loop 100 to change, thereby deteriorating the overall performance of the phase-locked loop and even causing loss of lock.

[0006] On the other hand, the charge pumps (taking the charge pump on the proportional path 130 as an example) 131 of the current dual-loop phase-locked loop 100 all adopt a general traditional architecture, such as Figure 2 shown. This kind of architecture cannot avoid the phenomenon that the output voltage of the loop filter 132 on the proportional path 130 deviates from the expected value during the frequency sweeping process. Summary of the Invention

[0007] In order to solve the above technical problems, the present disclosure provides a dual-loop phase-locked loop and its charge pump.

[0008] On the one hand, the present disclosure provides a charge pump for a dual-loop phase-locked loop. The dual-loop phase-locked loop couples a charge pump and a loop filter with a proportional path and an integration path between a frequency discriminator and a voltage-controlled oscillator. Among them, the charge pump located on the proportional path includes:

[0009] An upper current source and a lower current source, which are connected in series between a power supply terminal and the ground, and the charging current provided by the upper current source / the discharging current provided by the lower current source is controlled by a gating switch to change the potential of the output node between the upper current source and the lower current source;

[0010] A bias current source, which is connected between the power supply terminal and the aforementioned output node, and is used to adaptively adjust the charging current / discharging current flowing through the output node according to the change of the frequency sweeping slope to maintain the potential of the output node.

[0011] Among them, the bias current provided by the aforementioned bias current source is a preset expected current according to the frequency sweeping slope and the characteristics of the dual-loop phase-locked loop.

[0012] Preferably, the aforementioned charge pump further includes:

[0013] A first switch, which is connected between the aforementioned upper current source and the output node, and switches its on / off state in response to a first control signal to provide the aforementioned charging current.

[0014] A second switch, connected between the aforementioned output node and the lower current source, switches its on / off state in response to a second control signal to provide the aforementioned discharge current;

[0015] A third switch, connected between the aforementioned bias current source and the output node, switches its on / off state in response to a third control signal to regulate the charging current / discharging current flowing through the output node.

[0016] Preferably, the magnitude of the aforementioned bias current is the current value that makes the offset voltage amount output by the charge pump located on the aforementioned proportional path become zero when the dual-loop phase-locked loop switches from the locked mode to the frequency-sweeping mode and operates at a predetermined frequency-sweeping slope.

[0017] Preferably, the aforementioned upper current source, lower current source, and bias current source are current source devices of the same type.

[0018] Preferably, any one of the aforementioned upper current source, lower current source, and bias current source is a complementary metal-oxide-semiconductor device or a bipolar complementary metal-oxide-semiconductor device.

[0019] On the other hand, the present disclosure also provides a dual-loop phase-locked loop, which includes:

[0020] A voltage-controlled oscillator, which has a power supply terminal and a control terminal and is used to generate a high-frequency clock signal;

[0021] A frequency discriminator and phase detector, which is used to detect the phase difference between the phase of the high-frequency clock signal and the phase of the reference signal, and generate an integral signal representing the integral value of the phase difference and a proportional signal representing the current value of the phase difference;

[0022] An integral path, which includes a first charge pump and a first loop filter, and is used to receive the aforementioned integral signal and supply the adjusted integral signal to the power supply terminal of the aforementioned voltage-controlled oscillator;

[0023] A proportional path, which includes a second charge pump and a second loop filter, and is used to receive the aforementioned proportional signal and supply the adjusted proportional signal to the control terminal of the aforementioned voltage-controlled oscillator,

[0024] wherein, the aforementioned second charge pump is the aforementioned charge pump, which is used to adaptively regulate the charging current / discharging current flowing through the output node of the second charge pump according to the change of the frequency-sweeping slope to maintain the potential of the output node, and the aforementioned voltage-controlled oscillator generates a high-frequency clock signal with an oscillation frequency controlled by both the adjusted integral signal and the adjusted proportional signal, so that the phase of the high-frequency clock signal is locked to the phase of the aforementioned reference signal.

[0025] Preferably, the aforementioned dual-loop phase-locked loop further includes:

[0026] A frequency divider, coupled between the aforementioned voltage-controlled oscillator and the phase frequency detector, is configured to divide the aforementioned high-frequency clock signal to obtain a low-frequency signal.

[0027] Wherein, the aforementioned phase frequency detector detects the aforementioned phase difference by comparing the phase of the low-frequency signal with the phase of the aforementioned reference signal.

[0028] Preferably, the aforementioned first loop filter includes:

[0029] A first capacitor, a first resistor, and a second capacitor. The first end of the first capacitor and the first end of the first resistor are commonly connected to the output node of the aforementioned first charge pump. The second end of the first capacitor is grounded. The second end of the first resistor is serially connected to the second capacitor to ground, and the connection node of the first resistor and the second capacitor is connected to the aforementioned power supply terminal.

[0030] Preferably, the aforementioned second loop filter includes:

[0031] A second resistor, a third capacitor, a third resistor, and a fourth capacitor. The second resistor and the third capacitor are connected in parallel between the output node of the aforementioned second charge pump and ground. The first end of the third capacitor and the first end of the third resistor are commonly connected to the output node of the aforementioned second charge pump. The second end of the third resistor is serially connected to the fourth capacitor to ground, and the connection node of the third resistor and the fourth capacitor is connected to the aforementioned control terminal.

[0032] Preferably, the magnitude of the bias current in the aforementioned second charge pump is proportional to the aforementioned frequency sweep slope and proportional to the current at the output node on the aforementioned proportional path.

[0033] In a dual-loop phase-locked loop and its charge pump provided by the present disclosure, a charge pump and a loop filter with a proportional path and an integral path are coupled between the phase frequency detector and the voltage-controlled oscillator of the dual-loop phase-locked loop. Wherein, the charge pump located on the proportional path includes an upper current source, a lower current source, and a bias current source. The upper current source and the lower current source are serially connected between the power supply terminal and ground. The charging current provided by the upper current source / the discharging current provided by the lower current source is controlled by a gating switch to change the potential of the output node between the upper current source and the lower current source. The bias current provided by the bias current source is a preset desired current according to the frequency sweep slope and the characteristics of the dual-loop phase-locked loop, and is used to adaptively adjust the charging current / discharging current flowing through the output node following the change of the frequency sweep slope to maintain the potential of the output node. Thereby, the above-mentioned problem of voltage deviation generated when the dual-loop phase-locked loop works in the frequency sweep mode in the prior art can be effectively compensated, so that the system parameters of the dual-loop phase-locked loop can be accurately controlled, greatly improving the stability and reliability of the dual-loop phase-locked loop, and enabling the dual-loop phase-locked loop to maintain the desired system parameters under different frequency sweep slope requirements. Brief Description of the Drawings

[0034] Through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become clearer.

[0035] Figure 1 Fig. shows a circuit structure diagram of a dual-loop phase-locked loop in the prior art;

[0036] Figure 2 Show Figure 1 A schematic structural diagram of a charge pump located on the proportional path in the shown dual-loop phase-locked loop;

[0037] Figure 3 Fig. shows a circuit structure diagram of a dual-loop phase-locked loop provided by an embodiment of the present disclosure;

[0038] Figure 4 Show for Figure 3 A schematic structural diagram of the charge pump of the shown dual-loop phase-locked loop;

[0039] Figure 5 Show Figure 3 A circuit structure diagram of a first loop filter located on the integral path in the shown dual-loop phase-locked loop;

[0040] Figure 6 Show Figure 3 A circuit structure diagram of a second loop filter located on the proportional path in the shown dual-loop phase-locked loop. Detailed Embodiments

[0041] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant accompanying drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the content of the present disclosure more thorough and comprehensive.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. The terms used in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0043] In a wireless transceiver, a phase-locked loop (PLL) is generally used to synthesize a variable local oscillator signal from a reference signal source (such as a crystal oscillator), which has a stable output with low phase noise. The PLL generates an output signal locked to the reference signal. Generally, the desired output radio frequency is higher than the reference frequency from an appropriate reference source. When used as a local oscillator, an important characteristic of the PLL is the selectivity of its communication channels, that is, the gap between its output channels or its resolution.

[0044] The earliest and simplest type is an integer NPLL single loop, in which the output signal is fed back to the phase comparator of the PIL through a frequency divider with an integer division ratio N. Generally, through a reference frequency divider with an integer division ratio R, the comparison signal is derived from a reference signal. The selection of the output communication channel is equal to the comparison frequency. This type of PLL has been well developed and has a low enough power consumption suitable for battery applications. However, when the division ratios R and N are set to provide a high output frequency with a narrow communication channel selection, this simple type of PLL suffers from phase noise problems.

[0045] Another very important type of PLL is the fractional NPLL, which has the same structure as the integer NPLL except that the division ratio of the feedback frequency divider is an integer plus a rational fraction. The selection of the communication channel of the output signal is therefore also a rational fraction of the comparison frequency. However, it is very difficult to implement a fractional NPLL for low noise and low power. A high-performance fractional NPLL requires high complexity, consumes a large area of silicon and is not easily integrated with other low-noise systems on the same module.

[0046] An improvement over the single-loop PLL can be obtained by adopting a dual-loop PLL that combines two phase-locked loops.

[0047] The charge pump (taking the charge pump on the proportional path 130 as an example) 131 in the traditional dual-loop phase-locked loop architecture 100. When the dual-loop phase-locked loop 100 is locked, the output voltage of the charge pump 131 is 0. When the dual-loop phase-locked loop sweeps the frequency, the voltage of the charge pump 131 will change with different sweep slopes, causing the output voltage of the loop filter 132 on the proportional path 130 to change and deviate from its expected value. This deviation causes the loop parameters of the phase-locked loop to change, thereby deteriorating the overall performance of the phase-locked loop and even causing loss of lock, affecting the performance of the phase-locked loop.

[0048] Based on this, the dual-loop phase-locked loop (PLL) in the embodiments of the present disclosure is proposed to effectively make up for the above voltage deviation defect, so that the phase-locked loop maintains the expected system parameters under different sweep slope requirements.

[0049] Next, the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] Figure 3 Shows the circuit structure diagram of a dual-loop phase-locked loop provided by an embodiment of the present disclosure, Figure 4 Shows for Figure 3 The schematic structural diagram of the charge pump of the dual-loop phase-locked loop shown, Figure 5 Shows Figure 3 The circuit structure diagram of the first loop filter located on the integral path in the dual-loop phase-locked loop shown, Figure 6 Shows Figure 3 The circuit structure diagram of the second loop filter located on the proportional path in the dual-loop phase-locked loop shown.

[0051] Referring Figure 3 , an embodiment of the present disclosure provides a dual-loop phase-locked loop (PLL) 200, which can be applied to synthesize the local oscillator signal of a radio frequency transceiver, such as a mobile phone. In this embodiment, the dual-loop phase-locked loop 200 at least includes: a frequency discriminator and phase detector 210, an integral path 230, a proportional path 220, and a voltage-controlled oscillator 240.

[0052] Wherein, the voltage-controlled oscillator 240 has a power supply terminal b and a control terminal a, and is used to generate a high-frequency clock signal fout;

[0053] The frequency discriminator and phase detector 210 is used to detect the phase difference φ between the phase of the high-frequency clock signal fout and the phase of the reference signal fref, and generate an integral signal representing the integral value of the phase difference φ and a proportional signal representing the current value of the phase difference φ;

[0054] The integral path 230 includes a first charge pump 231 and a first loop filter 232, and is used to receive the aforementioned integral signal, and supply the adjusted integral signal Vco1 to the power supply terminal b of the aforementioned voltage-controlled oscillator 240;

[0055] The proportional path 220 includes a second charge pump 221 and a second loop filter 222, and is used to receive the aforementioned proportional signal, and supply the adjusted proportional signal Vco2 to the control terminal a of the aforementioned voltage-controlled oscillator 240,

[0056] Wherein, the aforementioned second charge pump 221 is used to adaptively adjust the charging current / discharging current flowing through the output node of the second charge pump 221 following the change of the sweep slope to maintain the potential of the output node, and the aforementioned voltage-controlled oscillator 240 generates a high-frequency clock signal fout having an oscillation frequency controlled by both the adjusted integral signal Vco1 and the adjusted proportional signal Vco2, so that the phase of the high-frequency clock signal fout is locked to the phase of the aforementioned reference signal fref.

[0057] In this embodiment, the voltage-controlled oscillator (VCO) 240 generates a high-frequency clock signal fout based on at least two controllable parameters, such as Vco1 and Vco2 that are separately controlled based on a proportional signal and an integral signal. And accordingly, the frequency of the high-frequency clock signal fout is adjusted according to the control parameters.

[0058] The frequency of the high-frequency clock signal fout provided by the voltage-controlled oscillator 240 is a function of the control voltage. In addition, the VCO has another controllable parameter. When the VCO has a ring oscillator topology including serially connected delay units, for example, the number of delay units, the size of the delay units, the value of the load capacitance of the delay units, the current passing through the delay units, etc. can all be used to control the frequency of the oscillation signal OUT. The proportional signal and the integral signal are separately used, for example, to adjust the control voltage and the size of the delay units.

[0059] In another embodiment, the voltage-controlled oscillator 240 can alternatively be implemented as an inductance-capacitance (LC) type oscillator. The frequency of the LC type oscillator depends on the inductance and capacitance of the LC type oscillator. In one example, the capacitance of the LC type oscillator is jointly determined by at least one variable capacitor and a capacitor bank. The variable capacitor has a voltage-controlled capacitor, and the capacitor bank has a plurality of capacitors optionally included in the LC type oscillator. The proportional signal and the integral signal are separately used, for example, to control the capacitance of the variable capacitor and the number of capacitors selected in the capacitor bank.

[0060] Furthermore, in this embodiment, the aforementioned double-loop phase-locked loop 200 further includes:

[0061] A frequency divider 250, which is coupled between the aforementioned voltage-controlled oscillator 240 and the frequency discriminator and phase detector 210, for dividing the aforementioned high-frequency clock signal fout to obtain a low-frequency signal fb. Among them, the aforementioned frequency discriminator and phase detector 210 detects the aforementioned phase difference φ by comparing the phase of the low-frequency signal fb with the phase of the aforementioned reference signal fref. In a frequency-sweeping system, the frequency sweeping of the output frequency is usually achieved by changing the input division ratio N (N is an integer) of the frequency divider 250.

[0062] In this embodiment, the frequency discriminator and phase detector 210 receives the frequency-divided low-frequency signal fb and the reference signal fref, and generates a pair of signals (the first control signal UP and the second control signal DN) with variable-width pulses. The pulse width varies based on the phase difference φ between the frequency-divided low-frequency signal fb and the reference signal fref. For example, when the frequency-divided low-frequency signal fb leads the reference signal fref with a positive phase difference, the second control signal DN has a wider pulse width proportional to the positive phase difference; when the frequency-divided low-frequency signal fb lags behind the reference signal fref with a positive phase difference, the first control signal UP has a wider pulse width proportional to the positive phase difference.

[0063] Furthermore, in this embodiment, the aforementioned dual-loop phase-locked loop 200 may further include an external crystal oscillator 201, which is used to provide the reference (frequency) signal fref.

[0064] Furthermore, referring Figure 5 to, in this embodiment, the aforementioned first loop filter 232 includes: a first capacitor C3, a first resistor R3, and a second capacitor C4. The first end of the first capacitor C3 and the first end of the first resistor R3 are commonly connected to the output node of the aforementioned first charge pump 231. The second end of the first capacitor C3 is grounded. The second end of the first resistor R3 is connected in series with the second capacitor C4 to ground, and the connection node of the first resistor R3 and the second capacitor C4 is connected to the aforementioned power supply terminal b.

[0065] Furthermore, referring Figure 6 to, in this embodiment, the aforementioned second loop filter 222 includes: a second resistor R1, a third capacitor C1, a third resistor R2, and a fourth capacitor C2. The second resistor R1 and the third capacitor C1 are connected in parallel between the output node of the aforementioned second charge pump 221 and ground. The first end of the third capacitor C1 and the first end of the third resistor R2 are commonly connected to the output node of the aforementioned second charge pump 221. The second end of the third resistor R2 is connected in series with the fourth capacitor C2 to ground, and the connection node of the third resistor R2 and the fourth capacitor C2 is connected to the aforementioned control terminal a.

[0066] Furthermore, referring Figure 4 to, in this embodiment, the second charge pump 221 located on the proportional path 220 includes: an upper current source I1, a lower current source I2, and a bias current source I3.

[0067] Wherein, the upper current source I1 and the lower current source I2 are connected in series between the power supply terminal and ground. The charging current provided by the upper current source I1 / discharging current provided by the lower current source I2 is controlled by a gating switch to change the potential of the output node between the upper current source I1 and the lower current source I2.

[0068] The bias current source I3 is connected between the power supply terminal and the aforementioned output node, and is used to adaptively adjust the charging current / discharging current flowing through the output node following the change of the frequency sweep slope, so as to maintain the potential of the output node. Among them, the bias current provided by the aforementioned bias current source I3 is a desired current preset according to the frequency sweep slope and the characteristics of the double-loop phase-locked loop.

[0069] Further, in this embodiment, any one of the aforementioned upper current source I1, lower current source I2, and bias current source I3 is a complementary metal oxide semiconductor (CMOS) device, or a bipolar complementary metal oxide semiconductor (BICMOS) device.

[0070] Further, in this embodiment, the aforementioned second charge pump 221 further includes:

[0071] A first switch K1, connected between the aforementioned upper current source I1 and the output node, and responsive to a first control signal UP to switch its on / off state to provide the aforementioned charging current;

[0072] A second switch K2, connected between the aforementioned output node and the lower current source I2, and responsive to a second control signal DN to switch its on / off state to provide the aforementioned discharging current;

[0073] A third switch K3, connected between the aforementioned bias current source I3 and the output node, and responsive to a third control signal OF to switch its on / off state to adjust the charging current / discharging current flowing through the output node.

[0074] Further, in this embodiment, the magnitude of the aforementioned bias current is the current value that makes the offset voltage amount output by the second charge pump 221 located on the aforementioned proportional path 220 become zero when the double-loop phase-locked loop 200 switches from the locked mode to the frequency sweep mode and operates at a predetermined frequency sweep slope.

[0075] Specifically, in combination with the foregoing description, the charge pump provided by the embodiment of the present disclosure for the double-loop phase-locked loop 200 adds an additional bias current source I3 to a traditional charge pump architecture. The magnitude of the bias current source I3 is a desired current predicted according to the frequency sweep slope and the characteristics of the phase-locked loop system, and its value is determined by the following steps:

[0076] Method 1:

[0077] 1) Fix the bias current value of the bias current source I3 in the second charge pump 221 located on the proportional path 220 in the double-loop phase-locked loop 200 to 0, and let the entire double-loop phase-locked loop 200 operate in the locked mode;

[0078] 2) On the basis of step 1, let the double-loop phase-locked loop 200 enter the frequency-sweeping mode, and its frequency-sweeping slope is set according to the requirements of the current working environment;

[0079] 3) In the traditional double-loop phase-locked loop 100 in the frequency-sweeping mode, there is an offset in the output voltage of the charge pump 131 on the proportional path 130. In the double-loop phase-locked loop 200, the offset voltage of the output of the second charge pump 221 on the proportional path 220 is measured by setting the current value of the bias current source I3 to 0;

[0080] 4) Increase the bias current value of the bias current source I3 from 0 upwards until the offset voltage of the second charge pump 221 in the proportional path 220 becomes zero. At this time, the offset voltage on the proportional path 220 will be the same as that in the locked mode;

[0081] 5) By repeating the above steps 1) to 4), the magnitudes of the bias currents required at different frequency-sweeping slopes can be obtained, enabling the double-loop phase-locked loop 200 to adapt to different application requirements.

[0082] Method 2:

[0083] Combined with the above Figure 4 shown circuit structure of the second charge pump 221, analyzing its principle shows that:

[0084] Frequency-sweeping phase difference

[0085] and

[0086] Bias current

[0087] wherein, is the frequency-sweeping slope, C3 represents the capacitance of the first loop filter 232 on the integral path 230, Icp1 represents the current magnitude of the output node of the second charge pump 221 on the proportional path 220, and Kvco represents the parameter of the voltage-controlled oscillator 240.

[0088] Therefore, the theoretical value can also be directly calculated according to the frequency-sweeping slope and the loop parameters of the double-loop phase-locked loop 200, and the specific steps are as follows:

[0089] 1) According to formula (1), it is known that the phase difference φ generated by the double-loop phase-locked loop 200 during frequency-sweeping, and this phase difference φ is related to the following parameters: the frequency-sweeping slope ((Framp) / (ΔT)), the capacitance C3 of the first loop filter 232 on the integral path 230, the current Icp1 magnitude of the output node of the second charge pump 221 on the proportional path 220, and the parameter Kvco of the voltage-controlled oscillator 240;

[0090] 2) According to formula (2), the relationship between the phase difference φ and the magnitude of the bias current I3 is known. By adjusting the magnitude of the bias current source I3, this offset phase is compensated back.

[0091] 3) After the phase compensation, the offset voltage will be zero, making the locking state of the dual-loop phase-locked loop 200 the same in the frequency sweep mode and the traditional mode.

[0092] 4) By repeating the above steps 1) to 3), the magnitudes of the bias currents required at different frequency sweep slopes can be obtained, so that the dual-loop phase-locked loop 200 can adapt to different application requirements.

[0093] Therefore, the system parameters of the dual-loop phase-locked loop 200 provided by the embodiments of the present disclosure can be accurately controlled, thereby greatly improving the stability and reliability of the phase-locked loop.

[0094] In summary, in a dual-loop phase-locked loop 200 and its charge pump 221 provided by the embodiments of the present disclosure, the second charge pump 221 located on the proportional path 220 includes an upper current source I1, a lower current source I2, and a bias current source I3. The upper current source I1 and the lower current source I2 are connected in series between the power supply terminal and the ground. The charging current provided by the upper current source I1 / the discharging current provided by the lower current source I2 is controlled by a selection switch to change the potential of the output node between the upper current source I1 and the lower current source I2. The bias current provided by the bias current source I3 is a desired current preset according to the frequency sweep slope and the characteristics of the dual-loop phase-locked loop 200, and is used to adaptively adjust the charging current / discharging current flowing through the output node following the change of the frequency sweep slope to maintain the potential of the output node. Thus, the problem of voltage deviation generated when the dual-loop phase-locked loop 100 works in the frequency sweep mode in the prior art can be effectively compensated, enabling the system parameters of the dual-loop phase-locked loop 200 to be accurately controlled, greatly improving the stability and reliability of the dual-loop phase-locked loop 200, and enabling the dual-loop phase-locked loop to maintain the desired system parameters under different frequency sweep slope requirements.

[0095] It should be noted that in the description of the present disclosure, it should be understood that terms such as "upper", "lower", "inner", etc. indicating the orientation or position relationship are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation to the present disclosure.

[0096] In addition, in this text, the terms "including", "comprising", or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article, or device that includes the said element.

[0097] Finally, it should be noted that: Obviously, the above embodiments are merely examples given for clearly illustrating the present disclosure and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present disclosure.

Claims

1. A charge pump for a dual-loop phase-locked loop, wherein the dual-loop phase-locked loop has a charge pump and a loop filter with a proportional path and an integral path coupled between a phase-frequency detector and a voltage-controlled oscillator. Characterized in that, The charge pump located on the proportional path includes: An upper current source and a lower current source, the upper current source and the lower current source are connected in series between a power supply terminal and ground, and a charging current provided by the upper current source / a discharging current provided by the lower current source is controlled by a gating switch to change the potential of an output node between the upper current source and the lower current source; A bias current source, the bias current source is connected between the power supply terminal and the output node, and a bias current is provided to the output node by the bias current source through a gating switch. Wherein, the dual-loop phase-locked loop operates in a locked mode and a frequency-sweeping mode. In the frequency-sweeping mode, the bias current source provides the bias current, the magnitude of the bias current is related to the frequency-sweeping slope of the dual-loop phase-locked loop, and the charge pump on the proportional path adaptively adjusts the charging current / discharging current flowing through the output node of the charge pump according to the change of the frequency-sweeping slope to maintain the potential of the output node.

2. The charge pump according to claim 1, Characterized in that, It further includes: A first switch, connected between the upper current source and the output node, and switches its on / off state in response to a first control signal to provide the charging current; A second switch, connected between the output node and the lower current source, and switches its on / off state in response to a second control signal to provide the discharging current; A third switch, connected between the bias current source and the output node, and switches its on / off state in response to a third control signal to adjust the charging current / discharging current flowing through the output node.

3. The charge pump according to claim 2, Characterized in that, The magnitude of the bias current is the current value that makes the offset voltage amount output by the charge pump located on the proportional path become zero when the dual-loop phase-locked loop switches from the locked mode to the frequency-sweeping mode and operates at a predetermined frequency-sweeping slope.

4. The charge pump according to claim 3, Characterized in that, The upper current source, the lower current source and the bias current source are current source devices of the same type.

5. The charge pump according to claim 3, Characterized in that, Any one of the upper current source, the lower current source and the bias current source is a complementary metal-oxide-semiconductor device or a bipolar complementary metal-oxide-semiconductor device.

6. A dual-loop phase-locked loop, Characterized in that, It includes: A voltage-controlled oscillator, the voltage-controlled oscillator has a power supply terminal and a control terminal for generating a high-frequency clock signal; A phase-frequency detector for detecting the phase difference between the phase of the high-frequency clock signal and the phase of a reference signal, and generating an integral signal representing the integral value of the phase difference and a proportional signal representing the current value of the phase difference; An integral path, the integral path includes a first charge pump and a first loop filter for receiving the integral signal and supplying the adjusted integral signal to the power supply terminal of the voltage-controlled oscillator. A proportional path, the proportional path including a second charge pump and a second loop filter, for receiving the proportional signal and supplying the regulated proportional signal to a control terminal of the voltage controlled oscillator; Wherein, the second charge pump is the charge pump according to any one of claims 1 to 5, for adaptively adjusting a charging current / discharging current flowing through an output node of the second charge pump following a change in a sweep slope to maintain a potential of the output node, and the voltage controlled oscillator generates a high-frequency clock signal having an oscillation frequency controlled by both the regulated integration signal and the proportional signal, such that a phase of the high-frequency clock signal is locked to a phase of the reference signal.

7. The dual-loop phase-locked loop according to claim 6, characterized in that, further comprising: a frequency divider, coupled between the voltage controlled oscillator and the phase frequency detector, for dividing the high-frequency clock signal to obtain a low-frequency signal, wherein, the phase frequency detector detects the phase difference by comparing a phase of the low-frequency signal with a phase of the reference signal.

8. The dual-loop phase-locked loop according to claim 7, characterized in that, the first loop filter includes: a first capacitor, a first resistor and a second capacitor, a first end of the first capacitor and a first end of the first resistor are commonly connected to an output node of the first charge pump, a second end of the first capacitor is grounded, a second end of the first resistor is serially connected to the second capacitor to ground, and a connection node of the first resistor and the second capacitor is connected to a power supply terminal.

9. The dual-loop phase-locked loop according to claim 8, characterized in that, the second loop filter includes: a second resistor, a third capacitor, a third resistor and a fourth capacitor, the second resistor and the third capacitor are connected in parallel between an output node of the second charge pump and ground, and a first end of the third capacitor and a first end of the third resistor are commonly connected to the output node of the second charge pump, a second end of the third resistor is serially connected to the fourth capacitor to ground, and a connection node of the third resistor and the fourth capacitor is connected to the control terminal.

10. The dual-loop phase-locked loop according to claim 9, characterized in that, a magnitude of a bias current in the second charge pump is proportional to the sweep slope and is proportional to a current of an output node on the proportional path.

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