SiC substrate, method for manufacturing SiC substrate, SiC semiconductor device, and method for manufacturing SiC semiconductor device

Abstract

The present application provides a new technology related to a SiC substrate and a SiC semiconductor having a dislocation conversion layer capable of reducing resistance. The present application is a SiC substrate and a SiC semiconductor device including a dislocation conversion layer (12) having a doping concentration of 1 x 10 15 cm ‑3 above. By including a dislocation conversion layer (12) having such a doping concentration, the propagation of basal plane dislocations to produce a high-resistance laminated defect can be suppressed, and the resistance during the manufacture of a SiC semiconductor device can be reduced.

Description

Technical Field

[0001] This invention relates to SiC substrates, methods for manufacturing SiC substrates, SiC semiconductor devices, and methods for manufacturing SiC semiconductor devices. Background Technology

[0002] Compared to silicon (Si), silicon carbide (SiC) has an insulation breakdown electric field that is an order of magnitude larger, a band gap that is three times larger, and thermal conductivity that is about three times higher. Therefore, SiC holds promise for applications in power devices, high-frequency devices, and high-temperature operating devices.

[0003] Basal plane dislocation (BPD) is known to be one of the fatal defects that cause fatal defects in SiC semiconductor devices.

[0004] Most of the bipolar dislocations (BPDs) in the SiC substrate are transformed into threading edge dislocations (TEDs) during the formation of the epitaxial growth layer (drift layer). However, there is a problem that some BPDs continue directly into the epitaxial growth layer.

[0005] When a forward current is applied to a device, if a minority of charge carriers reach the base plate defect (BPD), the BPD expands into a high-resistivity stacking fault (SF). That is, SF originates from the BPD due to the energy generated when holes and electrons recombine as minority charge carriers. When a high-resistivity portion is generated within the device, the device's reliability decreases.

[0006] To address this problem, a technique has been proposed to provide a dislocation transition layer for BPD→TED transformation between the substrate and the epitaxial growth layer (see, for example, Patent Document 1). By providing a dislocation transition layer with high dislocation transition efficiency between the substrate and the epitaxial growth layer, the continuation of BPD into the epitaxial growth layer is suppressed.

[0007] Furthermore, a technique has been proposed to provide a recombination promoting layer between the dislocation transition layer and the epitaxial growth layer to promote the recombination of a small number of charge carriers (for example, see Patent Document 2). In this way, by providing a recombination promoting layer between the dislocation transition layer and the epitaxial growth layer to eliminate the recombination of a small number of charge carriers, the energy generated by recombination is suppressed from being provided to the BPD to generate SF.

[0008] Existing technical documents

[0009] Patent documents

[0010] Patent Document 1: Japanese Patent Application Publication No. 2009-88223

[0011] Patent Document 2: Japanese Patent Application Publication No. 2018-166196 Summary of the Invention

[0012] The technical problem that the invention aims to solve

[0013] Figure 17 This is a cross-sectional view showing the structure of a SiC substrate that has undergone conventional treatment to suppress stacking defects. (See diagram below.) Figure 17 As shown, the SiC substrate 100 has: an n+ type SiC substrate 101, an n-type dislocation transition layer 102, an n+ type recombination promotion layer 103, and an n-type epitaxial growth layer 104.

[0014] In this conventional n-type dislocation transition layer 102, in order to improve the BPD→TED transition rate (hereinafter referred to as BPD→TED transition rate), the doping concentration needs to be set to a low level. For example, Patent Document 1 describes that it is desirable for the doping concentration of the dislocation transition layer to be 1×10⁻⁶. 15 cm -3 the following.

[0015] However, when the n-type dislocation transition layer 102 is configured with a low doping concentration as described in Patent Document 1, there is a problem of increased resistance in the SiC semiconductor device. That is, there is a trade-off between the BPD→TED transition rate and the resistance of the SiC semiconductor device, making it difficult to achieve both simultaneously.

[0016] Furthermore, in the conventional process of suppressing stacking defects, an n+ type recombination promoting layer 103 is formed to suppress the generation of SF. Therefore, it is necessary to grow an n-type dislocation transformation layer 102, an n+ type recombination promoting layer 103, and an n-type epitaxial growth layer 104 on an n+ type SiC substrate 101, which complicates the process, such as setting growth conditions.

[0017] In view of the above problems, the technical problem to be solved by the present invention is to provide a new technology related to SiC substrates and SiC semiconductors having dislocation transition layers that can reduce resistance.

[0018] Furthermore, a new technique for manufacturing SiC substrates and SiC semiconductors having dislocation transition layers capable of reducing resistance is provided.

[0019] means for solving problems

[0020] The present invention, which solves the above problems, is a SiC substrate comprising a doping concentration of 1×10⁻⁶. 15 cm -3 The above dislocation transformation layer.

[0021] By including a dislocation transition layer with such a doping concentration, the resistance in the dislocation transition layer can be reduced.

[0022] In a preferred embodiment of the present invention, a doping concentration of 1×10⁻⁶ is included. 17 cm -3 The above dislocation transformation layer.

[0023] By including such a doping concentration, the dislocation transition layer can function not only as a dislocation transition layer for BPD→TED transition, but also as a recombination promoting layer for promoting recombination of a small number of charge carriers.

[0024] In a preferred embodiment of the present invention, the dislocation transition layer has a thickness of 1 μm or more.

[0025] In this way, by forming a thicker dislocation transition layer compared to a conventional one, the dislocation transition rate can be increased, and recombination of a small number of charge carriers can be promoted.

[0026] In a preferred embodiment of the invention, the transition rate from basal dislocations to through-edge dislocations in the dislocation transition layer is greater than 95%.

[0027] Furthermore, in a preferred embodiment of the invention, the transition rate of the dislocation transition layer from a basal dislocation to a through-edge dislocation is 100%.

[0028] By simultaneously achieving high conversion rates and high doping concentrations, the number of layers grown on the substrate can be reduced compared to conventional methods. This, in turn, reduces the number of manufacturing steps for SiC substrates and lowers costs.

[0029] In a preferred embodiment of the present invention, a substrate and an epitaxial growth layer are further included, wherein the dislocation transition layer is disposed between the substrate and the epitaxial growth layer, and the doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer.

[0030] Furthermore, the present invention also relates to a method for manufacturing a SiC substrate. Specifically, the present invention, which solves the above-mentioned problems, is a method for manufacturing a SiC substrate, comprising: a crystal growth step to achieve a doping concentration of 1 × 10⁻⁶. 15 cm -3 The above dislocation transformation layers are grown under conditions of increased platform width.

[0031] In a preferred embodiment of the present invention, the crystal growth step is performed under SiC-C equilibrium vapor pressure conditions.

[0032] In a preferred embodiment of the invention, the crystal growth step is a step of growing crystals on a surface where macroscopic step clusters have not been formed.

[0033] Furthermore, the present invention also relates to a SiC semiconductor device. Specifically, the present invention, which solves the above-mentioned problems, is a SiC semiconductor device comprising a doping concentration of 1 × 10⁻⁶.15 cm -3 The above dislocation transformation layer.

[0034] In a preferred embodiment of the present invention, a doping concentration of 1×10⁻⁶ is included. 17 cm -3 The above dislocation transformation layer.

[0035] In a preferred embodiment of the present invention, the dislocation transition layer has a thickness of 1 μm or more.

[0036] In a preferred embodiment of the invention, the transition rate from basal dislocations to through-edge dislocations in the dislocation transition layer is greater than 95%.

[0037] Furthermore, in a preferred embodiment of the invention, the transition rate of the dislocation transition layer from a basal dislocation to a through-edge dislocation is 100%.

[0038] In a preferred embodiment of the present invention, a substrate and an epitaxial growth layer are further included, wherein the dislocation transition layer is disposed between the substrate and the epitaxial growth layer, and the doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer.

[0039] Furthermore, the present invention also relates to a method for manufacturing a SiC semiconductor device. Specifically, the present invention, which solves the above-mentioned problems, is a method for manufacturing a SiC semiconductor device, comprising: a crystal growth step to achieve a doping concentration of 1 × 10⁻⁶. 15 cm -3 The above dislocation transformation layers are grown under conditions of increased platform width.

[0040] In a preferred embodiment of the present invention, the crystal growth step is performed under SiC-C equilibrium vapor pressure conditions.

[0041] In a preferred embodiment of the invention, the crystal growth step is a step of growing crystals on a surface where macroscopic step clusters have not been formed.

[0042] Invention Effects

[0043] According to the disclosed technology, a new technology related to SiC substrates and SiC semiconductors having dislocation transition layers capable of reducing resistance can be provided.

[0044] Furthermore, based on the disclosed technology, a new technique for manufacturing SiC substrates and SiC semiconductors with dislocation transition layers capable of reducing resistance can be provided.

[0045] Other technical problems to be solved, features and advantages will become apparent from reading the detailed embodiments described below in conjunction with the accompanying drawings and claims. Attached Figure Description

[0046] Figure 1 This is a cross-sectional view showing the structure of a SiC substrate according to an embodiment.

[0047] Figure 2 This is a cross-sectional view showing the structure of a SiC substrate according to another embodiment.

[0048] Figure 3 This is an explanatory diagram showing the manufacturing steps of a SiC substrate according to an embodiment.

[0049] Figure 4 This is an explanatory diagram illustrating the steps for removing the modified layer according to the present invention.

[0050] Figure 5 This is an explanatory diagram illustrating the processing altered layer removal steps according to an embodiment.

[0051] Figure 6 This is an explanatory diagram illustrating the crystal growth steps according to the present invention.

[0052] Figure 7 This is an explanatory diagram showing the crystal growth steps according to an embodiment.

[0053] Figure 8 This is an explanatory diagram illustrating the epitaxial growth steps according to the present invention.

[0054] Figure 9 This is an explanatory diagram showing the epitaxial growth steps according to an embodiment.

[0055] Figure 10 This is an explanatory diagram showing a SiC substrate manufacturing apparatus according to an embodiment.

[0056] Figure 11 This is an explanatory diagram showing the manufacturing apparatus for the SiC substrate according to Example 1.

[0057] Figure 12 The results are based on the SIMS analysis of the SiC substrate in Example 1.

[0058] Figure 13 This is an explanatory diagram showing the method for determining the BPD→TED conversion rate.

[0059] Figure 14 This is a graph showing the relationship between the BPD→TED conversion rate and the platform width increase rate.

[0060] Figure 15 These are Arrhenius diagrams of the etching and crystal growth processes.

[0061] Figure 16 These are SEM images of the SiC substrate surface after etching and after crystal growth.

[0062] Figure 17 This is a cross-sectional view showing the structure of a SiC substrate that has undergone conventional treatment to suppress stacking defects. Detailed Implementation

[0063] Hereinafter, preferred embodiments of the SiC substrate, the method for manufacturing the SiC substrate, the SiC semiconductor device, and the method for manufacturing the SiC semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. The scope of the present invention is not limited to the embodiments shown in the drawings, and appropriate modifications can be made within the scope described in the claims. In this specification and the drawings, layers or regions prefixed with n or p signify that electrons or holes are respectively a large number of charge carriers. Furthermore, + and - appended to n or p respectively signify that the impurity concentration is higher and lower than that of layers or regions without + and - appended. When the designations for n or p containing + and - are the same, it indicates that the concentrations are close to each other, but not necessarily the same. Additionally, in the following description of the embodiments and the accompanying drawings, the same reference numerals are used to denote the same structures, and repeated descriptions are omitted.

[0064] SiC Substrates

[0065] Figure 1 This is a cross-sectional view showing the structure of the SiC substrate 10 according to an embodiment. Figure 1 As shown, the SiC substrate 10 according to the embodiment has: a base substrate 11 as an n+ type substrate, a dislocation transition layer 12 as an n+ type layer, and an epitaxial growth layer 13 as an n type layer.

[0066] In this specification, the surface on one side of the semiconductor device on which the SiC substrate 10 is fabricated (specifically, the surface on which the epitaxial growth layer 13 is deposited) is referred to as the main surface, and the surface opposite to the main surface is referred to as the back surface. Furthermore, the main surface and the back surface are collectively referred to as surfaces.

[0067] As the main surface, a surface with an offset angle of several degrees (e.g., 0.4 to 8°) from the (0001) or (000-1) crystal plane can be exemplified. Additionally, in this specification, in the notation of the Miller index, the hyphen "-" indicates that the index immediately following it is the index.

[0068] Typically, a step-plateau structure is formed on the surface of a single-crystal SiC that has been planarized at the atomic level. This step-plateau structure is a stepped structure consisting of alternating steps 14, which are steps at or above one molecular layer, and platforms 15, which are flat areas exposing the {0001} crystal plane.

[0069] In step 14, a 1-molecule layer (0.25 nm) is the minimum height (minimum unit). Multiple layers of this 1-molecule layer are overlapped to form various step heights. In this specification, step 14 is bundled and enlarged, and those with a height exceeding that of a single unit cell of each polymorph are referred to as macro step bundles (MSB).

[0070] That is, in the case of 4H-SiC, MSB refers to a step 14 formed by more than 4 molecular layers (more than 5 molecular layers) bundled together, and in the case of 6H-SiC, it refers to a step 14 formed by more than 6 molecular layers (more than 7 molecular layers) bundled together.

[0071] The substrate 11 can be any substrate formed by processing single-crystal SiC into a plate shape. For example, it can be a SiC wafer made by slicing a SiC ingot manufactured by sublimation or the like. In addition, any polymorph can be used as the crystal polymorph of single-crystal SiC.

[0072] Typically, the substrate 11 that has undergone mechanical processing (e.g., slicing, grinding / polishing) has: a processing-modified layer 111 with processing damage introduced, and a bulk layer 112 without such processing damage introduced.

[0073] Processed altered layer 111 includes, for example, strain 113, scratches 114, and potential scratches 115 (see reference). Figure 4 The presence or absence of this modified layer 111 can be confirmed by SEM-EBSD, TEM, μXRD, etc.

[0074] The substrate 11 is, for example, a nitrogen-doped SiC single-crystal substrate. The doping concentration of the substrate 11 is 1 × 10⁻⁶. 17 cm -3 The preferred value is 1×10. 18 cm -3 The above is preferred to be 1×10 19 cm -3 above.

[0075] Dislocation transition layer 12 is, for example, a nitrogen-doped SiC layer. The doping concentration of dislocation transition layer 12 is 1 × 10⁻⁶. 15 cm -3 The preferred value is 1×10. 16 cm -3 The above is preferred to be 1×10 17 cm -3 The above is further preferred to be 1×10 18 cm -3 The above is further preferred to be 1×10 19 cm -3 above.

[0076] The BPD→TED transition rate of the dislocation transition layer 12 is greater than 95.00%, preferably 96.00% or more, more preferably 97.00% or more, even more preferably 98.00% or more, and even more preferably 99.00% or more.

[0077] In other words, when the dislocation transition layer 12 is grown on the main surface of the substrate 11 with 5000 BPDs, the number of BPDs on the main surface of the dislocation transition layer 12 is 250 or less. Furthermore, when the dislocation transition layer 12 is grown on the main surface of the substrate 11 with 10000 BPDs, the number of BPDs on the main surface of the dislocation transition layer 12 is 500 or less.

[0078] Furthermore, when the dislocation transition layer 12 is grown on the main surface of the substrate 11 with 20,000 BPDs, the number of BPDs on the main surface of the dislocation transition layer 12 is less than 1,000.

[0079] Furthermore, the BPD→TED transition rate of the dislocation transition layer 12 is greater than 99.95%, preferably 99.96% or more, more preferably 99.97% or more, even more preferably 99.98% or more, even more preferably 99.99% or more, and even more preferably 100%.

[0080] That is, it is desirable that the BPD present on the substrate 11 is completely transformed into TED when the dislocation transition layer 12 is formed, and that there is no BPD on the main surface of the dislocation transition layer 12.

[0081] The thickness of the dislocation transition layer 12 is 1 μm or more, preferably 3 μm or more, more preferably 5 μm or more, even more preferably 7 μm or more, and even more preferably 10 μm or more.

[0082] The epitaxial growth layer 13 is, for example, a nitrogen-doped SiC layer. The doping concentration of the epitaxial growth layer 13 is lower than that of the dislocation transition layer 12. In other words, the doping concentration of the dislocation transition layer 12 is greater than that of the epitaxial growth layer 13, resulting in lower resistance during device operation.

[0083] Furthermore, it is known that in MOSFETs manufactured by forming an oxide film on the main surface of the epitaxial growth layer 13, the presence of the MSB has a fatal impact on operating performance and reliability.

[0084] Therefore, it is desirable that no MSB (Medium Substrate Block) is formed on the main surface of the epitaxial growth layer 13. Furthermore, it is desirable that the main surface of the epitaxial growth layer 13 has steps 14 of 1 cell height. The height of these steps 14, or the platform width W, can be confirmed using the method for evaluating SEM image contrast described in AFM or Japanese Patent Application Publication No. 2015-179082.

[0085] The SiC substrate 10 according to the present invention comprises a doping concentration of 1×10⁻⁶. 15 cm -3 The above describes the dislocation transition layer 12. In this way, by setting the dislocation transition layer 12 that performs the BPD→TED transition to a higher doping concentration than the conventional n-type dislocation transition layer 102, the resistance of the SiC semiconductor device can be reduced.

[0086] Furthermore, the SiC substrate 10 according to the present invention includes a doping concentration of 1×10⁻⁶. 17 cm -3 The dislocation transition layer 12 described above. That is, by setting a higher doping concentration than the formed epitaxial growth layer 13, recombination of a small number of charge carriers can be promoted. Thus, in addition to dislocation transition, the dislocation transition layer 12 can also function as a recombination promotion layer.

[0087] That is, it is desirable that the doping concentration of the dislocation transition layer 12 is higher than that of the epitaxial growth layer 13.

[0088] Furthermore, the dislocation transition layer 12 of the SiC substrate 10 according to the present invention has a thickness of 1 μm or more. By having a thickness of at least 1 μm, the BPD→TED transition rate can be improved.

[0089] Furthermore, by setting a thickness of 1 μm or more, the region for recombination of a small number of charge carriers can be expanded, and the distance between the region with high recombination frequency (the main surface side of the dislocation transition layer 12) and the region with a large number of BPDs (the back surface side of the dislocation transition layer 12) can be increased. Therefore, the energy generated by recombination can be suppressed from being supplied to the BPDs.

[0090] Furthermore, the SiC substrate 10 according to this embodiment has a three-layer structure consisting of a base substrate 11 as an n+ type substrate, a dislocation transition layer 12 as an n+ type layer, and an epitaxial growth layer 13 as an n-type layer. On the other hand, a conventional SiC substrate 100 has a four-layer structure consisting of an n+ type SiC base substrate 101, an n-type dislocation transition layer 102, an n+ type recombination promoting layer 103, and an n-type epitaxial growth layer 104 (see reference). Figure 17 According to this embodiment, the SiC substrate 10, compared with a conventional SiC substrate 100, can reduce the number of grown layers and the number of steps. This simplifies the growth conditions and reduces costs.

[0091] Figure 2 This is a cross-sectional view showing the structure of a SiC substrate 10 according to another embodiment. (See diagram below.) Figure 2 As shown, the SiC substrate 10 according to another embodiment is an epitaxial ready substrate including a base substrate 11 as an n+ type layer and a dislocation transition layer 12 as an n+ type layer.

[0092] In this way, the SiC substrate 10 can also be manufactured before the epitaxial growth layer 13 is formed.

[0093] Furthermore, it is known that when an epitaxial growth layer 13 is formed on a surface where MSBs are formed, defects caused by MSBs sometimes occur in the epitaxial growth layer 13.

[0094] Therefore, it is desirable that no MSB is formed on the main surface of the dislocation transformation layer 12. Furthermore, it is desirable that steps 14 of 1 cell height are arranged on the main surface of the dislocation transformation layer 12.

[0095] According to the present invention, a dislocation transition layer 12 is included, which is an n+ type layer with a higher doping concentration than the n-type dislocation transition layer 102 of the SiC substrate 100 subjected to conventional treatment to suppress stacking defects. This novel structure, in addition to suppressing SF generation, also significantly reduces the resistance of the SiC semiconductor device, simplifies the structure of the SiC substrate, and simplifies the manufacturing process.

[0096] Manufacturing methods for SiC substrates

[0097] Next, a detailed description of the manufacturing method of the SiC substrate according to the embodiments will be provided. Figure 3 This is an explanatory diagram showing the manufacturing steps of a SiC substrate according to an embodiment.

[0098] The method for manufacturing a SiC substrate according to this embodiment includes: a processing modification layer removal step S1, removing the processing modification layer 111 of the substrate 11; and a crystal growth step S2, increasing the doping concentration to 1×10⁻⁶ under the condition of increasing the platform width W. 15 cm -3 The above dislocation transformation layer is grown; and the epitaxial growth step S3 is performed to grow the epitaxial growth layer 13.

[0099] Alternatively, after the processing modification layer removal step S1, a bundle decomposition step S4 may be included to remove the MSBs formed on the main surface of the substrate 11. Alternatively, after the crystal growth step S2, a bundle decomposition step S4 may be included to remove the MSBs formed on the main surface of the dislocation transformation layer 12. Alternatively, after the epitaxial growth step S3, a bundle decomposition step S4 may be included to remove the MSBs formed on the main surface of the epitaxial growth layer 13.

[0100] The following is a detailed explanation of each step.

[0101] Furthermore, the bundle decomposition step S4 can be performed using a common method even if it is carried out in any order. Therefore, the bundle decomposition step S4 will be described after the processing modified layer removal step S1, the crystal growth step S2, and the epitaxial growth step S3.

[0102] <Processing and Deterioration Layer Removal Steps>

[0103] Figure 4 This is an explanatory diagram illustrating the processing-modified layer removal step S1 according to the present invention. The processing-modified layer removal step S1 is the step of removing the processing-modified layer 111 introduced into the n+ type substrate 11.

[0104] The processing modified layer removal step S1 can be performed using any method that can remove the processing modified layer 111. Examples include: Si vapor pressure etching (SiVE) method, which etches single crystal SiC by heating under Si vapor pressure; hydrogen etching method, which uses hydrogen as the etching gas; and chemical mechanical polishing (CMP).

[0105] The preferred implementation of this step will be described in detail below.

[0106] Figure 5 This is an explanatory diagram showing the processing altered layer removal step S1 according to an embodiment.

[0107] According to this embodiment, the modified layer removal step S1 is a step of etching the SiC substrate 10 by housing it in a quasi-enclosed space including a Si element supply source and a C element supply source and heating it.

[0108] Additionally, the term "quasi-closed space" in this specification refers to a space capable of evacuating the container or supplying dopant gas, but capable of sealing off at least a portion of the vapor generated within the container. This quasi-closed space can be formed within the main container 30 described later or within the high-melting-point container 50.

[0109] Specifically, the modified layer removal step S1 is a step in which the SiC substrate 10 is arranged in a manner opposite to the SiC material body 20 within the main container 30 that exposes the SiC material body 20, and then heated (see reference). Figure 5 (a) in the middle.

[0110] An etching space X is formed between a SiC substrate 10 and a SiC material body 20 at a temperature lower than that of the SiC substrate 10 by arranging them relative to each other.

[0111] In this etching space X, atomic transport occurs driven by the temperature gradient formed by the heating furnace 40, resulting in the etching of the SiC substrate 10.

[0112] Furthermore, by controlling the Si / C atomic ratio configured within the main container 30, heat treatment under SiC-Si equilibrium vapor pressure and heat treatment under SiC-C equilibrium vapor pressure can be selected.

[0113] The “SiC-Si vapor pressure environment” in this specification refers to the vapor pressure environment when SiC (solid) and Si (liquid phase) reach phase equilibrium through the gas phase.

[0114] The SiC-Si equilibrium vapor pressure environment is formed by heat treatment of a quasi-enclosed space with a Si / C atomic ratio exceeding 1. Specifically, when a SiC substrate 10 with a stoichiometric ratio of 1:1, a SiC material body 20 with a stoichiometric ratio of 1:1, and a Si vapor supply source 35 (Si particles, etc.) are disposed within a SiC main container 30 with ...

[0115] Furthermore, the “SiC-C equilibrium vapor pressure environment” in this specification refers to the vapor pressure environment when SiC (solid phase) and C (liquid phase) reach a phase equilibrium state through the gas phase.

[0116] The SiC-C equilibrium vapor pressure environment is formed by heat treatment of a quasi-enclosed space with a Si / C atomic ratio of less than 1. Specifically, when a SiC substrate 10 with a stoichiometric ratio of 1:1 and a SiC material body 20 with a stoichiometric ratio of 1:1 are disposed within a SiC main container 30, the Si / C atomic ratio within the main container 30 is 1 (refer to...). Figure 5 (a)). Alternatively, a C vapor supply source (C particles, etc.) can be configured to make the Si / C atomic ratio less than 1.

[0117] Furthermore, the modified layer removal step S1 involves placing the aforementioned main container 30 within a high-melting-point container 50 that exposes the Si vapor supply source 54 and then heating it (see [reference]). Figure 5 (a) in the middle.

[0118] In this way, by arranging the main container 30 together with the Si vapor supply source 54 within the high-melting-point container 50 forming a semi-enclosed space for heating, the venting of Si-containing gaseous species from the main container 30 can be suppressed. That is, by balancing the vapor pressure of Si-containing gaseous species inside the main container 30 with the vapor pressure of Si-containing gaseous species outside the main container 30, the environment inside the main container 30 can be maintained.

[0119] The SiC material body 20 is made of SiC, which is capable of receiving or transferring Si and C elements between itself and the SiC substrate 10 by heating relative to the SiC substrate 10. For example, a SiC container (main container 30) or a SiC substrate (SiC material substrate) can be used. In addition, any polymorph can be used as the crystal polymorph of the SiC material body 20, including polycrystalline SiC.

[0120] In addition, the SiC material body 20 can also be a sintered body obtained by sintering a Si element supply source and a C element supply source.

[0121] The driving force for transporting Si and C elements in this etching process can be the temperature gradient or chemical potential difference between the SiC substrate 10 and the SiC material body 20.

[0122] According to the processing modification layer removal step S1 of this embodiment, the SiC substrate 10 and the SiC material body 20 are arranged opposite each other, and heated in a temperature range of 1400°C or higher and 2300°C or lower, with the SiC substrate 10 as the high-temperature side and the SiC material body 20 as the low-temperature side.

[0123] Therefore, the following reactions 1) to 5) are continuously carried out, and as a result, it is believed that the etching of the SiC substrate 10 is performed (refer to...). Figure 5 (b) in the middle.

[0124] 1) SiC(s) → Si(v) + C(s)

[0125] 2) 2C(s) + Si(v) → SiC2(v)

[0126] 3) C(s) + 2Si(v) → Si₂C(v)

[0127] 4) Si(v) + SiC2(v) → 2SiC(s)

[0128] 5) Si₂C(v) → Si(v) + SiC(s)

[0129] 1) Explanation: Due to heating the SiC substrate 10 (SiC(s)), Si atoms (Si(v)) are detached from the surface of the SiC substrate 10 through thermal decomposition (Si atom sublimation step).

[0130] Explanation of 2) and 3): Due to the detachment of Si atoms (Si(v)), the C atoms (C(s)) remaining on the surface of the SiC substrate 10 react with the Si vapor (Si(v)) in the quasi-enclosed space. As a result, the C atoms (C(s)) sublimate from the surface of the SiC substrate 10 as Si2C or SiC2 (C atom sublimation step).

[0131] Explanation of 4) and 5): The sublimated Si2C or SiC2, etc., reach the SiC material body 20 in the quasi-closed space due to the temperature gradient and undergo crystal growth.

[0132] Thus, the processing modification layer removal step S1 according to this embodiment includes: a Si atom sublimation step, in which Si atoms are thermally sublimated from the surface of the SiC substrate 10; and a C atom sublimation step, in which C atoms remaining on the surface of the SiC substrate 10 are sublimated from the surface of the SiC substrate 10 by reacting with Si vapor in the quasi-enclosed space.

[0133] According to this embodiment, the etching temperature is preferably set in the range of 1400°C to 2300°C.

[0134] The etching rate according to this embodiment can be controlled by the above-mentioned temperature range and can be selected in the range of 0.001 μm / min to 2 μm / min.

[0135] According to this embodiment, the etching time can be set to any time to achieve the desired etching amount. For example, if the etching amount is to be set to 1 μm when the etching rate is 1 μm / min, the etching time is 1 minute.

[0136] According to this embodiment, the temperature gradient is set in the range of 0.1℃ / mm to 5℃ / mm.

[0137] Alternatively, an inert gas can be introduced during etching. This inert gas can be selected from Ar, He, N2, etc., and is obtained by... -5 By introducing this inert gas within the range of Pa to 10000 Pa, the vacuum level of the heating furnace 40 (main heating chamber 41) can be adjusted.

[0138] Alternatively, after the processing modification layer removal step S1, a bundle decomposition step S4 may be included to remove the MSB formed on the surface of the substrate 11.

[0139] Furthermore, in the processing modified layer removal step S1, if etching is performed under a SiC-Si vapor pressure environment where no MSB is formed on the main surface of the SiC substrate 10, the bundle decomposition step S4 may not be omitted. In other words, the processing modified layer removal step S1 and the bundle decomposition step S4 may be performed simultaneously.

[0140] <Crystal Growth Steps>

[0141] Figure 6 This is an explanatory diagram illustrating the crystal growth step S2 according to the present invention. The crystal growth step S2 is a step of growing an n+ type dislocation transformation layer 12 on an n+ type substrate 11 under the condition of increasing the platform width W.

[0142] Thus, by growing the dislocation transition layer 12 under the condition of increasing the plateau width W, both a high BPD→TED transition rate and a high doping concentration can be achieved simultaneously. Furthermore, the condition of increasing the plateau width W can be exemplified by a SiC-C equilibrium vapor pressure environment or a C-rich environment.

[0143] Therefore, any method that enables the SiC substrate 10 to grow crystals under SiC-C equilibrium vapor pressure or C-rich conditions can be used for crystal growth step S2. Examples include sublimation and chemical vapor deposition (CVD).

[0144] The preferred implementation of this step will be described in detail below.

[0145] Figure 7 This is an explanatory diagram showing the crystal growth step S2 according to the embodiment.

[0146] According to this embodiment, crystal growth step S2 is a step of housing the SiC substrate 10 in a quasi-enclosed space including a Si element supply source and a C element supply source and heating it to perform crystal growth (see reference). Figure 7 (a) in the middle.

[0147] Specifically, the crystal growth step S2 is the same as the modified layer removal step S1, which involves placing the SiC substrate 10 in a manner opposite to the SiC material body 20 within the main container 30, exposing the Si element supply source and the C element supply source, and then heating it (see reference). Figure 7 (b) in the middle.

[0148] The above-mentioned processing and altered layer removal step S1 is a step of conveying Si and C elements from the SiC substrate 10 to the SiC material body 20 to etch the SiC substrate 10.

[0149] In contrast, the crystal growth step S2 is a step of transporting Si and C elements from the SiC material body 20 to the SiC substrate 10 to perform crystal growth on the SiC substrate 10.

[0150] A crystal growth space Y is formed between a SiC substrate 10 and a SiC material body 20 at a temperature higher than that of the SiC substrate 10 by arranging them relative to each other.

[0151] In the crystal growth space Y, the temperature gradient formed by the heating furnace 40 drives the transport of atoms, and as a result, crystal growth can be carried out on the SiC substrate 10.

[0152] Crystal growth step S2 is a step in which the dislocation transformation layer 12 is grown under SiC-C equilibrium vapor pressure. Therefore, it is formed by heat treatment of a quasi-closed space with a Si / C atomic ratio of less than 1.

[0153] That is, the crystal growth step S2 is a step of heating the SiC substrate 10 and the SiC material body 20 in a quasi-closed space with a Si / C atomic ratio of more than 1, and forming a temperature gradient between the SiC substrate 10 and the SiC material body 20.

[0154] In addition, the crystal growth step S2 is the same as the modified layer removal step S1, in which the above-mentioned main container 30 is placed in a high melting point container 50 that exposes the Si vapor supply source 54 and heated to maintain the environment inside the main container 30.

[0155] According to the crystal growth step S2 of this embodiment, the SiC substrate 10 and the SiC material body 20 are arranged opposite to each other, and heated in a temperature range of 1400°C or higher and 2300°C or lower, with the SiC substrate 10 as the low-temperature side and the SiC material body 20 as the high-temperature side.

[0156] Therefore, by continuously performing reactions 1) to 5), it is believed that crystal growth on the SiC substrate 10 is achieved (refer to...). Figure 7 (b) in the middle.

[0157] 1) Poly-SiC(s)→Si(v)+C(s)

[0158] 2) 2C(s) + Si(v) → SiC2(v)

[0159] 3) C(s) + 2Si(v) → Si₂C(v)

[0160] 4) Si(v) + SiC2(v) → 2SiC(s)

[0161] 5) Si₂C(v) → Si(v) + SiC(s)

[0162] 1) Explanation: Due to heating the SiC material (Poly-SiC(s)), Si atoms (Si(v)) are removed from SiC through thermal decomposition.

[0163] Explanation of 2) and 3): Due to the detachment of Si atoms (Si(v)), the remaining C atoms (C(s)) react with Si vapor (Si(v)) in the quasi-closed space. As a result, the C atoms (C(s)) sublimate into Si2C or SiC2, etc., within the quasi-closed space.

[0164] Explanation of 4) and 5): The sublimated Si2C or SiC2, etc., reach / diffuse to the platform of SiC substrate 10 due to the temperature gradient (or chemical potential difference) and reach the step, thereby continuing the polymorphism of the SiC substrate 10 and growing (step flow growth).

[0165] At this time, the dopant of the SiC material body 20 is transported together with the raw materials (Si and C elements), thus maintaining the doping concentration of the SiC material body 20, and the dislocation transition layer 12 grows.

[0166] Therefore, by selecting the type or concentration of doping in the SiC material body 20, the dopant and doping concentration of the dislocation transition layer 12 can be controlled.

[0167] That is, when the desired nitrogen doping concentration is 1×10⁻⁶, 15 cm -3 In the case of the above dislocation transition layer 12, the nitrogen doping concentration is 1×10⁻⁶. 15 cm -3 The SiC material 20 described above is sufficient. Furthermore, to obtain a nitrogen doping concentration of 1×10⁻⁶... 17 cm -3 In the case of the above dislocation transition layer 12, the nitrogen doping concentration is 1×10⁻⁶. 17 cm -3 The SiC material body 20 mentioned above is sufficient.

[0168] Therefore, the doping concentration of the SiC material bulk 20 is 1×10⁻⁶. 15 cm -3 The preferred value is 1×10. 16 cm -3 The above is preferred to be 1×10 17 cm -3 The above is further preferred to be 1×10 18 cm -3 The above is further preferred to be 1×10 19 cm -3 above.

[0169] In addition, doping can also be achieved by supplying a doping gas during heat treatment.

[0170] The growth temperature according to this embodiment is preferably set in the range of 1400 to 2300°C.

[0171] The growth rate according to this embodiment can be controlled by the temperature range described above, and can be selected within the range of 0.001 to 2 μm / min.

[0172] According to this embodiment, the growth time can be set to any time to achieve the desired growth amount. For example, if the growth amount is to be set to 1 μm when the growth rate is 1 μm / min, the growth amount is 1 minute.

[0173] According to this embodiment, the temperature gradient is set in the range of 0.1 to 5 °C / mm.

[0174] In this method, a doping gas (N2, etc.) can be supplied, and it can be within 10... -5 It is introduced into the main heating chamber 41 within the range of up to 10000 Pa.

[0175] Furthermore, it is preferable that the crystal growth step S2 is performed on the surface where no MSB has formed. Therefore, it is desirable that, in the processing modification layer removal step S1, etching is performed in a SiC-Si vapor pressure environment where no MSB has formed on the main surface of the SiC substrate 10.

[0176] Furthermore, in the process of removing the modified layer S1, if etching is performed on the main surface of the SiC substrate 10 under the condition of forming MSB, it is desirable to perform the bundle decomposition step S4 (described later) before the crystal growth step S2.

[0177] Alternatively, a bundle decomposition step S4 can be included after the crystal growth step S2 to remove the MSB formed on the surface of the dislocation transition layer 12.

[0178] <Epipolar Growth Steps>

[0179] Figure 8 This is an explanatory diagram showing the epitaxial growth step S3 according to the present invention. Epitaxial growth step S3 is the step of growing an n-type epitaxial growth layer 13 on the dislocation transformation layer 12.

[0180] The epitaxial growth step S3 can employ any method capable of growing the epitaxial growth layer 13. Examples include chemical vapor deposition (CVD), physical vapor transport (PVT), and metastable solvent epitaxy (MSE).

[0181] The preferred implementation of this step will be described in detail below.

[0182] According to this embodiment, the epitaxial growth step S3 is the same as the crystal growth step S2, which involves housing the SiC substrate 10 in a quasi-enclosed space including a Si element supply source and a C element supply source and heating it to perform crystal growth.

[0183] Specifically, in the crystal growth step S2, the SiC substrate 10 and the SiC material body 20 are arranged opposite each other, and heated in a temperature range of above 1400°C and below 2300°C with the SiC substrate 10 as the low-temperature side and the SiC material body 20 as the high-temperature side (see reference). Figure 7 ).

[0184] The epitaxial growth step S3 is a step of crystal growth of the epitaxial growth layer 13, which is an n-type layer, with a lower doping concentration than the dislocation transition layer 12, which is an n+ type layer.

[0185] Therefore, the doping concentration of the SiC material bulk 20 used in the epitaxial growth step S3 is 1×10⁻⁶. 17 cm -3 The following is preferred: 1×10 16 cm -3 Hereinafter, 1×10 is more preferred. 15 cm -3 the following.

[0186] The growth temperature according to this embodiment is preferably set in the range of 1400 to 2300°C.

[0187] The growth rate according to this embodiment can be controlled by the temperature range described above, and can be selected within the range of 0.001 to 2 μm / min.

[0188] According to this embodiment, the growth time can be set to any time to achieve the desired growth amount. For example, if the growth rate is 1 μm / min and the desired growth amount is 1 μm, the growth amount is 1 minute.

[0189] The temperature gradient according to this embodiment is set in the range of 0.1 to 5 °C / mm.

[0190] Furthermore, the epitaxial growth step S3 is a step of crystal growth on a surface where MSB has not been formed. Therefore, it is desirable to perform the bundle decomposition step S4, which will be described later, before the epitaxial growth step S3.

[0191] Alternatively, a bundle decomposition step S4 can be included after the epitaxial growth step S3 to remove the MSBs formed on the surface of the epitaxial growth layer 13.

[0192] <Bundling Decomposition Steps>

[0193] The clustering and decomposition step S4 can be any method that can decompose the MSBs formed on the surface of the SiC substrate 10. For example, Si vapor pressure etching (SiVE) method, which etches single-crystal SiC by heating under Si vapor pressure, can be used.

[0194] The preferred implementation of this step will be described in detail below.

[0195] Figure 9 This is an explanatory diagram showing the bundle decomposition step S4 according to an embodiment.

[0196] According to this embodiment, the bundle decomposition step S4 is a step of etching or growing a crystal in which the SiC substrate 10 is housed in a quasi-closed space including a Si element supply source and a C element supply source and the substrate is etched in a SiC-Si equilibrium vapor pressure environment.

[0197] Specifically, the bundle decomposition step S4, like the modified layer removal step S1 and the crystal growth step S2, involves placing the SiC substrate 10 and the Si vapor supply source 35 opposite to the SiC material body 20 within the main container 30, exposing the SiC material body 20 (the Si element supply source and the C element supply source), and then heating it (see reference). Figure 9 ).

[0198] In addition, similar to the processing modification layer removal step S1 and the crystal growth step S2, the environment inside the main container 30 is maintained by placing the main container 30 inside a high melting point container 50 that exposes the Si vapor supply source 54 and heating it.

[0199] Figure 9 (a) shows a method of decomposing the MSB formed on the surface of the SiC substrate 10 by etching under SiC-Si equilibrium vapor pressure conditions.

[0200] That is, in such a manner that the SiC substrate 10 and the SiC material body 20 are disposed opposite to each other in a quasi-closed space where the Si / C atomic ratio exceeds 1, and heating is performed with the SiC substrate 10 as the high-temperature side and the SiC material body 20 as the low-temperature side.

[0201] On the other hand, Figure 9 The (b) in [reference] shows a method of decomposing and forming the MSB on the surface of the SiC substrate 10 by performing crystal growth in a SiC-Si equilibrium vapor pressure environment.

[0202] That is, in such a manner that the SiC substrate 10 and the SiC material body 20 are disposed opposite to each other in a quasi-closed space where the Si / C atomic ratio exceeds 1, and heating is performed with the SiC substrate 10 as the low-temperature side and the SiC material body 20 as the high-temperature side.

[0203] According to the bunch decomposition step S4 of the present embodiment, by heat-treating the SiC substrate 10 in a SiC-Si equilibrium vapor pressure environment, the MSB on the surface of the SiC substrate 10 can be decomposed and formed.

[0204] In addition, the etching conditions and growth conditions can be the conditions described in the processing and deterioration layer removal step S1 or the crystal growth step S2.

[0205] <Manufacturing apparatus for SiC substrate>

[0206] Hereinafter, a manufacturing apparatus for implementing the above-described manufacturing method of the SiC substrate will be described in detail.

[0207] As Figure 10 shown, the manufacturing apparatus for the SiC substrate according to the present embodiment includes: a main body container 30 capable of accommodating the SiC substrate 10; and a heating furnace 40 capable of heating to form a temperature gradient between the SiC substrate 10 and the SiC material body 20.

[0208] (Main body container)

[0209] The main body container 30 is a fitting container including an upper container 31 and a lower container 32 that can be fitted to each other. A minute gap 33 is formed at the fitting portion of the upper container 31 and the lower container 32, and is configured to be able to exhaust (vacuum) the inside of the main body container 30 from the gap 33.

[0210] The upper container 31 and the lower container

[0211] In addition, such as Figure 5 , Figure 7 , Figure 9 As shown, a structure can also be used to separately house the substrate-shaped SiC material body 20. In this case, a spacer (such as a substrate holding fixture 34) can be arranged between the substrate-shaped SiC material body 20 and the SiC substrate 10 to form an etching space X or a crystal growth space Y. It is desirable that the substrate holding fixture 34 is made of the same high-melting-point material as the high-melting-point container 50.

[0212] That is, the main container 30 is configured such that when heated while housing the SiC substrate 10, an atmosphere containing Si and C elements is generated in the internal space. In this embodiment, an atmosphere containing Si and C elements is formed in the internal space by heating the SiC material body 20 made of polycrystalline SiC.

[0213] Furthermore, it is desirable that the space within the heated main container 30 becomes a vapor pressure environment of a mixed system of gaseous species containing Si and gaseous species containing C. Examples of the Si-containing gaseous species include Si, Si2, Si3, Si2C, SiC2, and SiC. Examples of the C-containing gaseous species include Si2C, SiC2, SiC, and C. That is, it is preferable that the space contains SiC-based gases within a quasi-closed space.

[0214] The etching space X or crystal growth space Y is a space in which the raw material is transported from the SiC substrate 10 to the SiC material body 20 by means of the temperature gradient set between the SiC substrate 10 and the SiC material body 20, and is a space in which the raw material is transported from the SiC material body 20 to the SiC substrate 10.

[0215] For example, consider the following situation: the SiC substrate 10 is configured such that when comparing the temperature of the surface of the SiC substrate 10 with the temperature of the SiC material body 20 opposite to that surface, the temperature of the SiC substrate 10 is higher and the temperature of the SiC material body 20 is lower (refer to...). Figure 9 (a)). Thus, when the SiC substrate 10 and the SiC material body 20 are arranged opposite each other and heated in such a way that the SiC substrate 10 is the high-temperature side and the SiC material body 20 is the low-temperature side, the raw material is transported from the SiC substrate 10 to the SiC material body 20, and the Si substrate 10 is etched. That is, an etching space X is formed between the SiC material body 20 and the SiC substrate 10.

[0216] On the other hand, the following situation is considered: the SiC substrate 10 is configured such that when comparing the temperature of the surface of the SiC substrate 10 with the temperature of the SiC material body 20 opposite to that surface, the temperature of the SiC substrate 10 is lower and the temperature of the SiC material body 20 is higher (refer to...). Figure 9 (b)). Thus, when the SiC substrate 10 and the SiC material body 20 are arranged opposite each other and heated in such a way that the SiC substrate 10 is the low-temperature side and the SiC material body 20 is the high-temperature side, the raw material is transported from the SiC material body 20 to the SiC substrate 10, and single-crystal SiC grows on the SiC substrate 10. That is, a crystal growth space Y is formed between the SiC material body 20 and the SiC substrate 10.

[0217] <Heating Furnace>

[0218] like Figure 10 As shown, the heating furnace 40 includes: a main heating chamber 41, capable of heating the workpiece (SiC substrate 10, etc.) to a temperature of 1000°C or higher and 2300°C or lower; a preheating chamber 42, capable of preheating the workpiece to a temperature of 500°C or higher; a high melting point container 50, capable of housing the main container 30; and a moving device 43 (moving stage), capable of moving the high melting point container 50 from the preheating chamber 42 to the main heating chamber 41.

[0219] The main heating chamber 41 is formed as a regular hexagon in the top sectional view, and a high melting point container 50 is arranged inside it.

[0220] A heater 44 (mesh heater) is installed inside the main heating chamber 41. In addition, a multi-layer heat-reflective metal plate (not shown) is fixed to the side wall or top of the main heating chamber 41. The multi-layer heat-reflective metal plate is configured to reflect the heat from the heater 44 toward approximately the center of the main heating chamber 41.

[0221] Therefore, a heater 44 is arranged in the main heating chamber 41 to surround the high melting point container 50 containing the object to be processed, and a multi-layer heat-reflective metal plate is arranged on its outside, so that the temperature can be raised to a temperature of more than 1000°C and less than 2300°C.

[0222] Alternatively, the heater 44 can be, for example, a resistance heater or a high-frequency induction heater.

[0223] Furthermore, heater 44 may also employ a structure capable of forming a temperature gradient within the high-melting-point container 50. For example, heater 44 may also be configured to have multiple heaters arranged on the upper side. Additionally, heater 44 may be configured such that its width increases as it moves upwards. Alternatively, heater 44 may be configured to increase the supplied power as it moves upwards.

[0224] In addition, the main heating chamber 41 is connected to a vacuum forming valve 45 for venting the main heating chamber 41, an inert gas injection valve 46 for introducing inert gas into the main heating chamber 41, and a vacuum gauge 47 for measuring the vacuum level in the main heating chamber 41.

[0225] A vacuum forming valve 45 is connected to a vacuum pump (not shown) for evacuating the main heating chamber 41 by venting exhaust gas. Through this vacuum forming valve 45 and the vacuum pump, the vacuum level in the main heating chamber 41 can be adjusted to, for example, 10 Pa or less, more preferably 1 Pa or less, and even more preferably 10 Pa. -3 Pa or less. A turbomolecular pump can be exemplified as this vacuum pump.

[0226] An inert gas injection valve 46 is connected to an inert gas supply source (not shown). Through this inert gas injection valve 46 and the inert gas supply source, inert gas can be injected into a gas system with a capacity of 10... -5 An inert gas is introduced into the main heating chamber 41 within a range up to 10000 Pa. Ar, He, N2, etc., can be selected as the inert gas.

[0227] Furthermore, the inert gas injection valve 46 is a dopant gas supply device capable of supplying dopant gas into the main container 30. That is, by selecting a dopant gas (e.g., N2, etc.) as the inert gas, the doping concentration of the growth layer can be adjusted.

[0228] The preheating chamber 42 is connected to the main heating chamber 41 and is configured to allow the high-melting-point container 50 to be moved by the moving device 43. Furthermore, in this embodiment, the preheating chamber 42 is configured to utilize the residual heat from the heater 44 of the main heating chamber 41 for heating. For example, when the main heating chamber 41 is heated to 2000°C, the preheating chamber 42 is heated to approximately 1000°C, allowing for degassing of the workpiece (SiC substrate 10, main container 30, high-melting-point container 50, etc.).

[0229] The moving device 43 is configured to carry the high melting point container 50 and is capable of moving between the main heating chamber 41 and the preheating chamber 42. Since the transfer between the main heating chamber 41 and the preheating chamber 42 via the moving device 43 is completed in as little as 1 minute, heating and cooling rates of 1 to 1000 °C / min can be achieved.

[0230] In this way, because rapid heating and rapid cooling are possible, it is possible to observe surface shapes that are difficult to achieve in conventional devices and do not have a low-temperature growth history during heating and cooling.

[0231] In addition, Figure 10 In this configuration, the preheating chamber 42 is located below the main heating chamber 41, but it is not limited to this and can also be configured in any direction.

[0232] Furthermore, the moving device 43 according to this embodiment is a moving stage for placing the high-melting-point container 50. A small amount of heat is released from the contact area between the moving stage and the high-melting-point container 50. This allows a temperature gradient to be formed within the high-melting-point container 50 (and within the main container 30).

[0233] That is, in the heating furnace 40 of this embodiment, since the bottom of the high-melting-point container 50 is in contact with the moving stage, the temperature gradient is set such that the temperature decreases from the upper container 51 of the high-melting-point container 50 toward the lower container 52. Ideally, this temperature gradient is formed along the surface-back direction of the SiC substrate 10.

[0234] Furthermore, as described above, a temperature gradient can also be formed through the structure of heater 44. Alternatively, the heater 44 can be configured to reverse the temperature gradient.

[0235] (High melting point container)

[0236] Preferably, the heating furnace 40 forms an atmosphere containing Si, and the main container 30 is heated within this atmosphere. According to this embodiment, the Si-containing atmosphere within the heating furnace 40 is formed using a high-melting-point container 50 and a Si vapor supply source 54.

[0237] Furthermore, any method that can create an atmosphere containing Si elements around the main container 30 can certainly be used.

[0238] The high-melting-point container 50 is configured to contain a high-melting-point material. Examples include C as a general heat-resistant component, W, Re, Os, Ta, and Mo as high-melting-point metals, Ta9C8, HfC, TaC, NbC, ZrC, Ta2C, TiC, WC, and MoC as carbides, HfN, TaN, BN, Ta2N, ZrN, and TiN as nitrides, HfB2, TaB2, ZrB2, NB2, and TiB2 as borides, and polycrystalline SiC, etc.

[0239] The high-melting-point container 50, like the main container 30, is a fitted container comprising an upper container 51 and a lower container 52 that can fit together, and is configured to accommodate the main container 30. A small gap 53 is formed at the fitting portion of the upper container 51 and the lower container 52, and is configured to allow venting (vacuuming) of the high-melting-point container 50 through this gap 53.

[0240] Preferably, the high-melting-point container 50 has a Si vapor supply source 55 capable of supplying the vapor pressure of a gaseous species containing Si to the high-melting-point container 50. The Si vapor supply source 55 can be any structure that generates Si vapor within the high-melting-point container 50 upon heating, for example, solid Si (Si particles such as single-crystal Si wafers, Si powder, etc.) or Si compounds can be exemplified.

[0241] In the SiC substrate manufacturing apparatus according to this embodiment, TaC is used as the material of the high-melting-point container 50, and tantalum silicide is used as the Si vapor supply source 55. That is, as Figure 5 , Figure 7 , Figure 9 As shown, a tantalum silicide layer is formed on the inner side of the high melting point container 50, and is configured such that Si vapor is supplied from the tantalum silicide layer into the container during heating, thereby forming a Si vapor pressure environment.

[0242] Furthermore, any structure that forms a vapor pressure of a gaseous species containing Si elements within a high-melting-point container 50 during heating can be used.

[0243] "SiC Semiconductor Devices and Methods for Manufacturing SiC Semiconductor Devices"

[0244] The following description will take the case of manufacturing a pin diode using the SiC substrate 10 according to the embodiment as an example. For example, consider the following case: the SiC substrate 10 according to the embodiment is set to n-type to manufacture an n-channel pin diode. In this case, the substrate 11 becomes the cathode region, the dislocation transition layer 12 functions as a buffer layer, and the epitaxial growth layer 13 functions as the intrinsic semiconductor layer (i-layer).

[0245] First, p-type impurities, such as aluminum (Al), are implanted into the surface layer on the main surface side of the epitaxial growth layer 13 by ion implantation to form a p+ type anode region.

[0246] Next, an anode electrode is formed by depositing a film of nickel (Ni) or the like on the upper surface of the anode region and performing heat treatment, and a cathode electrode is formed on the upper surface of the cathode region. This allows the fabrication of an n-channel pin diode.

[0247] Here, the manufacturing method of SiC semiconductor devices is described using an n-channel pin diode as an example. However, the SiC substrate of the present invention can also be applied to bipolar devices, IGBT (Insulated Gate Bipolar Transistor) devices, parasitic diodes with MOS (Metal Oxide Semiconductor) structures, etc.

[0248] Furthermore, in the embodiment, an example is shown in which an n+ type dislocation transition layer 12 and an n-type epitaxial growth layer 13 are stacked on the main surface of an n+ type SiC substrate 10, but it can also be configured such that a p+ type dislocation transition layer 12 and a p-type epitaxial growth layer 13 are stacked on the main surface of a p+ type SiC substrate.

[0249] Example

[0250] The present invention will be described in more detail below by listing Example 1, Example 2, Example 3, Comparative Example 1, Comparative Example 2, and Comparative Example 3.

[0251] <Example 1>

[0252] The SiC substrate 10, after the modified layer 111 has been removed, is housed within the main container 30 and the high-melting-point container 50 (see reference). Figure 11 The material was heat-treated under the following conditions. Furthermore, in this embodiment 1, the main container 30 is formed using polycrystalline SiC, so that the main container 30 itself functions as a SiC material body 20 (a source of Si and a source of C elements).

[0253] [SiC substrate 10]

[0254] Polymorph: 4H-SiC

[0255] Substrate dimensions: 10mm wide × 10mm deep × 0.45mm thick

[0256] Deviation direction and deviation angle: <11-20> Direction deviation 4°

[0257] Growth surface: (0001) crystal plane

[0258] Presence or absence of processed metamorphic layer 111: No

[0259] MSB presence or absence: None

[0260] Step 14 height: 1.0 nm

[0261] Platform width W1: 14nm

[0262] Furthermore, the presence and depth of the processed modified layer 111 were confirmed using SEM-EBSD. Additionally, the presence and depth of the processed modified layer 111 could also be confirmed using TEM, μXRD, and Raman spectroscopy.

[0263] Furthermore, the presence or absence of MSB was confirmed using the methods for evaluating SEM image contrast described in AFM and Japanese Patent Application Publication No. 2015-179082.

[0264] In addition, the height of step 14 was measured using AFM.

[0265] In addition, as the value of platform width W (including platform width W1 and platform width W2), a line perpendicular to the steps 14 in the captured SEM image is drawn, and the number of steps 14 existing on the line is counted, thus adopting the average value of the platform width (platform width W = line length / number of steps on the line).

[0266] [Main container 30 (SiC material body 20)]

[0267] Material: Polycrystalline SiC

[0268] Container dimensions: 60mm in diameter × 4mm in height

[0269] Distance between SiC substrate 10 and the top surface of main container 30: 2mm

[0270] The Si / C atom ratio in the container is less than 1.

[0271] Dopant: N

[0272] Doping concentration: 5×10 17 cm -3 Up to 5×10 18 cm -3

[0273] [High melting point container 50]

[0274] Materials: TaC

[0275] Container dimensions: 160mm in diameter × 60mm in height

[0276] Si vapor supply source 54 (Si compound): TaSi2

[0277] [Heat Treatment Conditions]

[0278] The SiC substrate 10 configured under the above conditions was heat-treated under the following conditions.

[0279] Heating temperature: 1800℃

[0280] Heating time: 8 minutes

[0281] Growth rate: 0.5 μm

[0282] Temperature gradient: 1℃ / mm

[0283] By heating under the above-described heat treatment conditions, a dislocation transition layer 12 was grown on the SiC substrate 10 (crystal growth step S2). Furthermore, in Example 1, the dislocation transition layer 12 was grown to 0.5 μm, but by extending the heating time, it was possible to grow to over 1 μm.

[0284] Figure 12 This shows the SIMS analysis results of the SiC substrate according to Example 1. As shown... Figure 12 As shown, the doping concentration of the dislocation transition layer 12 according to Example 1 is 3 × 10⁻⁶. 17 cm -3 The doping concentration of the substrate 11 is 6 × 10⁻⁶. 18 cm -3 .

[0285] The dislocation transformation layer 12 grown in crystal growth step S2 according to Example 1 is as follows.

[0286] [Dislocation Transition Layer 12]

[0287] Dopant: N

[0288] Doping concentration: 3×10 17 cm -3

[0289] MSB presence or absence: Yes

[0290] Step 14 height: >1.0nm

[0291] Step end shape: serrated

[0292] Platform width W2: 55nm

[0293] BPD to TED conversion rate: 100%

[0294] Figure 13 This is an illustration of the method for determining the transformation rate from BPD to other defects / dislocations (TED, etc.) in crystal growth step S2.

[0295] Figure 13 Image (a) shows a substrate 11 with a processed modified layer 111. In this stage, a bulk phase phase (BPD) is present from the bulk layer 112 to the processed modified layer 111.

[0296] Figure 13 (b) shows the substrate 11 obtained by removing the modified layer 111 through the modified layer removal step S1. In this stage, the BPD is present on the substrate 11 (bulk layer 112).

[0297] Figure 13 (c) shows a SiC substrate 10 obtained by growing a dislocation transformation layer 12 through a crystal growth step S2. In this step, BPD present on the bulk layer 112 is transformed into TED with a certain probability. Here, unless a 100% transformation occurs, TED and BPD are mixed on the surface of the dislocation transformation layer 12.

[0298] Figure 13 Image (d) shows the condition of defects in the dislocation transition layer 12 after crystal growth step S2 on the SiC substrate 10, confirmed using the KOH dissolution etching method. This KOH dissolution etching method involves immersing the SiC substrate in a dissolved salt (KOH, etc.) heated to approximately 500°C, forming etching pits at dislocation or defect locations, and determining the type of dislocation based on the size / shape of the etching pits. This method allows the determination of the number of bipolar dislocation phases (BPDs) propagating in the dislocation transition layer 12 after crystal growth step S2.

[0299] Figure 13 (e) shows the state after the dislocation transition layer 12 is removed following the KOH dissolution etching method. In this method, after planarization to the depth of the etch pits by mechanical polishing, CMP, etc., the dislocation transition layer 12 is removed by SiVE method, etc., and the substrate 11 (bulk layer 112) is exposed.

[0300] Figure 13 (f) shows the condition of defects in the substrate 11 obtained by removing the dislocation transition layer 12 using KOH dissolution etching. This method yields the number of BPDs present on the substrate 11 directly below the dislocation transition layer 12.

[0301] By according to Figure 13 The sequence shown will be Figure 13 The number of BPDs propagating in dislocation transition layer 13 in (d) and Figure 13 By comparing the number of BPDs present on the surface of the substrate 11 in (f), the BPD→TED transformation rate, which transforms BPDs into other defects / dislocations, can be obtained in crystal growth step S2.

[0302] According to Example 1, a dislocation transformation layer 12 is grown on a surface without MSB formation under SiC-C equilibrium vapor pressure conditions, thereby fabricating a layer with a doping concentration of 1×10⁻⁶. 17 cm -3 The above-mentioned SiC substrate with a dislocation transition layer 12 having a high BPD→TED transition rate.

[0303] Furthermore, in Example 1, a doping concentration of 5 × 10⁻⁶ was used. 17 cm -3 Up to 5×10 18 cm -3 The SiC material body 20 was formed with a doping concentration of 1×10⁻⁶. 17 cm -3 The above dislocation transition layer 12 can also introduce doping gas to increase the doping concentration.

[0304] <Examples 2 and 3>

[0305] Next, referring to Examples 2, 3, Comparative Example 1, Comparative Example 2, and Comparative Example 3, the heat treatment conditions for improving the BPD→TED conversion rate will be described in detail.

[0306] The SiC semiconductor substrates of Examples 2, 3, Comparative Examples 1, 2, and 3 were manufactured under the conditions shown in Table 1. Furthermore, the depth of the processed modified layer 111 of the SiC substrate 10 used in these examples and comparative examples was confirmed by SEM-EBSD to be approximately 5 μm. In addition, the high-melting-point container 50 used had dimensions of 160 mm in diameter × 60 mm in height, and the main container 30 had dimensions of 60 mm in diameter × 4 mm in height.

[0307] [Table 1]

[0308]

[0309]

[0310]

[0311] In Example 2, the modified processing layer 111 was removed using Si vapor pressure etching without forming MSB (modified processing layer removal step S1), and growth was performed using sublimation in a SiC-C equilibrium vapor pressure environment (crystal growth step S2). As a result, the BPD→TED transition rate of the dislocation transformation layer 12 was 100%. At this time, the plateau width W1 before the crystal growth step S2 was 14 nm, and the plateau width W2 after the crystal growth step S2 was 55 nm (plateau width increase / decrease rate = 292.86%).

[0312] In Example 3, the modified layer 111 was removed using Si vapor pressure etching under MSB formation conditions (modified layer removal step S1), and growth was performed under the same conditions as in Example 2 (SiC-C equilibrium vapor pressure environment) (crystal growth step S2). As a result, the BPD→TED transition rate of the dislocation transformation layer 12 was 99.7%. At this time, the plateau width W1 before crystal growth step S2 was 26 nm, and the plateau width W2 after crystal growth step S2 was 40 nm (plateau width increase / decrease rate = 53.85%).

[0313] The results show that when MSB is formed on the surface of SiC substrate 10 before the growth of dislocation transition layer 12, the BPD→TED transition rate decreases compared to Example 2.

[0314] In Comparative Example 1, the processing-modified layer removal step S1 for removing the processing-modified layer 111 was not performed, and growth (crystal growth step S2) was carried out under the same conditions as in Examples 2 and 3 (at SiC-C equilibrium vapor pressure). As a result, the BPD→TED transition rate of the dislocation transformation layer 12 was 95.65%. At this time, the plateau width W1 before the crystal growth step S2 was 7 nm, and the plateau width W2 after the crystal growth step S2 was 45 nm (plateau width increase / decrease rate = 542.86%).

[0315] The results show that when a modified processing layer 111 remains on the SiC substrate 10 before the dislocation transition layer 12, the BPD→TED conversion rate decreases compared to Examples 2 and 3.

[0316] In Comparative Example 2, the modified processing layer 111 was removed under the conditions for forming the MSB (modified processing layer removal step S1), and growth was performed under the same conditions as in Examples 2 and 3 (at SiC-C equilibrium vapor pressure) (crystal growth step S2). As a result, the BPD→TED transformation rate of the dislocation transformation layer 12 was 96.77%. At this time, the plateau width W1 before the crystal growth step S2 was 50 nm, and the plateau width W2 after the crystal growth step S2 was 48 nm (plateau width increase / decrease rate = -4.00%).

[0317] The results show that when growth was performed on the SiC substrate with a reduced platform width in crystal growth step S2, the BPD→TED conversion rate decreased compared to Examples 2 and 3.

[0318] In addition, in the processing modified layer removal step S1 of Example 3, MSB was formed by introducing Ar gas at 10000 Pa, while in the processing modified layer removal step S1 of Comparative Example 2, MSB was formed by using TaSi2 in the tantalum silicide layer.

[0319] In Comparative Example 3, as in Example 2, the modified processing layer 111 was removed without forming an MSB (modified processing layer removal step S1), and growth was performed using sublimation in a SiC-Si equilibrium vapor pressure environment (crystal growth step S2). This SiC-Si equilibrium vapor pressure environment was formed by arranging a Si substrate within the main container 30. As a result, the BPD→TED transition rate of the dislocation transformation layer 12 was 93.24%.

[0320] The results show that when growth was carried out under SiC-Si equilibrium vapor pressure conditions, the BPD→TED conversion rate decreased compared to Example 2.

[0321] Furthermore, after careful research and experimentation on whether the BPD→TED conversion rate exhibits regularity, the inventors of this invention discovered that, for example... Figure 14 As shown, the BPD→TED conversion rate is closely related to the increase or decrease rate of the platform width W before and after epitaxial growth (platform width increase rate).

[0322] Figure 14 This is a graph obtained by plotting the plateau width increase rate ((plateau width before growth W2 - plateau width after growth W1) / plateau width after growth W1) on the horizontal axis and the BPD→TED conversion rate on the vertical axis. Figure 14 The curves shown illustrate multiple experimental results for several SiC substrates 10 with different platform widths W1 after the removal of the processing modified layer 111, grown at any of the growth temperatures of 1700 °C, 1800 °C, and 1900 °C, and grown at either the SiC-Si equilibrium vapor pressure environment or the SiC-C equilibrium vapor pressure environment, for a total thickness of 3 μm.

[0323] According to the results, when the plateau width increase rate is greater than 0, that is, when the SiC substrate 10 after the removal of the modified layer 111 is grown under the condition of increased plateau width W during crystal growth, the BPD→TED conversion rate is greater than 99.00%.

[0324] That is, according to the SiC substrate manufacturing method of the present invention, by including a processing and altered layer removal step S1 for removing the processing and altered layer 111 of the SiC substrate 10 and a crystal growth step S2 for growing under the condition of increased platform width W of the SiC substrate 10, the BPD→TED transition rate in the dislocation transition layer 12 can be improved.

[0325] Furthermore, according to the SiC substrate manufacturing method of the present invention, in the crystal growth step S2, by growing the dislocation transition layer 12 on the SiC substrate 10 where MSB has not been formed, the BPD→TED transition rate in the dislocation transition layer 12 can be approximately 100%.

[0326] [Thermodynamic Calculations]

[0327] Figure 15 (a) is a graph showing the relationship between heating temperature and etching rate in the etching step of the present invention. The horizontal axis of the graph is the reciprocal of temperature, and the vertical axis represents the etching rate logarithmically.

[0328] Figure 15 (b) is a graph showing the relationship between heating temperature and growth rate in the crystal growth step of the present invention. The horizontal axis of the graph is the reciprocal of temperature, and the vertical axis represents the growth rate logarithmically.

[0329] In Figure 15 In the graph, the result of heat treatment of SiC substrate 10 when SiC substrate 10 is placed in a space (within the main container 30) with a Si / C atomic ratio greater than 1 is indicated by ○. Furthermore, the result of heat treatment of SiC substrate 10 when SiC substrate 10 is placed in a space (within the main container 30) with a Si / C atomic ratio of less than 1 is indicated by ×.

[0330] Furthermore, no MSB is formed on the surface of the SiC substrate 10 at the ○ marked locations, and the height of the step 14 is the height of one unit cell. On the other hand, MSB is formed on the surface of the SiC substrate 10 at the × marked locations.

[0331] In addition, Figure 15 In the graph, the thermodynamic calculation results in the SiC-Si equilibrium vapor pressure environment are represented by dashed lines (Arrhenius diagram), and the thermodynamic calculation results in the SiC-C equilibrium vapor pressure environment are represented by double-dotted lines (Arrhenius diagram).

[0332] The following sections provide a detailed explanation of the thermodynamic calculations for the etching step and the crystal growth step.

[0333] (Thermodynamic calculations for the etching process)

[0334] In the thermodynamic calculations for the etching step, when the main container 30 is heated, the amount of vapor generated from the SiC substrate 10 (vapor species containing Si and vapor species containing C) can be converted into the etching rate. In this case, the etching rate of the SiC substrate 10 is calculated using Equation 1 below.

[0335] [Formula 1]

[0336]

[0337] Here, T is the temperature of the SiC substrate 10, m i It is a gaseous species (Si) x C y The mass of one molecule of ) is k, where k is the Boltzmann constant.

[0338] In addition, P i This value is obtained by adding the vapor pressures generated within the main container 30 by heating the SiC substrate 10. Additionally, as P... i Gas-phase species can be envisioned as SiC, Si2C, SiC2, etc.

[0339] Figure 15The dashed line in (a) represents the thermodynamic calculation results when single-crystal SiC is etched in a vapor pressure environment where SiC (solid) and Si (liquid phase) reach phase equilibrium through the gas phase. Specifically, thermodynamic calculations were performed using Equation 1 under the following conditions (i) to (iv): (i) is a SiC-Si equilibrium vapor pressure environment with constant volume; (ii) the etching driving force is the temperature gradient within the main container 30; (iii) the feed gases are SiC, Si2C, and SiC2; and (iv) the descaling coefficient of the feed from step 14 is 0.001.

[0340] Figure 15 The double-dotted line in (a) represents the thermodynamic calculation result when single-crystal SiC was etched in a vapor pressure environment where SiC (solid phase) and C (solid phase) reached phase equilibrium through the gas phase. Specifically, thermodynamic calculations were performed using Equation 1 under the following conditions (i) to (iv): (i) a constant volume SiC-C equilibrium vapor pressure environment; (ii) the etching driving force is the temperature gradient within the main container 30; (iii) the feed gases are SiC, Si2C, and SiC2; and (iv) the descaling coefficient of the feed from step 14 is 0.001.

[0341] In addition, the data for each chemical species used in the thermodynamic calculations were based on the values ​​from the JANAF thermochemical tables.

[0342] According to this Figure 15 As shown in the curve (a), the results obtained by etching the SiC substrate 10 in a space (within the main container 30) where the Si / C atomic ratio is greater than 1 are (marked with ○) consistent with the thermodynamic calculation results of single crystal SiC etching in a SiC-Si equilibrium vapor pressure environment.

[0343] Furthermore, it is known that the results (× mark) obtained by etching the SiC substrate 10 in a space (within the main container 30) where the Si / C atomic ratio is less than 1 tend to be consistent with the thermodynamic calculation results of single crystal SiC etching in a SiC-C equilibrium vapor pressure environment.

[0344] Furthermore, under the condition of etching the ○ mark area in the SiC-Si equilibrium vapor pressure environment, the formation of MSB was decomposed / suppressed, and a step 14 with a height of 1 nm (1 cell) was arranged on the surface of the SiC substrate 10.

[0345] On the other hand, MSB is formed at the × mark site etched under the SiC-C equilibrium vapor pressure environment.

[0346] (Thermodynamic calculations of crystal growth steps)

[0347] Next, in the thermodynamic calculations for the crystal growth step, when the bulk container 30 is heated, the partial pressure difference of the vapor generated from the SiC raw material and the SiC substrate can be converted into the growth rate. The chemical potential difference or temperature gradient can be considered as the growth driving force at this time. Furthermore, this chemical potential difference can be considered as the partial pressure difference of the gaseous species generated at the surfaces of the polycrystalline SiC (SiC material bulk 20) ​​and the single-crystal SiC (SiC substrate 10). In this case, the SiC growth rate is calculated using Equation 2 below.

[0348] [Equation 2]

[0349]

[0350] Here, T is the temperature on the SiC raw material side, m i For gaseous species (Si x C y The mass of one molecule of ) is k, where k is the Boltzmann constant.

[0351] In addition, P 原料i -P 衬底i The amount of SiC precipitated is the amount of raw material gas that becomes supersaturated and is used as the growth amount. As the raw material gas, SiC, Si2C, and SiC2 can be envisioned.

[0352] Right now, Figure 15 The dashed line in (b) represents the thermodynamic calculation result of growing single-crystal SiC using polycrystalline SiC as raw material in a vapor pressure environment where SiC (solid) and Si (liquid phase) are in phase equilibrium through the gas phase.

[0353] Specifically, thermodynamic calculations were performed using Equation 2 under the following conditions (i) to (iv): (i) a constant volume SiC-Si equilibrium vapor pressure environment; (ii) the growth driving force is the temperature gradient within the host container 30 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single-crystal SiC; (iii) the raw material gases are SiC, Si2C, and SiC2; and (iv) the adsorption coefficient of the raw material adsorbed onto the steps of the SiC substrate 10 is 0.001.

[0354] also, Figure 15 The double-dotted line in (b) represents the thermodynamic calculation result of growing single-crystal SiC using polycrystalline SiC as raw material in a vapor pressure environment where SiC (solid phase) and C (solid phase) are in phase equilibrium through the gas phase.

[0355] Specifically, thermodynamic calculations were performed using Equation 2 under the following conditions (i) to (iv): (i) a constant volume SiC-C equilibrium vapor pressure environment; (ii) the growth driving force is the temperature gradient within the host container 30 and the vapor pressure difference (chemical potential difference) between polycrystalline SiC and single-crystal SiC; (iii) the feed gases are SiC, Si2C, and SiC2; and (iv) the adsorption coefficient of the feed adsorbed onto the steps of the SiC substrate 10 is 0.001.

[0356] In addition, the data for each chemical species used in the thermodynamic calculations were based on the values ​​from the JANAF thermochemical tables.

[0357] According to this Figure 15 As shown in the curve (b), the results obtained by placing the SiC substrate 10 in a space (within the main container 30) with a Si / C atomic ratio greater than 1 and growing the growth layer on the SiC substrate 10 (marked with ○) tend to be consistent with the thermodynamic calculation results of SiC growth in a SiC-Si equilibrium vapor pressure environment.

[0358] Furthermore, it is known that the results obtained by placing the SiC substrate 10 in a space (within the main container 30) where the Si / C atomic ratio is less than 1 and growing a growth layer on the SiC substrate 10 (× mark) tend to be consistent with the thermodynamic calculation results of SiC growth in a SiC-C equilibrium vapor pressure environment.

[0359] Figure 16 (a) is a SEM image of the 4H-SiC(0001) crystal plane obtained by arranging the Si / C atomic ratio within the main container 30 to be less than 1 and growing the crystal at 1800℃. That is, it is... Figure 15 The example shown is the × marked region in (b), and is an example of a surface obtained by crystal growth of SiC substrate 10 under SiC-C equilibrium vapor pressure environment. Among the surface shapes obtained under these conditions, it can be seen that, for example, a step-plateau structure with a plateau width W of 40 to 200 nm and a step height of 3 to 14 nm is formed, and MSBs with serrated step ends are formed.

[0360] on the other hand, Figure 16 (b) is a SEM image of the 4H-SiC(0001) crystal plane obtained by arranging the Si / C atomic ratio within the main container 30 to exceed 1 and growing the crystal at 1800°C. That is, it is... Figure 15The example shown is the ○-marked region in (b), and is an example of a surface obtained by crystal growth under SiC-Si equilibrium vapor pressure conditions. In the surface shape obtained under these conditions, a step-plateau structure with a plateau width of 14 nm and a step height of 1.0 nm (total unit cell) is formed, and MSB is not formed.

[0361] In addition, the step height or platform width can be confirmed by the method for evaluating the contrast of SEM images described in AFM or Japanese Patent Application Publication No. 2015-179082.

[0362] Explanation of reference numerals in the attached figures

[0363] 10 SiC substrate 11 Substrate

[0364] 111 Processed metamorphic layer 112 Bulk layer 113 Strain

[0365] 114 Scratches 115 Potential Scratches

[0366] 12 Dislocation Transformation Layer 13 Epitaxial Growth Layer 14 Step

[0367] 15 Platform 20 SiC material body 30 Main container

[0368] 31 Upper container 32 Lower container 33 Gap

[0369] 34 Substrate holding fixture 35 Si vapor supply source 40 Heating furnace

[0370] 41 Main heating chamber; 42 Preheating chamber; 43 Moving device

[0371] 44 Heater 45 Pump for vacuum forming 46 Valve for inert gas injection

[0372] 47 Vacuum gauge 50 High melting point container 51 Upper container

[0373] 52 Lower container 53 Gap 54 Si vapor supply source

[0374] X Etching space Y Crystal growth space

[0375] S1 Processing and removal of the altered layer; S2 Crystal growth step

[0376] S3 Epitaxial growth step; S4 Bundle decomposition step

Claims

1. A SiC substrate comprising: A substrate having surfaces where the processed altered layer has been removed and / or where macroscopic step bundles have been broken down; A dislocation transition layer is a layer that transforms basal plane dislocations existing on the surface of the substrate into through-edge dislocations during the formation of the dislocation transition layer. It is a single layer directly formed on the surface of the substrate, and the doping concentration of the dislocation transition layer is 1 × 10⁻⁶. 15 cm -3 The above, and the transformation rate from the base dislocation to the through-edge dislocation is greater than 95%; and An epitaxial growth layer is formed on the surface of the dislocation transformation layer. The dislocation transformation layer is disposed between the substrate and the epitaxial growth layer. The doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer. The macroscopic step clustering refers to a step with a height exceeding 1 unit cell formed on the surface.

2. The SiC substrate according to claim 1, wherein, The doping concentration of the dislocation transition layer is 1×10⁻⁶. 17 cm -3 above.

3. The SiC substrate according to claim 1 or 2, wherein, The dislocation transition layer has a thickness of more than 1 μm.

4. The SiC substrate according to claim 1 or 2, wherein, The transformation rate from basal dislocations to through-edge dislocations in the dislocation transformation layer is 100%.

5. A method for manufacturing a SiC substrate, comprising: The crystal growth process achieves a doping concentration of 1×10⁻⁶ for the first layer. 15 cm -3 The dislocation transformation layer described above is directly grown on the surface of the substrate where the processed modified layer has been removed and / or the macroscopic step bundles have been broken down under SiC-C equilibrium vapor pressure conditions; and an epitaxial growth step is performed to grow an epitaxial growth layer on the surface of the dislocation transformation layer. The dislocation transformation layer is a layer that transforms the base surface dislocations present on the surface of the substrate into through edge dislocations during the formation of the dislocation transformation layer, and the transformation rate from the base surface dislocations to the through edge dislocations is greater than 95%. The doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer. The macroscopic step clustering refers to steps formed on the surface that exceed the height of one unit cell.

6. A SiC semiconductor device, comprising: A substrate having surfaces where the processed altered layer has been removed and / or where macroscopic step bundles have been broken down; A dislocation transition layer is a layer that transforms basal plane dislocations existing on the surface of the substrate into through-edge dislocations during the formation of the dislocation transition layer. It is a single layer directly formed on the surface of the substrate, and the doping concentration of the dislocation transition layer is 1 × 10⁻⁶. 15 cm -3 The above, and the transformation rate from the base dislocation to the through-edge dislocation is greater than 95%; and An epitaxial growth layer is formed on the surface of the dislocation transformation layer. The dislocation transformation layer is disposed between the substrate and the epitaxial growth layer. The doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer. The macroscopic step clustering refers to a step with a height exceeding 1 unit cell formed on the surface.

7. The SiC semiconductor device according to claim 6, wherein, The doping concentration of the dislocation transition layer is 1×10⁻⁶. 17 cm -3 above.

8. The SiC semiconductor device according to claim 6 or 7, wherein, The dislocation transition layer has a thickness of more than 1 μm.

9. The SiC semiconductor device according to claim 6 or 7, wherein, The transformation rate from basal dislocations to through-edge dislocations in the dislocation transformation layer is 100%.

10. A method for manufacturing a SiC semiconductor device, comprising: The crystal growth process achieves a doping concentration of 1×10⁻⁶ for the first layer. 15 cm -3 The dislocation transformation layer described above is directly grown on the surface of the substrate where the processed modified layer has been removed and / or the macroscopic step bundles have been broken down under SiC-C equilibrium vapor pressure conditions; and an epitaxial growth step is performed to grow an epitaxial growth layer on the surface of the dislocation transformation layer. The dislocation transformation layer is a layer that transforms the base surface dislocations present on the surface of the substrate into through edge dislocations during the formation of the dislocation transformation layer, and the transformation rate from the base surface dislocations to the through edge dislocations is greater than 95%. The doping concentration of the dislocation transition layer is higher than that of the epitaxial growth layer. The macroscopic step clustering refers to steps formed on the surface that exceed the height of one unit cell.

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