Video data decoding method, computer system and medium

Abstract

The present disclosure provides a video data decoding method, computer system, and medium. Video data comprising one or more quantized coefficients is received. Based on an index mapping, one or more index values ​​associated with the quantized coefficients are mapped to one or more step values. The video data is decoded based on the one or more step values.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 035,642, filed in the U.S. Patent and Trademark Office on June 5, 2020, and U.S. Patent Application No. 17 / 098,825, filed in the U.S. Patent and Trademark Office on November 16, 2020. The entire contents of the prior applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of data processing, and more particularly to video encoding and decoding processing. Background Art

[0004] Developed by the Alliance for Open Media (AOMedia), Video 1 (AV1) is the successor to VP9 and is a consortium of semiconductor companies, video-on-demand providers, video content producers, software developers, and web browser vendors, founded in 2015. Many components of the AV1 project stem from previous research work by Alliance members. Individual contributors began experimenting with the technology platform several years ago: Xiph's / Mozilla's Daala released code in 2010, Google's experimental VP9 evolution project, VP10, was announced on September 12, 2014, and Cisco's Thor was announced on August 11, 2015. Building on the VP9 codebase, AV1 incorporates additional technologies, several of which were developed within these experimental formats. The first version 0.1.0 of the AV1 reference codec was released on April 7, 2016. The Alliance announced the release of the AV1 bitstream specification, along with software-based reference encoders and decoders, on March 28, 2018. On June 25, 2018, the Confirmed Version 1.0.0 of the specification was released. On January 8, 2019, the Confirmed Version 1.0.0 of the specification, including Errata 1, was released. The AV1 bitstream specification includes the reference video codec. The Alliance for Open Media Video 2 (AV2) is currently under development. Summary of the Invention

[0005] Embodiments relate to methods, systems, and computer-readable media for encoding video data. According to one aspect, a method for encoding video data is provided. The method may include receiving video data comprising one or more quantized coefficients. Based on an index mapping, one or more index values ​​associated with the one or more quantized coefficients are mapped to one or more step values. Based on the one or more step values, the video data is decoded.

[0006] According to another aspect, a computer system for encoding video data is provided. The computer system may include one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage devices, and program instructions stored on at least one of the one or more storage devices, for execution by at least one of the one or more processors via at least one of the one or more memories. The computer system is capable of performing a method. The method may include receiving video data comprising one or more quantized coefficients, mapping one or more index values ​​associated with the one or more quantized coefficients to one or more step values ​​based on an index mapping, and decoding the video data based on the one or more step values.

[0007] According to another aspect, a computer-readable medium for encoding video data is provided. The computer-readable medium may include one or more computer-readable storage devices and program instructions stored on at least one tangible storage device of the one or more tangible storage devices, the program instructions being executable by a processor. The program instructions are executable by the processor to perform a method. The method may accordingly include receiving video data comprising one or more quantized coefficients; mapping one or more index values ​​associated with the one or more quantized coefficients to one or more step values ​​based on an index mapping; and decoding the video data based on the one or more step values. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings. The various features of the drawings are not drawn to scale because these illustrations are for clarity in conjunction with the detailed description to facilitate understanding by those skilled in the art. In the drawings:

[0009] Figure 1 illustrates a networked computer environment according to at least one embodiment;

[0010] Figure 2A is a diagram of Q_index to Qstep mapping for DC and AC coefficients in AV1 according to at least one embodiment;

[0011] Figure 2B is a graph of a unified Q_index to Qstep linear mapping for AV2 according to at least one embodiment;

[0012] Figure 2C is a diagram of a unified Q_index to Qstep Log2 mapping for AV2 according to at least one embodiment;

[0013] Figure 3is an operational flow chart of steps performed by a program for compressing a neural network model according to at least one embodiment;

[0014] Figure 4 According to at least one embodiment Figure 1 block diagrams of the internal and external components of computers and servers depicted in;

[0015] Figure 5 According to at least one embodiment, Figure 1 A block diagram of an illustrative cloud computing environment for a computer system is depicted in FIG.

[0016] Figure 6 According to at least one embodiment Figure 5 A block diagram of the functional layers of an illustrative cloud computing environment. DETAILED DESCRIPTION

[0017] Detailed embodiments of the claimed structures and methods are disclosed herein. However, it will be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. However, these structures and methods may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope to those skilled in the art. In the description, well-known features and technical details may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0018] Embodiments generally relate to the field of data processing, and more specifically to video encoding and decoding. The exemplary embodiments described below provide a system, method, and computer program for encoding / decoding video data. Thus, some embodiments have the potential to improve computing capabilities by increasing video encoding and decoding efficiency using AV2.

[0019] As previously mentioned, AOMedia Video 1 (AV1) was developed as the successor to VP9 by the Alliance for Open Media, a consortium of semiconductor companies, video-on-demand providers, video content producers, software developers, and web browser vendors founded in 2015. Many components of the AV1 project stem from previous research work by Alliance members. Individual contributors began experimenting with the technology platform several years ago: Xiph's / Mozilla's Daala released code in 2010, Google's experimental VP9 evolution project, VP10, was announced on September 12, 2014, and Cisco's Thor was announced on August 11, 2015. Building on the VP9 codebase, AV1 incorporates additional technologies, several of which were developed within these experimental formats. The first version 0.1.0 of the AV1 reference codec was released on April 7, 2016. The Alliance announced the release of the AV1 bitstream specification, along with software-based reference encoders and decoders, on March 28, 2018. On June 25, 2018, the confirmed version 1.0.0 of the specification was released. On January 8, 2019, the confirmed version 1.0.0 of the specification was released, including Errata 1. The AV1 bitstream specification includes the reference video codec. AOMedia Video 2 (AV2) is currently under development.

[0020] In AV1, quantization of transform coefficients can apply different quantization step sizes to DC and AC transform coefficients, and different quantization step sizes to luma and chroma transform coefficients. To specify the quantization step size, in the frame header, the base_q_idx syntax element is first signaled. It is an 8-bit fixed-length code that specifies the quantization step size for luma AC coefficients. The valid range of base_q_idx is [0, 255]. After that, the delta value of the Luma DC coefficient relative to base_q_idx (expressed as DeltaQYDc) is further signaled. In addition, if there is more than one color plane, the flag diff_uv_delta is signaled to indicate whether different quantization index values ​​are applied to the Cb and Cr color components. If the signaled diff_uv_delta is 0, only the delta values ​​of the chroma DC coefficient (expressed as DeltaQUDc) and AC coefficient (expressed as DeltaQUAc) relative to base_q_idx are signaled. Otherwise, the delta values ​​of the Cb and Cr DC coefficients (denoted as DeltaQUDc and DeltaQVDc) and AC coefficients (denoted as DeltaQUAc and DeltaQVAc) relative to base_q_idx are signaled. However, the resolution of the AV1 quantization step size is limited.

[0021] Therefore, increasing the resolution of the quantization step size may be advantageous. During the ongoing AV2 development process, various tools may be used in the quantizer design. For example, the separate lookup tables Dc_Qlookup[3]

[256] and Ac_Qlookup[3]

[256] may be merged. Ac_Qlookup[3]

[256] is retained and the DC quantization step size is obtained using an offset from it. The default offset is set to 8. In addition, separate lookup tables are used to obtain the quantizer step sizes for 8-bit, 10-bit and 12-bit internal bit depths, and the step sizes do not show any mathematical relationship. This can be replaced by a modified lookup table for 8-bit internal bit depth. The quantization step size generation process is unified and the corresponding 8-bit step size (obtained using Q_index) is scaled by 4 and 16 for 10-bit and 12-bit internal bit depths, respectively. In addition, the supported step size range may be increased without increasing the range of Q_index.

[0022] Various aspects are described herein with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer-readable media according to various embodiments. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0023] Now refer to Figure 1 , shows a functional block diagram of a networked computer environment for a video encoding and decoding system 100 (hereinafter referred to as the "system") for compressing a neural network model. It should be appreciated that Figure 1 This is merely an illustration of one implementation and is not intended to imply any limitations on the environments in which different embodiments may be implemented. Many modifications to the depicted environments may be made based on design and implementation requirements.

[0024] System 100 may include a computer 102 and a server computer 114. Computer 102 may communicate with server computer 114 via a communication network 110 (hereinafter referred to as "network"). Computer 102 may include a processor 104 and a software program 108 stored on a data storage device 106 and may be capable of interfacing with a user and communicating with server computer 114. Figure 4 As discussed, computer 102 may include internal components 800A and external components 900A, respectively, and server computer 114 may include internal components 800B and external components 900B, respectively. Computer 102 may be, for example, a mobile device, a phone, a personal digital assistant, a netbook, a laptop, a tablet computer, a desktop computer, or any other type of computing device capable of running programs, accessing a network, and accessing a database.

[0025] The server computer 114 may also operate in a cloud computing service model, such as Software as a Service (SaaS), Platform as a Service (PaaS), or Infrastructure as a Service (IaaS), as shown in the following combination: Figure 5 and Figure 6 The server computer 114 may also be located in a cloud computing deployment model, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud.

[0026] The server computer 114 that can be used to compress the neural network model can run a video encoding program 116 (hereinafter referred to as "the program") that can interact with the database 112. Figure 3 The video encoding program method is explained in more detail. In one embodiment, computer 102 can operate as an input device including a user interface, while program 116 can be primarily executed on server computer 114. In an alternative embodiment, program 116 can be primarily executed on one or more computers 102, while server computer 114 can be used to process and store data used by program 116. It should be noted that program 116 can be a stand-alone program or can be integrated into a larger video encoding program.

[0027] However, it should be noted that in some cases, the processing of program 116 may be shared in any ratio between computer 102 and server computer 114. In another embodiment, program 116 may be executed on more than one computer, server computer, or some combination of computers and server computers, such as multiple computers 102 communicating with a single server computer 114 via network 110. In another embodiment, for example, program 116 may be executed on multiple server computers 114, where multiple server computers 114 communicate with multiple client computers via network 110. Alternatively, the program may be executed on a network server, where the network server communicates with one server and multiple client computers via the network.

[0028] The network 110 may include a wired connection, a wireless connection, a fiber optic connection, or some combination thereof. In general, the network 110 may be any combination of connections and protocols that support communication between the computer 102 and the server computer 114. The network 110 may include various types of networks, such as a local area network (LAN), a wide area network (WAN) such as the Internet, a telecommunications network such as a public switched telephone network (PSTN), a wireless network, a public switched network, a satellite network, a cellular network (e.g., a fifth generation (5G) network, a long-term evolution (LTE) network, a third generation (3G) network, a code division multiple access (CDMA) network, etc.), a public land mobile network (PLMN), a metropolitan area network (MAN), a private network, an ad hoc network, an intranet, a fiber-based network, etc., and / or combinations of these or other types of networks.

[0029] Figure 1 The number and arrangement of devices and networks shown are provided as examples. Figure 1 There may be more devices and / or networks, fewer devices and / or networks, different devices and / or networks, or differently arranged devices and / or networks than those shown. Figure 1 Two or more of the devices shown may be implemented in a single device, or Figure 1 The single device shown may be implemented as multiple distributed devices. Additionally or alternatively, one set of devices (eg, one or more devices) of system 100 may perform one or more functions described as being performed by another set of devices of system 100.

[0030] Now refer to Figure 2A, depicting the Q_index to Qstep mapping for DC and AC coefficients in AV1, Figure 200A. The decoded values ​​of DeltaQYDc, DeltaQUAc, DeltaQUDc, DeltaQVAc, and DeltaQVDc can be added to base_q_idx to derive the quantization indices Q_index's. These Q_index's are further mapped to quantization step sizes according to two tables. For the DC coefficient, the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit internal bit depths is specified by the lookup table Dc_Qlookup[3]

[256] , and the mapping from quantization index to quantization step size for 8-bit, 10-bit, and 12-bit internal bit depths is specified by the lookup table Ac_Qlookup[3]

[256] .

[0031] Now refer to Figure 2B , which depicts the unified Q_index to Qstep linear mapping for AV2 in Figure 200B. The valid range of Q_index is [0,255], which maps to the step range [4,6879]. Although the step range is larger, the valid range of Q_index is the same. This limitation of the quantization step resolution is more pronounced for 10-bit and 12-bit internal bit depths, where the corresponding 8-bit step sizes (obtained using q_idx) are scaled by 4 and 16, respectively. This affects the bitrate granularity that the codec can achieve

[0032] Now refer to Figure 2C , Figure 200C depicts a uniform Q_index to Qstep Log2 mapping for AV2. The mapping from Q_index to quantization step size may not exhibit a consistent mathematical relationship. The initial entry in step size exhibits a linear relationship with Q_index, while the rest of the mapping is mostly exponential. The switch from linear to exponential mapping is not smooth. Furthermore, at lower Q_indexes, the step size jumps abruptly, which is more noticeable for 10-bit and 12-bit internal bit depth encodings, as they are amplified by 4 and 16, respectively.

[0033] The exponential mapping from Q_index to Qstep can be expressed as: Qstep = a*b Q_index / c

[0034] The linear mapping can be expressed as: Qstep = x*Q_index+y

[0035] Where a, b, and c are constants for a certain range of Q_index. In one embodiment, a, b, and c remain constant over the entire range of Q_index. In one embodiment, the value of b may include, but is not limited to, 2. In one embodiment, the value of a may include, but is not limited to, 4, 8, 16, 19, 24, 32. In one embodiment, c may be, but is not limited to, a factor that serves as an upper limit or Q_index range. An example of a Q_index range used in AV1 is 256. In one embodiment, the value of c may include, but is not limited to, 3, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64.

[0036] In one embodiment, Q_index may be divided into multiple ranges, and a, b, and c may remain unchanged in each range (piecewise exponential). In one embodiment, the value of b may include, but is not limited to, 2. In one embodiment, the value of a may include, but is not limited to, 4, 8, 16, 19, 24, and 32. In one embodiment, c may be, but is not limited to, an upper limit or a factor of the Q_index range. An example of the Q_index range used in AV1 is 256. In one embodiment, the value of c may include, but is not limited to, 3, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64.

[0037] According to one or more embodiments, a combination of piecewise linear mapping of Q_index to Qstep and exponential mapping may be used. In one embodiment, the full range of Q_index (e.g., [0, T N ]) is divided into multiple ranges, for example, [0,T0], [T0+1,T1], ..., [T N-1 +1,T N ], and within each range, either linear or exponential mapping can be used. In one embodiment, the value of b may include, but is not limited to, 2. In one embodiment, the value of a may include, but is not limited to, 4, 8, 16, 19, 24, 32. In one embodiment, c may be, but is not limited to, a factor serving as an upper limit or Q_index range. An example of a Q_index range used in AV1 is 256. In one embodiment, the value of x may include, but is not limited to, 1, 2, 4, 8. In one embodiment, the value of y may include, but is not limited to, 4, 8, 16, 32.

[0038] According to one or more embodiments, an extended Q_index to Qstep mapping scheme may be used. In one embodiment, the Q_index range may be increased without increasing the Qstep range. In one embodiment, the extended Q_index range may be used for 8, 10, 12, 16-bit internal bit depth codec configurations. In one embodiment, the 8-bit internal bit depth codec configuration uses a subset of the extended Q_index. In one embodiment, the extended Q_index range may be flexibly assigned to a subset of the quantization step size range to achieve more granularity over that range. In one embodiment, the extended Q_index range may be used to achieve more granularity for very high bit rates (lower quantization step sizes). In one embodiment, the extended Q_index range may be used to achieve more granularity for very low bit rates (higher quantization step sizes). In one embodiment, the extended Q_index range may be used to achieve more granularity at bit rates other than very high and very low bit rates. In one embodiment, the ranges of both Q_index and Qstep are increased.

[0039] According to one or more embodiments, the range of Q_index values ​​depends on the internal bit depth of the codec. In one embodiment, the range of Q_index values ​​is larger for larger internal bit depths. In one embodiment, when using an exponential mapping of Q_index to Qstep, for internal bit depth a and internal bit depth b, where b is greater than a, the range of Q_index values ​​for internal bit depths a and b are represented as [0, QA] and [0, QB], respectively, then QB = QA + (ba) * c. In one example, the range of Q_index values ​​for an 8-bit internal bit depth is [0, 255], then the range of Q_index values ​​for 10-bit and 12-bit internal bit depths is [0, 255 + 2 * c] and [0, 255 + 4 * c], respectively. Example values ​​of c include, but are not limited to, 4, 5, 6, 7, 8, 9, 10, 11, ..., 32, ..., 64. In one embodiment, the Qstep values ​​available for one internal bit depth setting a are a subset of the Qstep values ​​available for a larger internal bit depth setting b (b is greater than a). In one embodiment, the Qstep values ​​available for an internal bit depth setting a are [Q0, Q1, ..., Q NA-1 ], and the Qstep values ​​that can be used for an internal bit depth setting b are [Q0,Q1,…,Q NA-1 ,…,Q NB-1 ].

[0040] In one example, the Qstep values ​​that can be used for an internal bit depth setting of 8 are:

[0041] qstep

[256] ={4,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,53,54,55,56,58,59,60,62,63,65,66,68,69,71,73,74,76,78,80,81,83,85,87,89,91,94,96,98,100,103,105,107,110,113,115,118,121,123,126,129,132,135,139,142,145,149,152,156,159,163,167,171,175,179,183,187,192,196,201,205,210,215,220,225,230,236,241,247,253,259,265,271,277,284,290,297,304,311,318,326,333,341,349,357,366,374,383,392,401,411,420,430,440,450,461,472,483,494,505,517,529,542,554,567,581,594,608,622,637,652,667,682,698,715,731,749,766,784,802,821,840,860,880,901,922,943,965,988,1011,1034,1059,1083,1109,1135,1161,1188,1216,1244,1274,1303,1334,1365,1397,1429,1463,1497,1532,1568,1605,1642,1680,1720,1760,1801,1843,1886,1930,1975,2022,2069,2117,2167,2217,2269,2322,2376,2432,2489,2547,2607,2667,2730,2794,2859,2926,2994,3064,3136,3209,3284,3361,3439,3520,3602,3686,3772,3861,3951,4043,4138,4234,4333,4435,4538,4644,4753,4864,4978,5094,5213,5335,5460,5587,5718,5852,5988,6128,6271,6418,6568,6722,6879,};,

[0042] In one example, the Qstep values ​​that can be used for an internal bit depth setting of 10 are:

[0043] qstep

[256] ={4,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,53,54,55,56,58,59,60,62,63,65,66,68,69,71,73,74,76,78,80,81,83,85,87,89,91,94,96,98,100,103,105,107,110,113,115,118,121,123,126,129,132,135,139,142,145,149,152,156,159,163,167,171,175,179,183,187,192,196,201,205,210,215,220,225,230,236,241,247,253,259,265,271,277,284,290,297,304,311,318,326,333,341,349,357,366,374,383,392,401,411,420,430,440,450,461,472,483,494,505,517,529,542,554,567,581,594,608,622,637,652,667,682,698,715,731,749,766,784,802,821,840,860,880,901,922,943,965,988,1011,1034,1059,1083,1109,1135,1161,1188,1216,1244,1274,1303,1334,1365,1397,1429,1463,1497,1532,1568,1605,1642,1680,1720,1760,1801,1843,1886,1930,1975,2022,2069,2117,2167,2217,2269,2322,2376,2432,2489,2547,2607,2667,2730,2794,2859,2926,2994,3064,3136,3209,3284,3361,3439,3520,3602,3686,3772,3861,3951,4043,4138,4234,4333,4435,4538,4644,4753,4864,4978,5094,5213,5335,5460,5587,5718,5852,5988,6128,6271,6418,6568,6722,6879,7040,7040,7204,7372,7545,7721,7902,8086,8275,8469,8667,8869,9077,9289,9506,9728,9955,10188,10426,10670,10919,11175,11436,11703,11977,12257,12543,12836,13 136,13443,13757,14079,14408,14745,15090,15442,15803,16173,16551,16937,17333,17738,18153,18577,19012,19456,19911,20376,20852,21340,21839,22349,22871,23406,23953,24513,25086,25672,26272,26886,27515}};

[0044] Now refer to Figure 3 , depicts an operational flow chart illustrating the steps of a video encoding method 300. In some embodiments, Figure 3 One or more of the process blocks in the Figure 1 ) and server computer 114 ( Figure 1 ) is executed. In some embodiments, Figure 3 One or more of the process blocks in FIG. 1 may be performed by another device or group of devices independent of, or including, computer 102 and server computer 114 .

[0045] At 302 , method 300 includes receiving video data comprising one or more quantized coefficients.

[0046] At 304, method 300 includes mapping one or more index values ​​associated with one or more quantized coefficients to one or more step values ​​based on an index map. The one or more coefficients associated with the index map are constant for a range associated with the index value. The method may further include dividing the index map into one or more portions, and for each of the one or more portions, the one or more coefficients associated with the index map are constant. Mapping the step value to the index value based on a piecewise linear map and an exponential map. The method may further include dividing the range associated with the index value into one or more sub-ranges, and applying a linear map or the exponential map to each sub-range. Increasing a first range associated with the index value without increasing a second range associated with the step value. Flexibly allocating the first range to a subset of the second range. Increasing the first range associated with the index value and the second range associated with the step value. The method may further include depending the range associated with the index value on an internal bit depth associated with the video data. For a greater internal bit depth, the range associated with the index value is greater.

[0047] At 306 , method 300 includes decoding the video data based on the one or more step size values.

[0048] It is understandable that Figure 3 This merely provides an illustration of one implementation and does not imply any limitation on how different embodiments may be implemented. Many modifications may be made to the depicted environments depending on design and implementation requirements.

[0049] Figure 4 According to the illustrative embodiment Figure 1 400. It should be understood that Figure 4 This merely provides an illustration of one implementation and does not imply any limitations on the environments in which different embodiments may be implemented. Many modifications to the depicted environments may be made depending on design and implementation requirements.

[0050] Computer 102 ( Figure 1 ) and server computer 114 ( Figure 1 ) may include Figure 4The illustrated groups of internal components 800A, 800B and external components 900A, 900B include one or more processors 820, one or more computer-readable random access memories (RAMs) 822, one or more computer-readable read-only memories (ROMs) 824 on one or more buses 826, one or more operating systems 828, and one or more computer-readable tangible storage devices 830.

[0051] The processor 820 is implemented in hardware, firmware, or a combination of hardware and software. The processor 820 is a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), a microprocessor, a microcontroller, a digital signal processor (DSP), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or another type of processing component. In some embodiments, the processor 820 includes one or more processors that can be programmed to perform functions. The bus 826 includes components that allow communication between internal components 800A and 800B.

[0052] Server computer 114 ( Figure 1 ) on one or more operating systems 828, software programs 108 ( Figure 1 ) and video encoding program 116 ( Figure 1 ) are stored in the corresponding one or more computer-readable tangible storage devices 830 for execution by the one or more corresponding processors 820 via the one or more corresponding RAMs 822 (typically including cache). Figure 4 In the illustrated embodiment, each computer-readable tangible storage device 830 is a magnetic disk storage device of an internal hard drive. Alternatively, each computer-readable tangible storage device 830 is a semiconductor memory device, such as ROM 824, EPROM, flash memory, optical disk, magneto-optical disk, solid-state disk, compact disk (CD), digital versatile disk (DVD), floppy disk, magnetic cassette, magnetic tape, and / or other types of non-volatile computer-readable tangible storage devices that can store computer programs and digital information.

[0053] Each set of internal components 800A, 800B also includes a read / write (R / W) drive or interface 832 to read and write one or more portable computer-readable tangible storage devices 936, such as CD-ROMs, DVDs, memory sticks, tapes, magnetic disks, optical disks, or semiconductor storage devices. For example, the software program 108 ( Figure 1 ) and video encoding program 116 ( Figure 1 ) can be stored on one or more corresponding portable computer-readable tangible storage devices 936, read through the corresponding R / W drive or interface 832 and loaded into the corresponding hard disk drive 830.

[0054] Each set of internal components 800A, 800B also includes a network adapter or interface 836, such as a TCP / IP adapter card; a wireless Wi-Fi interface card; or a 3G, 4G or 5G wireless interface card or other wired or wireless communication link. Figure 1 ) on the software program 108 ( Figure 1 ) and video encoding program 116 ( Figure 1 ) can be downloaded from an external computer to the computer 102 ( Figure 1 ) and the server computer 114. The software program 108 and the video encoding program 116 on the server computer 114 are loaded from the network adapter or interface 836 to the corresponding hard disk drive 830. The network can include copper wire, fiber optic, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers.

[0055] Each set of external components 900A, 900B may include a computer display monitor 920, a keyboard 930, and a computer mouse 934. External components 900A, 900B may also include a touch screen, a virtual keyboard, a touchpad, a pointing device, and other human-computer interface devices. Each set of internal components 800A, 800B also includes a device driver 840 that interfaces with the computer display monitor 920, the keyboard 930, and the computer mouse 934. The device driver 840, the R / W driver or interface 832, and the network adapter or interface 836 comprise hardware and software (stored in the storage device 830 and / or ROM 824).

[0056] It is understood in advance that although the present disclosure includes detailed descriptions about cloud computing, the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, some embodiments can be implemented in conjunction with any other type of computing environment now known or later developed.

[0057] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with the service provider. The cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0058] The features are as follows.

[0059] On-demand self-service: Cloud consumers can automatically and unilaterally provision computing capacity, such as server time and network storage, as needed without manual interaction with the service provider.

[0060] Broad network access: Functionality is available over the network and accessed through standard mechanisms that facilitate use with heterogeneous thin-client platforms or thick-client platforms (e.g., mobile phones, laptops, and Personal Digital Assistants (PDAs)).

[0061] Resource pooling: Pooling a provider's computing resources to serve multiple consumers using a multi-tenant model, dynamically allocating and reallocating different physical and virtual resources based on demand. There is a sense of location independence, as consumers generally have no control or knowledge of the exact location of the provided resources, but may be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0062] Rapid elasticity: Capacity can be quickly and elastically provisioned, in some cases automatically, to quickly scale out and quickly released to quickly scale back in. To the consumer, the capacity available for provisioning often appears unlimited and can be purchased at any time in any quantity.

[0063] Metered Services: Cloud systems automatically control and optimize resource usage by using metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of the services being used.

[0064] The service model is as follows.

[0065] Software as a Service (SaaS): The ability provided to consumers is to use the provider's applications running on the cloud infrastructure. These applications can be accessed from a variety of client devices through a thin client interface such as a web browser (e.g., web-based email). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functions, with the possible exception of limited user-specific application configuration settings.

[0066] Platform as a Service (PaaS): The ability provided to consumers is to deploy applications they create or acquire onto cloud infrastructure. These applications are built using programming languages ​​and tools supported by the provider. Consumers do not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they do have control over deployed applications and possibly the configuration of the application hosting environment.

[0067] Infrastructure as a Service (IaaS): The capabilities provided to consumers are processing, storage, networking, and other basic computing resources, on which consumers can deploy and run arbitrary software, including operating systems and applications. Consumers do not manage or control the underlying cloud infrastructure, but they can control the operating system, storage, deployed applications, and may have limited control over selected network components (for example, host firewalls).

[0068] The deployment model is as follows.

[0069] Private cloud: Cloud infrastructure is run solely for an organization. It may be managed by the organization or a third party and may exist on-premises or off-premises. Community cloud: Cloud infrastructure is shared by multiple organizations and supports a specific community with shared concerns (e.g., mission, security requirements, policies, and compliance considerations). It may be managed by the organization or a third party and may exist on-premises or off-premises. Public cloud: Cloud infrastructure is available to the public or large industry groups and is owned by the organization selling cloud services.

[0070] Hybrid cloud: A cloud infrastructure is a combination of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting to enable load balancing between clouds)

[0071] The cloud computing environment is service-oriented and focuses on statelessness, low coupling, modularity, and semantic interoperability. The core of cloud computing is the infrastructure consisting of a network of interconnected nodes.

[0072] refer to Figure 5, depicts an illustrative cloud computing environment 500. As shown, the cloud computing environment 500 includes one or more cloud computing nodes 10, with which cloud consumers can communicate using local computing devices, such as, for example, personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C, and / or automobile computer systems 54N. The cloud computing nodes 10 can communicate with each other. They can be physically or virtually grouped in one or more networks (not shown), such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 500 to provide infrastructure as a service, platform as a service, and / or software as a service, without the cloud consumer needing to maintain resources on local computing devices for these services. It should be understood that Figure 5 The types of computing devices 54A-N shown in FIG are illustrative only, and cloud computing node 10 and cloud computing environment 500 may communicate with any type of computerized device over any type of network and / or network-addressable connection (eg, using a web browser).

[0073] refer to Figure 6 , showing a cloud computing environment 500 ( Figure 5 ) provides a set of functional abstraction layers 600. It should be understood in advance that Figure 6 The components, layers, and functions shown in are merely illustrative, and the embodiments are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0074] The hardware and software layer 60 includes hardware components and software components. Examples of hardware components include: mainframes 61; servers based on the Reduced Instruction Set Computer (RISC) architecture 62; servers 63; blade servers 64; storage devices 65; and network and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0075] Virtualization layer 70 provides an abstraction layer from which examples of the following virtual entities can be provided: virtual servers 71 ; virtual storage 72 ; virtual networks 73 , including virtual private networks; virtual applications and operating systems 74 ; and virtual clients 75 .

[0076] In one example, the management layer 80 may provide the functionality described below. Resource provisioning 81 provides dynamic acquisition of computing resources and other resources for performing tasks within a cloud computing environment. Metering and pricing 82 tracks the cost of resource utilization within the cloud computing environment and provides billing and invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides authentication for cloud consumers and tasks and protects data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management to meet the required service levels. Service level agreement (SLA) planning and fulfillment 85 provides pre-arrangement and procurement of cloud computing resources, where future demand is anticipated based on the SLA.

[0077] Workload layer 90 provides examples of functionality that can utilize a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and video codec 96. Video codec 96 can encode and / or decode video data.

[0078] Some embodiments may involve systems, methods, and / or computer-readable media integrated at any possible level of technical detail. The computer-readable medium may include a computer-readable non-volatile storage medium (or media) having computer-readable program instructions thereon that cause a processor to perform operations.

[0079] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device (e.g., a punched card or raised structure in a groove having instructions recorded thereon), and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transient signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through optical fibers), or electrical signals transmitted through wires.

[0080] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0081] The computer readable program code / instruction for performing an operation can be an assembly instruction, an instruction set architecture (ISA) instruction, a machine instruction, a machine dependent instruction, a microcode, a firmware instruction, a state setting data, the configuration data of an integrated circuit, or a source code or an object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as SmallTalk, C++, etc.) and procedural programming languages ​​(such as "C" programming language or similar programming languages). The computer readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer, and partially on a remote computer, or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (for example, by using the Internet of an Internet Service Provider (ISP)). In some embodiments, electronic circuits including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs) may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuits to perform aspects or operations.

[0082] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, such that the instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that can direct a computer, programmable data processing device, and / or other device to operate in a specific manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture that includes a plurality of instructions, wherein the plurality of instructions implement various aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0083] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device, thereby producing a computer-implemented process, such that the instructions executed on the computer, other programmable apparatus, or other device implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0084] The flowcharts and block diagrams in the figure illustrate the possible implementation architecture, functions and operations of the system, method and computer-readable medium according to various embodiments. In this regard, each frame in the flowchart or block diagram can represent a module, segment or part of an instruction, which includes one or more executable instructions for implementing a specified logical function. The method, computer system and computer-readable medium may include additional frames, fewer frames, different frames, or frames arranged differently than those frames depicted in the figure. In some alternative embodiments, the functions indicated in the frame may not occur in the order indicated in the figure. For example, the two frames shown in succession can actually be performed simultaneously or substantially simultaneously, or these frames can sometimes be performed in the opposite order, depending on the functions involved. It should also be noted that each frame in the block diagram and / or flowchart illustration, and the combination of frames in the block diagram and / or flowchart illustration can be implemented by a dedicated hardware-based system that performs a specified function, or action, or performs a combination of dedicated hardware and computer instructions.

[0085] Obviously, the systems and / or methods described herein can be implemented in various forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not a limitation of implementation. Thus, the operation and behavior of the systems and / or methods are described herein without reference to specific software code—it being understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0086] Elements, actions or instructions used herein should not be interpreted as critical or necessary unless clearly described as such. In addition, as used herein, the articles "one" and "an" are intended to include one or more projects and can be used interchangeably with "one or more". In addition, as used herein, the term "set" is intended to include one or more projects (e.g., related projects, unrelated projects, a combination of related projects and unrelated projects, etc.), and can be used interchangeably with "one or more". When only intended to refer to an project, the term "one" or similar language is used. In addition, as used herein, the terms "has", "have", "having" etc. are intended to be open terms. Further, the phrase "based on" is intended to mean "based at least in part on", unless otherwise clearly stated.

[0087] The description of the various aspects and embodiments has been presented for illustrative purposes, but the description is not intended to be exhaustive or limited to the disclosed embodiments. Although combinations of features are referenced in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure that may be implemented. In fact, many of these features can be combined in ways that are not specifically listed in the claims and / or disclosed in the specification. Although each dependent claim listed below may be directly dependent on only one claim, the disclosure that may be implemented includes each dependent claim in combination with every other claim in the claim group. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A video data decoding method, characterized in that: include: receiving video data comprising one or more quantized coefficients; Mapping one or more index values ​​associated with the quantized coefficients to one or more step values ​​based on a linear mapping and an exponential mapping, wherein a value range of the index values ​​is divided into a plurality of sub-ranges, and the linear mapping or the exponential mapping is selected for each sub-range; and The video data is decoded based on the one or more step values.

2. The method according to claim 1, characterized in that One or more coefficients associated with the index map are constant for the entire range of index values.

3. The method according to claim 1, characterized in that One or more coefficients associated with the index map are constant for each of the sub-ranges of the index values.

4. The method according to claim 1, wherein The method further includes increasing the first range of index values ​​without increasing the second range of step values.

5. The method according to claim 4, characterized in that The method further includes flexibly allocating the first range to a subset of the second range.

6. The method according to claim 1, characterized in that The method further includes increasing the first range of index values ​​and the second range of step values.

7. The method according to any one of claims 1 to 6, characterized in that The range of values ​​of the index value depends on the internal bit depth associated with the video data.

8. The method according to claim 7, characterized in that For a larger internal bit depth, the index value has a larger range of values.

9. A video data encoding method, characterized in that: include: determining one or more quantization coefficients for the video data; Mapping one or more index values ​​associated with the quantized coefficients to one or more step values ​​based on a linear mapping and an exponential mapping, wherein a value range of the index values ​​is divided into a plurality of sub-ranges, and the linear mapping or the exponential mapping is selected for each sub-range; and The video data is encoded based on the one or more step values.

10. A computer system, characterized in that: include: A receiving module, configured to receive video data including one or more quantized coefficients; a mapping module, configured to map one or more index values ​​associated with the quantized coefficients to one or more step values ​​based on linear mapping and exponential mapping, wherein a value range of the index values ​​is divided into a plurality of sub-ranges, and the linear mapping or the exponential mapping is selected for each sub-range; A decoding module is configured to decode the video data based on the one or more step values.

11. The computer system according to claim 10, wherein: One or more coefficients associated with the index map are constant for the entire range of index values.

12. The computer system according to claim 10, wherein: One or more coefficients associated with the index map are constant for each of the sub-ranges of the index values.

13. The computer system according to claim 10, wherein: The computer system further includes a first increasing module for increasing the first range of the index value without increasing the second range of the step value.

14. The computer system according to claim 13, wherein: The computer system further includes an allocation module for flexibly allocating the first range to a subset of the second range.

15. The computer system according to any one of claims 10 to 14, wherein: The computer system further includes a second increasing module for increasing the first range of the index value and the second range of the step value.

16. The computer system according to any one of claims 10 to 14, characterized in that: The range of values ​​of the index value depends on the internal bit depth associated with the video data.

17. A computer system, characterized in that: include: one or more computer-readable non-volatile storage media for storing computer program code; as well as, One or more computer processors, configured to access the computer program code and operate according to instructions of the computer program code to execute the method according to any one of claims 1 to 9.

18. A non-volatile computer-readable medium, characterized in that The non-transitory computer-readable medium stores a computer program for compressing a neural network model, wherein the computer program is used to cause one or more computer processors to execute the method according to any one of claims 1 to 9.

19. A method for storing a video stream, characterized in that: Execute the method of claim 9 to generate a video stream, and store the video stream.

20. A method for transmitting a video stream, characterized in that: Execute the method of claim 9 to generate a video stream, and transmit the video stream.

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