Device and Method for Reducing Time Walk in a PET System

Abstract

The present invention relates to a device and method for reducing time walk in a PET system. The device includes: a high-threshold DAC, a low-threshold DAC, a high-threshold comparator, a low-threshold comparator, a delay circuit, a logic AND gate, and a TDC; the output end of the high-threshold DAC is connected to the first input end of the high-threshold comparator; the output end of the low-threshold DAC is connected to the first input end of the low-threshold comparator, and the output end of the detector is connected to the second input end of the high-threshold comparator and the second input end of the low-threshold comparator; the output end of the high-threshold comparator is connected to the first input end of the logic AND gate; the output end of the low-threshold comparator is connected to the second input end of the logic AND gate via the delay circuit; the output end of the logic AND gate outputs a time pulse signal to the TDC. The device of the present invention adopts a high-low dual-threshold comparator, which can effectively reduce the false triggering of noise, reduce time walk, and thus improve the time resolution of the PET system.

Description

Technical Field

[0001] The present invention relates to a detection technology of a PET detection system, and particularly to an apparatus and method for reducing time walk in a PET system. Background Art

[0002] PET (Positron Emission Tomography), Chinese for positron emission tomography, is a technology developed in nuclear medicine. During a PET examination, a patient is injected with a radioactive drug. Currently, the commonly used radioactive drug is deoxyglucose labeled with the positron 18F (i.e., 18F-FDG). The radioactive drug is distributed throughout the human body as the body metabolizes it. The radionuclide undergoes β+ decay, releasing positrons that move a short distance in the human body and then collide and annihilate with negatively charged free electrons in human tissues, releasing a pair of γ photons with opposite directions and each having an energy of 511 Kev. This pair of γ photons is captured by a detector composed of scintillation crystals. When the scintillation crystals are hit by high-energy rays, ionization and excitation occur, and fluorescence is emitted during de-excitation. The fluorescence is converted into an electrical pulse signal through photoelectric conversion, amplified and shaped, the time and energy information of the pulse signal is extracted, and then coincidence events occurring at the same time are selected by a coincidence circuit. After data processing, they are sent to a workstation for image reconstruction, and then images of cross-sectional, coronal, and sagittal planes of various parts of the human body are obtained. By the different uptake capabilities of diseased sites for the radioactive drug labeled with radionuclides, the degree of abnormal metabolism of the diseased part is shown.

[0003] The application of the time-of-flight technology (Time of Flight, TOF) can improve the time resolution of PET, so that PET can obtain better image quality with a lower injection dose of the drug. The TOF technology requires accurately measuring the time when γ photons reach the detector. The weak signal captured by the detector is amplified to obtain a time signal. The leading edge of the time signal is very steep. A pulse leading edge with time information is generated through a discrimination circuit, and then the arrival time of the square wave signal, that is, the time when γ photons reach the detector, is measured through a TDC.

[0004] Due to the non-fixed amplitude and different rising-edge slopes of the time signal, a time walk phenomenon occurs when measuring time with a discrimination circuit with a fixed level. As Figure 1As shown, the time signals of Event 1 and Event 2 occur at the same moment, but the two events have different rising-edge slopes due to different energies. After discrimination with a fixed-level threshold, time walk2 is larger than time walk1. To reduce the influence of time walk, the general approach is to set the threshold of the comparator very low. However, if it is set too low, it will be triggered by noise, causing difficulties for subsequent processing. Therefore, the threshold is set higher than the noise. In actual applications, especially for SiPM detectors, the noise is relatively large, such as the noise caused by dark current. To reduce the false triggering caused by the noise band, the threshold is set relatively high, which will result in a relatively large time walk.

[0005] Therefore, how to reduce the time walk of the time discrimination circuit and thereby improve the time resolution of the PET is a problem that the PET system needs to solve. Summary of the Invention

[0006] (1) Technical problems to be solved

[0007] In view of the above-mentioned disadvantages and deficiencies of the prior art, the present invention provides a device and method for reducing time walk in a PET system to achieve improving the time resolution of the PET detector and thereby improving the PET image resolution.

[0008] (2) Technical solutions

[0009] To achieve the above object, the main technical solutions adopted by the present invention include:

[0010] In a first aspect, an embodiment of the present invention provides a device for reducing time walk in a PET system, which includes:

[0011] A high-threshold DAC, a low-threshold DAC, a high-threshold comparator, a low-threshold comparator, a delay circuit, a logic AND gate, and a TDC;

[0012] The output end of the high-threshold DAC is connected to the first input end of the high-threshold comparator;

[0013] The output end of the low-threshold DAC is connected to the first input end of the low-threshold comparator,

[0014] The output end of the detector is connected to the second input ends of the high-threshold comparator and the low-threshold comparator;

[0015] The output end of the high-threshold comparator is connected to the first input end of the logic AND gate;

[0016] The output end of the low-threshold comparator is connected to the second input end of the logic AND gate via the delay circuit;

[0017] The output terminal of the logic AND gate outputs a time pulse signal to the TDC;

[0018] The output terminal of the high-threshold comparator outputs a digital strobe signal, and the output terminal of the low-threshold comparator outputs a digital pulse signal;

[0019] The output terminal of the high-threshold DAC outputs a high-threshold level signal, and the output terminal of the low-threshold DAC outputs a low-threshold level signal.

[0020] Optionally, the high-threshold level signal is a level signal lower than the time signal of 511 Kev;

[0021] The low-threshold level signal covers the voltage from the bottom to the top of the noise band;

[0022] The delay time range of the delay circuit is 8 to 16 ns.

[0023] Optionally, the delay circuit is a monostable flip-flop;

[0024] When the monostable flip-flop does not receive a high-level pulse signal, it maintains a steady-state output of a low-level pulse signal;

[0025] When the monostable flip-flop receives a high-level pulse signal, after a delay time, it flips from the steady state to the transient state and outputs a high-level pulse signal;

[0026] After the monostable flip-flop outputs a high-level pulse signal, it automatically returns to the steady state.

[0027] Optionally, the delay time is adjusted by adjusting the RC parameters of the monostable flip-flop.

[0028] Optionally, the delay circuit, the logic AND gate, and the TDC are integrated and implemented in the FPGA; the delay circuit is configured into a fixed-delay mode through the IDELAY of the FPGA;

[0029] Inside the FPGA, a lookup table is used to implement the logic AND gate, that is, the truth table of the logic AND gate is written into the RAM. For the signals input to the first input terminal and the second input terminal, two addresses are input to look up the table, and the information corresponding to the address is found and then output.

[0030] In a second aspect, an embodiment of the present invention further provides a method for a device for reducing time walk in any PET system according to the first aspect, which includes:

[0031] The high-threshold level signal output by the high-threshold DAC and the time signal output by the detector pass through the high-threshold comparator and output a digital strobe signal;

[0032] When the voltage of the time signal output by the detector is higher than the low threshold level signal output by the low threshold DAC, the low threshold comparator outputs a digital pulse signal to the delay circuit. After being delayed by the delay circuit, it enters the logic AND gate. The delayed digital pulse signal and the logic strobe signal are ANDed by the logic AND gate, and the delayed pulse signal passes through the logic AND gate and enters the TDC for time measurement, achieving a reduction in time walk.

[0033] Optionally, when the voltage of the time signal output by the detector is higher than the high threshold level signal output by the high threshold DAC, the high threshold comparator outputs a logic strobe 1 signal;

[0034] When the voltage of the time signal output by the detector is lower than the high threshold level signal output by the high threshold DAC, the high threshold comparator outputs a logic strobe 0 signal;

[0035] When the logic AND gate receives the logic strobe 1 signal, it allows the delayed digital pulse signal to pass through.

[0036] In a third aspect, an embodiment of the present invention further provides a PET system, including: a detector that outputs a time signal, and a device for reducing time walk in any of the PET systems described in the first aspect above.

[0037] (III) Beneficial effects

[0038] In the present invention, a high and low dual-threshold comparator is adopted. The high threshold comparator outputs a strobe signal to allow the signal generated by the low threshold discriminator to pass through, reducing the mis-triggering of noise. The threshold of the low threshold comparator can be set very low, reducing time walk, thereby improving the time resolution of the PET. Description of the drawings

[0039] Figure 1 A schematic diagram of time walk showing the corresponding energies of two events in the prior art;

[0040] Figure 2 A schematic diagram of time walk of the dual-threshold discrimination method provided by an embodiment of the present invention

[0041] Figure 3 A schematic diagram of a device for reducing time walk provided by an embodiment of the present invention;

[0042] Figure 4 A schematic diagram of an analog integrated circuit and a dedicated TDC chip constituting the above device provided by an embodiment of the present invention;

[0043] Figure 5 A schematic diagram of a device for reducing time walk based on FPGA provided by another embodiment of the present invention. Detailed implementation manners

[0044] For better explaining the present invention for easier understanding, the present invention will be described in detail below with reference to the accompanying drawings through specific embodiments.

[0045] For better understanding the solution shown in the embodiments of the present invention, the implementation principle of the embodiments of the present invention will be described in combination with Figure 2 As shown, double threshold discrimination is adopted. The voltage of the low threshold level signal is set very low, so that the high voltage of the low threshold level signal is within the voltage range of the noise band, thereby reducing time walk. The voltage of the high threshold level signal is set relatively high, and the signal generated by the low threshold discriminator is passed through by the strobe signal generated by the high threshold discriminator, thereby reducing false triggering. Figure 2 As shown, double threshold discrimination is adopted. The voltage of the low threshold level signal is set very low, so that the high voltage of the low threshold level signal is within the voltage range of the noise band, thereby reducing time walk. The voltage of the high threshold level signal is set relatively high, and the signal generated by the low threshold discriminator is passed through by the strobe signal generated by the high threshold discriminator, thereby reducing false triggering.

[0046] Embodiment 1

[0047] As Figures 2 to 5 shown, this embodiment provides a device for reducing time walk in a PET system, which includes:

[0048] A high threshold DAC, a low threshold DAC, a high threshold comparator, a low threshold comparator, a delay circuit, a logic AND gate, and a TDC (Timer Digital Converter);

[0049] The output end of the high threshold DAC is connected to the first input end of the high threshold comparator; the high threshold DAC (digital-to-analog converter) is used to output a DAC of a high threshold comparison voltage value;

[0050] The output end of the low threshold DAC is connected to the first input end of the low threshold comparator, and the low threshold DAC is used to output a DAC of a high threshold comparison voltage value;

[0051] The output end of the detector is connected to the second input end of the high threshold comparator and the second input end of the low threshold comparator;

[0052] The output end of the high threshold comparator is connected to the first input end of the logic AND gate;

[0053] The output end of the low threshold comparator is connected to the second input end of the logic AND gate via the delay circuit;

[0054] The output end of the logic AND gate outputs a time pulse signal to the TDC;

[0055] The output end of the high threshold comparator outputs a digital strobe signal, and the output end of the low threshold comparator outputs a digital pulse signal;

[0056] The output terminal of the high-threshold DAC outputs a high-threshold level signal, and the output terminal of the low-threshold DAC outputs a low-threshold level signal.

[0057] In this embodiment, the high-threshold level signal is set to a voltage lower than the time signal of the 511 Kev event; the low-threshold level signal is set in the voltage range from the bottom to the top of the noise band; the delay time range of the delay circuit is set to 8 - 16 ns.

[0058] It can be understood that the time signal output by the detector is divided into two paths and simultaneously enters one end of the input of the high-threshold comparator and the low-threshold comparator.

[0059] The high-threshold level signal output by the high-threshold DAC is connected to the other end of the input of the high-threshold comparator. The output level voltage range of the high-threshold DAC covers the peak voltage of the time signal with an energy of 300 Kev - 600 Kev.

[0060] When adjusting the parameters of the PET system, in order to see the Compton scattering curve, the output level of the high-threshold DAC is generally set at a level lower than the 511 Ke time signal. In this embodiment, the rising edge time of the time signal output by the detector using the LYSO crystal is 8 - 16 ns. In order to adapt to the dynamic range of the rising time of 8 ns, the high-threshold level can be set such that the width of the gating signal output by the high-threshold comparator for the time signal greater than 300 Kev is greater than 8 ns.

[0061] The logic signal output by the high-threshold comparator is a digital gating signal. When the voltage of the time signal is higher than the high-threshold level, the high-threshold comparator outputs a logic 1 gating signal, otherwise it outputs a logic 0 gating signal. The digital gating signal output by the high-threshold comparator is connected to one end of the input of the logic AND gate.

[0062] The low-threshold level signal output by the low-threshold DAC is connected to the other end of the input of the low-threshold comparator. The output level voltage range of the low-threshold DAC can cover the voltage from the bottom to the top of the noise band. In order to better reduce time walk, in this implementation, the low-threshold level is set at a position slightly above the middle of the noise band.

[0063] The logic signal output by the low-threshold comparator is a digital pulse signal. When the voltage of the time signal is lower than the low-threshold level, it outputs a logic 1 signal, otherwise it outputs a logic 0 signal. The digital pulse signal output by the low-threshold comparator is connected to one end of the input of a delay circuit such as a monostable flip-flop.

[0064] As Figure 3 shown, the delay circuit of this embodiment can be a monostable flip-flop; at this time, the delay time can be adjusted by adjusting the RC parameters of the monostable flip-flop.

[0065] When the monostable flip-flop does not receive a high-level pulse signal, it maintains a steady-state output of a low-level pulse signal; when the monostable flip-flop receives a high-level pulse signal, after a delay time, it flips from the steady state to the transient state and outputs a high-level pulse signal; after the monostable flip-flop outputs a high-level pulse signal, it automatically returns to the steady state.

[0066] It can be understood that the monostable flip-flop maintains a steady state when there is no high-level pulse signal input, that is, it outputs a low level; when there is a high-level pulse signal input, after a certain delay, it flips from the steady state to the transient state, that is, it outputs a high level; after a period of time, the circuit will automatically return to the steady state, that is, it outputs a low level. The time from the steady state to the transient state, that is, the delay for the pulse signal, can be adjusted by the RC parameters inside the monostable flip-flop to determine the length of the delay.

[0067] In this embodiment, the rising edge time of the output time signal of the detector using the LYSO crystal is 8 - 16 ns, that is, the signal output by the high threshold comparator is 8 - 16 ns later than the signal output by the low threshold comparator. The signal output by the low threshold comparator needs to be delayed by 16 ns to be ANDed with the signal output by the high threshold comparator. Therefore, the delay setting of the monostable flip-flop is greater than 16 ns. The length of the time from the transient state to automatically return to the steady state depends on the RC parameters outside the monostable flip-flop and has nothing to do with the length of the action time of the trigger signal. In order to reduce the dead time of the delayed pulse signal, this time should be configured as short as possible.

[0068] The delayed pulse signal output by the monostable flip-flop is connected to one end of the input of the logic AND gate.

[0069] The logic AND gate mainly realizes the AND operation of the gating signal and the delayed pulse signal. Only when there is a gating signal can the delayed pulse signal pass through, which can reduce the triggering of noise. In order not to lose the fast rising edge information of the pulse signal, a high-speed logic AND gate can be used.

[0070] The time pulse signal output by the logic AND gate enters the TDC for time measurement. The rising edge of the time pulse signal represents time information, and the TDC measures the arrival time of the rising edge as the time when the detector receives the γ photon.

[0071] In Figure 3 this embodiment, the device of this embodiment is implemented in a combination manner of an analog integrated circuit and a dedicated TDC chip. Except for the dedicated TDC chip, the others are all set in the analog integrated circuit.

[0072] In addition, as Figure 4 shown, in this embodiment, the delay circuit, the logic AND gate and the TDC are integrated and implemented in the FPGA; the delay circuit is configured into a fixed delay mode through the IDELAY of the FPGA;

[0073] Inside the FPGA, a lookup table is used to implement a logical AND gate. That is, the description of the logical AND gate (which is a truth table) is written into the RAM. For the signals input to the first input terminal and the second input terminal, two addresses are input to look up the table, the information corresponding to the addresses is found, and then output.

[0074] That is to say, taking the simulation of an integrated circuit and Xilinx's FPGA as an example, as Figure 5 shown. Different from the first embodiment, the delay circuit, logical AND, and TDC are all implemented inside the FPGA.

[0075] For the delay circuit, inside the FPGA, the IDELAY can accurately delay the required time. In this embodiment, the FPGA uses spartan-6, the IDELAY is configured in the fixed delay mode (IDELAY_TYPE = FIXED), and the tap number is configured to 150 to achieve a 10ns delay.

[0076] For the logical AND, inside the FPGA, it can be implemented using a lookup table (Look-Up-Table). The LUT is essentially a RAM. The description of the logical AND is written into the RAM in advance. In this way, for the two-input signals, it is equivalent to inputting two addresses to look up the table, finding the content corresponding to the addresses, and then outputting.

[0077] In addition, in other embodiments, the above-mentioned device can also be fully integrated in an ASIC chip for implementation. This embodiment does not limit it, and it can be selected according to actual needs.

[0078] The device of this embodiment can be implemented in both a circuit and a chip to reduce time walk and improve the time resolution of the PET.

[0079] In addition, the embodiment of the present invention also provides a method for a device to reduce time walk in a PET system, which includes:

[0080] The high-threshold level signal output by the high-threshold DAC and the time signal output by the detector pass through the high-threshold comparator to output a digital strobe signal;

[0081] When the voltage of the time signal output by the detector is higher than the low-threshold level signal output by the low-threshold DAC, the low-threshold comparator outputs a digital pulse signal to the delay circuit. After being delayed by the delay circuit, it enters the logical AND gate. The delayed digital pulse signal and the logical strobe signal are ANDed by the logical AND gate, and the delayed pulse signal passes through the logical AND gate and enters the TDC for time measurement to achieve reduction of time walk.

[0082] Specifically, when the voltage of the time signal output by the detector is higher than the high-threshold level signal output by the high-threshold DAC, the high-threshold comparator outputs a logical strobe 1 signal;

[0083] When the voltage of the time signal output by the detector is lower than the high threshold level signal output by the high threshold DAC, the high threshold comparator outputs a logic gating 0 signal;

[0084] When the logic AND gate receives a logic gating 1 signal, it allows the delayed digital pulse signal to pass through.

[0085] On the other hand, an embodiment of the present invention further provides a PET system, including: a detector that outputs a time signal, and a device for reducing time walk in any of the PET systems described in the first aspect above.

[0086] In addition, it should be noted that in the description of this specification, the descriptions of terms such as "an embodiment", "some embodiments", "embodiment", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0087] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications after learning the basic creative concepts. Therefore, the claims should be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0088] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention should also include these modifications and variations.

Claims

1. A device for reducing time walk in a PET system, characterized in that, Comprising: A high-threshold DAC, a low-threshold DAC, a high-threshold comparator, a low-threshold comparator, a delay circuit, a logic AND gate, and a TDC; The output terminal of the high-threshold DAC is connected to the first input terminal of the high-threshold comparator; The output terminal of the low-threshold DAC is connected to the first input terminal of the low-threshold comparator, The output terminal of the detector is connected to the second input terminal of the high-threshold comparator and the second input terminal of the low-threshold comparator; The output terminal of the high-threshold comparator is connected to the first input terminal of the logic AND gate; The output terminal of the low-threshold comparator is connected to the second input terminal of the logic AND gate via the delay circuit; The output terminal of the logic AND gate outputs a time pulse signal to the TDC; The output terminal of the high-threshold comparator outputs a digital strobe signal, and the output terminal of the low-threshold comparator outputs a digital pulse signal; The output terminal of the high-threshold DAC outputs a high-threshold level signal, and the output terminal of the low-threshold DAC outputs a low-threshold level signal; the high voltage of the low-threshold DAC is within the voltage range of the noise band; The high-threshold level signal is a strobe signal whose width is greater than 8 ns output by the high-threshold comparator for a time signal greater than 300 Kev.

2. The device according to claim 1, wherein: The high-threshold level signal is a level signal lower than the time signal of 511 Kev; The low-threshold level signal covers the voltage from the bottom to the top of the noise band; The delay time range of the delay circuit is 8 - 16 ns.

3. The device according to claim 1, wherein: The delay circuit is a monostable flip-flop; When the monostable flip-flop does not receive a high-level pulse signal, it maintains a steady-state output of a low-level pulse signal; When the monostable flip-flop receives a high-level pulse signal, after a delay time, it flips from the steady state to the transient state and outputs a high-level pulse signal; After the monostable flip-flop outputs a high-level pulse signal, it automatically returns to the steady state.

4. The device according to claim 3, wherein: The delay time is adjusted by adjusting the RC parameters of the monostable flip-flop.

5. The device according to claim 1, wherein: The delay circuit, the logic AND gate, and the TDC are integrated and implemented in the FPGA; the delay circuit is configured into a fixed-delay mode through the IDELAY of the FPGA; Inside the FPGA, the logic AND gate is implemented by using a look-up table, that is, the truth table of the logic AND gate is written into the RAM, and for the signals input to the first input terminal and the second input terminal, two addresses are input to look up the table, and the information corresponding to the address is found and then output.

6. A method for a device in a PET system according to any one of claims 1 to 5 to reduce time walk, characterized in that, Comprising: The high-threshold level signal output by the high-threshold DAC and the time signal output by the detector pass through the high-threshold comparator to output a digital strobe signal; When the voltage of the time signal output by the detector is higher than the low-threshold level signal output by the low-threshold DAC, the low-threshold comparator outputs a digital pulse signal to the delay circuit, and after being delayed by the delay circuit, it enters the logic AND gate. The delayed digital pulse signal and the logic strobe signal are ANDed by the logic AND gate, and the delayed pulse signal of the logic AND gate enters the TDC for time measurement, realizing the reduction of time walk.

7. The method according to claim 6, wherein when the voltage of the time signal output by the detector is higher than the high threshold level signal output by the high-threshold DAC, the high-threshold comparator outputs a logic gating 1 signal; when the voltage of the time signal output by the detector is lower than the high threshold level signal output by the high-threshold DAC, the high-threshold comparator outputs a logic gating 0 signal; when the logic AND gate receives the logic gating 1 signal, it allows the delayed digital pulse signal to pass through.

8. A PET system, comprising: A detector for outputting a time signal, and a device for reducing time walk in the PET system according to any one of claims 1 to 5 above.

Images