Data bus duty cycle distortion compensation

Abstract

This application relates to data bus duty cycle distortion compensation. An electrical circuit arrangement includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit operably coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle of a plurality of signals communicated via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles, and comparing the representative duty cycle of the plurality of signals communicated via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting trim values associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles, and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim values.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to data bus duty cycle distortion compensation in electrical circuitry of memory devices, such as memory subsystems. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application provides an electrical circuit device comprising: a signal bus including a plurality of parallel signal paths; and a calibration circuit operatively coupled to the signal bus, the calibration circuit comprising: a multi-input integrator circuit coupled to the plurality of parallel signal paths, the multi-input integrator circuit being configured to determine a representative duty cycle among a plurality of duty cycles of a plurality of signals transmitted via the plurality of parallel signal paths; a comparator circuit coupled to the multi-input integrator circuit, the comparator circuit being configured to compare the representative duty cycle of the plurality of signals transmitted via the plurality of parallel signal paths with a reference value to determine a comparison result; a control system coupled to the comparator circuit, the control system being configured to adjust a fine-tuning value associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles; and a decoder circuit coupled to the control system, the decoder circuit being configured to calibrate the plurality of duty cycles of the plurality of signals using the adjusted fine-tuning value.

[0004] In another aspect, this application provides an electrical circuit device comprising: a signal bus including a plurality of parallel signal paths; and a calibration circuit operatively coupled to the signal bus to perform operations including: determining a representative duty cycle among a plurality of duty cycles of a plurality of signals transmitted via the plurality of parallel signal paths; comparing the representative duty cycle of the plurality of signals transmitted via the plurality of parallel signal paths with a reference value to determine a comparison result; adjusting a fine-tuning value associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles; and using the adjusted fine-tuning value to calibrate the plurality of duty cycles of the plurality of signals.

[0005] In another aspect, this application provides a method comprising: determining a representative duty cycle of a plurality of signals transmitted via a plurality of parallel signal paths, the plurality of signals including a plurality of duty cycles; comparing the representative duty cycle of the plurality of signals transmitted via the plurality of parallel signal paths with a reference value to determine a comparison result; adjusting a fine-tuning value associated with the plurality of duty cycles of the plurality of signals based on the comparison result to compensate for distortion in the plurality of duty cycles; and using the adjusted fine-tuning value to calibrate the plurality of duty cycles of the plurality of signals. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram illustrating a portion of a memory device having a duty cycle distortion calibration circuit system according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart of an example method for compensating for data bus duty cycle distortion in an electrical circuit apparatus according to some embodiments of the present disclosure.

[0010] Figure 4 A block diagram illustrating a portion of a memory device having a pad_io distortion sensor according to some embodiments of the present disclosure.

[0011] Figure 5 This is a block diagram illustrating a portion of a memory device having a pad_io distortion calibration circuitry system according to some embodiments of the present disclosure.

[0012] Figure 6 A block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] This disclosure relates to data bus duty cycle distortion compensation in the electrical circuitry of a memory device, such as a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem containing one or more memory devices, such as those for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more memory dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. The logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of such values.

[0015] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of a memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and can include a group of memory cells, a group of word lines, a word line, or an individual memory cell.

[0016] Clock signals are used to coordinate the operation of electrical circuits in electrical circuit devices, such as memory devices. The duty cycle of a clock signal is the ratio of the pulse duration of the clock signal to its cycle period. The duty cycle of a clock signal can become distorted due to various sources, including amplifiers that make up the clock tree, large propagation distances between amplifier stages in the clock tree, and / or parasitic conductor capacitances. Duty cycle distortion skews the timing tolerance defined by the clock signal in the electrical circuit device. As a result, electrical circuits using distorted clock signals may have smaller timing windows in which data is transmitted and / or processed, which can lead to reduced pulse widths, data errors, and unreliable circuit performance. Reducing duty cycle distortion becomes increasingly challenging as input / output speeds increase (e.g., as the clock signal cycle decreases), meaning that the consequences of duty cycle distortion are even more pronounced at high input / output speeds. Furthermore, electrical circuits at different locations (e.g., on different electrical circuit dies or memory dies) can experience different degrees of clock signal duty cycle distortion due to different distortion sources located along corresponding clock branches of the clock tree that define the clock signal path.

[0017] Furthermore, many electrical circuit devices utilize multi-branch data paths comprising multiple parallel signal paths from a common source to a common destination. Although each parallel signal path can be formed using the same circuitry (i.e., with the same schematic and layout), processing variations introduced during the manufacture of the components forming the parallel signal paths can lead to differences in the degree of duty cycle distortion associated with each signal path. Therefore, many duty cycle distortion compensation techniques, such as those utilizing standard or default fine-tuning settings or those calibrating multiple parallel signal paths based on the characteristics of only one of the signal paths, are insufficient. Even if any such compensation technique takes into account systematic distortions and / or die-to-die variations in the electrical circuit device, it still cannot compensate for and may even adversely affect local variations between individual parallel signal paths. Consequently, considerable duty cycle distortion remains, and the duty cycle distortion attributable to local variations may be even worse than before the use of such techniques, resulting in increased errors in the signals transmitted via multiple parallel signal paths. This reduces the accuracy of the electrical circuit device and can produce suboptimal performance.

[0018] This disclosure addresses the above and other drawbacks by compensating for data bus duty cycle distortion in an electrical circuit arrangement. In one embodiment, the data bus (i.e., the signal bus) comprises multiple parallel signal paths, each having unique characteristics that can affect the associated duty cycle of the signal transmitted thereon. Taking into account those differences, a calibration circuit determines a representative duty cycle for multiple signals transmitted via the multiple parallel signal paths of the data bus. In one embodiment, a multi-input integrator circuit comprising multiple passive low-pass filters receives signals from the multiple parallel signal paths and generates a DC level representation of the duty cycle for each signal. The representative duty cycle may include, for example, an average of the DC level representation. In one embodiment, this representative duty cycle is compared to a reference value. Depending on whether the representative duty cycle is greater than or less than the reference value, the calibration circuit may adjust a fine-tuning value associated with the duty cycle to compensate for any distortion. The calibration circuit may further calibrate the duty cycle of the signals transmitted via the multiple parallel signal paths by applying the adjusted fine-tuning value.

[0019] The advantages of this method include, but are not limited to, improved performance in memory subsystems or other electronic circuit devices at least in part attributable to more accurate signal calibration. For example, the techniques described herein allow for compensation for systematic duty cycle distortion and / or die-to-die variations in electrical circuit devices, as well as local variations between individual parallel signal paths. Depending on the implementation, duty cycle distortion attributable to these local variations is reduced, specifically when the number of parallel signal paths is relatively low. Therefore, more overall duty cycle distortion can be compensated, thereby reducing errors in signals transmitted via multiple parallel signal paths. Additionally, the calibration routines described herein can be performed relatively quickly to reduce latency and improve signal transmission time.

[0020] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such media.

[0021] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0022] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0023] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0024] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110 to, for example, write data to memory subsystem 110 and read data from memory subsystem 110.

[0025] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0026] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0027] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND type flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array for bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0028] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination of such arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as MLC, TLC, QLC, or PLC portions. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. In the case of some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0029] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0030] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0031] The memory subsystem controller 115 may be a processing device that includes one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0032] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0033] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0035] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) within the same memory device package for media management. An example of a managed memory device is a managed NAND (MNAND) device.

[0036] In one embodiment, memory subsystem 110 is an example of an electrical circuit device as described herein, and memory device 130 is an example of an electrical circuit die. In one embodiment, memory subsystem 110 includes a clock generator (now shown) that may be located within memory device 130 or elsewhere within memory subsystem 110. The clock generator generates clock signals for coordinating the operation of the electrical circuitry within memory subsystem 110. The clock generator may transmit the clock signals to various components of memory subsystem 110 via a clock tree. For example, the clock generator may send clock signals to memory subsystem controller 115 via a first clock branch and to memory device 130 via a second clock branch of the clock tree. In other embodiments, memory subsystem 110 may alternatively rely on an externally supplied clock signal (e.g., provided by an external host or by a processor or controller separate from the electrical circuitry). In other embodiments, the clock signal may be partially generated and / or partially externally supplied and partially generated and / or partially supplied by the circuitry located within memory subsystem 110.

[0037] In one embodiment, clock signals and / or any other signals (e.g., data signals, command signals) may be transmitted via a signal bus, either internal or external to the memory device 130. The signal bus may include, for example, multiple parallel signal paths. Each of the multiple parallel signal paths may be identical in design and composition; however, the components used to form each of the multiple parallel signal paths may have processing variations introduced during manufacturing. These variations can affect the duty cycle of the signals transmitted via the multiple parallel signal paths. Therefore, in one embodiment, the memory device 130 includes calibration circuitry 150, which can calibrate the duty cycle of those signals in a manner that takes into account local variations between the multiple parallel signal paths. In one embodiment, calibration circuitry 150 may determine a representative duty cycle (e.g., average duty cycle) of all signals transmitted via the multiple parallel signal paths and compare the representative duty cycle with a reference value to determine a comparison result. Based on the comparison result, calibration circuitry may adjust a fine-tuning value associated with the duty cycle of the signal to compensate for distortion in the duty cycle, and the adjusted fine-tuning value can be used to calibrate all duty cycles. Furthermore, in embodiments comprising multiple electrical circuit dies (e.g., memory devices), calibration circuitry 150 may be used on all or a subset of the electrical circuit dies. In these and other embodiments, calibration circuitry 150 may be used in addition to or in place of other calibration circuitry systems (e.g., DLL calibration circuitry systems) and / or other techniques (e.g., general static tuning values ​​for all electrical circuit dies). Moreover, as described herein, calibration circuitry 150 consumes a relatively small amount of area and a relatively small amount of power compared to other circuitry systems used for calibration (e.g., DLL calibration circuitry systems). Calibration circuitry 150 also does not require a warm-up cycle and can begin calibration during the first iteration of the clock signal. Additionally, calibration circuitry 150 may utilize stable tuning (e.g., digital tuning) and bias (e.g., voltage and / or current) values ​​specific to each individual electrical circuit die, thereby taking into account die-to-die variations in the duty cycle distortion exhibited by the clock signal. Further details regarding the operation of calibration circuitry 150 are described below.

[0038] Figure 2This is a block diagram illustrating a portion of a memory device 130 with a duty cycle distortion calibration circuitry system according to some embodiments of the present disclosure. As illustrated, a portion of the memory device 130 may include multi-branch data paths comprising multiple parallel signal paths, such as signal paths 202, 204, 206, and 208 for transmitting signals from a common source to a common destination. For ease of description, each of signal paths 202, 204, 206, and 208 may have a corresponding input (i.e., in0, in1, in2, in3) and a corresponding output (i.e., out0, out1, out2, out3). In one embodiment, the signals transmitted via signal paths 202, 204, 206, and 208 may already contain duty cycle distortion from sources outside the memory device 130 (e.g., attributable to the board design and / or other sources of the memory subsystem 110). Signal paths 202, 204, 206, and 208 can be used to transmit signals to any number of destinations within memory device 130, including, for example, memory arrays, such as NAND memory arrays, or to some other integrated circuit system. Depending on the embodiment, duty cycle distortion can be added along the internal signal paths to the signal from the source and can be accumulated together with distortion already introduced by sources encountered along signal paths located outside memory device 130. Because calibration circuit 150 samples the signals at the outputs of signal paths 202, 204, 206, and 208 (i.e., at outputs out0, out1, out2, and out3), both sources of duty cycle distortion can be detected and taken into account during calibration. In other embodiments, memory device 130 may include multiple duty cycle distortion calibration circuits 150 and may sample and calibrate signals at all points or subsets of points along the internal signal paths described herein.

[0039] In one embodiment, the calibration circuitry 150 includes a multi-input integrator 210, a comparator 220, a control system 230, and a decoder 240. Depending on the embodiment, the control system 230 and decoder 240 may be part of a local media controller 135, such as... Figure 1 As shown in the figure. In other embodiments, the calibration circuit 150 may include any combination of these or other components, and / or some or all of these components may be omitted.

[0040] In one embodiment, calibration circuit 150 samples signals from multiple parallel signal paths 202, 204, 206, and 208 to calibrate the duty cycle of each signal. More specifically, multi-input integrator 210 receives signals at the outputs (i.e., out0, out1, out2, out3) of signal paths 202, 204, 206, and 208. In one embodiment, multi-input integrator 210 includes corresponding passive low-pass filters (LPFs) 212, 214, 216, and 218, each corresponding to one of the multiple parallel signal paths 202, 204, 206, and 208. Passive low-pass filters 212, 214, 216, and 218 convert voltage signals into corresponding DC (e.g., analog) levels representing the duty cycles of the voltage signals from signal paths 202, 204, 206, and 208. The outputs of each of the passive low-pass filters 212, 214, 216, and 218 are combined to represent an average DC level representation 222 (i.e., [DC(out0) + DC(out1) + DC(out2) + DC(out3)] / n, where n represents the number of signal paths / passive low-pass filters). Comparator 220 converts the average DC level representation 222 into a digital signal representation and compares the digital signal representation with a reference value. In one embodiment, the reference value is half the voltage source level (i.e., Vcc / 2), which corresponds to a duty cycle of 50. Comparator 220 provides one or more results of the comparison (i.e., whether the average DC level representation 222 is greater than or less than the reference value) to control system 230. The control system 230 of the state machine may perform algorithms (e.g., binary sweep algorithm and / or bisection search) to calculate and / or adjust (e.g., using a lookup table) one or more fine-tuning values ​​(e.g., digital fine-tuning values) to reduce the duty cycle of voltage signals with larger duty cycles and increase the duty cycle of voltage signals with smaller duty cycles. One or more fine-tuning values ​​are passed to a decoder 240 (e.g., a digital-to-analog converter), which converts the fine-tuning values ​​into duty cycle fine-tuning settings (e.g., bias voltage and / or bias current) in the voltage signals fed into multiple parallel signal paths 202, 204, 206, and 208. In one embodiment, the same duty cycle fine-tuning setting based on the average DC level representation 222 is applied to each of the multiple parallel signal paths 202, 204, 206, and 208.

[0041] Figure 3This is a flowchart of an example method for compensating for data bus duty cycle distortion in an electrical circuit device according to some embodiments of the present disclosure. Method 300 may be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The calibration is performed by the calibration component 150. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 305, a representative value is determined. For example, the processing logic of the memory device 130 (e.g., in conjunction with the local media controller 135 of the calibration component 150) determines the representative value, such as the representative duty cycle of a signal transmitted via multiple parallel signal paths, such as parallel signal paths 202, 204, 206, and 208. In one embodiment, the calibration component 150 obtains a DC level (e.g., analog level) representation of the duty cycle of the transmitted voltage signal. For example, the calibration component 150 can obtain a DC level representation of the duty cycle of the voltage signal by passing the voltage signal through respective low-pass filters, such as passive low-pass filters 212, 214, 216, and 218. In one embodiment, the outputs of each of the respective low-pass filters are combined to produce a DC level representation, such as an average DC level representation.

[0043] At operation 310, a comparison is made. For example, the processing logic may convert the DC level representation of the duty cycle into a digital signal representation and compare the digital signal representation with a reference value. In one embodiment, calibration component 150 may pass the DC level representation of the duty cycle to a comparator (e.g., comparator 220), which (e.g., an auto-zero comparator) is capable of handling very small voltage offsets to convert the DC level representation into a digital signal representation and compare the digital signal representation with a reference value. In one embodiment, the reference value is half the voltage source level (i.e., Vcc / 2). The comparator may then pass a comparison result indicating whether the average DC level 222 is greater than or less than the reference value to a control system (e.g., control system 230). In some embodiments, the result may include a digital signal representation of the magnitude of the difference between the average DC level 222 and the reference value.

[0044] At operation 315, the tuning value is adjusted. For example, processing logic may calculate and / or adjust one or more digital tuning values ​​for the electrical circuit die, such as memory device 130, and store the digital tuning values. In some embodiments, the digital tuning value may generally correspond to a voltage signal transmitted via multiple parallel signal lines. For example, the control system of calibration circuit 150 (e.g., control system 230) may perform a binary sweep algorithm and / or a bipartite search (e.g., over multiple iterations) to calculate and / or adjust the digital tuning value and store the digital tuning value (e.g., on a state machine, a controller of the electrical circuit device, a controller of the electrical circuit die, and / or a host device). In embodiments where the state machine stores the digital tuning value at a location different from the state machine, the digital tuning value may be provided to the state machine (e.g., when the calibration circuit system is activated). In these and other embodiments, the digital tuning value may be passed to the state machine to verify the digital tuning value and / or verify the digital tuning value stored on the state machine.

[0045] The newly calculated and / or adjusted digital trim value can be used to make the duty cycle of the voltage signal smaller or larger. In embodiments where the result from the comparator includes an indication of the magnitude of the difference between the representative duty cycle and a reference value, the state machine (i.e., control system 230) can calculate and / or adjust the trim value based on said difference (e.g., using a lookup table, a binary sweep algorithm, and / or a bipartite search) to adjust the trim value. In these and other embodiments, the trim value can also be calculated and / or adjusted based on the results of previous iterations of the calibration circuitry system. For example, in the first iteration of calibrating the voltage signal, circuit 150 may adjust the duty cycle by a certain amount (e.g., 12.5%). In the next iteration, the calibration circuit 150 may (e.g., from the result sent from the self-comparator to the state machine) notice that the difference between the representative duty cycle of the voltage signal and the reference value in the second iteration is smaller or larger than the difference in the first iteration, and therefore may calculate and / or adjust the digital trim value to adjust the duty cycle of the voltage signal to a smaller, larger, and / or equivalent amount than the adjustment made in the first iteration (e.g., less than, greater than, and / or equivalent to 12.5% ​​of the percentage).

[0046] At operation 320, the duty cycle is calibrated. For example, processing logic may convert a digital trim value into one or more bias voltages and / or bias currents, which can be used to calibrate the duty cycle of voltage signals transmitted via multiple parallel signal paths to account for duty cycle distortion. For example, control system 230 may pass the digital trim value to a bias circuitry system (e.g., decoder 240), which may convert the digital trim value into one or more bias voltages and / or bias currents. The bias circuitry system may apply one or more bias voltages and / or bias currents to multiple parallel signal paths 202, 204, 206, and 208 (e.g., directly after, or shortly thereafter, inputs in0, in1, in2, and in3). In another embodiment, the digital trim value may be used directly to enable / disable one or more pins of the pull-up / pull-down network of digital gates to adjust the duty cycle of the voltage signal without utilizing decoder 240 or other bias circuitry systems. In some embodiments, the process may automatically return to operation 305 for the next iteration of distortion calibration. In other embodiments, the process may wait to return to operation 305 until guided back (e.g., by a controller of an electrical circuit device; a controller within an electrical circuit die; and / or a host system). In this way, the process can calibrate (e.g., on a single and / or multiple iterations) the duty cycle of signals transmitted via multiple parallel signal paths by calculating one or more optimized digital fine-tuning values ​​to account for distortion introduced by external and / or internal distortion sources.

[0047] Figure 4This is a block diagram illustrating a portion of a memory device with a pad-io distortion sensor according to some embodiments of the present disclosure. For example, certain electronic circuitry of the memory device 130 may utilize differential data strobe signals, such as DQS 402 and DQSN 404. In one embodiment, DQS 402 and DQSN 404 are complementary data strobe signals that can provide a synchronization reference for data inputs and outputs in the memory device 130, such as data received or transmitted at I / O pins of the device. Although the I / O pins may be referenced, they may include any conductive nodes that enable electrical connection to the memory device 130 via external devices, such as commonly used conductive pads or conductive bumps. Because the differential data strobe signals DQS 402 and DQSN 404 are transmitted via separate signal paths within the memory device 130, each signal may experience different levels of distortion. For example, each signal may typically experience distortion attributable to the read clock signal RDCLK in memory device 130 (i.e., RDCLK distortion), but may also experience distortion individually associated with the corresponding I / O pin (i.e., pad_io distortion). Since the differential data strobe signals DQS 402 and DQSN 404 are complementary, in one case, RDCLK distortion and pad_io distortion will be additive, and in other cases, RDCLK distortion and pad_io distortion may cancel each other out to some extent. When the data pattern of a pad_io pair (i.e., a group of two data or data strobe signals) is the same as the differential clock, RDCLK distortion will be added to the distortion of one signal from the pad_io pair, but subtracted from the other. For example, if the RDCLK distortion is A and the pad_io distortion is B (where A and B are not absolute values, but can be positive or negative), then the total distortion for one pad_io will be B+A and the total distortion for the other will be BA. Therefore, the average of B+A and BA is exactly B. Thus, in one embodiment, sensing circuitry 450 can be used to more accurately sense the level of pad_io distortion without utilizing separate sensing and calibration circuitry systems for each signal path. In one embodiment, sensing circuitry 450 includes a multi-input integrator 410 and a comparator 420. In other embodiments, sensing circuitry 450 may include any combination of these or other components, and / or some or all of these components may be omitted.

[0048] In one embodiment, sensing circuitry 450 samples signals DQS 402 and DQSN 404 to determine the duty cycle of each signal. In one embodiment, multi-input integrator 410 includes corresponding passive low-pass filters (LPFs) 412 and 414, each corresponding to one of the signal paths. Passive low-pass filters 412 and 414 convert the voltage signals into a DC level (e.g., analog level) representation of the voltage signal's duty cycle. The outputs of each of passive low-pass filters 412 and 414 are combined to represent an average DC level representation 422 (i.e., [DC(DQS) + DC(DQSN)] / 2). Comparator 420 converts the average DC level representation 422 into a digital signal representation and compares the digital signal representation to a reference value. In one embodiment, the reference value is half the voltage source level (i.e., Vcc / 2), corresponding to a duty cycle of 50. Comparator 420 produces one or more results of the comparison (i.e., whether the average DC level representation 422 is greater than or less than the reference value). Therefore, the polarity of the result indicates whether the pad_io distortion of the data strobe signals DQS 402 and DQSN 404 is greater than or less than zero.

[0049] Figure 5 The following is a block diagram illustrating a portion of a memory device having a pad_io distortion calibration circuitry system according to some embodiments of the present disclosure. In one embodiment, differential data strobe signals such as DQS 402 and DQSN 404, along with a set of data signals (e.g., DQ0-DQn-1), are all associated with a read clock signal RDCLK in memory device 130. Since each signal is associated with a common RDCLK signal, the total distortion calibration can be concurrent. Therefore, in one embodiment, differential data strobe signals DQS 402 and DQSN 404 form a pad_io pair, and the remaining data signals DQ0-DQn-1 are arranged in additional pad_io pairs. For example, pad_io pair 500 may include pad_io 502 and pad_io 504 corresponding to data signals DQ0 and DQ1, respectively, and pad_io pair 505 may include pad_io 506 and pad_io 508 corresponding to data signals DQn-2 and DQn-1, respectively. In one embodiment, there is no... Figure 5The additional pad_io pairs described herein. For each pad_io pair, such as pad_io pair 500 and pad_io pair 505, one DQ signal has the same data pattern as the data strong signal DQS, and the other DQ signal has the same data pattern as DQSN. Therefore, in one embodiment, a calibration circuit 550 may be used to sense the level of pad_io distortion more accurately without utilizing a separate sensing and calibration circuitry system for each signal path. In one embodiment, the calibration circuit 550 includes a multi-input integrator 510, a comparator 520, a control system 530, and a decoder 540. Depending on the embodiment, the control system 530 and the decoder 540 may be part of the local media controller 135, such as Figure 1 As shown in the figure. In other embodiments, the calibration circuit 550 may include any combination of these or other components, and / or some or all of these components may be omitted.

[0050] In one embodiment, calibration circuit 550 samples the signal from each pad_io pair to calibrate the duty cycle of each signal. More specifically, multi-input integrator 510 receives the signal at the output of each pad_io. In one embodiment, multi-input integrator 510 includes corresponding passive low-pass filters (LPFs) 512, 514, 516, and 518, each corresponding to one of the pad_ios. Passive low-pass filters 512, 514, 516, and 518 convert the voltage signal into a corresponding DC level (e.g., analog level) representation of the duty cycle of the voltage signal from the pad_io. The outputs of each of passive low-pass filters 512, 514, 516, and 518 are combined to represent an average DC level representation 522 (i.e., [DC(DQS) + DC(DQSN) + DC(DQ0) + DC(DQ1) ... + DC(DQn-1)] / n + 2, where n represents the number of data signals DQ). Comparator 520 converts the average DC level representation 522 into a digital signal representation and compares the digital signal representation with a reference value. In one embodiment, the reference value is half the voltage source level (i.e., Vcc / 2), which corresponds to a duty cycle of 50. Comparator 520 provides one or more results of the comparison (i.e., whether the average DC level representation 522 is greater than or less than the reference value) to control system 530. Control system 530, which is a state machine, may perform algorithms (e.g., binary sweep algorithm and / or bisection search) to calculate and / or adjust (e.g., using a lookup table) one or more trim values ​​(e.g., digital trim values) to reduce the duty cycle of voltage signals with larger duty cycles and increase the duty cycle of voltage signals with smaller duty cycles. One or more trim values ​​are passed to decoder 540 (e.g., digital-to-analog converter), which converts the one or more trim values ​​into duty cycle trim settings (e.g., bias voltage and / or bias current) for the voltage signals fed into pad_io. In one embodiment, the same duty cycle fine-tuning setting based on the average DC level is applied to each of pad_io.

[0051] Figure 6 This describes an example machine of computer system 600, within which an instruction set for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used for controller operations (e.g., for executing an operating system to perform corresponding...). Figure 1(Operation of the local media controller 135). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0052] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, although a single machine is described, the term "machine" should be considered to also include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any one or more of the methods discussed herein.

[0053] The example computer system 600 includes a processing device 602 that communicates with each other via a bus 630, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 618.

[0054] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 communicating via network 620.

[0055] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more sets of instructions 626 or software embodying any one or more of the methods or functions described herein. In one embodiment, this medium 624 may also be written to by a local media controller 135, a memory subsystem controller 115, or other components. The instructions 626 may also reside wholly or at least partially in main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to Figure 1 The memory subsystem 110.

[0056] In one embodiment, instruction 626 includes instructions for implementing the corresponding Figure 1 The local media controller 135 provides functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0057] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here is, and generally is, considered a self-consistent sequence of operations that produce a desired result. Operations are those that require the physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0058] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system, or other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0059] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct devices more specialized for carrying out the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0061] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0062] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. An electrical circuit device comprising: A signal bus, which includes multiple parallel signal paths; as well as A calibration circuit operatively coupled to the signal bus, the calibration circuit comprising: A multi-input integrator circuit coupled to the plurality of parallel signal paths, the multi-input integrator circuit being used to determine the average value of a plurality of duty cycles of a plurality of signals transmitted via the plurality of parallel signal paths. A comparator circuit coupled to the multi-input integrator circuit, the comparator circuit being used to compare the average value of the multiple duty cycles of the multiple signals transmitted via the multiple parallel signal paths with a reference value to determine a comparison result; A control system coupled to the comparator circuit, the control system being configured to adjust, based on the comparison result, fine-tuning values ​​associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles; and A decoder circuit coupled to the control system, the decoder circuit being used to calibrate the plurality of duty cycles of the plurality of signals using the adjusted fine-tuning value.

2. The electrical circuit apparatus of claim 1, wherein the multi-input integrator circuit includes a plurality of passive low-pass filters coupled to the plurality of parallel signal paths, the plurality of passive low-pass filters being used to obtain a plurality of DC level representations of the plurality of duty cycles of the plurality of signals, and wherein the output of the multi-input integrator circuit includes a DC level representation among the plurality of DC level representations.

3. The electrical circuit apparatus of claim 2, wherein the comparator circuit is used to convert the DC level representation into a representative digital signal representation, and wherein the comparator circuit is used to compare the DC level representation with the reference value in order to compare the average value of the plurality of duty cycles of the plurality of signals transmitted via the plurality of parallel signal paths with the reference value.

4. The electrical circuit device according to claim 1, wherein the reference value includes half of the voltage source level.

5. The electrical circuit apparatus of claim 1, wherein the decoder circuit is configured to convert the fine-tuning value into one or more bias voltages and / or bias currents, and to apply the one or more bias voltages and / or bias currents to the plurality of signals transmitted via the plurality of parallel signal paths to calibrate the plurality of duty cycles.

6. The electrical circuit device according to claim 1, further comprising: A memory array, wherein the signal bus of the plurality of parallel signal paths is coupled to the memory array.

7. The electrical circuit apparatus of claim 1, wherein the distortion in the plurality of duty cycles is at least in part based on processing variations in the components forming the plurality of parallel signal paths.

8. An electrical circuit device comprising: A signal bus, which includes multiple parallel signal paths; as well as A calibration circuit, operatively coupled to the signal bus, is configured to perform operations including: Determine the average value of multiple duty cycles of multiple signals transmitted via the multiple parallel signal paths; The average value of the multiple duty cycles of the multiple signals transmitted via the multiple parallel signal paths is compared with a reference value to determine the comparison result; Based on the comparison results, the fine-tuning values ​​associated with the plurality of duty cycles of the plurality of signals are adjusted to compensate for distortion in the plurality of duty cycles; as well as The adjusted fine-tuning value is used to calibrate the multiple duty cycles of the multiple signals.

9. The electrical circuit device of claim 8, wherein the calibration circuit is configured to perform additional operations including: Multiple passive low-pass filters are used to obtain multiple DC level representations of the multiple duty cycles of the multiple signals; Determine the DC level representation among the plurality of DC level representations; as well as A comparator is used to convert the DC level representation into a representative digital signal representation.

10. The electrical circuit apparatus of claim 9, wherein comparing the average of the plurality of duty cycles of the plurality of signals transmitted via the plurality of parallel signal paths with the reference value includes using the comparator to compare the DC level representation with the reference value.

11. The electrical circuit device of claim 8, wherein the reference value comprises half of the voltage source level.

12. The electrical circuit device of claim 8, wherein the calibration circuit is configured to perform additional operations including: The fine-tuning value is converted into one or more bias voltages and / or bias currents; and The multiple duty cycles are calibrated by applying one or more bias voltages and / or bias currents to the multiple signals transmitted via the multiple parallel signal paths.

13. The electrical circuit device according to claim 8, further comprising: A memory array, wherein the signal bus of the plurality of parallel signal paths is coupled to the memory array.

14. The electrical circuit apparatus of claim 8, wherein the distortion in the plurality of duty cycles is at least in part based on processing variations in the components forming the plurality of parallel signal paths.

15. A method of operating an electrical circuit device, comprising: Determine the average duty cycle of multiple signals transmitted via multiple parallel signal paths, wherein the multiple signals include multiple duty cycles; The average duty cycle of the multiple signals transmitted via the multiple parallel signal paths is compared with a reference value to determine the comparison result; Based on the comparison results, the fine-tuning values ​​associated with the plurality of duty cycles of the plurality of signals are adjusted to compensate for distortion in the plurality of duty cycles; as well as The adjusted fine-tuning value is used to calibrate the multiple duty cycles of the multiple signals.

16. The method of claim 15, further comprising: Multiple passive low-pass filters are used to obtain multiple DC level representations of the multiple duty cycles of the multiple signals; Determine the DC level representation among the plurality of DC level representations; as well as A comparator is used to convert the DC level representation into a representative digital signal representation.

17. The method of claim 16, wherein comparing the average duty cycle of the plurality of signals transmitted via the plurality of parallel signal paths with the reference value includes using the comparator to compare the DC level representation with the reference value.

18. The method of claim 15, wherein the reference value comprises half of the voltage source level.

19. The method of claim 15, further comprising: The fine-tuning value is converted into one or more bias voltages and / or bias currents; as well as The multiple duty cycles are calibrated by applying one or more bias voltages and / or bias currents to the multiple signals transmitted via the multiple parallel signal paths.

20. The method of claim 15, wherein the distortion in the plurality of duty cycles is at least in part based on processing variations in the components forming the plurality of parallel signal paths.

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