Shift register unit and its control method, gate driving circuit and its control method

Abstract

The present disclosure provides a shift register unit, which mainly relates to the field of display technology. Specifically, it includes: an input circuit for providing the potential of an input signal terminal to a pull-up node under the control of a first control signal terminal and a first clock signal terminal; a pull-down control circuit for controlling the potential of a pull-down node based on the potential of the pull-up node; an output circuit for providing the potential of a power supply signal terminal or a reference signal terminal to an output signal terminal under the control of the pull-up node and the pull-down node; a scan control circuit for storing the potential of the input signal terminal under the control of the first clock signal terminal and a scan control terminal, and for controlling the potential of the pull-up node based on the stored potential under the control of a second control signal terminal. The present disclosure also provides a control method for a shift register unit, a gate driving circuit, and a control method therefor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a shift register unit and a control method thereof, a gate driving circuit and a control method thereof. Background Art

[0002] In a display device, a plurality of pixels arranged in an array can be driven by a gate driving circuit. Usually, the gate driving circuit needs to scan each row of pixels in a preset order, which makes the scanning method of the display pixels not flexible enough to meet diverse requirements. Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided a shift register unit, including:

[0004] An input circuit, connected to an input signal terminal, a first control signal terminal, a first clock signal terminal, and a pull-up node, configured to provide the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal;

[0005] A pull-down control circuit, connected to the pull-up node and a pull-down node, configured to control the potential of the pull-down node based on the potential of the pull-up node;

[0006] An output circuit, connected to the pull-up node, the pull-down node, a power signal terminal, a reference signal terminal, and an output signal terminal, configured to provide the potential of the power signal terminal or the reference signal terminal to the output signal terminal under the control of the pull-up node and the pull-down node;

[0007] A scan control circuit, connected to the input signal terminal, the first clock signal terminal, a second control signal terminal, and a scan control terminal, configured to store the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal, and to control the potential of the pull-up node based on the stored potential under the control of the second control signal terminal.

[0008] In some embodiments, the scan control circuit includes:

[0009] A first scan control sub-circuit, connected to the input signal terminal, the first clock signal terminal, the scan control terminal, and a control node of the second control circuit, configured to store the potential of the input signal terminal at the control node under the control of the first clock signal terminal and the scan control terminal; and

[0010] A second scan control sub-circuit, connected to the second control signal terminal, the control node, the pull-up node, and the power signal terminal, configured to provide the potential of the power signal terminal to the pull-up node under the control of the second control signal terminal and the potential of the control node.

[0011] In some embodiments, the pull-down control circuit includes:

[0012] A first pull-down control sub-circuit, connected to the pull-up node and the pull-down node, for controlling the potential of the pull-down node based on the potential of the pull-up node; and

[0013] A second pull-down control sub-circuit, connected to the input signal terminal, the first clock signal terminal, the second clock signal terminal, and the pull-down node, for controlling the potential of the pull-down node based on the potentials of the input signal terminal, the first clock signal terminal, and the second clock signal terminal.

[0014] In some embodiments, it further includes a pull-up node reset circuit, which is connected to the pull-up node reset terminal and the pull-up node, for resetting the pull-up node under the control of the pull-up node reset terminal.

[0015] In some embodiments, it further includes a control node reset circuit, which is connected to the control node reset terminal and the control node, for resetting the control node under the control of the control node reset terminal.

[0016] In some embodiments, the first scan control sub-circuit includes at least one first transistor, a second transistor, and a first capacitor, wherein,

[0017] The at least one first transistor is serially connected between the input signal terminal and the first pole of the second transistor, and the gate of the first transistor is connected to the scan control terminal;

[0018] The gate of the second transistor is connected to the first clock signal terminal, and the second pole of the second transistor is connected to the control node;

[0019] The first pole of the first capacitor is connected to the control node, and the second pole of the first capacitor is connected to the reference signal terminal.

[0020] In some embodiments, the number of the first transistors is two, and the first scan control sub-circuit further includes a first voltage stabilizing transistor, wherein,

[0021] The two first transistors are serially connected between the input signal terminal and the first pole of the second transistor, the gates of the two first transistors are connected to the scan control terminal, and the first pole of one of the two first transistors is connected to the second pole of the other first transistor at a first voltage stabilizing node;

[0022] The gate of the first voltage stabilizing transistor is connected to the control node, the first pole of the first voltage stabilizing transistor is connected to the power signal terminal, and the second pole of the first voltage stabilizing transistor is connected to the first voltage stabilizing node.

[0023] In some embodiments, the second scan control sub-circuit includes a third transistor and at least one fourth transistor;

[0024] The gate of the third transistor is connected to the control node, and the first pole of the third transistor is connected to the power signal terminal;

[0025] The at least one fourth transistor is connected in series between the second pole of the third transistor and the pull-up node, and the gate of the fourth transistor is connected to the second control signal terminal.

[0026] In some embodiments, the first pull-down control sub-circuit includes: at least one fifth transistor, the at least one fifth transistor is connected in series between the reference signal terminal and the pull-down node, and the gate of the at least one fifth transistor is connected to the pull-up node.

[0027] In some embodiments, the second pull-down control sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor. Among them, the gate of the sixth transistor is connected to the second clock signal terminal, and the first pole of the sixth transistor is connected to the power signal terminal; the gate of the seventh transistor is connected to the input signal terminal, the first pole of the seventh transistor is connected to the second clock signal terminal, and the second pole of the seventh transistor is connected to the second pole of the sixth transistor; the gate of the eighth transistor is connected to the second pole of the sixth transistor, the first pole of the eighth transistor is connected to the first clock signal terminal; the gate of the ninth transistor is connected to the first clock signal terminal, the first pole of the ninth transistor is connected to the second pole of the eighth transistor, and the second pole of the ninth transistor is connected to the pull-down node; the first pole of the second capacitor is connected to the gate of the eighth transistor, and the second pole of the second capacitor is connected to the second pole of the eighth transistor.

[0028] In some embodiments, the pull-up node reset circuit includes at least one tenth transistor, the at least one tenth transistor is connected in series between the reference signal terminal and the pull-up node, and the gate of the at least one tenth transistor is connected to the pull-up node reset terminal.

[0029] In some embodiments, the number of the tenth transistors is two, and the pull-up node reset circuit further includes a second voltage stabilizing transistor, where

[0030] Two tenth transistors are connected in series between the reference signal terminal and the pull-up node. The gates of the two tenth transistors are connected to the pull-up node reset terminal. The first pole of one of the two tenth transistors is connected to the second pole of the other tenth transistor at the second regulated voltage node.

[0031] The gate of the second regulated voltage transistor is connected to the pull-up node. The first pole of the second regulated voltage transistor is connected to the power supply signal terminal. The second pole of the second regulated voltage transistor is connected to the second regulated voltage node.

[0032] In some embodiments, the control node reset circuit includes at least one eleventh transistor. The at least one eleventh transistor is connected in series between the reference signal terminal and the control node. The gate of the at least one eleventh transistor is connected to the control node reset terminal.

[0033] In some embodiments, the input circuit includes a twelfth transistor and at least one thirteenth transistor. The gate of the twelfth transistor is connected to the first control signal terminal. The first pole of the twelfth transistor is connected to the input signal terminal. The at least one thirteenth transistor is connected in series between the second pole of the twelfth transistor and the pull-up node. The gate of the at least one thirteenth transistor is connected to the first clock signal terminal.

[0034] According to another aspect of the present disclosure, a gate driving circuit is provided, including an N-stage cascaded shift register unit. The shift register unit is the shift register unit provided by the present disclosure. Wherein,

[0035] The output signal terminal of the (n - i)-th stage shift register unit is connected to the input signal terminal of the n-th stage shift register unit, where N is an integer greater than 1, n is an integer and 1 < n ≤ N, and i is an integer greater than or equal to 1.

[0036] In some embodiments, i = 1. The first control signal terminal and the second control signal terminal of each stage of the shift register unit are respectively connected to receive a first control signal and a second control signal. The scan control terminal is connected to receive a scan control signal;

[0037] The first clock signal terminal of the odd-stage shift register unit is connected to receive a first clock signal. The second clock signal terminal is connected to receive a second clock signal. The pull-up node reset terminal is connected to receive a first pull-up node reset signal.

[0038] The first clock signal terminal of the even-stage shift register unit is connected to receive a second clock signal. The second clock signal terminal is connected to receive a first clock signal. The pull-up node reset terminal is connected to receive a second pull-up node reset signal.

[0039] According to another aspect of the present disclosure, a control method for a shift register unit is provided, including:

[0040] In a first mode, the scan control circuit stores the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal, and the stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power supply signal terminal to the output signal terminal;

[0041] In a second mode, the input circuit provides the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power supply signal terminal to the output signal terminal.

[0042] In some embodiments, the method further includes: after the output circuit provides the potential of the power supply signal terminal to the output signal terminal, the pull-up node reset circuit resets the pull-up node under the control of the pull-up node reset terminal.

[0043] In some embodiments, the method further includes: after the stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal, the control node reset circuit resets the control node under the control of the control node reset terminal.

[0044] According to another aspect of the present disclosure, a control method for a gate driving circuit is provided, including:

[0045] In a first period, control the k-th stage shift register unit to operate in the first mode, and control the (k + 1)-th to N-th stage shift register units to operate in the second mode, so that the k-th to N-th stage shift register units generate sequentially shifted output signals with a first pulse width, where k is an integer and 1 < k ≤ N;

[0046] In a second period, control the first to (k - 1)-th stage shift register units to operate in the second mode, so that the first to (k - 1)-th stage shift register units generate sequentially shifted output signals with a second pulse width,

[0047] Wherein,

[0048] In a shift register unit operating in a first mode, a scan control circuit stores the potential of an input signal terminal under the control of a first clock signal terminal and a scan control terminal, and the stored potential causes the scan control circuit to pull up the potential of a pull-up node under the control of a second control signal terminal. The potential of the pull-up node causes a pull-down node control circuit to pull down the potential of a pull-down node and causes an output circuit to provide the potential of a power signal terminal to the output signal terminal;

[0049] In a shift register unit operating in a second mode, an input circuit provides the potential of an input signal terminal to a pull-up node under the control of a first control signal terminal and a first clock signal terminal. The potential of the pull-up node causes a pull-down node control circuit to pull down the potential of a pull-down node and causes an output circuit to provide the potential of a power signal terminal to an output signal terminal.

[0050] In some embodiments, it further includes: in a second time period, after an output signal is generated by a (k-1)-th stage shift register unit, one of a first pull-up node reset signal and a second pull-up node reset signal is used to control a pull-up node reset circuit of a k-th stage shift register unit to reset the pull-up node under the control of a pull-up node reset terminal. Description of the Drawings

[0051] Figure 1 is a schematic block diagram of a shift register unit according to an embodiment of the present disclosure;

[0052] Figure 2 is a circuit diagram of a shift register unit according to another embodiment of the present disclosure;

[0053] Figure 3 is a circuit diagram of a shift register unit according to another embodiment of the present disclosure;

[0054] Figure 4 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0055] Figure 5 is an operation timing diagram of a gate driving circuit according to an embodiment of the present disclosure;

[0056] Figure 6 is a flowchart of a control method for a shift register unit according to an embodiment of the present disclosure; and

[0057] Figure 7 is a flowchart of a control method for a gate driving circuit according to an embodiment of the present disclosure. Detailed Description of the Embodiments

[0058] Although the present disclosure will be fully described with reference to the accompanying drawings that contain preferred embodiments of the present disclosure, it should be understood before this description that those of ordinary skill in the art may modify the disclosure described herein while achieving the technical effects of the present disclosure. Therefore, it should be understood that the above description is a broad disclosure to those of ordinary skill in the art, and its content is not intended to limit the exemplary embodiments described in the present disclosure.

[0059] In addition, in the following detailed description, for the sake of explanation, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are illustrated in a schematic manner to simplify the drawings.

[0060] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings as understood by those skilled in the art. The "first", "second" and similar terms used in the embodiments of the present disclosure do not denote any order, quantity or importance, but are only used to distinguish different components.

[0061] Furthermore, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, these two components may be connected or coupled by wire or wirelessly.

[0062] All transistors employed in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Preferably, the thin film transistors used in the embodiments of the present disclosure may be oxide semiconductor transistors. Since the source and drain of the thin film transistors adopted herein are symmetric, their source and drain can be interchanged. In the embodiments of the present disclosure, one of the source and drain is referred to as the first pole, and the other of the source and drain is referred to as the second pole.

[0063] Figure 1 A schematic block diagram of a shift register unit according to an embodiment of the present disclosure is shown.

[0064] As Figure 1 shown, the shift register unit includes an input circuit 10, a pull-down control circuit 20, an output circuit 30, and a scan control circuit 40.

[0065] The input circuit 10 is connected to an input signal terminal IN, a first control signal terminal CLK_B, a first clock signal terminal CKB, and a pull-up node Q. The input circuit 10 can provide the potential of the input signal terminal IN to the pull-up node Q under the control of the first control signal terminal CLK_B and the first clock signal terminal CKB.

[0066] The pull - down control circuit 20 is connected to the pull - up node Q and the pull - down node QB, and is configured to control the potential of the pull - down node QB based on the potential of the pull - up node Q.

[0067] The output circuit 30 is connected to the pull - up node Q, the pull - down node QB, the power signal terminal VGH, the reference signal terminal VGL, and the output signal terminal OUT. The pull - down control circuit 20 can provide the potential of the power signal terminal VGH or the reference signal terminal VGL to the output signal terminal OUT under the control of the pull - up node Q and the pull - down node QB.

[0068] The scan control circuit 40 is connected to the input signal terminal IN, the first clock signal terminal CKB, the second control signal terminal CLK_A, and the scan control terminal RD. The scan control circuit 40 can store the potential of the input signal terminal IN under the control of the first clock signal terminal CKB and the scan control terminal RD, and control the potential of the pull - up node Q based on the stored potential under the control of the second control signal terminal CLK_A.

[0069] In an embodiment of the present disclosure, the signals of the scan control terminal RD and the first clock signal terminal CKB can be used to cause the scan control circuit 40 to pre - store the potential of the input signal terminal IN in advance, and when an output signal needs to be generated, the signal of the second control signal terminal CLK_A is used to cause the scan control circuit to control the potential of the pull - up node Q based on the stored potential, so that the output circuit generates an output signal. In this way, in addition to generating an output signal based on the signal of the input signal terminal, the shift register unit can also be controlled by the signal of a separate scan control terminal to generate an output signal, so that it is possible to flexibly select the shift register unit to be controlled among multiple shift register units of the gate driving circuit as needed to generate an output signal.

[0070] Figure 2 It is a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0071] As Figure 2 shown, the shift register unit includes an input circuit 210, a pull - down control circuit 220, an output circuit 230, and a scan control circuit 240. The above descriptions of the input circuit 10, the pull - down control circuit 20, the output circuit 30, and the scan control circuit 40 also apply to the input circuit 210, the pull - down control circuit 220, the output circuit 230, and the scan control circuit 240, and the present disclosure will not repeat them here.

[0072] According to an embodiment of the present disclosure, the scan control circuit 240 includes a first scan sub - circuit 241 and a second scan sub - circuit 242.

[0073] For example, the first scan control sub - circuit 241 is connected to the input signal terminal IN, the first clock signal terminal CKB, the scan control terminal RD, and the control node M of the second control circuit. The first scan control sub - circuit 241 can store the potential of the input signal terminal IN at the control node M under the control of the first clock signal terminal CKB and the scan control terminal RD. In some embodiments, as Figure 2 shown, the first scan control sub - circuit 241 may include at least one first transistor T1, a second transistor T2, and a first capacitor C1. As Figure 2 shown, in this embodiment, one first transistor T1 is taken as an example. The first transistor T1 is connected in series between the input signal terminal IN and the first pole of the second transistor T2. For example, the first pole of the first transistor T1 is connected to the input signal terminal IN, and the second pole is connected to the first pole of the second transistor T2. The gate of the first transistor T1 is connected to the scan control terminal RD. The gate of the second transistor T2 is connected to the first clock signal terminal CKB, and the second pole of the second transistor T2 is connected to the control node M. The first pole of the first capacitor C1 is connected to the control node M, and the second pole of the first capacitor C1 is connected to the reference signal terminal VGL.

[0074] For example, the second scan control sub - circuit 242 is connected to the second control signal terminal CLK_A, the control node M, the pull - up node Q, and the power supply signal terminal VGH. The second scan control sub - circuit 242 can supply the potential of the power supply signal terminal VGH to the pull - up node Q under the control of the second control signal terminal CLK_A and the potential of the control node M. In some embodiments, as Figure 2 shown, the second scan control sub - circuit 242 includes a third transistor T3 and at least one fourth transistor T4. The gate of the third transistor T3 is connected to the control node M, and the first pole of the third transistor T3 is connected to the power supply signal terminal VGH. Figure 2 Taking one fourth transistor T4 as an example, the fourth transistor T4 is connected in series between the second pole of the third transistor T3 and the pull - up node Q, and the gate of the fourth transistor T4 is connected to the second control signal terminal CLK_A.

[0075] According to an embodiment of the present disclosure, the pull - down control circuit 220 includes a first pull - down control sub - circuit 221 and a second pull - down control sub - circuit 222.

[0076] For example, the first pull - down control sub - circuit 221 is connected to the pull - up node Q and the pull - down node QB. The first pull - down control sub - circuit 221 can control the potential of the pull - down node QB based on the potential of the pull - up node Q. In some embodiments, as Figure 2 shown, the first pull - down control sub - circuit 221 may include at least one fifth transistor T5. Figure 2Taking a fifth transistor T5 as an example, the fifth transistor T5 is connected in series between the reference signal terminal VGL and the pull - down node QB, and the gate of the fifth transistor T5 is connected to the pull - up node QB.

[0077] For example, the second pull - down control sub - circuit 222 is connected to the input signal terminal IN, the first clock signal terminal CKB, the second clock signal terminal CK, and the pull - down node QB, and is configured to control the potential of the pull - down node QB based on the potentials of the input signal terminal IN, the first clock signal terminal CKB, and the second clock signal terminal CK. In some embodiments, as Figure 2 shown, the second pull - down control sub - circuit 220 includes a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a second capacitor C2. The gate of the sixth transistor T6 is connected to the second clock signal terminal CK. The gate of the sixth transistor T6 is connected to the second clock signal terminal, the first pole of the sixth transistor T6 is connected to the power supply signal terminal. The gate of the seventh transistor T7 is connected to the input signal terminal, the first pole of the seventh transistor T7 is connected to the second clock signal terminal, and the second pole of the seventh transistor T7 is connected to the second pole of the sixth transistor. The gate of the eighth transistor T8 is connected to the second pole of the sixth transistor, the first pole of the eighth transistor T8 is connected to the first clock signal terminal. The gate of the ninth transistor T9 is connected to the first clock signal terminal, the first pole of the ninth transistor T9 is connected to the second pole of the eighth transistor, and the second pole of the ninth transistor T9 is connected to the pull - down node. The first pole of the second capacitor C2 is connected to the gate of the eighth transistor, and the second pole of the second capacitor C2 is connected to the second pole of the eighth transistor.

[0078] According to an embodiment of the present disclosure, the shift register unit may further include a pull - up node reset circuit 250. The pull - up node reset circuit 250 is connected to the pull - up node reset terminal SC and the pull - up node Q. The pull - up node reset circuit 250 can reset the pull - up node Q under the control of the pull - up node reset terminal SC. For example, as Figure 2 shown, the pull - up node reset circuit 250 may include at least one tenth transistor T10. Figure 2 Taking a tenth transistor T10 as an example, the tenth transistor T10 is connected in series between the reference signal terminal VGL and the pull - up node Q, and the gate of the tenth transistor T10 is connected to the pull - up node reset terminal SC.

[0079] According to an embodiment of the present disclosure, the shift register unit may further include a control node reset circuit 260. The control node reset circuit 600 is connected to the control node reset terminal T_reset and the control node M. The control node reset circuit 600 can reset the control node M under the control of the control node reset terminal T_reset. For example, as Figure 2As shown, the control node reset circuit 260 may include at least one eleventh transistor T11. Figure 2 Taking one eleventh transistor T11 as an example, the eleventh transistor T11 is connected in series between the reference signal terminal VGL and the control node M, and the gate of the eleventh transistor T11 is connected to the control node reset terminal T_reset.

[0080] According to an embodiment of the present disclosure, the input circuit 210 may include a twelfth transistor T12 and at least one thirteenth transistor T13. The gate of the twelfth transistor T12 is connected to the first control signal terminal CLK_B, and the first pole of the twelfth transistor T12 is connected to the input signal terminal IN. The thirteenth transistor T13 is connected in series between the second pole of the twelfth transistor T12 and the pull-up node Q. Figure 2 Taking one thirteenth transistor T13 as an example, the first pole of the thirteenth transistor T13 is connected to the second pole of the twelfth transistor T2, the second pole of the thirteenth transistor T13 is connected to the pull-up node Q, and the gate of the thirteenth transistor T13 is connected to the first clock signal terminal CKB.

[0081] According to an embodiment of the present disclosure, the output circuit 230 includes a fourteenth transistor T14, a fifteenth transistor T15, a third capacitor C3, and a fourth capacitor C4. The gate of the fourteenth transistor T14 is connected to the pull-up node Q, the first pole of the fourteenth transistor T14 is connected to the power supply signal terminal VGH, and the second pole of the fourteenth transistor T14 is connected to the output signal terminal OUT. The gate of the fifteenth transistor T15 is connected to the pull-down node QB, the first pole of the fifteenth transistor T15 is connected to the reference signal terminal VGL, and the second pole of the fifteenth transistor T15 is connected to the output signal terminal OUT. The first pole of the third capacitor C3 is connected to the pull-up node Q, and the second pole is connected to the output signal terminal OUT. The first pole of the fourth capacitor C4 is connected to the pull-down node QB, and the second pole is connected to the reference signal terminal VGL.

[0082] Figure 3 is a circuit diagram of a shift register unit according to another embodiment of the present disclosure.

[0083] As Figure 3 shown, the shift register unit includes an input circuit 310, a pull-down control circuit 320, an output circuit 330, and a scan control circuit 340. The above descriptions of the input circuit 210, the pull-down control circuit 220, the output circuit 230, and the scan control circuit 240 are equally applicable to the input circuit 310, the pull-down control circuit 320, the output circuit 330, and the scan control circuit 340, and the present disclosure will not repeat them here. Figure 3 The shift register unit of Figure 2The shift register unit differs at least in that the number of at least one of the first transistor, the fourth transistor, the fifth transistor, the tenth transistor, the eleventh transistor, and the thirteenth transistor can be two. For the sake of clarity, the different parts will be mainly described in detail below.

[0084] As Figure 3 shown, different from the first scan control sub-circuit 241 shown in Figure 2 , the number of first transistors in the first scan control sub-circuit 341 is two, namely the first transistor T1_a and the first transistor T1_b. The first scan control sub-circuit 341 further includes a first voltage stabilizing transistor T_stab_1. For example, the first transistor T1_a and the first transistor T1_b are connected in series between the input signal terminal IN and the first pole of the second transistor T2. The gates of the first transistor T1_a and the first transistor T1_b are both connected to the scan control terminal RD. The first pole of one of the two first transistors, the first transistor T1_a, is connected to the second pole of the other first transistor T1_b at the first voltage stabilizing node. The gate of the first voltage stabilizing transistor T_stab_1 is connected to the control node M. The first pole of the first voltage stabilizing transistor T_stab_1 is connected to the power signal terminal VGH. The second pole of the first voltage stabilizing transistor T_stab_1 is connected to the first voltage stabilizing node.

[0085] According to an embodiment of the present disclosure, different from the first scan control sub-circuit 242 shown in Figure 2 , the number of fourth transistors in the second scan control sub-circuit 342 is two, namely the fourth transistor T4_a and the fourth transistor T4_b. The fourth transistor T4_a and the fourth transistor T4_b are connected in series between the second pole of the third transistor T3 and the pull-up node Q. The gates of the fourth transistor T4_a and the fourth transistor T4_b are both connected to the second control signal terminal CLK_A.

[0086] According to an embodiment of the present disclosure, different from the first pull-down control sub-circuit 221 shown in Figure 2 , the number of fifth transistors in the first pull-down control sub-circuit 321 is two, namely the fifth transistor T5_a and the fifth transistor T5_b. The fifth transistor T5_a and the fifth transistor T5_b are connected in series between the reference signal terminal VGL and the pull-down node QB. The gates of the fifth transistor T5_a and T5_b are connected to the pull-up node QB.

[0087] According to an embodiment of the present disclosure, different from the pull-up reset circuit 250 shown in Figure 2 , the pull-up node reset circuit 350 includes two tenth transistors, namely the tenth transistor T10_a and the tenth transistor T10_b. The pull-up node reset circuit 350 further includes a second voltage stabilizing transistor T_stab_2. AsFigure 3 As shown, the tenth transistor T10_a and the tenth transistor T10_b are connected in series between the reference signal terminal VGL and the pull-up node Q, and the gates of the tenth transistor T10_a and the tenth transistor T10_b are both connected to the pull-up node reset terminal SC1. The first pole of the tenth transistor T10_a is connected to the second pole of the tenth transistor T10_b at the second voltage stabilization node. The gate of the second voltage stabilization transistor T_stab_2 is connected to the pull-up node Q, the first pole of the second voltage stabilization transistor T_stab_2 is connected to the power supply signal terminal VGH, and the second pole of the second voltage stabilization transistor T_stab_2 is connected to the second voltage stabilization node.

[0088] According to an embodiment of the present disclosure, different from Figure 2 the control node reset circuit 260 shown, the number of the eleventh transistors in the control node reset circuit 360 is two, namely the eleventh transistor T11_a and the eleventh transistor T11_b. As Figure 3 shown, the eleventh transistor T11_a and the eleventh transistor T11_b are connected in series between the reference signal terminal VGL and the control node M, and the gates of the eleventh transistor T11_a and the eleventh transistor T11_b are both connected to the control node reset terminal T_reset, and the first pole of the eleventh transistor T11_a is connected to the second pole of the eleventh transistor T11_b at the first voltage stabilization node.

[0089] According to an embodiment of the present disclosure, different from Figure 2 the input circuit 210 shown, the number of the thirteenth transistors in the input circuit 310 is two, namely the thirteenth transistor T13_a and the thirteenth transistor T13_b. As Figure 3 shown, the thirteenth transistor T13_a and the thirteenth transistor T13_b are connected in series between the second pole of the twelfth transistor T12 and the pull-up node Q. The gates of the thirteenth transistor T13_a and the thirteenth transistor T13_b are both connected to the first clock signal terminal CKB.

[0090] Figure 4 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure.

[0091] As Figure 4 shown, the gate driving circuit includes N cascaded shift register units 410, 420, 430, and the shift register units 410, 420, 430 can be implemented by the shift register units of any of the above embodiments. Figure 4 For the sake of convenience of description, only 3 shift register units are shown herein. However, the embodiments of the present disclosure are not limited thereto, and the number N of the shift register units can be set as required.

[0092] According to an embodiment of the present disclosure, the output signal terminal of the (n - i)-th stage shift register unit is connected to the input signal terminal of the n-th stage shift register unit. N is an integer greater than 1, n is an integer and 1 < n ≤ N, and i is an integer greater than or equal to 1. For example, as Figure 4 shown, taking i = 1 as an example, the output signal terminal OUT of the first-stage shift register unit 410 is connected to the input signal terminal IN of the second-stage shift register unit 420; the output signal terminal OUT of the second-stage shift register unit 420 is connected to the input signal terminal IN of the third-stage shift register unit 430, and so on.

[0093] According to an embodiment of the present disclosure, the first control signal terminal CLK_B and the second control signal terminal CLK_A of each stage shift register unit are respectively connected to receive the first control signal clk_b and the second control signal clk_a, and the scan control terminal RD is connected to receive the scan control signal rd.

[0094] According to an embodiment of the present disclosure, the first clock signal terminal CKB of the odd-stage shift register unit is connected to receive the first clock signal ckb, the second clock signal terminal CK is connected to receive the second clock signal ck, and the pull-up node reset terminal SC is connected to receive the first pull-up node reset signal sc1. The first clock signal terminal CKB of the even-stage shift register unit is connected to receive the second clock signal ck, the second clock signal terminal CK is connected to receive the first clock signal ckb, and the pull-up node reset terminal SC is connected to receive the second pull-up node reset signal sc2.

[0095] For example, in Figure 4 , the first control signal terminal CLK_B and the second control signal terminal CLK_A of the first-stage shift register unit 410 are respectively connected to receive the first control signal clk_b and the second control signal clk_a, the scan control terminal RD is connected to receive the scan control signal rd, the first clock signal terminal CKB is connected to receive the first clock signal ckb, the second clock signal terminal CK is connected to receive the second clock signal ck, and the pull-up node reset terminal is connected to receive the first pull-up node reset signal sc1. The input signal terminal IN of the first-stage shift register unit 410 is connected to receive the start signal stu. The first control signal terminal CLK_B and the second control signal terminal CLK_A of the second-stage shift register unit 420 are respectively connected to receive the first control signal clk_b and the second control signal clk_a, the scan control terminal RD is connected to receive the scan control signal rd, the first clock signal terminal CKB is connected to receive the first clock signal ck, the second clock signal terminal CK is connected to receive the second clock signal ckb, and the pull-up node reset terminal is connected to receive the second pull-up node reset signal sc2. The input signal terminal IN of the second-stage shift register unit 420 is connected to receive the output signal provided by the first-stage shift register unit 410.

[0096] The first control signal terminal CLK_B and the second control signal terminal CLK_A of the third-stage shift register unit 430 are respectively connected to receive the first control signal clk_b and the second control signal clk_a, the scan control terminal RD is connected to receive the scan control signal rd, the first clock signal terminal CKB is connected to receive the first clock signal ckb, the second clock signal terminal CK is connected to receive the second clock signal ck, and the pull-up node reset terminal is connected to receive the first pull-up node reset signal sc1. The input signal terminal IN of the third-stage shift register unit 430 is connected to receive the output signal provided by the second-stage shift register unit 420.

[0097] Figure 5 It is the operation timing diagram of the gate driving circuit according to the embodiment of the present disclosure.

[0098] As Figure 5 shown, in this embodiment, 11 cascaded shift register units are taken as an example for illustration, however, the embodiments of the present disclosure are not limited thereto. The operation timing of Figure 2 will be described below in combination with the shift register unit and Figure 4 the gate driving circuit of Figure 5

[0099] In the starting frame, the first control signal clk_b is at a high level and the second control signal clk_a is at a low level, causing the first control signal terminal CLK_B of the first-stage shift register unit to maintain a high level and the twelfth transistor T12 of the input circuit to conduct. In response to the high-level first clock signal ckb received at the first clock signal terminal CKB, the thirteenth transistor T13 of the input circuit conducts, thereby providing the potential of the start signal stu received at the input signal terminal IN to the pull-up node Q, making the pull-up node Q at a high level. The high level of the pull-up node Q causes the fifth transistor T5 of the first pull-down node control sub-circuit to conduct, providing the potential of the reference signal terminal VGL to the pull-down node QB and pulling down the potential of the pull-down node QB, making the pull-down node QB at a low level. In addition, with the high level of the pull-up node Q, the fourteenth transistor T14 of the output circuit conducts, providing the potential of the power supply signal terminal VGH to the output signal terminal OUT, thereby generating a high-level output signal G1 by the first-stage shift register unit. During this period, since the start signal stu received at the input signal terminal IN is at a high level, the second pull-down control sub-circuit 222 keeps the pull-down node QB at a low level all the time. For example, since the first clock signal ckb is at a high level and the second clock signal ck is at a low level, the sixth transistor T6 is turned off, and the high level of the input signal terminal IN causes the seventh transistor T7 to conduct, thereby providing the low level of the second clock signal terminal CK to the node QB. Therefore, although the high level of the second clock signal terminal CKB causes the ninth transistor T9 to conduct, the low level of the node QB causes the eighth transistor T8 to turn off, and the pull-down node QB still remains at a low level. After that, the start signal stu becomes low, the first clock signal ckb becomes low, the second clock signal ck becomes high, the transistor T6 conducts, providing the high level of the power supply signal terminal VGH to the node QP, making the eighth transistor T8 conduct, thereby providing the high level of the first clock signal terminal CKB to the first pole of the ninth transistor T9. The ninth transistor T9 conducts due to the high level of the first clock signal terminal CKB, thereby providing the high level of the first pole to the pull-down node QB. The high level of the pull-down node QB causes the fifteenth transistor T15 to conduct, and thus the output signal G1 of the output signal terminal OUT becomes low, completing the signal output of the first-stage shift register unit.

[0100] The output signal G1 provided by the output signal terminal OUT of the first-stage shift register unit is provided to the input signal terminal IN of the second-stage shift register unit, causing the second-stage to the eleventh-stage shift register units to work in a similar manner, thereby generating sequentially shifted output signals G2 to G11, thus completing the scanning of the starting frame.

[0101] During the scanning of the starting frame, as Figure 5As shown, during the period when the scan control signal rd is at a high level, the first clock signal ckb is at a high level, the second clock signal ck is at a high level, and the output signals G6 and G7 generated by the sixth-stage shift register unit and the seventh-stage shift register unit are at a high level. The scan control signal rd received by the scan control terminals RD of the sixth and seventh-stage shift register units being at a high level causes the first transistors T1 of the two to conduct. Since the first clock signal ckb is at a high level, the first clock signal terminal CKB of the seventh-stage shift register unit is at a high level, causing the second transistor T2 of the seventh-stage shift register unit to conduct, and providing the potential of its input signal terminal IN (i.e., the high level of the output signal G6) to the control node M. The presence of the first capacitor C1 causes this high level to be stored at the control node M. Since the second clock signal ck received by the first clock signal terminal CKB of the eighth-stage shift register unit is at a low level, although the input signal terminal IN of the eighth-stage shift register unit receives a high-level input signal (the output signal G7 of the seventh-stage shift register unit), the low level of the first clock signal terminal CKB of the eighth-stage shift register unit causes the second transistor T2 to turn off, and the high level of its input signal terminal IN cannot be stored at the node M.

[0102] Next, within the second frame, the first control signal CLK_B and the second control signal CLK_A are inverted, that is, the first control signal CLK_B becomes low level, and the second control signal CLK_A becomes high level, which causes the fourth transistors T4 of each stage shift register unit to conduct and the twelfth transistors T12 to turn off. Since only the seventh-stage shift register unit stores a high level at the control node M in the starting frame among each stage shift register unit, the conduction of the fourth transistor T4 of the seventh-stage shift register unit G7 causes the high level stored at the control node M to be provided to the pull-up node Q. The high level of the pull-up node Q causes the fifth transistor T5 to conduct, and the potential of the reference signal terminal VGL is provided to the pull-down node QB. The high level of the pull-up node Q also causes the fourteenth transistor T14 to conduct, and the potential of the power supply signal terminal VGH is provided to the output signal terminal OUT, causing the seventh-stage shift register unit to generate a high-level output signal G7. The eighth-stage to the last stage (the eleventh stage in this embodiment) shift register units are cascaded and generate sequentially shifted output signals G8 to G11 in the above manner.

[0103] After the output signal G11 is generated by the last-stage (the 11th stage in this embodiment) shift register unit, the start signal stu is at a high level to enable the first-stage shift register unit to generate the output signal G1. The output signal G1 is provided to the input signal terminal IN of the second-stage shift register unit G2, causing the second-stage shift register unit to generate an output signal G2 that is shifted relative to the output signal G1, and so on, causing the first to sixth-stage shift register units to generate sequentially shifted output signals G1 to G6, thereby completing the scanning of the second frame. From Figure 5 It can be seen that in the second frame, the seventh to eleventh-stage shift register units first sequentially generate output signals G7 to G11, and then the first to sixth-stage shift register units sequentially generate output signals G1 to G6, thereby realizing the selection of any row as the starting row for scanning using the scan control signal rd, and starting to scan other rows from the first row after scanning to the last row.

[0104] During the scanning of the second frame, the control node reset signal t_reset is also used to reset the control node M of each stage shift register unit. As Figure 5 shown, before the output signal G8 is generated by the eighth-stage shift register unit, the second control signal clk_a returns to a low level and the first control signal clk_b returns to a high level, so as to turn off the fourth transistor T4 and turn on the twelfth transistor T12 of each stage shift register unit, thereby not affecting the normal output of the eighth to eleventh-stage shift register units. After the second control signal clk_a returns to a low level and the first control signal clk_b returns to a high level, the control node reset signal t_reset is at a high level, thereby turning on the eleventh transistor T11 of each stage shift register unit, providing the potential of the reference signal terminal VGL to the control node M, and resetting the control node M.

[0105] During the scanning of the second frame, the first pull-up node reset signal sc1 is also used to reset the pull-up node Q of each stage shift register unit. As Figure 5 shown, after the output signal G6 is generated by the sixth-stage shift register unit, the first pull-up node reset signal sc1 is at a high level and the first control signal terminal clk_b is at a low level, causing the tenth transistor T10 of each odd-stage shift register unit to turn on and the twelfth transistor T12 to turn off, providing the potential of the reference signal terminal VGL to the pull-up node Q, and resetting the pull-up node Q. Therefore, although the input signal received by the seventh-stage shift register unit (i.e., the output signal G6 of the sixth-stage shift register unit) is at a high level, the reset of its pull-up node and the turn-off of the twelfth transistor T12 cause the output signal G7 generated by the seventh-stage shift register unit to be at a low level. Correspondingly, the output signals G8 to G11 of the cascaded eighth to eleventh-stage shift register units are also all at a low level.

[0106] In the process of generating output signals G1 to G11 in each stage of the shift register unit in the second frame, in a similar manner, the high level of the scan control signal rd causes the tenth-stage shift register unit to store a high level at the control node M.

[0107] Next, in the third frame, in a similar manner, the tenth-stage shift register unit generates a high-level output signal G10 in response to the inversion of the first control signal clk_a and the second control signal clk_b because a high level is pre-stored at the control node M, and further causes the tenth to eleventh-stage shift register units to generate sequentially shifted output signals G10 and G11.

[0108] After the last-stage (eleventh-stage) shift register unit generates the output signal G11, in a similar manner, the start signal stu is used to cause the first to ninth-stage shift register units to generate sequentially shifted output signals G1 to G9. Figure 5 It can be seen that in the third frame, it is realized that the scanning first goes from the tenth row to the last row (eleventh row), and then from the first row to the ninth row.

[0109] In some embodiments, in each frame, the pulse width of a group of later-generated output signals can be made adjustable by setting the pulse width of the start signal stu. For example, in the second frame, the pulse widths of the output signals G1 to G6 can be made different from the pulse widths of the output signals G7 to G11 by setting the pulse width of the start signal stu. For example, the output signals G7 to G11 can have a first pulse width, and the output signals G1 to G6 can have a second pulse width. In some embodiments, the second pulse width can be greater than the first pulse width, so that the pulse widths of the gate driving signals received by the pixels in the seventh to eleventh rows are greater than the pulse widths of the gate driving signals received by the pixels in the first to sixth rows, and further can cooperate with the source driving circuit to enable the sub-pixels in different regions of the display panel to be displayed at different frequencies. For example, in eye tracking, after determining the eye fixation area in the display panel, assuming that the starting row of the eye fixation area is the seventh-row sub-pixels, then the gate driving circuit can generate output signals G7 to G11 with the first pulse width in the above manner, so that the seventh to eleventh-row sub-pixels are turned on in sequence; then generate output signals G1 to G6 with the second pulse width, so that the first to sixth-row sub-pixels are turned on in sequence. Since the second pulse width is greater than the first pulse width, it can cooperate with the source driving circuit to make the display frequency of the eye fixation area higher than that of other regions. In the time period corresponding to the third frame, in a similar manner, the pulse widths of the output signals G1 to G9 of the first to ninth-stage shift register units can be made different from the pulse widths of the output signals G10 and G11 of the tenth and eleventh-stage shift register units, so as to realize the display of different regions of the display panel at different frequencies.

[0110] Figure 6 It is a flowchart of a control method for a shift register unit according to an embodiment of the present disclosure.

[0111] As Figure 6 shown, the method 600 may include operation S610 and operation S620.

[0112] In operation S610, in the first mode, the scan control circuit stores the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal, and the stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal.

[0113] In operation S620, in the second mode, the input circuit provides the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal.

[0114] For example, taking the Figure 2 shown shift register unit as an example, in the first mode, the scan control circuit 240 stores the potential of the input signal terminal IN under the control of the first clock signal terminal CKB and the scan control terminal RD. The stored potential causes the scan control circuit 240 to pull up the potential of the pull-up node Q under the control of the second control signal terminal CLK_A. The potential of the pull-up node Q causes the pull-down node control circuit 220 to pull down the potential of the pull-down node QB and causes the output circuit 240 to provide the potential of the power signal terminal VGH to the output signal terminal OUT.

[0115] For example, taking the Figure 2 shown shift register unit as an example, in the second mode, the input circuit 210 provides the potential of the input signal terminal IN to the pull-up node Q under the control of the first control signal terminal CLK_B and the first clock signal terminal CKB. The potential of the pull-up node Q causes the pull-down node control circuit 220 to pull down the potential of the pull-down node QB and causes the output circuit 240 to provide the potential of the power signal terminal VGH to the output signal terminal OUT.

[0116] According to an embodiment of the present disclosure, after the output circuit provides the potential of the power signal terminal VGH to the output signal terminal OUT, the pull-up node reset circuit may reset the pull-up node Q under the control of the pull-up node reset terminal SC. For example, takingFigure 2 Taking the shift register unit shown as an example, after the output circuit 240 provides the potential of the power signal terminal VGH to the output signal terminal OUT, the pull-up node reset circuit 250 resets the pull-up node Q under the control of the pull-up node reset terminal SC.

[0117] Figure 7 It is a flowchart of a control method for a gate driving circuit according to an embodiment of the present disclosure.

[0118] As Figure 7 shown, method 700 may include operation S710 and operation S720.

[0119] In operation S710, in a first period, the k-th stage shift register unit is controlled to operate in a first mode, and the (k + 1)-th to N-th stage shift register units are controlled to operate in a second mode, so that the k-th to N-th stage shift register units generate sequentially shifted output signals with a first pulse width.

[0120] In operation S720, in a second period, the 1st to (k - 1)-th stage shift register units are controlled to operate in a second mode, so that the 1st to (k - 1)-th stage shift register units generate sequentially shifted output signals with a second pulse width.

[0121] According to an embodiment of the present disclosure, k is an integer and 1 < k ≤ N.

[0122] According to an embodiment of the present disclosure, in the shift register unit operating in the first mode, the scan control circuit stores the potential of the input signal terminal IN under the control of the first clock signal terminal CKB and the scan control terminal RD, and the stored potential causes the scan control circuit to pull up the potential of the pull-up node Q under the control of the second control signal terminal CLK_A. The potential of the pull-up node Q causes the pull-down node control circuit to pull down the potential of the pull-down node QB and causes the output circuit to provide the potential of the power signal terminal VGH to the output signal terminal OUT.

[0123] According to an embodiment of the present disclosure, in the shift register unit operating in the second mode, the input circuit provides the potential of the input signal terminal IN to the pull-up node Q under the control of the first control signal terminal CLK_B and the first clock signal terminal CKB. The potential of the pull-up node Q causes the pull-down node control circuit to pull down the potential of the pull-down node QB and causes the output circuit to provide the potential of the power signal terminal VGH to the output signal terminal OUT.

[0124] For example, as described above with reference to Figure 5 described, in order for the gate driving circuit to generate in the second frame as Figure 5The output signal shown controls the seventh-stage shift register unit to operate in the first mode to generate the output signal G7 in the first time period (including the first frame described above and the time period before the output signal G1 is generated in the second frame), and the other shift register units operate in the second mode to generate the output signals G8 to G11; in the second time period (the time period after the output signal G1 is generated in the second frame), it controls the first to sixth-stage shift register units to operate in the second mode to generate the output signals G1 to G6.

[0125] Those skilled in the art can understand that the embodiments described above are all exemplary, and those skilled in the art can make improvements to them. The structures described in various embodiments can be freely combined without conflicts in structure or principle.

[0126] After the preferred embodiments of the present disclosure are described in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the protection scope and spirit of the appended claims, and the present disclosure is not limited to the implementation manners of the exemplary embodiments described in the specification.

Claims

1. A shift register unit, comprising: an input circuit, connected to an input signal terminal, a first control signal terminal, a first clock signal terminal, and a pull-up node, for providing the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal; a pull-down control circuit, connected to the pull-up node and a pull-down node, for controlling the potential of the pull-down node based on the potential of the pull-up node; an output circuit, connected to the pull-up node, the pull-down node, a power supply signal terminal, a reference signal terminal, and an output signal terminal, for providing the potential of the power supply signal terminal or the reference signal terminal to the output signal terminal under the control of the pull-up node and the pull-down node; a scan control circuit, connected to the input signal terminal, the first clock signal terminal, a second control signal terminal, and a scan control terminal, for storing the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal, and for controlling the potential of the pull-up node based on the stored potential under the control of the second control signal terminal; wherein, the scan control circuit includes a first scan control sub-circuit, connected to the input signal terminal, the first clock signal terminal, the scan control terminal, and a control node, for storing the potential of the input signal terminal at the control node under the control of the first clock signal terminal and the scan control terminal.

2. The shift register unit according to claim 1, wherein, the scan control circuit further includes: a second scan control sub-circuit, connected to the second control signal terminal, the control node, the pull-up node, and the power supply signal terminal, for providing the potential of the power supply signal terminal to the pull-up node under the control of the second control signal terminal and the potential of the control node.

3. The shift register unit according to claim 1, wherein, the pull-down control circuit includes: a first pull-down control sub-circuit, connected to the pull-up node and the pull-down node, for controlling the potential of the pull-down node based on the potential of the pull-up node; and a second pull-down control sub-circuit, connected to the input signal terminal, the first clock signal terminal, a second clock signal terminal, and the pull-down node, for controlling the potential of the pull-down node based on the potentials of the input signal terminal, the first clock signal terminal, and the second clock signal terminal.

4. The shift register unit according to claim 1, further comprising a pull-up node reset circuit, connected to a pull-up node reset terminal and the pull-up node, for resetting the pull-up node under the control of the pull-up node reset terminal.

5. The shift register unit according to claim 2, further comprising a control node reset circuit, connected to a control node reset terminal and the control node, for resetting the control node under the control of the control node reset terminal.

6. The shift register unit according to claim 2, wherein, the first scan control sub-circuit includes at least one first transistor, a second transistor, and a first capacitor, wherein, The at least one first transistor is connected in series between the input signal terminal and the first pole of the second transistor, and the gate of the first transistor is connected to the scan control terminal; The gate of the second transistor is connected to the first clock signal terminal, and the second pole of the second transistor is connected to the control node; The first pole of the first capacitor is connected to the control node, and the second pole of the first capacitor is connected to the reference signal terminal.

7. The shift register unit according to claim 6, wherein, The number of the first transistors is two, and the first scan control sub-circuit further includes a first voltage stabilizing transistor, wherein, The two first transistors are connected in series between the input signal terminal and the first pole of the second transistor, the gates of the two first transistors are connected to the scan control terminal, and the first pole of one of the two first transistors and the second pole of the other first transistor are connected to a first voltage stabilizing node; The gate of the first voltage stabilizing transistor is connected to the control node, the first pole of the first voltage stabilizing transistor is connected to the power supply signal terminal, and the second pole of the first voltage stabilizing transistor is connected to the first voltage stabilizing node.

8. The shift register unit according to claim 2, wherein, The second scan control sub-circuit includes a third transistor and at least one fourth transistor; The gate of the third transistor is connected to the control node, and the first pole of the third transistor is connected to the power supply signal terminal; The at least one fourth transistor is connected in series between the second pole of the third transistor and the pull-up node, and the gate of the fourth transistor is connected to the second control signal terminal.

9. The shift register unit according to claim 3, wherein, The first pull-down control sub-circuit includes: at least one fifth transistor, the at least one fifth transistor is connected in series between the reference signal terminal and the pull-down node, and the gate of the at least one fifth transistor is connected to the pull-up node.

10. The shift register unit according to claim 3, wherein, The second pull-down control sub-circuit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a second capacitor, wherein, The gate of the sixth transistor is connected to the second clock signal terminal, and the first pole of the sixth transistor is connected to the power supply signal terminal; The gate of the seventh transistor is connected to the input signal terminal, the first pole of the seventh transistor is connected to the second clock signal terminal, and the second pole of the seventh transistor is connected to the second pole of the sixth transistor; The gate of the eighth transistor is connected to the second pole of the sixth transistor, and the first pole of the eighth transistor is connected to the first clock signal terminal; The gate of the ninth transistor is connected to the first clock signal terminal, the first pole of the ninth transistor is connected to the second pole of the eighth transistor, and the second pole of the ninth transistor is connected to the pull-down node; The first pole of the second capacitor is connected to the gate of the eighth transistor, and the second pole of the second capacitor is connected to the second pole of the eighth transistor.

11. The shift register unit according to claim 4, wherein, The pull-up node reset circuit includes at least one tenth transistor, and the at least one tenth transistor is serially connected between the reference signal terminal and the pull-up node, and the gate of the at least one tenth transistor is connected to the pull-up node reset terminal.

12. The shift register unit according to claim 11, wherein, the number of the tenth transistors is two, and the pull-up node reset circuit further includes a second voltage stabilizing transistor, wherein, the two tenth transistors are serially connected between the reference signal terminal and the pull-up node, the gates of the two tenth transistors are connected to the pull-up node reset terminal, and the first pole of one of the two tenth transistors is connected to the second pole of the other tenth transistor at a second voltage stabilizing node, the gate of the second voltage stabilizing transistor is connected to the pull-up node, the first pole of the second voltage stabilizing transistor is connected to the power signal terminal, and the second pole of the second voltage stabilizing transistor is connected to the second voltage stabilizing node.

13. The shift register unit according to claim 5, wherein, the control node reset circuit includes at least one eleventh transistor, and the at least one eleventh transistor is serially connected between the reference signal terminal and the control node, and the gate of the at least one eleventh transistor is connected to the control node reset terminal.

14. The shift register unit according to any one of claims 1 to 13, wherein, the input circuit includes a twelfth transistor and at least one thirteenth transistor, the gate of the twelfth transistor is connected to the first control signal terminal, the first pole of the twelfth transistor is connected to the input signal terminal, the at least one thirteenth transistor is serially connected between the second pole of the twelfth transistor and the pull-up node, and the gate of the at least one thirteenth transistor is connected to the first clock signal terminal.

15. A gate driving circuit includes N cascaded shift register units, and the shift register unit is the shift register unit according to any one of claims 1 to 14, wherein, the output signal terminal of the (n - i)-th stage shift register unit is connected to the input signal terminal of the n-th stage shift register unit, where N is an integer greater than 1, n is an integer and 1 < n ≤ N, and i is an integer greater than or equal to 1.

16. The gate driving circuit according to claim 15, wherein, i = 1, the first control signal terminal and the second control signal terminal of each stage of shift register unit are respectively connected to receive a first control signal and a second control signal, and the scan control terminal is connected to receive a scan control signal; the first clock signal terminal of the odd-stage shift register units is connected to receive a first clock signal, the second clock signal terminal is connected to receive a second clock signal, and the pull-up node reset terminal is connected to receive a first pull-up node reset signal, the first clock signal terminal of the even-stage shift register units is connected to receive a second clock signal, the second clock signal terminal is connected to receive a first clock signal, and the pull-up node reset terminal is connected to receive a second pull-up node reset signal.

17. A control method for a shift register unit according to any one of claims 1 to 14, including: In the first mode, the scan control circuit stores the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal, and the stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal; In the second mode, the input circuit provides the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal.

18. The method according to claim 17, further comprising: After the output circuit provides the potential of the power signal terminal to the output signal terminal, the pull-up node reset circuit resets the pull-up node under the control of the pull-up node reset terminal.

19. The method according to claim 17, further comprising: After the stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal, the control node reset circuit resets the control node under the control of the control node reset terminal.

20. A control method for a gate driving circuit according to any one of claims 15 to 16, comprising: In a first time period, controlling the k-th stage shift register unit to operate in the first mode, and controlling the (k + 1)-th to N-th stage shift register units to operate in the second mode, so that the k-th to N-th stage shift register units generate sequentially shifted output signals with a first pulse width, where k is an integer and 1 < k ≤ N; In a second time period, controlling the first to (k - 1)-th stage shift register units to operate in the second mode, so that the first to (k - 1)-th stage shift register units generate sequentially shifted output signals with a second pulse width, wherein, In the shift register unit operating in the first mode, the scan control circuit stores the potential of the input signal terminal under the control of the first clock signal terminal and the scan control terminal. The stored potential causes the scan control circuit to pull up the potential of the pull-up node under the control of the second control signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal; In the shift register unit operating in the second mode, the input circuit provides the potential of the input signal terminal to the pull-up node under the control of the first control signal terminal and the first clock signal terminal. The potential of the pull-up node causes the pull-down node control circuit to pull down the potential of the pull-down node and causes the output circuit to provide the potential of the power signal terminal to the output signal terminal.

21. The method according to claim 20, further comprising: In the second time period, after the output signal is generated by the (k - 1)-th stage shift register unit, one of the first pull-up node reset signal and the second pull-up node reset signal is used to control the pull-up node reset circuit of the k-th stage shift register unit to reset the pull-up node under the control of the pull-up node reset terminal.

Images