Semiconductor structure and preparation method thereof

Abstract

The present invention relates to a semiconductor manufacturing method, comprising: providing a substrate; forming a well region on the substrate, forming a first doped region within the well region, and forming a second doped region on the surface of the first doped region; etching the substrate where the second doped region is located to form a lead-out region trench and a window trench; forming a polycrystalline material layer on the sidewalls and bottom wall of the lead-out region trench and the sidewalls of the window trench, the polycrystalline material layer filling the lead-out region trench to form a lead-out structure; etching the polycrystalline material layer on the sidewalls of the window trench to a specified depth to form a gate polycrystalline. The polycrystalline material layer is only formed on the sidewalls of the window trench, and there is no need to remove the polycrystalline material layer in the center after completely filling the window trench. In the present application, the polycrystalline material layer in the window trench is already consistent with the thickness of the gate polycrystalline at the beginning of its formation. The etching of the polycrystalline material layer changes the height of the polycrystalline material layer, which completely solves the problem of etching back the polycrystalline material layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] For high-voltage VDMOS transistors, the drain is located on the semiconductor surface. A small, deep trench is needed to lead the source from the semiconductor bottom. The lead-out polysilicon must be formed on the sidewalls of the device trench. To form the lead-out polysilicon, the device trench must first be filled with polycrystalline, and then the polycrystalline on the sidewalls must be etched back. This makes it difficult to achieve a good polysilicon fill while simultaneously achieving highly conductive polysilicon. This is because, in typical polysilicon trench filling processes, due to the characteristics of the furnace tube, the lower the furnace tube temperature, the better the polysilicon fill, but the polysilicon resistance is significantly increased. Higher furnace tube temperatures facilitate polysilicon doping to achieve low-resistance polysilicon, but the polysilicon fill is poor, which can affect the device's electrical performance.

[0003] In addition, since gaps are generated when the polycrystalline fills the trench, when the polycrystalline on the sidewall is etched back, the etching gas will penetrate into the gap and preferentially etch the bottom of the gap, which causes the etched polysilicon to be V-shaped. This phenomenon is more obvious when the trench size is larger. In addition, if the etching depth of the polysilicon does not reach the bottom of the gap, the gap will still exist in the polysilicon after the etching is completed, and the gap will be magnified during the etching process, which will affect the subsequent process of forming the sidewall polysilicon. There may be a situation where the polysilicon thickness is insufficient, or there may be residual oxide in the gap in the subsequent process flow, resulting in the polysilicon below the gap being difficult to etch during the subsequent etching back of the polysilicon, resulting in polysilicon residue. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the above technical problems, which has the advantage of not causing gaps due to the inability of polysilicon in the growth trench to be completely closed to affect the subsequent process progress.

[0005] A semiconductor manufacturing method comprising:

[0006] providing a substrate;

[0007] forming a well region in the substrate, and forming at least a first doped region on an upper surface layer of the well region, wherein the well region and the first doped region have different conductivity types;

[0008] Etching the substrate to form a lead-out region trench and a window trench extending from the substrate surface through the first doped region and into the well region, wherein the lead-out region trench and the window trench are connected, and forming a gate oxide layer on the sidewalls and bottom wall of the lead-out region trench and the sidewalls and bottom wall of the window trench;

[0009] Filling the lead-out region trench with a polycrystalline material layer to form a lead-out structure, and forming a polycrystalline material layer on the sidewall of the window trench, wherein the polycrystalline material layer in the lead-out region trench is electrically connected to the polycrystalline material layer on the sidewall of the window trench;

[0010] The polycrystalline material layer on the sidewall of the window trench is etched back to a specified depth to form a gate polycrystalline.

[0011] In one embodiment, the following relationship is satisfied:

[0012] b<2a<(c+d);

[0013] Wherein, a is the thickness of the polycrystalline material layer on the sidewall of the window trench;

[0014] b is the width of the lead-out groove;

[0015] c is the width of the window groove;

[0016] d is a constant, and the value of d includes 0.2um~0.4um.

[0017] In one embodiment, the first doping region includes at least two concentration gradient doping regions, and the doping concentration of the first doping region decreases from high to low along the direction from the substrate surface to the well region.

[0018] In one embodiment, the width of the lead-out region groove is 0.3-7 um, and the depth is 2-5 um; the width of the window groove is 0.8-1.4 um, and the depth is 2-5 um.

[0019] In one embodiment, the step of filling the lead-out region trench with a polycrystalline material layer to form a lead-out structure, and forming a polycrystalline material layer on the sidewall of the window trench, wherein the polycrystalline material layer in the lead-out region trench is electrically connected to the polycrystalline material layer on the sidewall of the window trench, comprises:

[0020] Growing the polycrystalline material layer on the surface of the substrate, in the lead-out region trench, on the sidewalls of the window trench and on the bottom wall of the window trench, wherein the polycrystalline silicon layer completely fills the lead-out region trench;

[0021] The polycrystalline material layer on the substrate surface and the bottom wall of the window trench is removed by etching.

[0022] In one embodiment, the lead-out region trench is filled with a polycrystalline material layer to form a lead-out structure, and a polycrystalline material layer is formed on the sidewall of the window trench. After the polycrystalline material layer in the lead-out region trench is electrically connected to the polycrystalline material layer on the sidewall of the window trench,

[0023] Before etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline, the method further includes:

[0024] A second doping region is formed on the upper surface of the first doping region, and a third doping region is formed at the bottom of the window trench. The second doping region and the third doping region have the same conductivity type as the first doping region.

[0025] In one embodiment, the forming of a well region in the substrate, forming at least a first doped region on an upper surface layer of the well region, wherein the well region and the first doped region have different conductivity types, further comprises:

[0026] A second doping region is formed on the upper surface of the first doping region, wherein the second doping region has the same conductivity type as the first doping region.

[0027] The lead-out region groove is filled with a polycrystalline material layer to form a lead-out structure, and a polycrystalline material layer is formed on the sidewall of the window groove. After the polycrystalline material layer in the lead-out region groove is electrically connected to the polycrystalline material layer on the sidewall of the window groove,

[0028] Before etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline, the method further includes:

[0029] A third doping region is formed at the bottom of the window trench, and the third doping region has the same conductivity type as the first doping region.

[0030] In one embodiment, etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline includes:

[0031] Filling a first filling dielectric layer between the polycrystalline material layers on both side walls of the window trench;

[0032] forming a pattern mask layer on the surface of the substrate, wherein the opening of the pattern mask layer exposes the window groove;

[0033] The polycrystalline material layer on the sidewall of the window trench is etched back based on the pattern mask layer and the filling dielectric layer to form a gate polycrystalline.

[0034] In an optional implementation, after etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline, the method further includes:

[0035] Filling a second filling dielectric layer between the first filling dielectric layer and the sidewall of the window trench, wherein a cavity exists inside the second filling dielectric layer;

[0036] An interlayer dielectric layer is deposited on the upper surface of the substrate.

[0037] In one embodiment, the depths of the lead-out region trench and the window trench are 0.1 um to 0.3 um deeper than the implantation depth of the first doped region.

[0038] The present application also provides a semiconductor structure, comprising:

[0039] substrate;

[0040] a well region, the well region being located in the substrate, the upper surface layer of the first well region comprising at least a first doped region, and the well region and the first doped region having a different conductivity type;

[0041] A lead-out region trench and a window trench, extending from the substrate surface through the first doped region and into the well region, the lead-out region trench and the window trench being in communication, and a gate oxide layer being formed on the sidewalls and bottom wall of the lead-out region trench and the sidewalls and bottom wall of the window trench;

[0042] A lead-out structure formed by a polycrystalline material layer filling the lead-out region groove;

[0043] The gate polysilicon is formed by a polycrystalline material layer located on the sidewall of the window trench, and the height of the gate polysilicon is smaller than the depth of the window trench.

[0044] In one embodiment, the semiconductor structure further includes a second doped region located on an upper surface layer of the first doped region;

[0045] an intermediate dielectric layer, located in the window trench and filling the window trench, wherein a cavity exists inside the intermediate dielectric layer;

[0046] The third doping region is located in the substrate at the bottom of the window trench.

[0047] In one embodiment, the following relationship is satisfied:

[0048] b<2a<(c+d);

[0049] Wherein, a is the thickness of the polycrystalline material layer on the sidewall of the window trench;

[0050] b is the width of the lead-out groove;

[0051] c is the width of the window groove;

[0052] d is a constant, and the value of d includes 0.2um~0.4um.

[0053] In one embodiment, the first doping region includes at least two concentration gradient doping regions, and the doping concentration of the first doping region decreases from high to low along the direction from the substrate surface to the well region.

[0054] Through the above technical solution, the polycrystalline material layer is only formed on the side walls of the window groove, and there is no need to remove the polycrystalline material layer in the center after the window groove is completely filled. In this application, the polycrystalline material layer in the window groove is consistent with the thickness of the finally formed gate polycrystalline at the beginning of its formation. The etching of the polycrystalline material layer changes the height of the polycrystalline material layer, which completely solves the problem of etching back the polycrystalline material layer, so that the height of the gate polycrystalline can be controlled and is not affected by the process window. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 is a flow chart of a method for preparing a semiconductor device in one embodiment of the present invention;

[0056] Figure 2 A schematic diagram of a cross-sectional structure of a semiconductor device after forming a second doped region in one embodiment of the present invention;

[0057] Figure 3 A schematic diagram of a cross-sectional structure of a semiconductor device after forming a window trench in one embodiment of the present invention;

[0058] Figure 4 A schematic diagram of the cross-sectional structure of a semiconductor device after a gate oxide layer is formed in one embodiment of the present invention;

[0059] Figure 5 A schematic diagram of the cross-sectional structure of a semiconductor device after a polycrystalline material layer is formed in one embodiment of the present invention;

[0060] Figure 6 FIG. 1 is a schematic diagram of a cross-sectional structure of a semiconductor device after forming a lead-out structure in one embodiment of the present invention, and FIG. Figure 6 A schematic cross-sectional view of a semiconductor structure after a lead-out structure is formed in one embodiment of the present invention;

[0061] Figure 7 A schematic diagram of a cross-sectional structure of a semiconductor device after forming a third doping region in one embodiment of the present invention;

[0062] Figure 8 A schematic diagram of the cross-sectional structure of a semiconductor device after forming a first filling dielectric layer in one embodiment of the present invention;

[0063] Figure 9 A schematic diagram of the cross-sectional structure of a semiconductor device after gate polycrystal formation in one embodiment of the present invention;

[0064] Figure 10 is a schematic diagram of a cross-sectional structure of a semiconductor device after forming a second filling dielectric layer in one embodiment of the present invention, and Figure 10 FIG. 1 is a schematic diagram of the cross-sectional structure of a semiconductor structure in one embodiment of the present invention.

[0065] Figure numerals: 10, substrate; 11, well region; 12, first doped region; 121, N-type doped region; 122, N-type doped region; 13, second doped region; 14, lead-out region groove; 15, window groove; 16, polycrystalline material layer; 17, lead-out structure; 18, gate polycrystalline; 19, gate oxide layer; 20, first filling dielectric layer; 21, second filling dielectric layer; 22, cavity; 23, third doped region; 24, interlayer dielectric layer. DETAILED DESCRIPTION

[0066] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the present invention.

[0067] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used in this specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0068] In the description of the present invention, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0069] For high-voltage VDMOS transistors, the drain is located on the semiconductor surface. A small, deep trench is needed to lead the source from the semiconductor bottom. The lead-out polysilicon must be formed on the sidewalls of the device trench. To form the lead-out polysilicon, the device trench must first be filled with polycrystalline, and then the polycrystalline on the sidewalls must be etched back. This makes it difficult to achieve a good polysilicon fill while simultaneously achieving highly conductive polysilicon. This is because, in typical polysilicon trench filling processes, due to the characteristics of the furnace tube, the lower the furnace tube temperature, the better the polysilicon fill, but the polysilicon resistance is significantly increased. Higher furnace tube temperatures facilitate polysilicon doping to achieve low-resistance polysilicon, but the polysilicon fill is poor, which can affect the device's electrical performance.

[0070] In addition, since gaps are generated when the polycrystalline fills the trench, when the polycrystalline on the sidewall is etched back, the etching gas will penetrate into the gap and preferentially etch the bottom of the gap, which causes the etched polysilicon to be V-shaped. This phenomenon is more obvious when the trench size is larger. In addition, if the etching depth of the polysilicon does not reach the bottom of the gap, the gap will still exist in the polysilicon after the etching is completed, and the gap will be magnified during the etching process, which will affect the subsequent process of forming the sidewall polysilicon. There may be a situation where the polysilicon thickness is insufficient, or there may be residual oxide in the gap in the subsequent process flow, resulting in the polysilicon below the gap being difficult to etch during the subsequent etching back of the polysilicon, resulting in polysilicon residue.

[0071] In order to reduce the occurrence of the above problems, Figure 1 As shown, the present invention provides a semiconductor manufacturing method, comprising:

[0072] Step S10: providing a substrate 10;

[0073] Step S20: forming a well region 11 in the substrate 10, and forming at least a first doping region 12 on the upper surface of the well region 11. The first doping region 12 has a different conductivity type from the well region 11, such as Figure 2 As shown;

[0074] Step S30: Etching the substrate 10 to form a lead-out trench 14 and a window trench 15 extending from the surface of the substrate 10 through the first doped region 13 and into the well region 11. The lead-out trench 14 and the window trench 15 are connected, and a gate oxide layer 19 is formed on the sidewalls and bottom wall of the lead-out trench 14 and the sidewalls and bottom wall of the window trench 15. Figure 3 and Figure 4 As shown;

[0075] Step S40: Fill the lead-out region trench 14 with a polycrystalline material layer to form a lead-out structure 17, and form a polycrystalline material layer on the sidewall of the window trench 15. The polycrystalline material layer in the lead-out region trench 14 and the polycrystalline material on the sidewall of the window trench 15 are electrically connected. Figure 6 As shown;

[0076] Step S50: etching back the polycrystalline material layer 16 on the sidewall of the window trench 15 to a specified depth to form a gate polycrystalline 18, such as Figure 9 shown.

[0077] Through the above technical solution, the polycrystalline material layer 16 is only formed on the sidewalls of the window trench 15, and there is no need to remove the polycrystalline material layer 16 in the center after the window trench 15 is completely filled. In this application, the polycrystalline material layer 16 in the window trench 15 is already consistent with the thickness of the gate polycrystalline 18 to be formed at the beginning. The etching of the polycrystalline material layer 16 changes the height of the polycrystalline material layer 16, which completely solves the problem of etching back the polycrystalline material layer 16 and the problem of gaps generated by polysilicon trench filling, making the height of the gate polycrystalline 18 controllable and unaffected by the process window. At the same time, this method greatly increases the process window, facilitating the formation of the third doped region 23.

[0078] For step S10, specifically, in an optional embodiment, the material of the substrate 10 can be silicon, germanium, GaAs (gallium arsenide), InP (indium phosphide) or GaN (gallium nitride), that is, the substrate 10 can be a silicon substrate, a germanium substrate, a GaAs substrate, an InP substrate or a GaN substrate, etc.; in this embodiment, the substrate 10 can be a silicon substrate.

[0079] For step S20, Figure 2 As shown, specifically, in an optional embodiment, a photomask is used to define the implantation area, and the well region 11 and the first doped region 12 are formed by ion implantation. In an optional embodiment, a second doped region 13 is also formed on the upper surface of the first doped region 12. That is, in this optional embodiment, the second doped region 13 and the first doped region 12 are formed in the same implantation step, and the second doped region 13, the first doped region 12, and the well region 11 are stacked in sequence from top to bottom. In an optional embodiment, the first doped region 12 and the second doped region 13 are both doped regions of the first conductivity type, and the well region 11 is a well region of the second conductivity type. The first conductivity type can be N-type, and the second conductivity type can be P-type. The second doping region 13 may be an N+-type doping region, and the second doping region 13 forms the drain terminal of the semiconductor device in subsequent processes; the first doping region 12 includes at least two concentration gradient doping regions, and the doping concentration of the first doping region 12 decreases from large to small along the direction pointing from the surface of the substrate 10 to the well region 11. In an optional embodiment, the first doping region 12 may include an N-type doping region 121 and an N-type doping region 122, and the N-type doping region 121 and the N-type doping region 122 are stacked in sequence from top to bottom, and the second doping region 13 forms the voltage-withstand region of the semiconductor device; the well region 11 may be a P-type doping region, serving as the channel region of the semiconductor device. The ion implantation in this solution can directly form P-type / (N-type / N-type) / N+-type regions as the channel region / voltage-withstand region / drain terminal.

[0080] like Figure 3As shown, the interface between the well region 11 and the first doped region 12 is 0.1um to 0.3um higher than the bottom walls of the lead-out region trench 14 and the window trench 15, and can be 0.1um, 0.2um or 0.3um. Therefore, the implantation conditions of the first doped region 12, the second doped region 13 and the well region 11 need to be determined according to the depths of the lead-out region trench 14 and the window trench 15 corresponding to different voltage levels. Taking the depths of the lead-out region trench 14 and the window trench 15 both being 2.5um as an example, the junction depth of the PN junction is approximately at 2.3um. The doping distribution formed during implantation makes the PN junction just form a longitudinal concentration difference at a position 0.2um above the bottom walls of the lead-out region trench 14 and the window trench 15, and the breakdown voltage ability will be better.

[0081] For step S30, as Figure 3 shown, specifically, in an optional embodiment, a mask layer or a photoresist layer is used to define the morphologies of the lead-out region trench 14 and the window trench 15 on the surface of the substrate 10, and then the lead-out region trench 14 and the window trench 15 are etched out using an etching gas. The lead-out region trench 14 is connected to the window trench 15. The number of window trenches 15 can be any number, and all the window trenches 15 are connected to the lead-out region trench 14. In the illustrations herein, the number of window trenches 15 is 1, and the illustrations herein fail to show how the window trench 15 is connected to the lead-out region trench 14. The lead-out region trench 14 surrounds the window trench 15. When the number of window trenches 15 is 2, both ends of each window trench 15 are connected to the lead-out region trench 14, and the lead-out region trench 14 and the window trench 15 surrounded by it are approximately in the shape of a Chinese character "mu" from a top view perspective.

[0082] In one embodiment, the width of the lead-out region trench 14 is 0.3 to 7um, and can be 0.3um, 5um or 7um; the depth is 2 to 5um, and can be 2um, 3um or 5um; the width of the window trench 15 is 0.8 to 1.4um, and can be 0.8um, 1um or 1.4um; the depth is 2 to 5um, and can be 2um, 3um or 5um.

[0083] In one embodiment, after step S30 and before step S40, it further includes:

[0084] Step S31: A repair layer is formed on the side walls and bottom walls of the lead-out region trench 14 and the window trench 15;

[0085] Step S32: The repair layer is removed by a wet etching process;

[0086] Step S33: A gate oxide layer 19 is formed on the side walls and bottom walls of the lead-out region trench 14 and the window trench 15, as Figure 4 shown.

[0087] Specifically, the repair layer can be a silicon oxide layer. A furnace is used to grow a 20-110 angstrom layer of silicon oxide on the sidewalls and bottom wall of the lead-out region trench 14 and the sidewalls and bottom wall of the window trench 15. This is then removed by wet rinsing. This can reduce surface damage caused by deep trench corrosion, improve the capping problem at the top of the lead-out region trench 14 and the window trench 15, and enhance the integrity of the gate oxide layer on the sidewalls. After removing the repair layer, a furnace is used again to grow a thicker gate oxide layer 19 of 200-1000 angstroms. In one embodiment, the bottom corners of the lead-out region trench 14 are rounded; the bottom corners of the window trench 15 are rounded. The rounded corners at the bottom ensure uniform growth of the gate oxide layer 19 at the corners, that is, the thickness of the gate oxide layer 19 in the channel region is uniform, maintaining a stable threshold voltage.

[0088] Step S40 specifically includes the following steps:

[0089] Step S401: growing a polycrystalline material layer 16 on the surface of the substrate 10, the sidewalls of the lead-out region trench 14, the bottom wall of the lead-out region trench 14, the sidewalls of the window trench 15, and the bottom wall of the window trench 15. Figure 5 As shown;

[0090] Step S402: etching and removing the polycrystalline material layer 16 on the surface of the substrate 10 and the bottom wall of the window groove 15, as shown in FIG. Figure 6 shown.

[0091] Specifically, the polycrystalline material layer 16 may be a polysilicon layer, and the thickness of the grown polycrystalline material layer 16 satisfies the following conditions:

[0092] b<2a<(c+d);

[0093] Among them, such as Figure 6 As shown, a is the thickness of the polycrystalline material layer 16 on the sidewall of the window trench 15;

[0094] b is the width of the lead-out groove 14;

[0095] c is the width of the window groove 15;

[0096] d is a constant, and the value of d includes 0.2um~0.4um, and can be 0.2um, 0.3um or 0.4um.

[0097] By meeting the above conditions, it is ensured that the polycrystalline material layer 16 grown on the sidewalls of the window trench 15 does not grow to fill the bottom of the window trench 15, while the lead-out region trenches 14 on both sides of the window trench 15 are completely filled with polycrystalline material. In one embodiment, the polycrystalline material layer 16 grown on the sidewalls of the window trench 15 is 2000 angstroms thick, the lead-out region trench 14 is 0.3 μm wide, and the window trench 15 is 1.1 μm wide.

[0098] In an optional embodiment, after step S40 and before step S50, the method further includes step S41: forming a second doping region 13 on the upper surface of the first doping region 12, and forming a third doping region 23 at the bottom of the window trench 15. That is, in this optional embodiment, the second doping region 13 and the third doping region 23 are formed in the same implantation step, and the second doping region 13, the third doping region 23 and the first doping region have the same conductivity type, such as Figure 7 shown.

[0099] Regarding step S41, in an optional embodiment, in the previous step of forming the gate oxide layer, a relatively thick oxide layer is simultaneously formed on the surface of the substrate 10. Therefore, no photomask is required when forming the third doped region 23, and the third doped region 23 can be directly formed at the bottom of the window trench 15 by an ion implantation process. The third doped region 23 is a source terminal and is a doped region of the first conductivity type, and can be an N+ type doped region.

[0100] In an optional embodiment, step S50 specifically includes the following steps:

[0101] Step S501 : filling a first filling dielectric layer 20 between the polycrystalline material layers 16 on both side walls of the window trench 15 ;

[0102] Step S502: forming a pattern mask layer on the surface of the substrate 10, wherein the opening of the pattern mask layer exposes the window trench 15, such as Figure 8 As shown;

[0103] Step S503: etching back the polycrystalline material layer 16 on the sidewall of the window trench 15 based on the pattern mask layer and the filling dielectric layer to form a gate polycrystalline 18, such as Figure 9 shown.

[0104] Specifically, a first filling dielectric material layer is used to fill the gap between the polycrystalline material layer 16 on both side walls of the window trench 15. The first filling dielectric material layer on the surface of the substrate 10 is then removed to form a first filling dielectric layer 20. The first filling dielectric material may be a high-density plasma. A patterned mask layer can be formed by exposing and developing a photoresist layer. Because the openings in the patterned mask layer expose the window trench 15, the polycrystalline material layer 16 on both side walls of the window trench 15 is also exposed. After the polycrystalline material layer 16 is etched to a specified depth, the remaining polycrystalline material layer 16 forms the gate polycrystalline 18. In an optional embodiment, the height of the gate polycrystalline 18 may be 1 μm.

[0105] In an optional embodiment, step S50 further includes the following steps:

[0106] Step S60 : filling a second filling dielectric layer 21 between the first filling dielectric layer 20 and the sidewall of the window trench 15 , wherein a cavity 22 exists inside the second filling dielectric layer 21 ;

[0107] Step S70: depositing an interlayer dielectric layer 24 on the upper surface of the substrate 10;

[0108] Step S80: Lead out the second doping region 13, the third doping region 23 and the lead-out structure 17 to form a device, such as Figure 10 shown.

[0109] Specifically, a second filling dielectric material is used to fill the groove between the first filling dielectric layer 20 and the sidewall of the window trench 15. Since the groove is small and deep, it is easy to form a cavity 22. Therefore, there is a cavity 22 inside the second filling dielectric layer 21. The dielectric constant of air is greater than that of silicon oxide, so the lateral withstand voltage will increase. Therefore, there is no need to increase the width of the window trench 15 to increase the lateral withstand voltage. After the second filling dielectric layer 21 is completed, if other devices need to be added, it can be ground to the surface of the substrate 10. If no other devices are needed, an interlayer dielectric layer 24 can be directly deposited on the surface of the substrate 10, and by etching the lead-out holes of the first doped region 12, the second doped region 13 and the lead-out structure 17, the second doped region 13, the third doped region 23 and the lead-out structure 17 are led out to form a device. The second doped region 13 is the drain terminal, the third doped region 23 is the source terminal, and the lead-out structure 17 is the gate.

[0110] like Figure 6 and Figure 10 As shown, the present application also provides a semiconductor structure, including: a substrate 10; a well region 11, the well region 11 is located in the substrate 10, the upper surface layer of the well region 11 includes at least a first doped region 12, and the first doped region 12 and the well region 11 have different conductivity types; a lead-out region trench 14 and a window trench 15, which penetrate the first doped region 12 from the surface of the substrate 10 and extend into the well region 11, the lead-out region trench 14 and the window trench 15 are connected, and a gate oxide layer 19 is formed on the sidewalls and bottom walls of the lead-out region trench 14 and the sidewalls and bottom walls of the window trench 15; a lead-out structure 17, which is formed by a polycrystalline material layer 16 filling the lead-out region trench 14; a gate polysilicon 18, which is formed by the polycrystalline material layer 16 located on the sidewalls of the window trench 15, and the height of the gate polysilicon 18 is less than the depth of the window trench 15.

[0111] In an optional embodiment, the semiconductor structure further includes a second doped region 13 located on the upper surface of the first doped region 12; an intermediate dielectric layer located in and filling the window trench 15, with a cavity 22 existing inside the intermediate dielectric layer; and a third doped region 23 located in the substrate 10 at the bottom of the window trench 15.

[0112] The material of the substrate 10 can be silicon, germanium, GaAs (gallium arsenide), InP (indium phosphide) or GaN (gallium nitride), that is, the substrate 10 can be a silicon substrate, a germanium substrate, a GaAs substrate, an InP substrate or a GaN substrate, etc.; in this embodiment, the substrate 10 can be a silicon substrate.

[0113] The second doping region 13, the first doping region 12, and the well region 11 are stacked sequentially from top to bottom. In an optional embodiment, the first doping region 12, the second doping region 13, and the third doping region 23 are all doping regions of the first conductivity type, and the well region 11 is a well region of the second conductivity type. The first conductivity type can be N-type, and the second conductivity type can be P-type. The second doping region 13 can be an N+-type doping region, and the second doping region 13 forms the drain terminal of the semiconductor device in subsequent processes; the first doping region 12 includes at least two concentration gradient doping regions, and the doping concentration of the first doping region 12 decreases from high to low along the direction pointing to the well region 11 from the surface of the substrate 10. In an optional embodiment, the first doping region 12 can include an N-type doping region 121 and an N-type doping region 122, and the N-type doping region 121 and the N-type doping region 122 are stacked sequentially from top to bottom. The second doping region 13 forms the voltage-withstand region of the semiconductor device; the well region 11 can be a P-type doping region, serving as the channel region of the semiconductor device. The third doping region 23 is a source terminal. The third doping region 23 is a doping region of the first conductivity type, and can be an N+ type doping region. The ion implantation in this solution can directly form a P-type / (N-type / N-type) / N+ type region as a channel region / voltage-withstand region / drain terminal.

[0114] The interface between the well region 11 and the first doped region 12 is 0.1um to 0.3um higher than the bottom wall of the lead-out region groove 14 and the window groove 15, which can be 0.1um, 0.2um or 0.3um. Therefore, the injection conditions of the first doped region 12, the second doped region 13 and the well region 11 need to be determined according to the depth of the lead-out region groove 14 and the depth of the window groove 15 at different voltage levels. Taking the depth of the lead-out region groove 14 and the depth of the window groove 15 as an example, the junction depth of the PN junction is approximately 2.3um. The doping distribution formed during the injection makes the PN junction just 0.2um above the bottom wall of the lead-out region groove 14 and the window groove 15, forming a longitudinal concentration difference, and the voltage resistance will be better. The third doped region 23 is the source end, and the third doped region 23 is a doped region of the first conductive type, which can be an N+ type doped region.

[0115] The number of window trenches 15 can be any number, and all window trenches 15 are connected to the lead-out area trench 14. In the illustration of this article, the number of window trenches 15 is 1. The lead-out area trench 14 surrounds the window trench 15. When the number of window trenches 15 is 2, both ends of each window trench 15 are connected to the lead-out area trench 14. The lead-out area trench 14 and the window trench 15 it surrounds form a "mu" shape in the top view.

[0116] In one embodiment, the width of the lead-out area trench 14 is 0.3 - 7um, and it can be 0.3um, 5um or 7um; the depth is 2 - 5um, and it can be 2um, 3um or 5um; the width of the window trench 15 is 0.8 - 1.4um, and it can be 0.8um, 1um or 1.4um; the depth is 2 - 5um, and it can be 2um, 3um or 5um.

[0117] The polycrystalline material layer 16 can be a polysilicon layer, and the thickness of the grown polycrystalline material layer 16 satisfies the following conditions:

[0118] b < 2a < (c + d);

[0119] Among them, as Figure 6 shown, a is the thickness of the polycrystalline material layer 16 on the sidewall of the window trench 15;

[0120] b is the width of the lead-out area trench 14;

[0121] c is the width of the window trench 15;

[0122] d is a constant, and the value range of d includes 0.2um - 0.4um, and it can be 0.2um, 0.3um or 0.4um.

[0123] By satisfying the above conditions, it can be ensured that the polycrystalline material layer 16 grown on the sidewall of the window trench 15 will not grow to the bottom of the filled window trench 15, while the lead-out area trenches 14 on both sides of the window trench 15 will be filled with polycrystalline material. In one embodiment, the thickness of the polycrystalline material layer 16 grown on the sidewall of the window trench 15 is 2000 angstroms, the width of the lead-out area trench 14 is 0.3um, and the width of the window trench 15 is 1.1um.

[0124] The intermediate dielectric layer includes a first filling dielectric layer 20 and a second filling dielectric layer 21. The first filling dielectric layer 20 is formed before the gate polycrystal 18 is formed and is filled between the polycrystalline material layers 16 on both sidewalls of the window trench 15. The first filling dielectric material can be high-density plasma. After etching the polycrystalline material layer 16 in the window trench 15 to a specified depth, the remaining polycrystalline material layer 16 forms the gate polycrystal 18. In an optional embodiment, the height of the gate polycrystal 18 can be 1um.

[0125] The second filling dielectric layer 21 is formed after the gate polycrystalline 18 is formed, and fills the space between the first filling dielectric layer 20 and the window trench 15. The second filling dielectric material is used to fill the trench between the first filling dielectric layer 20 and the sidewall of the window trench 15. Since the trench is small and deep, it is easy to form a cavity 22. Therefore, the cavity 22 exists within the second filling dielectric layer 21. The dielectric constant of air is greater than that of silicon oxide, so the lateral withstand voltage is increased. Therefore, there is no need to increase the width of the window trench 15 to increase the lateral withstand voltage.

[0126] Through the above technical solution, the polycrystalline material layer 16 is only formed on the sidewalls of the window groove 15. There is no need to remove the polycrystalline material layer 16 in the center after the window groove 15 is completely filled. In this application, the polycrystalline material layer 16 in the window groove 15 is consistent with the thickness of the gate polycrystalline 18 formed at the beginning of its formation. What is changed by etching the polycrystalline material layer 16 is the height of the polycrystalline material layer 16, which completely solves the problem of etching back the polycrystalline material layer 16, so that the height of the gate polycrystalline 18 can be controlled and is not affected by the process window. This solution greatly increases the process window, and there is a cavity 22 in the second filling dielectric layer 21 between the source and drain ends. The dielectric constant of air is greater than that of silicon oxide, so the lateral withstand voltage will increase. The doping distribution formed at the beginning of the injection of this solution makes the PN junction just 0.2um above the bottom wall of the lead-out area groove 14 and the window groove 15, forming a longitudinal concentration difference, and the withstand voltage capability will be better.

[0127] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor, characterized in that: include: providing a substrate; forming a well region in the substrate, and forming at least a first doped region on an upper surface layer of the well region, wherein the well region and the first doped region have different conductivity types; Etching the substrate to form a lead-out region trench and a window trench extending from the substrate surface through the first doped region and into the well region, wherein the lead-out region trench and the window trench are connected, and forming a gate oxide layer on the sidewalls and bottom wall of the lead-out region trench and the sidewalls and bottom wall of the window trench; Filling the lead-out region trench with a polycrystalline material layer to form a lead-out structure, and forming a polycrystalline material layer on the sidewall of the window trench, wherein the polycrystalline material layer in the lead-out region trench is electrically connected to the polycrystalline material layer on the sidewall of the window trench; forming a second doping region on the upper surface of the first doping region and forming a third doping region at the bottom of the window trench, wherein the second doping region and the third doping region have the same conductivity type as the first doping region; etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline; The second doping region, the third doping region and the lead-out structure are led out to form a device, wherein the second doping region is a drain terminal, the third doping region is a source terminal, and the lead-out structure is a gate terminal.

2. The semiconductor manufacturing method according to claim 1, wherein: The following relations are satisfied: b<2a<(c+d); Wherein, a is the thickness of the polycrystalline material layer on the sidewall of the window trench; b is the width of the lead-out groove; c is the width of the window groove; d is a constant, and the value of d includes 0.2um~0.4um.

3. The semiconductor manufacturing method according to claim 1, wherein: The first doping region includes at least two concentration gradient doping regions, and the doping concentration of the first doping region decreases from high to low along the direction from the substrate surface to the well region.

4. The semiconductor manufacturing method according to claim 1, wherein: The width of the lead-out groove is 0.3-7um, and the depth is 2-5um; the width of the window groove is 0.8-1.4um, and the depth is 2-5um.

5. The semiconductor manufacturing method according to claim 1, wherein: The step of filling the lead-out region trench with a polycrystalline material layer to form a lead-out structure, and forming a polycrystalline material layer on the sidewall of the window trench, wherein the polycrystalline material layer in the lead-out region trench is electrically connected to the polycrystalline material layer on the sidewall of the window trench, comprises: Growing the polycrystalline material layer on the surface of the substrate, in the lead-out region trench, on the sidewalls of the window trench and on the bottom wall of the window trench, wherein the polycrystalline material layer completely fills the lead-out region trench; The polycrystalline material layer on the substrate surface and the bottom wall of the window trench is removed by etching.

6. The semiconductor manufacturing method according to claim 1, wherein: The method further comprises forming a well region in the substrate, forming at least a first doped region on an upper surface layer of the well region, wherein the well region and the first doped region have different conductivity types, and further comprising: A second doping region is formed on the upper surface of the first doping region, wherein the second doping region has the same conductivity type as the first doping region. The lead-out region groove is filled with a polycrystalline material layer to form a lead-out structure, and a polycrystalline material layer is formed on the sidewall of the window groove. After the polycrystalline material layer in the lead-out region groove is electrically connected to the polycrystalline material layer on the sidewall of the window groove, Before etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline, the method further includes: A third doping region is formed at the bottom of the window trench, and the third doping region has the same conductivity type as the first doping region.

7. The semiconductor manufacturing method according to claim 1, wherein: The step of etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline further comprises: Filling a first filling dielectric layer between the polycrystalline material layers on both side walls of the window trench; forming a pattern mask layer on the surface of the substrate, wherein the opening of the pattern mask layer exposes the window groove; The polycrystalline material layer on the sidewall of the window trench is etched back based on the pattern mask layer and the filling dielectric layer to form a gate polycrystalline.

8. The semiconductor manufacturing method according to claim 7, characterized in that: After etching back the polycrystalline material layer on the sidewall of the window trench to a specified depth to form a gate polycrystalline, the method further includes: Filling a second filling dielectric layer between the first filling dielectric layer and the sidewall of the window trench, wherein a cavity exists inside the second filling dielectric layer; An interlayer dielectric layer is deposited on the upper surface of the substrate.

9. The semiconductor manufacturing method according to claim 1, wherein: The depths of the lead-out region trench and the window trench are 0.1 um to 0.3 um deeper than the implantation depth of the first doping region.

10. A semiconductor structure, characterized in that include: substrate; a well region, the well region being located in the substrate, the upper surface layer of the well region comprising at least a first doped region, and the well region and the first doped region having a different conductivity type; A lead-out region trench and a window trench extend from the substrate surface through the first doped region and into the well region, the lead-out region trench and the window trench being in communication, a gate oxide layer being formed on the sidewalls and bottom wall of the lead-out region trench and the sidewalls and bottom wall of the window trench, and the polycrystalline material layer in the lead-out region trench being electrically connected to the polycrystalline material layer on the sidewalls of the window trench; A lead-out structure formed by a polycrystalline material layer filling the lead-out region groove; a gate polysilicon layer formed of a polycrystalline material layer located on the sidewall of the window trench, wherein the height of the gate polysilicon layer is less than the depth of the window trench; a second doping region, located on an upper surface layer of the first doping region; a third doped region located in the substrate at the bottom of the window trench; The second doping region, the third doping region and the lead-out structure are led out to form a device, the second doping region is a drain terminal, the third doping region is a source terminal, and the lead-out structure is a gate terminal.

11. The semiconductor structure according to claim 10, wherein: The semiconductor structure further includes an intermediate dielectric layer located in the window trench and filling the window trench, and a cavity exists inside the intermediate dielectric layer.

12. The semiconductor structure according to claim 10, wherein: The following relations are satisfied: b<2a<(c+d); Wherein, a is the thickness of the polycrystalline material layer on the sidewall of the window trench; b is the width of the lead-out groove; c is the width of the window groove; d is a constant, and the value of d includes 0.2um~0.4um.

13. The semiconductor structure according to claim 10, wherein: The first doping region includes at least two concentration gradient doping regions, and the doping concentration of the first doping region decreases from high to low along the direction from the substrate surface to the well region.

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