Semiconductor structure and method of forming the same
By etching the support layer and forming a second dielectric layer of the same material, the cross-sectional size of the trench is increased, which solves the problem of increased resistance caused by lattice defects and gate sidewall deformation in semiconductor devices and improves device performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2020-10-30
- Publication Date
- 2026-05-29
AI Technical Summary
During the fabrication of existing semiconductor devices, lattice defects and gate sidewall deformation caused by ion implantation lead to increased contact window resistance and thin-film resistance, affecting device performance.
The remaining support layer is formed by etching the support layer and covering it with a second dielectric layer of the same material. The dielectric layer above the source/drain doped regions is removed, the trench cross-sectional size is increased, and a larger area of source/drain conductive plugs is formed.
While ensuring the quality of gate structure processing, the resistance of source and drain conductive plugs was reduced, thereby lowering the contact window resistance and thin-film resistance of semiconductor devices and improving device performance.
Smart Images
Figure CN114446878B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology
[0002] During the fabrication of semiconductor devices, ion implantation doping can easily lead to lattice defects in the semiconductor structure due to the high energy of the implanted ions. To eliminate some of these lattice defects, the semiconductor structure needs to be annealed.
[0003] In existing HKMG (high dielectric constant insulating layer + metal gate) fabrication technology, a polysilicon gate is typically formed first, and then the polysilicon gate structure is replaced with a high dielectric constant insulating layer + metal gate structure. However, during the annealing process, the gate sidewalls are prone to deformation, resulting in incomplete removal of the polysilicon. Therefore, to prevent deformation of the gate sidewalls, the dielectric layer between the gate structures needs to be removed and a support layer filled in.
[0004] However, the contact window resistance and thin-film resistance of the semiconductor devices obtained through the above processing result in poor semiconductor device performance. Summary of the Invention
[0005] The technical problem solved by the embodiments of the present invention is how to improve the performance of semiconductor devices.
[0006] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:
[0007] A substrate is provided, the substrate including a substrate, a gate structure located above the substrate, source and drain doped regions located on both sides of the gate structure, a first dielectric layer covering the surface of the source and drain doped regions, and a support layer located between adjacent source and drain doped regions, the top surface of the support layer being higher than or equal to the top surface of the gate structure;
[0008] The support layer is etched to obtain a remaining support layer, the top surface of which is lower than the top surface of the gate structure;
[0009] A second dielectric layer is formed, which at least covers the remaining support layer, and the top surface of the second dielectric layer is at least flush with the top surface of the first dielectric layer. The material of the second dielectric layer is the same as that of the first dielectric layer.
[0010] At least the first dielectric layer and the second dielectric layer above the top surface of the source / drain doped region, and the second dielectric layer above the remaining support layer are removed to expose the source / drain doped region and form a first trench;
[0011] The first trench is filled to form a source / drain conductive plug that is electrically connected to the source / drain doped region.
[0012] Optionally, the method for forming the semiconductor structure further includes:
[0013] A second trench is formed, the second trench exposing the substrate located between adjacent source / drain doped regions;
[0014] The second trench is filled to form a substrate conductive plug that is electrically connected to the substrate.
[0015] Optionally, the top surface of the remaining support layer is lower than the top surface of the source / drain doped region, or the top surface of the remaining support layer is flush with the top surface of the source / drain doped region.
[0016] Optionally, the step of forming the second dielectric layer includes:
[0017] A second dielectric material layer is formed, which covers the remaining support layer and the gate structure;
[0018] The second dielectric material layer is planarized to form a second dielectric layer, the top surface of which is flush with the top surface of the gate structure.
[0019] Optionally, the method further includes the following steps before forming the first trench:
[0020] An isolation layer is formed, which covers the second dielectric layer.
[0021] Optionally, after the step of forming the isolation layer and before the step of forming the first trench, the method further includes:
[0022] A third dielectric layer is formed, which covers the isolation layer.
[0023] Optionally, the step of etching the support layer includes:
[0024] The support layer is etched using both dry and wet etching processes.
[0025] Optionally, the gate structure includes a high-dielectric-constant metal gate structure.
[0026] Optionally, the substrate further includes a gate conductive structure located above and electrically connected to the high-dielectric-constant metal gate structure.
[0027] This invention also provides a semiconductor structure, comprising:
[0028] The substrate includes a substrate, a gate structure located above the substrate, source and drain doped regions located on both sides of the gate structure, and a first dielectric layer covering the surface of the source and drain doped regions;
[0029] A remaining support layer is located between adjacent gate structures and covers the surface of the source / drain doped regions between the gate structures and the surface of the substrate. The top surface of the remaining support layer is lower than the top surface of the gate structure.
[0030] A second dielectric layer, which at least covers the remaining support layer, and whose top surface is at least flush with the top surface of the first dielectric layer, and whose material is the same as that of the first dielectric layer;
[0031] The source / drain conductive plugs are electrically connected to the source / drain doped regions.
[0032] Optionally, the semiconductor structure further includes:
[0033] The substrate conductive plug is electrically connected to the source / drain doped region.
[0034] Optionally, the top surface of the remaining support layer is lower than the top surface of the source / drain doped region, or the top surface of the remaining support layer is flush with the top surface of the source / drain doped region.
[0035] Optionally, the top surface of the second dielectric layer is flush with the top surface of the source / drain doped region.
[0036] Optionally, the semiconductor structure further includes:
[0037] An isolation layer covers the supplementary medium layer.
[0038] Optionally, the semiconductor structure further includes:
[0039] A third dielectric layer covers the isolation layer.
[0040] Optionally, the gate structure includes a high-dielectric-constant metal gate structure.
[0041] Optionally, the substrate further includes a gate conductive structure located above and electrically connected to the high-dielectric-constant metal gate structure.
[0042] The semiconductor structure formation method provided in this embodiment of the invention, after completing the gate structure processing, further etches the support layer to obtain the remaining support layer, and then forms a processing platform for opening the first trench by forming a second dielectric layer covering the remaining support layer. Since the first dielectric layer and the second dielectric layer are made of the same material, when forming the first trench, the first and second dielectric layers above the source / drain doped regions, as well as the second dielectric layer above the remaining support layer, can be removed simultaneously. This allows for an increase in the cross-sectional size of a portion of the first trench, and further increases in the cross-sectional size of a portion of the source / drain conductive plug formed within the first trench. This achieves electrical connection between the source / drain doped regions while reducing the resistance of the source / drain conductive plug. It can be seen that the semiconductor structure formation method provided in this embodiment of the invention can achieve the formation of the source / drain conductive plug while ensuring the gate structure processing requirements and processing quality. Furthermore, by removing a portion of the support layer located between adjacent source / drain doped regions, the cross-sectional size of the formed source / drain conductive plug can be increased, reducing the resistance of the source / drain conductive plug. This, in turn, reduces the contact window resistance and thin-film resistance of the obtained semiconductor device, thereby improving the performance of the semiconductor device. Attached Figure Description
[0043] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0044] Figures 1a to 3c This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0045] Figures 4a to 10c This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method provided by the present invention. Detailed Implementation
[0046] The devices currently being formed still have performance issues. This paper analyzes the reasons for the poor performance of the devices by combining a semiconductor structure formation method.
[0047] Please refer to Figures 1a-3c , Figures 1a to 3c This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure. In each group of figures, figure b is a schematic diagram of the structure obtained by the cross-sectional line along A-A' in figure a, figure c is a schematic diagram of the structure obtained by the cross-sectional line along B-B' in figure a, and figure a is a schematic diagram of the structure obtained by the cross-sectional line along C-C' in figure b or along D-D' in figure c.
[0048] like Figures 1a-1c As shown, a substrate is provided, the substrate including a substrate 110, a gate structure 12 located above the substrate 110, source / drain doped regions 130 located on both sides of the gate structure 12, a substrate dielectric layer 150 covering the surface of the source / drain doped regions 130, and a support layer 140 located between adjacent source / drain doped regions 130, the top surface of the support layer 140 being higher than or equal to the top surface of the gate structure 12. The gate structure 12 includes a gate body 122 and a gate sidewall 121, and a gate conductive structure 123 may also be formed above the gate structure 12. The gate conductive structure 123 is electrically connected to the gate structure 12, facilitating the subsequent formation of a structure electrically connected to the gate.
[0049] according to Figure 1a As can be seen, the top surface of the support layer 140 is higher than the top surface of the gate structure 12 and flush with the top surface of the gate conductive structure 123. Between adjacent gate structures 12, there is still some dielectric material and some gate sidewalls where the middle of the gate structure has been removed. On the sidewalls of these gate sidewalls and on the top surface of the source / drain doped regions, there is also some protective material.
[0050] according to Figure 1b and Figure 1c It can be seen that, in the aforementioned Figure 1a The support layer 140 is also formed in the partially parallel structure shown.
[0051] like Figures 2a-2c As shown, an isolation layer 160 and a top dielectric layer 170 are formed covering the support layer 140 and the gate conductive structure 123.
[0052] like Figures 3a-3c As shown, a source / drain conductive plug 181 and a substrate conductive plug 182 are formed, wherein the source / drain conductive plug 181 is electrically connected to the source / drain doped region 130, and the substrate conductive plug 182 is electrically connected to the substrate 110.
[0053] like Figure 3a and Figure 3c As shown, in the cross-section of the semiconductor structure, the source / drain conductive plug 181 is electrically connected to the source / drain doped region 130.
[0054] exist Figure 3cAs can be seen, the reduced generation space of the source / drain conductive plug 181 decreases its cross-sectional area, thereby indirectly increasing its resistance. Similarly, although the cross-section of the substrate conductive plug 182 is not shown, its resistance also increases due to the reduced generation space.
[0055] In this way, the contact window resistance and thin-film resistance of the resulting semiconductor device are relatively large.
[0056] To address the above problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising:
[0057] A substrate is provided, the substrate including a substrate, a gate structure located above the substrate, source and drain doped regions located on both sides of the gate structure, a first dielectric layer covering the surface of the source and drain doped regions, and a support layer located between adjacent source and drain doped regions, the top surface of the support layer being higher than or equal to the top surface of the gate structure;
[0058] The support layer is etched to obtain a remaining support layer, the top surface of which is lower than the top surface of the gate structure;
[0059] A second dielectric layer is formed, which at least covers the remaining support layer, and the top surface of the second dielectric layer is at least flush with the top surface of the first dielectric layer. The material of the second dielectric layer is the same as that of the first dielectric layer.
[0060] At least the first dielectric layer and the second dielectric layer above the top surface of the source / drain doped region, and the second dielectric layer above the remaining support layer are removed to expose the source / drain doped region and form a first trench;
[0061] The first trench is filled to form a source / drain conductive plug that is electrically connected to the source / drain doped region.
[0062] The semiconductor structure formation method provided in this embodiment of the invention, after completing the gate structure processing, further etches the support layer to obtain the remaining support layer, and then forms a processing platform for opening the first trench by forming a second dielectric layer covering the remaining support layer. Since the first dielectric layer and the second dielectric layer are made of the same material, when forming the first trench, the first and second dielectric layers above the source / drain doped regions, as well as the second dielectric layer above the remaining support layer, can be removed simultaneously. This allows for an increase in the cross-sectional size of a portion of the first trench, and further increases in the cross-sectional size of a portion of the source / drain conductive plug formed within the first trench. This achieves electrical connection between the source / drain doped regions while reducing the resistance of the source / drain conductive plug. It can be seen that the semiconductor structure formation method provided in this embodiment of the invention can achieve the formation of the source / drain conductive plug while ensuring the gate structure processing requirements and processing quality. Furthermore, by removing a portion of the support layer located between adjacent source / drain doped regions, the cross-sectional size of the formed source / drain conductive plug can be increased, reducing the resistance of the source / drain conductive plug. This, in turn, reduces the contact window resistance and thin-film resistance of the obtained semiconductor device, thereby improving the performance of the semiconductor device.
[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0064] Please refer to Figures 4a-10c , Figures 4a to 10c This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure. In each group of figures, figure b is a schematic diagram of the structure obtained by the cross-sectional line along A-A' in figure a, figure c is a schematic diagram of the structure obtained by the cross-sectional line along B-B' in figure a, and figure a is a schematic diagram of the structure obtained by the cross-sectional line along C-C' in figure b or along D-D' in figure c.
[0065] like Figures 4a-4c As shown, a substrate is provided, the substrate including a substrate 210, a gate structure 22 located above the substrate 210, source / drain doped regions 230 located on both sides of the gate structure 22, a first dielectric layer 250 covering the surface of the source / drain doped regions 230, and a support layer 240 located between adjacent source / drain doped regions 230, the top surface of the support layer 240 being higher than or equal to the top surface of the gate structure 22.
[0066] The substrate is used to provide a processing foundation and support for subsequent processing.
[0067] The gate structure 22 may include a gate body 222 and a gate sidewall 221, and a gate conductive structure 223 may be formed on top of the gate structure 22. The gate conductive structure 223 is electrically connected to the gate structure 22, facilitating the subsequent formation of a structure electrically connected to the gate.
[0068] The gate structure 22 can be selected as needed. To improve the performance of the resulting semiconductor structure, in one embodiment, the gate structure 22 includes a high-dielectric-constant metal gate structure.
[0069] By setting the gate structure 22 as a high dielectric constant metal gate structure, the gate capacitance can be effectively reduced and the control performance of the gate structure 22 can be improved.
[0070] In one specific embodiment, the specific steps for forming the substrate may include:
[0071] An initial substrate is provided, the substrate comprising a substrate, a gate structure located above the substrate, source / drain doped regions located on both sides of the gate structure, and a dielectric layer filling trenches between adjacent gates, wherein each source / drain doped region has a gate structure on both sides, the gate structure comprising at least a gate sidewall and a gate body, the gate body being a polysilicon gate.
[0072] The two gate structures and a portion of the dielectric layer between the adjacent source and drain doped regions are etched, wherein the gate structure is retained on one side of each source and drain doped region and the gate structure is removed on the other side. For convenience, some gate sidewalls may not be removed.
[0073] Then, the formed trench is filled with a support layer material to form a support layer;
[0074] Remove the portion above the top surface of the gate structure to expose the polysilicon gate;
[0075] The polysilicon gate is then etched away to form a high-dielectric-constant metal gate structure within the gate sidewall.
[0076] In order to etch away the polysilicon gate, a plane suitable for photoresist adhesion must be formed on the polysilicon gate. If a support layer material is not filled into the formed trench, but only a general dielectric material, such as silicon oxide, is used, the high stress of silicon oxide during annealing can easily cause deformation of the gate sidewalls, resulting in incomplete removal of the polysilicon. Therefore, to prevent deformation of the gate sidewalls, the dielectric layer between the gate structures needs to be removed and a support layer filled in.
[0077] according to Figure 4aAs can be seen, the top surface of the support layer 240 is higher than the top surface of the gate structure 22 and flush with the top surface of the gate conductive structure 223. A portion of dielectric material and a portion of gate sidewalls remain between adjacent gate structures 22. On the sidewalls of these gate sidewalls and on the top surface of the source / drain doped regions 230, a portion of protective material remains. The aforementioned portion of dielectric material, the portion of gate sidewalls from which the gate structure has been removed, and the portion of protective material may or may not be present.
[0078] like Figure 4b and Figure 4c As shown, a plurality of fins are formed on the substrate 210, and a substrate dielectric layer is provided between each gate structure 22 and the substrate 210. The source and drain doped regions 230 are formed above the fins.
[0079] The substrate 210 can be any suitable substrate material known to those skilled in the art, such as silicon, germanium, silicon-germanium, gallium arsenide, indium phosphide, etc., which are bulk semiconductor substrate materials.
[0080] The material of the substrate dielectric layer can be silicon oxide, etc.
[0081] like Figure 4c As shown, the first dielectric layer 250 covers the surface of the source / drain doped region 230.
[0082] like Figures 5a-5c As shown, the support layer 240 is etched to obtain the remaining support layer 241, wherein the top surface of the remaining support layer 241 is lower than the top surface of the gate structure 22.
[0083] Etching the support layer 240 can reduce the space occupied by the support layer 240, leaving more space for the conductive plugs to be formed later.
[0084] Since the portion of the support layer 240 removed compared to the remaining support layer 241 no longer occupies space, the subsequently formed source / drain conductive plug 291 can be divided into three segments: the upper segment is the portion above the top surface of the original support layer 241, the middle segment is the portion below the top surface of the original support layer 240 but above the top surface of the remaining support layer 241, and the lower segment is the portion below the top surface of the remaining support layer 241. The upper and lower segments are identical to those in the prior art source / drain conductive plug 291, so their resistance remains unchanged. The middle segment, due to the removal of the support layer 240, effectively increases the cross-sectional area of the subsequently formed source / drain conductive plug 291, thereby reducing its resistance.
[0085] The method for etching the support layer 240 can be selected as needed. To improve the efficiency and removal degree of etching the support layer 240, in one specific embodiment, a dry etching process and a wet etching process are used to etch the support layer 240. Specifically, a dry etching process can be used first to remove most of the support layer 240 to be etched, and then a wet etching process can be used to further remove the remaining support layer 240 material on the sidewalls. By using a dry etching process and a wet etching process to etch the support layer 240, the etching efficiency is improved while the support layer 240 is removed more cleanly.
[0086] The height of the remaining support layer 241 can be selected as needed.
[0087] For example, in Figure 5a and Figure 5c In this process, the top surface of the remaining support layer 241 is flush with the top surface of the source / drain doped region 230.
[0088] In this way, since the support layer 240 above the top surface of the source / drain doped region 230 is completely removed, the subsequent source / drain conductive plug 291 forms a complete column, and the resistance of the resulting source / drain conductive plug 291 is relatively small.
[0089] Of course, in another specific embodiment, in order to further reduce the space occupied by the support layer 240, the top surface of the remaining support layer 241 can be made lower than the top surface of the source / drain doped region 230.
[0090] Of course, when the top surface of the remaining support layer 241 is lower than the top surface of the source / drain doped region 230, not only can the resistance of the obtained source / drain conductive plug 291 be minimized, but the second dielectric layer 260 formed subsequently can also fill the trenches obtained by etching the support layer 240 to a greater extent, thereby improving the isolation and support function of the second dielectric layer 260.
[0091] Of course, to further reduce the space occupied by the support layer 240, in another specific embodiment, the support layer 240 can be completely removed, in which case the height of the remaining support layer 241 is 0. By completely removing the support layer 240, the isolation and support functions of the second dielectric layer 260 can be improved.
[0092] To subsequently form the source / drain conductive plugs 291 and the substrate conductive plugs 292, a dielectric layer needs to be formed on the source / drain doped regions 230 and the substrate 210. For example... Figures 6a-7cAs shown, a second dielectric layer 260 is formed, which at least covers the remaining support layer 241, and the top surface of the second dielectric layer 260 is at least flush with the top surface of the first dielectric layer 250. The material of the second dielectric layer 260 is the same as that of the first dielectric layer 250.
[0093] The formation of the second dielectric layer 260 can provide a platform for the subsequent formation of trenches for source / drain conductive plugs 291 and substrate conductive plugs 292.
[0094] like Figures 6a-6c As shown, a second dielectric material layer is formed, which covers the remaining support layer 241 and the gate structure 22.
[0095] Since it is difficult to precisely form a dielectric layer only within the trenches obtained by etching the support layer 240, the trenches obtained by etching the support layer 240 can be filled first, and the remaining support layer 241 and the gate structure 22 can be covered to form a second dielectric material layer.
[0096] like Figures 7a-7c As shown, the second dielectric material layer is planarized to form a second dielectric layer 260. To facilitate subsequent etching, the top surface of the second dielectric layer 260 is at least flush with the top surface of the first dielectric layer 250.
[0097] In forming the second dielectric material layer, the formed second dielectric material layer can be planarized using processes such as chemical mechanical polishing to form the second dielectric layer 260.
[0098] The second dielectric layer 260 can cover the remaining support layer 241, and the top surface of the second dielectric layer 260 is at least flush with the top surface of the gate structure 22, thereby facilitating the formation of the subsequent isolation layer 270.
[0099] The material of the second dielectric layer 260 is the same as that of the first dielectric layer 250, which can simplify the subsequent removal process of the first dielectric layer 250 and the second dielectric layer 260. The removal of the first dielectric layer 250 and the second dielectric layer 260 can be achieved in one step.
[0100] like Figures 8a-9c As shown, an isolation layer 270 is formed, which covers the second dielectric layer 260.
[0101] The isolation layer 270 can be formed by deposition. The function of the isolation layer 270 includes protecting the structure it covers, particularly the gate conductive structure 223, and isolating it from other structures.
[0102] In other embodiments, the step of forming the isolation layer 270 may be omitted.
[0103] The material of the isolation layer 270 can be silicon nitride, silicon carbide, etc.
[0104] like Figures 9a-9c As shown, a third dielectric layer 280 is formed, which covers the isolation layer 270.
[0105] The third dielectric layer 280 serves to provide support height, facilitating the formation of conductive plugs of suitable height.
[0106] In other embodiments, the step of forming the third dielectric layer 280 may be omitted.
[0107] The material of the third dielectric layer 280 can be silicon oxide, etc. Figures 10a-10c As shown, at least the first dielectric layer 250 and the second dielectric layer 260 above the top surface of the source / drain doped region 230, as well as the second dielectric layer 260 above the remaining support layer 241, are removed to expose the source / drain doped region 230, forming a first trench, and the first trench is filled to form a source / drain conductive plug 291 electrically connected to the source / drain doped region 230.
[0108] from Figure 10c As can be seen, the material of the second dielectric layer 260 is the same as that of the first dielectric layer 250, so the first dielectric layer 250 and the second dielectric layer 260 can be etched simultaneously.
[0109] Since the portion of the support layer 240 removed compared to the remaining support layer 24 no longer occupies space, the source / drain conductive plug 291 can be divided into three segments: the upper segment is the portion above the top surface of the original support layer 240, the middle segment is the portion below the top surface of the original support layer 240 but above the top surface of the remaining support layer 241, and the lower segment is the portion below the top surface of the remaining support layer 241. The upper and lower segments are identical to those in the prior art source / drain conductive plug 291, so their resistance remains unchanged. The middle segment, due to the removal of the support layer 240, effectively increases the cross-sectional area of the subsequently formed source / drain conductive plug 291, thereby indirectly reducing its resistance.
[0110] The source and drain conductive plug 291 can be made of metals such as tungsten, aluminum, and copper, or other conductive materials.
[0111] Of course, when the height of the remaining support layer 241 is lower than the top surface height of the source / drain doped region 230, the lower segment does not exist. In this case, the conclusion is the same, and will not be repeated here.
[0112] The semiconductor structure formation method provided in this embodiment of the invention, by etching the support layer 240 to obtain the remaining support layer 241, and then forming the source / drain conductive plug 291, can effectively reduce the volume occupied by the support layer 240 in the source / drain conductive plug 291 portion. Since the portion of the support layer 240 removed compared to the remaining support layer 241 no longer occupies space, it is equivalent to increasing the cross-sectional area of the subsequently formed source / drain conductive plug 291, thereby indirectly reducing the resistance of the source / drain conductive plug 291. This, in turn, can reduce the contact window resistance and thin-film resistance of the obtained semiconductor device, thereby improving the performance of the semiconductor device.
[0113] Of course, depending on the needs, corresponding conductive plugs can also be formed on the substrate 210.
[0114] Therefore, refer to Figures 10a-10c In one specific embodiment, the method for forming a semiconductor structure provided by the present invention further includes: forming a second trench, the second trench exposing the substrate 210 located between adjacent source and drain doped regions 230; filling the second trench to form a substrate conductive plug 292 electrically connected to the substrate 210.
[0115] The second trench and the first trench can be formed simultaneously, and then the substrate conductive plug 292 and the source / drain conductive plug 291 can be formed simultaneously.
[0116] Of course, the second trench and the first trench can be formed separately, and the substrate conductive plug 292 and the source-drain conductive plug 291 can also be formed separately.
[0117] The material of the substrate conductive plug 292 can be selected from metals such as tungsten, aluminum, and copper, or other conductive materials.
[0118] Similarly, since the portion of the support layer 240 removed compared to the remaining support layer 241 no longer occupies space, the cross-sectional area of the subsequently formed substrate conductive plug 292 is increased, thereby indirectly reducing the resistance of the substrate conductive plug 292.
[0119] To address the issue of poor performance of semiconductor structures, this invention also provides a semiconductor structure.
[0120] Please continue to refer to this. Figures 10a-10c The semiconductor structure provided in this embodiment of the invention includes:
[0121] The substrate includes a substrate 210, a gate structure 22 located above the substrate 210, and source / drain doped regions 230 located on both sides of the gate structure 22.
[0122] A remaining support layer 241 is located between adjacent gate structures 22 and covers the surface of the source / drain doped region 230 between the gate structures 22 and the surface of the substrate 210. The top surface of the remaining support layer 241 is lower than the top surface of the gate structure 22.
[0123] A second dielectric layer 260 covers the remaining support layer 241, and its top surface is at least flush with the top surface of the gate structure 22.
[0124] The source / drain conductive plug 291 is electrically connected to the source / drain doped region 230.
[0125] In the semiconductor structure provided by this invention, the volume occupied by the remaining support layer 241 in the source / drain conductive plug 291 portion is significantly reduced compared to existing semiconductor structures. This is equivalent to increasing the cross-sectional area of the subsequently formed source / drain conductive plug 291, thereby indirectly reducing the resistance of the source / drain conductive plug 291. This, in turn, can reduce the contact window resistance and thin-film resistance of the resulting semiconductor device, thereby improving the performance of the semiconductor device.
[0126] Of course, depending on the needs, corresponding conductive plugs can also be formed on the substrate 210. Therefore, in one specific embodiment, the semiconductor structure further includes: a substrate conductive plug 292, electrically connected to the source / drain doped region 230.
[0127] Similarly, the volume occupied by the remaining support layer 241 in the substrate conductive plug 292 is significantly reduced compared to existing semiconductor structures, which is equivalent to increasing the cross-sectional area of the subsequently formed substrate conductive plug 292, thereby indirectly reducing the resistance of the substrate conductive plug 292. This can further reduce the contact window resistance and thin-film resistance of the resulting semiconductor device, thereby improving the performance of the semiconductor device.
[0128] The thickness of the remaining support layer 241 can be selected as needed.
[0129] In one specific embodiment, the top surface of the remaining support layer 241 is flush with the top surface of the source / drain doped region 230. Thus, since the entire portion of the support layer 240 above the top surface of the source / drain doped region 230 is removed, the subsequent source / drain conductive plug 291 forms a complete cylinder, resulting in a lower resistance of the obtained source / drain conductive plug 291.
[0130] Of course, in order to reduce the space occupied by the support layer 240, in one specific embodiment, the top surface of the remaining support layer 241 is lower than the top surface of the source / drain doped region 230.
[0131] Of course, when the top surface of the remaining support layer 241 is lower than the top surface of the source / drain doped region 230, not only can the resistance of the obtained source / drain conductive plug 291 be minimized, but the second dielectric layer 260 formed subsequently can also fill the trenches obtained by etching the support layer 240 to a greater extent, thereby improving the isolation and support function of the second dielectric layer 260.
[0132] Of course, to further reduce the space occupied by the support layer 240, in another specific embodiment, the support layer 240 can be completely removed, in which case the height of the remaining support layer 241 is 0. By completely removing the support layer 240, more of the subsequently formed second dielectric layer 260 can be filled, thereby improving the isolation and support functions of the second dielectric layer 260.
[0133] The gate structure 22 includes a gate body 222 and a gate sidewall 221. A gate conductive structure 223 may also be formed on top of the gate structure 22. The gate conductive structure 223 is electrically connected to the gate structure 22, facilitating the subsequent formation of a structure electrically connected to the gate.
[0134] The gate structure 22 can be selected as needed. To improve the performance of the resulting semiconductor structure, in one embodiment, the gate structure 22 includes a high-dielectric-constant metal gate structure.
[0135] By setting the gate structure 22 as a high dielectric constant metal gate structure, the gate capacitance can be effectively reduced and the control performance of the gate structure 22 can be improved.
[0136] To protect the gate structure 22 or the gate conductive structure 223, the semiconductor structure provided in this embodiment of the invention further includes: an isolation layer 270 covering the supplementary dielectric layer to form an isolation layer 270, wherein the isolation layer 270 covers the second dielectric layer 260.
[0137] The isolation layer 270 can be formed by deposition. The function of the isolation layer 270 includes protecting the structure it covers, particularly the gate conductive structure 223.
[0138] To facilitate the formation of a conductive plug of suitable height, the semiconductor structure provided in this embodiment of the invention further includes a third dielectric layer 280 covering the isolation layer 270. The third dielectric layer 280 provides support height to facilitate the formation of a conductive plug of suitable height.
[0139] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.
[0140] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a substrate, a gate structure located above the substrate, source and drain doped regions located on both sides of the gate structure, a first dielectric layer covering the surface of the source and drain doped regions, and a support layer located between adjacent source and drain doped regions, the top surface of the support layer being higher than or equal to the top surface of the gate structure; The support layer is etched to obtain a remaining support layer, the top surface of which is lower than the top surface of the gate structure; A second dielectric layer is formed, which at least covers the remaining support layer, and the top surface of the second dielectric layer is at least flush with the top surface of the first dielectric layer. The material of the second dielectric layer is the same as that of the first dielectric layer. At least the first dielectric layer and the second dielectric layer above the top surface of the source / drain doped region, and the second dielectric layer above the remaining support layer are removed to expose the source / drain doped region and form a first trench; The first trench is filled to form a source / drain conductive plug that is electrically connected to the source / drain doped region.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: A second trench is formed, the second trench exposing the substrate located between adjacent source / drain doped regions; The second trench is filled to form a substrate conductive plug that is electrically connected to the substrate.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The top surface of the remaining support layer is lower than the top surface of the source / drain doped region, or the top surface of the remaining support layer is flush with the top surface of the source / drain doped region.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the second dielectric layer includes: A second dielectric material layer is formed, which covers the remaining support layer and the gate structure; The second dielectric material layer is planarized to form a second dielectric layer, the top surface of which is flush with the top surface of the gate structure.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming the first trench is preceded by: An isolation layer is formed, which covers the second dielectric layer.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, After the step of forming the isolation layer and before the step of forming the first trench, the method further includes: A third dielectric layer is formed, which covers the isolation layer.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of etching the support layer includes: The support layer is etched using both dry and wet etching processes.
8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The gate structure includes a high dielectric constant metal gate structure.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The substrate further includes a gate conductive structure, which is located above and electrically connected to the high dielectric constant metal gate structure.
10. A semiconductor structure, characterized in that, include: The substrate includes a substrate, a gate structure located above the substrate, source and drain doped regions located on both sides of the gate structure, and a first dielectric layer covering the surface of the source and drain doped regions; A remaining support layer is located between adjacent gate structures and between the source and drain doped regions, and covers the surface of the substrate. The top surface of the remaining support layer is lower than the top surface of the gate structure. A second dielectric layer, which at least covers the remaining support layer, and whose top surface is at least flush with the top surface of the first dielectric layer, and whose material is the same as that of the first dielectric layer; The source / drain conductive plugs are electrically connected to the source / drain doped regions.
11. The semiconductor structure as claimed in claim 10, characterized in that, Also includes: The substrate conductive plug is electrically connected to the source / drain doped region.
12. The semiconductor structure as claimed in claim 10, characterized in that, The top surface of the remaining support layer is lower than the top surface of the source / drain doped region, or the top surface of the remaining support layer is flush with the top surface of the source / drain doped region.
13. The semiconductor structure as described in claim 10, characterized in that, The top surface of the second dielectric layer is flush with the top surface of the source / drain doped region.
14. The semiconductor structure as claimed in claim 10, characterized in that, Also includes; An isolation layer covers the second dielectric layer.
15. The semiconductor structure as described in claim 14, characterized in that, Also includes: A third dielectric layer covers the isolation layer.
16. The semiconductor structure as claimed in claim 11, characterized in that, The gate structure includes a high dielectric constant metal gate structure.
17. The semiconductor structure as claimed in claim 16, characterized in that, The substrate further includes a gate conductive structure, which is located above and electrically connected to the high dielectric constant metal gate structure.