Integrated circuit including a metal-insulator-metal type capacitor structure and corresponding manufacturing method

Abstract

An integrated circuit includes a semiconductor substrate, a conductive layer above the front surface of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal type capacitor structure is located in a trench within the pre-metal dielectric region. The capacitor structure includes a first metal layer electrically connected to the conductive layer, a second metal layer electrically connected to the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

Description

[0001] Priority claim

[0002] This application claims the priority benefit of French Patent Application No. 2011274, filed on November 3, 2020, the content of which is incorporated herein by reference in its entirety to the maximum extent permitted by law. Technical field

[0003] Embodiments and implementations relate to integrated circuits and, more particularly, to capacitive elements of integrated circuits. Background art

[0004] A major requirement for embodiments of capacitive elements is to have the highest possible capacitance value per unit of surface, known as "surface capacitance".

[0005] To increase the surface capacitance of capacitive structures of the metal oxide semiconductor (MOS) type, it has been proposed to form conductive electrodes by filling trenches extending vertically deep into the semiconductor substrate.

[0006] Increasing the depth of the trenches allows increasing the surface capacitance, but this method is limited on the one hand by the trench etching time, which is proportional to the depth of the trenches, and on the other hand by the fact that the tools for etching deep trenches are not necessarily available in a given production line, and integrating such tools into the production line can be very costly.

[0007] Therefore, it is desirable to increase the surface capacitance of capacitive elements according to techniques that are not very restrictive and compatible with the integrated circuit production chain that provides etched trenches with a limited depth. Summary of the invention

[0008] According to one aspect, there is provided, in this regard, an integrated circuit including a semiconductor substrate, a conductive layer above the front side of the substrate, a first metal track in a first metal level, a pre-metal dielectric region located between the conductive layer and the first metal level, and at least one capacitive structure located in the volume of the pre-metal dielectric region, the at least one capacitive structure being a metal-insulator-metal type capacitive structure. The metal-insulator-metal type capacitive structure includes: a first metal layer configured to be electrically connected to the conductive layer; a second metal layer configured to be electrically connected to the first metal track; and a dielectric layer between the first metal layer and the second metal layer.

[0009] The capacitive structure will be of the metal-insulator-metal (MIM) type, although capacitive elements conventionally designated by these terms are not normally located in the pre-metal dielectric region but in the last metal level of the interconnects, where the constraints (in particular, the spatial constraints) are different from those in the pre-metal dielectric region.

[0010] Thus, a metal-insulator-metal type capacitor structure located in a pre-metal dielectric region may experience spatial stress determined by other components formed on the substrate. However, the MIM type capacitor structure according to this aspect can be advantageously disposed in the free space of the pre-metal dielectric, but the underlying substrate surface is occupied by another component, for example, the other component is a capacitor element of MOS type as described above, or else a resistive element located in or on the substrate.

[0011] Therefore, the integration of the capacitor structure does not actually occupy any additional surface on the substrate, thus allowing to benefit from the additional capacitance interface and being "free" in terms of overall dimensions.

[0012] According to one embodiment, the conductive layer is made of polysilicon and includes a thin layer of metal silicide, and the first metal layer includes a diffusion barrier layer chemically bonded to the thin layer of metal silicide.

[0013] This allows to ensure a good electrical connection between the conductive layer and the first metal layer of each metal-insulator-metal capacitor structure.

[0014] According to one embodiment, each capacitor structure of metal-insulator-metal type is disposed in a trench in the volume of the pre-metal dielectric region, the first metal layer is conformal with the sidewalls and bottom of the trench, the dielectric layer is conformal with the sidewalls and bottom of the first metal layer, and the second metal layer is conformal with the sidewalls and bottom of the dielectric layer.

[0015] Thus, the metal, insulator, and metal layers of the capacitor structure are arranged to nest with each other in a U-shape and are arranged along the length of the trench so as to increase the size of the interface between the first conductive layer and the second conductive layer, thereby increasing the capacitance value of each capacitor structure.

[0016] According to one embodiment, the dielectric interface electrically insulates the conductive layer and the semiconductor substrate, and the conductive layer and the dielectric interface are configured to form a metal-oxide-semiconductor type capacitor structure with the semiconductor substrate.

[0017] Therefore, the conductive layer is not only used for electrically connecting the first metal layer of the MIM type capacitor structure, but also for forming the MOS type capacitor structure. Thus, the surface occupied on the substrate is used for both types of capacitor structures, thereby forming a capacitor element with a larger capacitance value using the same overall dimensions.

[0018] According to one embodiment, the conductive layer includes a horizontal portion covering the surface of the semiconductor substrate and includes at least one vertical portion extending perpendicularly into the substrate from said surface.

[0019] This embodiment is advantageous in terms of surface capacitance and in terms of the overall dimensions of the electrical connection between the conductive layer and the vertical and horizontal portions of the MOS capacitor structure.

[0020] According to one embodiment, the vertical portion of the conductive layer has a structure similar to that of the vertical gate of a buried access transistor, which is a memory cell of a non-volatile memory.

[0021] In other words, a co-integration of the fabrication of a MOS-type capacitor structure with the fabrication of a non-volatile memory (e.g., of the electrically erasable and programmable read-only memory (EEPROM) type) is proposed, which is advantageous especially in terms of cost.

[0022] According to one embodiment, the conductive layer is configured to be electrically connected to a second metal track of a first metal level, and the semiconductor substrate is configured to be electrically connected to a third metal track of the first metal level, and the second metal track and the third metal track can be coupled to each other or to a first metal track.

[0023] Thus, depending on the coupling of the metal tracks, in the same embodiment of the integrated circuit, only a MIM-type capacitor structure can be used, only a MOS-type capacitor structure can be used, or else two capacitor structures coupled in parallel can be used.

[0024] According to one embodiment, the conductive layer is located above a resistive conductive strip that belongs to a resistive element having two terminals, and the first metal track, the conductive layer, and the terminals of the resistive element are coupled so as to form a resistor-capacitor circuit with the at least one capacitor structure of the metal-insulator-metal type.

[0025] Again, the MIM-type capacitor structure is free in terms of the overall dimensions for forming an RC circuit at the location of the resistive strip.

[0026] According to another aspect, there is provided a method of manufacturing an integrated circuit, the method comprising: forming a conductive layer above the front side of a semiconductor substrate; forming a pre-metal dielectric region above the conductive layer; forming at least one capacitor structure called a metal-insulator-metal type capacitor structure in the volume of the pre-metal dielectric region, including: forming a first metal layer configured to be electrically connected to the conductive layer, forming a dielectric layer on the first metal layer, and forming a second metal layer on the dielectric layer; and forming a contact through the pre-metal dielectric region and forming a metal track of a first metal level above the pre-metal dielectric region, the contact being configured to electrically connect the second metal layer to the first metal track of the first metal level.

[0027] According to one embodiment, the conductive layer is formed of polysilicon. The formation of the first conductive layer includes silicidation, which forms a thin layer of metal silicide on the conductive layer, and the formation of the first metal layer includes the formation of a diffusion barrier layer. The method includes a non-oxidizing annealing step that is capable of generating a chemical bond between the diffusion barrier layer and the thin layer of metal silicide.

[0028] According to one embodiment, the formation of each capacitor structure of the metal-insulator-metal type includes etching trenches in the volume of the pre-metal dielectric region. The formation of the first metal layer includes conformal deposition conformal to the sides and bottom of the trenches. The formation of the dielectric layer includes conformal deposition conformal to the sides and bottom of the first metal layer. And the formation of the second metal layer includes over-deposition conformal to the sides and bottom of the dielectric layer and filling of each trench, followed by mechanical-chemical planarization (or chemical-mechanical polishing (CMP)), which removes the excess portion of the second metal layer outside the trenches.

[0029] According to one embodiment, the formation of the conductive layer includes the formation of a dielectric interface that electrically insulates the conductive layer and the semiconductor substrate, and the formation of the conductive layer is configured such that the conductive layer and the dielectric interface form a metal-oxide-semiconductor type capacitor structure with the semiconductor substrate.

[0030] According to one embodiment, the formation of the conductive layer includes: etching at least one trench that extends in the substrate perpendicular to the surface of the substrate; filling the at least one trench with a conductive material that overflows above a portion of the surface, such that the conductive layer includes a horizontal portion covering the surface and includes at least one vertical portion extending deeply into the substrate perpendicular to the surface.

[0031] According to one embodiment, the steps of etching the at least one trench and filling the at least one trench are carried out simultaneously with similar steps for forming a buried access transistor with a vertical gate in a method for manufacturing memory cells of a non-volatile memory.

[0032] According to one embodiment, the method includes: forming contacts configured to electrically connect the conductive layer to a second metal track of a first metal level, and forming contacts configured to electrically connect the semiconductor substrate to a third metal track of the first metal level, where the second metal track and the third metal track can be coupled to each other or to a first metal track.

[0033] According to one embodiment, the method includes forming a resistive conductive bar, the resistive conductive bar being intended to belong to a resistive element having two terminals, forming a conductive layer above the resistive conductive bar, and the method includes coupling a first metal track, the conductive layer, and the terminals of the resistive element so as to form a resistive-capacitive circuit with the at least one capacitive structure of the metal-insulator-metal type. Description of the Drawings

[0034] After examining the embodiments and implementations and the detailed description of the drawings, other advantages and features of the present invention will become apparent, and these embodiments and implementations are in no way restrictive, where:

[0035] Figure 1 Illustrates an example of an integrated circuit including a capacitive structure of the metal-dielectric-metal (MIM) type;

[0036] Figures 2 to 9 Illustrates the steps in the manufacturing method;

[0037] Figure 10 Is illustrated in perspective view a structure obtained by a method of the type described above with respect to Figures 2 to 9 description;

[0038] Figure 11 Illustrates Figure 10 a top view of the structure of;

[0039] Figure 12 and Figure 13 respectively illustrate Figure 10 and Figure 11 perspective and top views of alternatives of the integrated circuit structure shown in;

[0040] Figure 14 Illustrates the application of the capacitive structure with respect to Figure 1 description in the context of manufacturing a resistive-capacitive RC circuit. Detailed Description

[0041] Figure 1 Illustrates an example of an integrated circuit, which specifically includes a semiconductor substrate SUB typically made of silicon, a capacitive structure of the metal-dielectric-metal (MIM) type, and a metal track PM1.

[0042] Hereinafter, the "capacitive structure of the metal-dielectric-metal type" can be directly designated by referring to the reference numeral MIMCAP, that is, designated by the term "capacitive structure MIMCAP".

[0043] The front-end-of-line (FEOL) semiconductor portion includes a semiconductor substrate SUB and semiconductor components produced in and on the substrate from the front face FA of the substrate, such as transistors, diodes, or MOS-type capacitive elements. The front face FA of the substrate generally defines a horizontal plane, and is typically oriented vertically such that the "bottom" faces the volume of the substrate SUB and the "top" faces the exterior of the front face FA, where the components are formed at the front face FA.

[0044] The back-end-of-line (BEOL) interconnect portion includes a stack of metal levels M1. Each metal level includes: metal tracks PM1 that trace the path of the interconnect, vias that contact the metal tracks of adjacent metal levels, and inter-metal dielectric layers DIM1, CA1 that electrically insulate the metal tracks from adjacent metal levels. The final interconnect level is typically intended for packaging the integrated circuit package.

[0045] The middle-of-line (MEOL) portion located between the semiconductor portion FEOL and the interconnect portion BEOL includes a dielectric region DPM, which is commonly referred to as the pre-metal dielectric, for electrically separating and insulating the structures formed in the semiconductor portion FEOL from the first metal level M1 of the interconnect portion BEOL. Typically, metal contacts vertically pass through the pre-metal dielectric layer DPM to connect the components of the semiconductor portion FEOL to the metal tracks of the first metal level M1.

[0046] For example, the pre-metal dielectric layer DPM is made of phosphosilicate glass or optionally of silicon dioxide. A stop layer CA belonging to the pre-metal dielectric region DPM may be provided at the semiconductor portion FEOL to stop the etching of contact formation.

[0047] A capacitive structure MIMCAP is located in the portion MEOL, within the volume of the pre-metal dielectric region DPM.

[0048] The capacitive structure MIMCAP includes a stack of a first metal layer CM1, a dielectric layer CD, and a second metal layer CM2.

[0049] The first metal layer CM1 of each capacitive structure MIMCAP is electrically connected to a conductive layer PS belonging to the semiconductor portion FEOL. In this example, the conductive layer PS is located on the front face FA of the semiconductor substrate SUB.

[0050] The second metal layer CM2 of each capacitive structure MIMCAP is electrically connected to the first metal track PM1 via a contact CNT1.

[0051] In particular, the thickness of the dielectric layer CD located between the first metal layer CM1 and the second metal layer CM2 of each capacitive structure MIMCAP allows the capacitance value of the capacitive structure MIMCAP to be set.

[0052] As will be shown below with respect to Figures 2 to 9 or Figures 10 to 13 a trench (TRDPM) is formed in the volume of the pre-metal dielectric region DPM to accommodate the capacitive structure MIMCAP. The trench has a shape that is narrow in width (horizontally in the view of Figure 1 ), elongated in length (perpendicular to the view of Figure 1 ), and has a depth (vertically in the view of Figure 1 ) that is intended to allow the formation of a contact CNT1 between the top of the capacitive structure MIMCAP and the first metal level M1.

[0053] The trenches are formed to have the maximum possible density. In this regard, the lateral space between two trenches can also be made as small as possible.

[0054] Thus, the capacitive structures MIMCAP are arranged as laterally spaced and longitudinally extending parallel bars, the bottoms of which are in contact with the conductive layer PS and which are surrounded in the volume of the pre-metal dielectric region DPM.

[0055] For example, the first metal layer CM1 is formed of a thin layer of titanium nitride TiN, or alternatively by the superposition of a thin layer of titanium Ti and a thin layer of titanium nitride TiN (it should be noted that strictly speaking, titanium nitride is a ceramic, but is generally considered a metal compound in the semiconductor and microelectronics industries).

[0056] For example, the dielectric layer CD is formed of a metal oxide, advantageously selected for its high dielectric constant (compared to the reference dielectric constant of silicon dioxide), for example, such metal oxide being tantalum pentoxide Ta2O5 or other metal or silicon oxides or nitrides.

[0057] For example, the second metal layer CM2 is formed by the superposition of a thin layer of titanium Ti and a thin layer of titanium nitride TiN (or alternatively by a thin layer of titanium nitride TiN alone) and a body made of a metal such as tungsten W.

[0058] For example, the conductive layer PS is formed of polysilicon and advantageously includes, on its upper surface in electrical contact with the first metal layer CM1 of the capacitive structure MIMCAP, a thin layer of metal silicide SIM (for example, cobalt silicide CoSi2).

[0059] For example, the contact CNT1 includes the superposition of a thin diffusion barrier layer and a metal body. The thin diffusion barrier layer is made, for example, of titanium Ti and titanium nitride TiN, and the body is made of tungsten W.

[0060] In fact, the examples given above for the first metal layer CM1 and the second metal layer CM2 correspond to the use of a thin diffusion barrier layer for the metal contact CNT1, which is generally intended to limit the diffusion of metal from the contact into the materials of the semiconductor part FEOL while being conductive.

[0061] However, the thin diffusion barrier layer advantageously allows a chemical bond to be formed between the first metal layer CM1 and a thin layer of metal silicide SIM of the conductive polysilicon layer PS. The chemical bond is generated by an annealing stage and allows for a better electrical connection.

[0062] Thus, the use of the diffusion barrier material allows for an improvement in the electrical connection between the first metal layer CM1 of the capacitive structure MIMCAP and the conductive layer PS, and enables a stable and controlled capacitive effect.

[0063] In particular, the annealing stage after the deposition of the thin diffusion barrier layer causes an alloy reaction between the silicon of the metal silicide and the material (such as titanium) of the thin diffusion barrier layer. This reaction not only improves the via resistance between the thin diffusion barrier layer and the polysilicon, but also improves the reliability of such an electrical contact.

[0064] The structure thus produced has a lower risk of defects at the contact, and thus it is not necessary to conventionally connect the first metal layer CM1 of the capacitive structure MIMCAP to a specific metal wire. The first metal layer CM1 is actually directly connected to the conductive layer of polysilicon PS.

[0065] In summary, this allows for the simplification of the arrangement and manufacturing of various components without deteriorating the reliability, especially for optimizing the density of the capacitive structure.

[0066] The conductive layer PS can in turn be made, for example, in the same way as the gate of a MOS transistor or the electrode of a MOS capacitive element, and in this case, includes a dielectric interface OX that electrically insulates the conductive layer PS from the semiconductor substrate SUB.

[0067] In fact, the conductive layer PS and the dielectric interface OX can advantageously be specifically configured to form a capacitive structure of the metal-oxide-semiconductor MOSCAP type with the semiconductor substrate SUB.

[0068] Hereinafter, a "capacitive structure of the metal-oxide-semiconductor type" can be directly designated by referring to the reference numeral "MOSCAP", that is, by the term "capacitive structure MOSCAP".

[0069] Figures 2 to 9 Illustrates the result of the steps of an exemplary method for manufacturing the capacitive structure MIMCAP described with respect to Figure 1 the steps described. Figure 1 and Figures 2 to 9Common elements have the same reference numerals and will not be described in detail for each figure.

[0070] Figure 2 Illustrated is the result of manufacturing steps of a semiconductor front-end-of-line (FEOL) portion and a pre-metal dielectric region (DPM) in an example of manufacturing an integrated circuit including a MOS-type capacitor structure (MOSCAP).

[0071] The manufacturing of the capacitor structure MOSCAP includes forming a conductive layer P0 on a substrate SUB in the semiconductor FEOL portion. Thus, the conductive layer P0 is configured to form a capacitor structure, called a metal-oxide-semiconductor capacitor structure MOSCAP, with the semiconductor substrate SUB.

[0072] For example, as Figure 1 shown, the capacitor structure MOSCAP can be planar, but Figures 2 to 9 the example advantageously corresponds to a capacitor structure MOSCAP in which the conductive layer P0 includes a horizontal portion H covering the front face FA of the substrate SUB and includes at least one vertical portion V extending perpendicularly into the substrate SUB from the front face FA.

[0073] In this regard, the formation of the conductive layer P0 includes: etching trenches TRSUB extending in the substrate SUB perpendicular to the front face FA, and forming a dielectric interface OX on the front face FA and on the side and bottom of the etched trenches TRSUB in the substrate SUB. Thus, the dielectric interface OX will allow the capacitive interface between the conductive layer P0 and the semiconductor substrate SUB to be electrically insulated. Then, a conductive material P0, such as polysilicon, is used to fill the trenches TRSUB, and the conductive material P0 overflows above a portion of the surface FA. Then, in particular, the conductive material P0 is etched through a photolithographic mask so that the conductive layer P0 includes a horizontal portion H defined on the front face FA and includes a vertical portion V in the trenches TRSUB.

[0074] The horizontal portion H and the vertical portion V thus advantageously belong to a single monolithic structure, that is, made of a single block of material. Alternatively, the horizontal portion H and the vertical portion V can be formed separately and then electrically connected, so that the trenches TRSUB include a conductive material separated from the conductive material forming the conductive layer P0 and covering the trenches.

[0075] Furthermore, the steps of etching the at least one trench TRSUB and filling the at least one trench TRSUB can advantageously be carried out simultaneously with similar steps for forming a buried access transistor with a vertical gate in a method for manufacturing memory cells of a non-volatile memory.

[0076] In fact, the fabrication of the capacitive structure MOSCAP can be implemented concurrently with the step of etching a trench of a similar structure in the memory region of the semiconductor substrate and with the step of filling the etched trench with a conductive material of a similar nature to the vertical gate, which vertical gate belongs to the buried access transistor of the non-volatile memory cell. The memory cell typically further includes a floating gate state transistor coupled in series with the access transistor.

[0077] Silicidation of the conductive layer P0 of polysilicon allows for the formation of a thin layer of metal silicide SIM on the upper surface of the conductive layer P0.

[0078] Then, a pre-metal dielectric region DPM is formed above the front face FA of the conductive layer P0 and the substrate SUB. The formation of the pre-metal dielectric region DPM provides for: the formation of a stop layer CA made, for example, of silicon nitride, and the formation of the pre-metal dielectric volume itself made, for example, of phosphosilicate glass or silicon dioxide. The upper part of the pre-metal dielectric region DPM is planarized by mechanical-chemical planarization.

[0079] At this stage, the original method for fabricating the capacitive structure MOSCAP (wherein the fabrication of the capacitive structure MIMCAP is inscribed) would provide for the formation of metal contacts through the pre-metal dielectric region DPM.

[0080] Figure 3 Illustrated is the result of the etching step in the pre-metal dielectric layer DPM for the formation of the capacitive structure MIMCAP.

[0081] A mask MSK is used on the pre-metal dielectric region DPM, the mask MSK having an etching pattern including openings OUV obtained by lithography. The openings OUV have a shape elongated in length (perpendicular to Figure 3 the view) and are arranged in parallel, spaced apart in the width direction (horizontally in Figure 3 the view).

[0082] By means of anisotropic dry etching, such as reactive ion bombardment etching (e.g., reactive ion etching (RIE)), trenches TRDPM are opened in the volume of the pre-metal dielectric region DPM. The RIE etching is initially configured to: selectively etch the pre-metal dielectric material DPM made, for example, of silicon dioxide, and be stopped by the material of the stop layer CA located on the conductive layer P0, the stop layer CA being made, for example, of silicon nitride. Secondly, the RIE etching is configured to: selectively etch the stop layer CA in order to expose the silicided surface SIM of the conductive layer P0 at the bottom of the trenches TRDPM, without etching or etching very little the pre-metal dielectric material DPM made, for example, of silicon dioxide.

[0083] Thus, the trench TRDPM opened in the volume of the pre-metal dielectric part DPM will accommodate the capacitor structure MIMCAP.

[0084] In this example, the trench TRDPM opened in the pre-metal dielectric part DPM is aligned with the vertical part V of the conductive layer P0. Nevertheless, the trench TRDPM can be staggered between each vertical part V of the conductive layer P0, or have no specific relationship with the position of the vertical part V of the conductive layer P0.

[0085] Figure 4 Illustrated is the result of the steps of the superposition of the metal layer, insulating layer, and metal layer forming the capacitor structure MIMCAP after the mask MSK is selectively removed.

[0086] First, the first metal layer CM1 is deposited conformally, that is, with a substantially constant thickness conforming to the profile of the structure on which it is placed, that is, the first metal layer CM1 is deposited on the top of the pre-metal dielectric DPM, on the sides and the bottom of the trench TRDPM.

[0087] Thus, the first metal layer CM1 is in contact with the thin layer of the metal silicide SIM of the conductive layer P0.

[0088] The first metal layer CM1 includes at least one thin layer of, for example, titanium nitride, and optionally also includes a thin layer of titanium.

[0089] The formation of the first metal layer CM1 is carried out, for example, by physical vapor deposition (PVD) or by chemical vapor deposition (CVD) (including its variants, such as plasma-assisted (PECVD), at low pressure (LPCVD)) or by atomic layer deposition (ALD), etc.

[0090] The first metal layer CM1 is advantageously formed by steps similar to the formation of the diffusion barrier layer usually provided for metal contacts.

[0091] The dielectric layer CD is deposited conformally on the first metal layer CM1, and in particular conforms to the sides and the bottom of the first metal layer CM1 located in the trench TRDPM.

[0092] The dielectric layer CD includes, for example, tantalum oxide or another dielectric material, such as a metal or silicon oxide or nitride.

[0093] The formation of the dielectric layer CD is carried out, for example, by PVD or CVD.

[0094] The second metal layer CM2 is deposited so as to overfill the remaining free volume within the trench TRDPM. Thus, the second metal layer CM2 is electrically separated from the first metal layer CM1 by the dielectric layer CD.

[0095] Advantageously, the formation of the second metal layer CM2 includes depositing a thin layer of titanium and a thin layer of titanium nitride, or alternatively only depositing a thin layer of titanium nitride, and then filling the remaining free volume within the trench TRDPM with a metal such as tungsten in excess.

[0096] For reasons of readability of the drawings, Figures 4 to 9 details of the thin layer of titanium and the thin layer of titanium nitride are not shown.

[0097] The formation of the composition of the second metal layer CM2 is carried out, for example, by PVD or CVD.

[0098] All the components of the second metal layer CM2 can advantageously be formed by steps similar to those for forming the metal in contact with the diffusion barrier layer.

[0099] In fact, as previously mentioned with respect to Figure 2 and as will be mentioned below with respect to Figure 7 and Figure 8 appearing, the fabrication of the capacitive structure MIMCAP is incorporated into the integrated circuit manufacturing method when forming metal contacts. Thus, providing the formation of the first metal layer CM1 and the second metal layer CM2 using techniques similar or even identical to those used for forming metal contacts allows, on the one hand, the use of known and mastered techniques and, on the other hand, does not significantly modify the process of the integrated circuit production chain. In fact, in this case, the formation of the additional capacitive structure MIMCAP can use the same tools and reactors as those used in the conventional methods for manufacturing metal contacts.

[0100] Figure 5 Illustrates the result of a mechanical-chemical planarization step for removing the excess portions from the second metal layer CM2, the dielectric layer CD, and the first metal layer CM1 located on top of the pre-metal dielectric DPM. In addition, the mechanical-chemical planarization is configured to: remove a significant thickness Epol from the upper part of the pre-metal dielectric region DPM and from the upper part of the capacitive structure MIMCAP within the volume of the pre-metal dielectric region DPM.

[0101] Figure 6 Illustrates the result of depositing a thickness Edep of dielectric material DPM that is substantially equal to the thickness Epol removed by mechanical-chemical planarization to return to the original thickness of the pre-metal dielectric region DPM, that is, having substantially the same height as the pre-metal dielectric region obtained with respect to Figure 2 obtained.

[0102] Thus, the capacitive structure MIMCAP has a narrow shape in width (horizontally in the view of Figure 6 ), is elongated in length (perpendicular to the view of Figure 6 ), and has a depth (inFigure 6 in a vertical direction in the view of , the depth starting from the deviation of the thickness Edep from the top of the front metal dielectric region DPM until the conductive layer P0. The thickness deviation Edep will allow the formation of the contact CNT1 on top of the capacitive structure MIMCAP.

[0103] Figure 7 The figure shows Figure 2 the step of etching a hole to form a metal contact after the step of , as would be provided in a conventional method.

[0104] Anisotropic dry etching uses a mask MSKCNT, and the pattern of the mask MSKCNT defines an opening OUVCNT facing the second metal layer CM2 of the capacitive structure MIMCAP.

[0105] The alignment of the opening can tolerate an offset over a partial thickness of the dielectric layer CD without causing a short circuit between the second metal layer CM2 and the first metal layer CM1.

[0106] In fact, the opening will be sealed and filled with a conductive material, and the formation of the contact CNT1 will be provided to electrically connect the second metal layer CM2 of the capacitive structure MIMCAP, advantageously allowing the avoidance of forming a short circuit between the first metal layer CM1 and the second metal layer CM2.

[0107] However, alternatives to the steps described with respect to Figure 4 or Figure 5 can provide electrical insulation between the first metal layer CM1 and the second metal layer CM2 on the upper part of the capacitive structure MIMCAP. For example, Figure 4 the mechanical-chemical planarization on the structure of can be stopped by the horizontal part of the dielectric layer CD. Thus, a free opening will be obtained on top of the second metal layer CM2, but the first metal layer CM1 will remain covered by the dielectric layer CD. In this case, the second metal layer CM2 can be directly electrically contacted by the metal track PM1 at its free opening without the risk of short circuit with the first metal layer CM1. Moreover, the parts outside the production of the capacitive element MIMCAP of the stack of the first metal layer CM1, the dielectric layer CD, and the second metal layer CM2 can be etched.

[0108] Moreover, other openings OUVCNT are positioned opposite to other positions to be contacted in the partial FEOL, such as on the thin layer of the metal silicide SIMSUB of the contact point CNTSUB on the front face FA of the substrate SUB, or on the thin layer of the metal silicide of the conductive layer P0 (invisible in Figure 7 ).

[0109] Figure 8Illustrated is the result of forming a metal contact diffusion barrier layer on the sides and bottom of the opening OUVCNT, the metal contact diffusion barrier layer being, for example, a stack Ti / TiN of a thin layer of titanium and a thin layer of titanium nitride.

[0110] At this point in the method, the step of "filling with a barrier layer" (the term is taken from the common expression "barrier fill") is advantageously carried out, for example by means of a non-oxidizing annealing. The step of filling with a barrier layer "barrier fill" allows an alloy to be formed between the material of the thin diffusion barrier layer (such as titanium) and the material of the surface to be contacted (such as the silicon of the metal silicide SIM), in order to strengthen the electrical contact between these layers.

[0111] Thus, the step of filling with a barrier layer "barrier fill" particularly improves the electrical connection between the first metal layer CM1 of the capacitive structure MIMCAP and the thin layer of the metal silicide SIM of the conductive layer made of polysilicon P0.

[0112] Then, the metal bodies W of the contacts CNT1, CNT3 ( Figure 9 ) are formed, for example by means of an over-deposition of a metal W (usually tungsten) and by planarizing by mechanical-chemical planarization until reaching the top of the pre-metal dielectric region DPM.

[0113] Figure 9 Illustrated is the result of forming the first metal level M1.

[0114] In this example, the first metal level M1 includes metal tracks PM1, the metal tracks PM1 electrically connecting the second metal layer CM2 of the capacitive structure MIMCAP together via the first contact CNT1, and also electrically connecting the second metal layer CM2 to the substrate SUB via another contact CNT3.

[0115] Thus, in addition to the first capacitive interface of the capacitive structure MOSCAP between the conductive layer P0 and the substrate SUB, an additional capacitive interface between the conductive layer P0 and the substrate SUB is provided via the metal tracks PM1 by means of the capacitive structure MIMCAP, without occupying additional space on the substrate SUB.

[0116] Figure 10 Illustrated in perspective view is the structure obtained by a method of the type described above with respect to Figures 2 to 9 wherein the pre-metal dielectric region is made transparent.

[0117] Figure 11 Illustrated is Figure 10 a top view of the structure. The stacked elements are represented by transparency.

[0118] The coordinate system X, Y, Z orients the space in which Figure 10 andFigure 11 The above-mentioned horizontal lies in the XY plane, is longitudinal in the X direction and transverse in the Y direction, and the vertical is indicated by the Z direction. Figures 1 to 9 Therefore, it is represented in the YZ plane in this orientation.

[0119] As mentioned above regarding Figure 1 and Figures 2 to 9 the components described have the same reference numerals and will not be described in detail in their entirety.

[0120] Nonetheless, in the examples of Figure 10 and Figure 11 on the one hand, the capacitive structure MIMCAP is not aligned above the trench TRSUB of the capacitive element MOSCAP, but is positioned opposite the space between each trench TRSUB of the capacitive element MOSCAP.

[0121] On the other hand, it should be noted that the first metal track PM1 of the first metal level M1 is connected to the second metal layer CM2 of the capacitive structure MIMCAP via the first contact CNT1. The second metal track PM2 of the first metal level M1 is connected to the conductive layer P0 via the second contact CNT2. The third metal track PM3 of the first metal level M1 is connected to the region of the substrate called the active region ACT via the third contact CNT3, and the active region ACT contains the capacitive structure MOSCAP and is generally defined by the shallow isolation region STI.

[0122] Therefore, the first metal track PM1 constitutes the terminal of the first capacitive electrode E1, the second metal track PM2 constitutes the terminal of the second capacitive electrode E2, and the third metal track PM3 constitutes the terminal of the third capacitive electrode E3.

[0123] The capacitive structure MIMCAP includes the first electrode E1 and the second electrode E2, and the capacitive structure MOSCAP includes the second electrode E2 and the third electrode E3.

[0124] In the equivalent circuit diagram, the capacitive structure MIMCAP and the capacitive structure MOSCAP are connected to the common second electrode E2.

[0125] Therefore, by connecting the first electrode E1 and the third electrode E3 together, a parallel assembly of the capacitive structure MIMCAP and the capacitive structure MOSCAP is obtained. It is also possible to short-circuit the capacitive structure MIMCAP by connecting the first electrode E1 and the second electrode E2 together to use only the capacitive structure MOSCAP, or it is also possible to short-circuit the capacitive structure MOSCAP by connecting the second electrode E2 and the third electrode E3 together to use only the capacitive structure MIMCAP.

[0126] In other words, this allows the capacitance value of the circuit to be modulated by choosing to use either one of the two capacitor structures MIMCAP, MOSCAP or a combination thereof.

[0127] Finally, it should be noted that in Figure 10 and Figure 11 In the example of, the longitudinal ends of the capacitor structure MIMCAP are positioned substantially opposite to the definition of the active region ACT by the insulating trench STI. Thus, the first contact CNT1 is positioned towards the inside of the active region ACT, while the second contact CNT2 is positioned towards the outside of the active region ACT, above the insulating trench STI.

[0128] Figure 12 and Figure 13 illustrate Figure 10 and Figure 11 Alternative structures of the integrated circuit shown in.

[0129] In this alternative, the capacitor structure MIMCAP extends longitudinally towards the outside of the active region ACT, extending above the insulating trench STI. Thus, the first contact CNT1 is located outside the conductive layer P0, while the second contact CNT2 is located between the first contact CNT1 and the active region ACT, above the insulating trench STI. The second contact CNT2 is positioned in the lateral space between the capacitor structures MIMCAP.

[0130] This particularly allows the length of the capacitor structure MIMCAP to be increased and thus the capacitance value of the capacitor structure MIMCAP to be increased.

[0131] The other elements of the integrated circuit are the same as those shown in Figure 10 and Figure 11 in the example.

[0132] Figure 14 illustrates an example of the application of the metal - dielectric - metal "MIM" type capacitor structure MIMCAP described with respect to Figure 1 in the context of manufacturing a resistor - capacitor RC circuit. The common elements previously described with respect to Figure 1 have the same reference numerals and will not be described in full again.

[0133] In this example, the conductive layer PS of the semiconductor front - end - of - line FEOL is placed on another conductive layer P1, which is referred to as the resistor conductor strip P1 and belongs to the resistor element RES.

[0134] The resistor conductor strip P1 is also made of polysilicon, for example, and is formed on the insulating region STI, which is of the shallow insulating trench type, for example.

[0135] The resistive semiconductor bar P1 is configured to have a resistance value and includes two open ends. The open ends include thin layers of metal silicide SIM, which are electrically coupled via respective contacts CNTI, CNTO to metal tracks PMI, PMO of the first metal level M1. The metal tracks PMI, PMO thus implement the terminals IN, OUT of the resistive element RES.

[0136] The conductive layer PS is electrically insulated from the resistive conductor bar P1 by a dielectric thickness ONO, which includes a stack of, for example, an oxide layer, a nitride layer, and a silicon oxide layer.

[0137] Advantageously, in particular, the fabrication of the resistive conductor bar P1, the dielectric thickness ONO, and the conductive layer PS can be carried out in the manner of fabricating a floating-gate transistor, or even simultaneously during the same steps of the fabrication method.

[0138] According to this production of the semiconductor front-end-of-line (FEOL), by means of a method of the type described above with respect to Figures 3 to 9 a capacitive structure MIMCAP is fabricated in the pre-metal dielectric region DPM.

[0139] Thus, by electrically coupling the first electrode E1 of the capacitive structure MIMCAP to the terminal OUT (referred to as the output terminal) of the resistive element RES, and by electrically coupling the second terminal E2 of the capacitive structure MIMCAP to a reference potential (i.e., ground), the components of the circuit diagram of an RC series resistor-capacitor circuit are obtained. Figure 14 The output terminal OUT forms the output of the RC series resistor-capacitor circuit, while the other terminal IN of the resistive element RES forms the input of the RC series resistor-capacitor circuit.

[0140] Nonetheless, by coupling the first electrode E1 of the capacitive structure MIMCAP to the terminal IN of the resistive element RES, and by electrically coupling the second electrode E2 of the capacitive structure MIMCAP to the terminal OUT of the resistive element RES, a parallel resistor-capacitor circuit component is obtained.

[0141] Thus, due to the advantageous production of the capacitive structure MIMCAP in the volume of the pre-metal dielectric region, a resistor-capacitor (RC) circuit including the resistive element RES and the capacitive element MIMCAP can be produced on the surface of a substrate SUB that is no larger than the surface occupied by the resistive element RES alone.

[0142] Moreover, the present invention is not limited to the embodiments and implementations described with respect to Figures 1 to 14 but encompasses all variations, for example, the materials selected can be different from the examples given above, or alternatively, the elements of the semiconductor FEOL located beneath the conductive layers PS, P0 can be different and applied to other electrical components.

Claims

1. An integrated circuit, comprising: a semiconductor substrate; a conductive layer above the front side of the semiconductor substrate; a first metal track in a first metal layer; a dielectric region between the conductive layer and the first metal layer; and at least one metal-insulator-metal capacitor structure in a trench opening within the dielectric region, the at least one metal-insulator-metal capacitor structure comprising: a first metal layer configured to be electrically connected to the conductive layer, a second metal layer configured to be electrically connected to the first metal track, and a dielectric layer between the first metal layer and the second metal layer; a dielectric interface electrically insulating between the conductive layer and the semiconductor substrate, wherein the conductive layer and the dielectric interface are configured to form a metal-oxide-semiconductor type capacitor structure with the semiconductor substrate.

2. The integrated circuit according to claim 1, wherein the conductive layer is made of polysilicon and includes a layer of metal silicide, and wherein the first metal layer includes a diffusion barrier layer chemically bonded to the layer of metal silicide.

3. The integrated circuit according to claim 1, wherein the first metal layer of the at least one metal-insulator-metal capacitor structure is conformal with the side and bottom of the trench opening, wherein the dielectric layer is conformal with the surface of the first metal layer, and wherein the second metal layer is conformal with the surface of the dielectric layer.

4. The integrated circuit according to claim 1, wherein the conductive layer includes a horizontal portion covering the surface of the semiconductor substrate and includes at least one vertical portion extending perpendicularly to the surface into the semiconductor substrate in depth.

5. The integrated circuit according to claim 4, wherein the at least one vertical portion of the conductive layer has a structure corresponding to the vertical gate of a buried access transistor, the buried access transistor belonging to a memory cell of a non-volatile memory.

6. The integrated circuit according to claim 1, wherein the conductive layer is electrically connected to a second metal track of the first metal layer, and wherein the semiconductor substrate is electrically connected to a third metal track of the first metal layer, and wherein the second metal track and the third metal track are electrically connected to each other.

7. The integrated circuit according to claim 1, wherein the conductive layer is electrically connected to a second metal track of the first metal layer, and wherein the semiconductor substrate is electrically connected to a third metal track of the first metal layer, and wherein the second metal track and the third metal track are electrically connected to the first metal track.

8. The integrated circuit according to claim 1, further comprising a resistive conductive bar belonging to a resistive element having two terminals, wherein the conductive layer is above the resistive conductive bar, and wherein the first metal track, the conductive layer, and the terminals of the resistive element are electrically connected to form a resistor-capacitor circuit with the at least one capacitor structure of the metal-insulator-metal type.

9. A method for manufacturing an integrated circuit, comprising: A conductive layer is formed above the front side of the semiconductor substrate; A dielectric region is formed above the conductive layer; At least one capacitor structure of the metal-insulator-metal type is formed in a trench within the dielectric region by: forming a first metal layer configured to be electrically connected to the conductive layer, forming a dielectric layer on the first metal layer, and forming a second metal layer on the dielectric layer; A contact is formed through the dielectric region; And A metal track of the first metal layer level is formed on the dielectric region; Wherein the contact electrically connects the second metal layer to the first metal track of the first metal layer level; Wherein forming the conductive layer includes forming a dielectric interface that electrically insulates the conductive layer from the semiconductor substrate, and wherein the conductive layer and the dielectric interface form a capacitor structure of the metal-oxide-semiconductor type with the semiconductor substrate.

10. The method according to claim 9, wherein the conductive layer is formed of polysilicon, wherein forming the conductive layer includes silicidation, the silicidation forming a thin layer of metal silicide on the conductive layer, and wherein forming the first metal layer includes forming a diffusion barrier layer, the method further comprising: Performing a non-oxidizing annealing to generate a chemical bond between the diffusion barrier layer and the thin layer of metal silicide.

11. The method according to claim 9, further comprising etching the trench in the dielectric region, and wherein forming the first metal layer includes performing a conformal deposition conformal to the sides and bottom of the trench, wherein forming the dielectric layer includes performing a conformal deposition conformal to the surface of the first metal layer, and wherein forming the second metal layer includes performing an over-deposition conformal to the dielectric layer and filling the trench; the method further comprises performing a chemical-mechanical planarization to remove the excess portion of the second metal layer.

12. The method according to claim 9, wherein forming the conductive layer comprises: Etching at least one trench that extends in depth into the semiconductor substrate perpendicular to the surface of the semiconductor substrate; Filling the at least one trench with a conductive material that overflows above a portion of the surface, wherein the conductive layer includes a horizontal portion covering the surface and includes at least one vertical portion extending deeply perpendicular to the surface into the semiconductor substrate.

13. The method according to claim 12, wherein etching the at least one trench and filling the at least one trench are performed simultaneously with the following steps: etching and filling to form a buried access transistor with a vertical gate for a memory cell of a non-volatile memory.

14. The method according to claim 9 further comprises: Forming a contact to electrically connect the conductive layer to a second metal track of the first metal layer level, and forming a contact to electrically connect the semiconductor substrate to a third metal track of the first metal layer level, wherein the second metal track and the third metal track are electrically connected to each other.

15. The method according to claim 9 further comprises: Form contacts to electrically connect the conductive layer to a second metal track of the first metal level and to electrically connect the semiconductor substrate to a third metal track of the first metal level, wherein the second and third metal tracks are electrically connected to the first metal track.

16. The method according to claim 9 further comprises: Form a resistive conductive bar of a resistive element having two terminals, wherein the conductive layer is formed over the resistive conductive bar; And electrically connect the first metal track, the conductive layer, and the terminals of the resistive element so as to form a resistor-capacitor circuit with the at least one capacitor structure of the metal-insulator-metal type.

17. An integrated circuit, comprising: A semiconductor substrate having a front side; A dielectric region over the front side; A first metal level over the dielectric region; A conductive layer between the front side and the dielectric region; Wherein the dielectric region includes a plurality of trench openings extending through the dielectric region to an upper surface of the conductive layer; A metal-insulator-metal capacitor structure in each trench opening, wherein each metal-insulator-metal capacitor structure includes: a first metal layer lining sidewalls and a bottom of each trench opening and further in electrical contact with the upper surface of the conductive layer; a dielectric layer over the first metal layer; and a second metal layer over the dielectric layer; Electrical connection of the second metal layer of each metal-insulator-metal capacitor structure to the first metal level; and An additional dielectric layer between the conductive layer and the front side of the semiconductor substrate; wherein the conductive layer, the additional dielectric layer, and the semiconductor substrate form a metal-oxide-semiconductor type capacitor structure.

18. The integrated circuit according to claim 17, wherein the conductive layer comprises: A polysilicon layer; And a silicide layer; Wherein the first metal layer is in electrical contact with the silicide layer.

19. The integrated circuit of claim 17, wherein the semiconductor substrate includes substrate trenches extending from the front side into the semiconductor substrate, and wherein the conductive layer includes a horizontal portion extending over the front side of the semiconductor substrate and a vertical portion within the substrate trenches.

20. The integrated circuit of claim 19, wherein the additional dielectric layer lines sidewalls and a bottom of the substrate trenches.

21. The integrated circuit of claim 17, further comprising: A resistive track between the front side and the conductive layer; And An insulating layer between the resistive track and the conductive layer; The resistive track having a first terminal and a second terminal, wherein the first terminal is electrically connected to each metal-insulator-metal capacitor structure.

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