Semiconductor device and method for manufacturing semiconductor device

Abstract

The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. A semiconductor device includes: a laminate including a conductive pattern and an insulating pattern; a cell plug that passes through the laminate; a semiconductor layer; a peripheral transistor arranged on the semiconductor layer; a first conductor that couples the peripheral transistor to the cell plug; a second conductor that is coupled to the conductive pattern; a through plug that is coupled to the second conductor; and a through gate that surrounds the through plug, wherein the through gate is arranged at substantially the same height as the semiconductor layer.

Description

Technical Field

[0001] Various embodiments of the present invention generally relate to semiconductor devices and methods of manufacturing such semiconductor devices, and more specifically, to a three-dimensional semiconductor device and a method of manufacturing such a three-dimensional semiconductor device. Background Technology

[0002] Semiconductor memory devices may include memory cells for storing data. Because three-dimensional semiconductor memory devices include memory cells arranged in three dimensions, the number of memory cells per unit area of ​​the substrate can be increased.

[0003] The number of memory cells stacked on top of each other can be increased to improve the integration density of three-dimensional semiconductor memory devices. However, as the number of stacked memory cells increases, the operational reliability of three-dimensional semiconductor memory devices may decrease. Summary of the Invention

[0004] Various embodiments relate to a semiconductor device with a reduced size and a method of manufacturing the semiconductor device.

[0005] According to an embodiment, a semiconductor device may include: a stack including conductive patterns and insulating patterns; a cell plug passing through the stack; a semiconductor layer; a peripheral transistor disposed on the semiconductor layer; a first conductor connecting the peripheral transistor to the cell plug; a second conductor connecting to the conductive patterns; a through plug connecting to the second conductor; and a through gate surrounding the through plug, wherein the through gate is disposed at substantially the same height as the semiconductor layer.

[0006] According to an embodiment, a semiconductor device may include: a stack including conductive and insulating patterns; a cell plug passing through the stack; a semiconductor layer; a peripheral transistor disposed on the semiconductor layer; a first conductor connecting the peripheral transistor to the cell plug; a second conductor connecting to the conductive patterns; a through plug connecting to the second conductor; and a through gate surrounding the through plug, wherein the through gate comprises the same material as the semiconductor layer.

[0007] According to an embodiment, a semiconductor device may include: a stack comprising a plurality of conductive patterns and a plurality of insulating patterns alternately stacked; a unit plug passing through the stack; a plurality of through plugs electrically connected to the conductive patterns, the plurality of through plugs including a first through plug disposed in a first direction and a second through plug disposed in the first direction; a first through gate surrounding the first through plug; a second through gate surrounding the second through plug; and a separation structure insulating the first through gate from the second through gate.

[0008] According to an embodiment, a method of manufacturing a semiconductor device may include the following steps: forming a laminate including conductive patterns and insulating patterns; forming a cell plug through the laminate; forming a substrate including a first region and a second region on the first region; forming a through plug surrounded by the substrate; electrically connecting the through plug to the conductive patterns; removing the first region from the substrate to expose a portion of the through plug; and forming a contact connected to said portion of the through plug. Attached Figure Description

[0009] Figure 1A This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure;

[0010] Figure 1B It is along Figure 1A A cross-sectional view taken by line A1-A1';

[0011] Figure 1C This is a plan view showing the semiconductor layer and the gate of a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 1D yes Figure 1B A magnified view of region A;

[0013] Figure 1E yes Figure 1B A magnified view of region B;

[0014] Figure 2A , Figure 3 , Figure 4A , Figure 5A , Figure 6A , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure;

[0015] Figure 2B It is along Figure 2AA cross-sectional view taken from line A2-A2';

[0016] Figure 4B It is along Figure 4A A cross-sectional view taken from line A3-A3';

[0017] Figure 5B It is along Figure 5A A cross-sectional view taken by line A4-A4';

[0018] Figure 6B It is along Figure 6A A cross-sectional view taken from line A5-A5';

[0019] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure; and

[0020] Figure 14 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0021] The specific structural or functional descriptions shown are merely examples of embodiments of the concepts disclosed in this specification to illustrate examples of embodiments of the concepts. Examples of embodiments of the concepts may be implemented in various forms, but these descriptions are not limited to the examples of embodiments described in this specification.

[0022] Figure 1A This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is along Figure 1A The cross-sectional view taken by line A1-A1'. Figure 1C This is a plan view showing the semiconductor layer and the gate of a semiconductor device according to an embodiment of the present disclosure. Figure 1D yes Figure 1B A magnified view of region A. Figure 1E yes Figure 1B A magnified view of region B.

[0023] Reference Figures 1A-1C A semiconductor device may include a cell region CER and a connection region COR. In a plan view defined by a first direction D1 and a second direction D2, the cell region CER and the connection region COR may be distinguishable from each other. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be orthogonal to each other.

[0024] The semiconductor device may include a source structure SOS. The source structure SOS may be in the form of a plate extending along a plane defined along a first direction D1 and a second direction D2. The source structure SOS may include a conductive material. For example, the source structure SOS may include doped polysilicon.

[0025] According to an embodiment, the source structure SOS may be disposed on a first substrate (not shown) supporting the source structure SOS. The first substrate may have the shape of a plate extending along a plane defined in a first direction D1 and a second direction D2. For example, the first substrate may be a semiconductor substrate.

[0026] A stacked structure STA can be disposed on the source structure SOS. The stacked structure STA may include conductive patterns CP and insulating patterns IP alternately stacked on a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. For example, the third direction D3 may be orthogonal to the first direction D1 and the second direction D2.

[0027] The conductive pattern CP can be used as a word line or select line in a semiconductor device. The conductive pattern CP may include a conductive material. The insulating pattern IP may include an insulating material. For example, the insulating pattern IP may include an oxide.

[0028] The laminate STA may include a stepped structure STE. The stepped structure STE may be defined by a conductive pattern CP and an insulating pattern IP of the laminate STA. The conductive pattern CP and the insulating pattern IP of the laminate STA may be formed in a stepped manner to form the stepped structure STE. The stepped structure STE may be arranged in a connection region COR.

[0029] A first insulating layer 110 may be provided to cover the laminate STA. The first insulating layer 110 may cover the stepped structure STE of the laminate STA. The first insulating layer 110 may include an insulating material. For example, the first insulating layer 110 may include an oxide or a nitride.

[0030] Cell plugs (CEPs) can be formed through the stack-up STA. Cell plugs (CEPs) can extend onto the third direction D3. Cell plugs (CEPs) can be located within the cell region CER. Each cell plug (CEP) may include a fill layer F1, a channel layer CL surrounding the fill layer F1, and a memory layer MEL surrounding the channel layer CL.

[0031] The filler layer F1 may extend onto D3. The filler layer F1 may include an insulating material. For example, the filler layer F1 may include an oxide.

[0032] The channel layer CL may extend onto the third direction D3. The channel layer CL may include a semiconductor material. For example, the channel layer CL may include polysilicon. The channel layer CL may be coupled to the source structure SOS. The channel layer CL may contact the source structure SOS. The channel layer CL may be electrically coupled to the source structure SOS.

[0033] The memory layer MEL may extend onto D3. The memory layer MEL may include a tunnel insulating layer surrounding the channel layer CL, a data storage layer surrounding the tunnel insulating layer, and a barrier layer surrounding the data storage layer. The tunnel insulating layer may include a material that allows charge tunneling. For example, the tunnel insulating layer may include an oxide. According to one embodiment, the data storage layer may include a material that traps charge. For example, the data storage layer may include a nitride. According to another embodiment, the data storage layer may include various types of materials depending on the data storage method. For example, the data storage layer may include silicon, a phase change material, or nanodots. The barrier layer may include a material capable of blocking charge movement. For example, the barrier layer may include an oxide. The memory layer MEL may be spaced apart from the source structure SOS. A portion of an insulating pattern IP may be interposed between the memory layer MEL and the source structure SOS.

[0034] A second insulating layer 120 may be provided to cover the first insulating layer 110. The second insulating layer 120 may include an insulating material. For example, the second insulating layer 120 may include an oxide or a nitride.

[0035] A third insulating layer 130 may be provided to cover the second insulating layer 120. The third insulating layer 130 may include an insulating material. For example, the third insulating layer 130 may include an oxide or a nitride.

[0036] A bit line contact structure BCS can be formed through the first insulating layer 110 and the second insulating layer 120. The bit line contact structure BCS can be disposed in the cell region CER. The bit line contact structure BCS can be coupled to the cell plug CEP. The bit line contact structure BCS can be electrically coupled to the channel layer CL of the cell plug CEP. The bit line contact structure BCS may include a first bit contact BC1 in the first insulating layer 110 and a second bit line contact BC2 in the second insulating layer 120. The first bit contact BC1 can be coupled to the cell plug CEP, and the second bit line contact BC2 can be coupled to the first bit contact BC1. Each of the first bit contact BC1 and the second bit line contact BC2 of the bit line contact structure BCS may include a conductive material.

[0037] The bit line BL may be disposed in the third insulating layer 130. The bit line BL may be disposed in the cell region CER. The bit line BL may extend in the second direction D2. The bit lines BL may be spaced apart from each other in the first direction D1. The bit line BL may be electrically connected to the cell plug CEP through the bit line contact structure BCS. The bit line BL may be connected to the second bit line contact BC2 of the bit line contact structure BCS. The bit line BL may include a conductive material.

[0038] A word line contact structure (WCS) can be formed passing through a first insulating layer 110, a second insulating layer 120, and a third insulating layer 130. The word line contact structure (WCS) can be disposed in a connection region (COR). The word line contact structure (WCS) can be coupled to a conductive pattern (CP). The word line contact structure (WCS) can be electrically coupled to the conductive pattern (CP). The word line contact structure (WCS) may include a first word line contact (WC1) penetrating the first insulating layer 110, a second word line contact (WC2) in the second insulating layer 120, and a word line pad (WP) in the third insulating layer 130. The first word line contact (WC1) can be coupled to the conductive pattern (CP), the second word line contact (WC2) can be coupled to the first word line contact (WC1), and the word line pad (WP) can be coupled to the second word line contact (WC2). The first word line contact (WC1), the second word line contact (WC2), and the word line pad (WP) of the word line contact structure (WCS) may include a conductive material.

[0039] A fourth insulating layer 140 may be provided to cover the third insulating layer 130. The fourth insulating layer 140 may include an insulating material. For example, the fourth insulating layer 140 may include an oxide or a nitride.

[0040] A fifth insulating layer 150 may be provided to cover the fourth insulating layer 140. The fifth insulating layer 150 may include an insulating material. For example, the fifth insulating layer 150 may include an oxide or a nitride.

[0041] A sixth insulating layer 160 may be provided to cover the fifth insulating layer 150. The sixth insulating layer 160 may include an insulating material. For example, the sixth insulating layer 160 may include an oxide or a nitride.

[0042] A first bonding structure BDS1 and a second bonding structure BDS2 can be formed through the fourth insulating layer 140. The first bonding structure BDS1 can be disposed in the cell region CER. The second bonding structure BDS2 can be disposed in the connection region COR. The first bonding structure BDS1 can be connected to the bit line BL. The first bonding structure BDS1 can be electrically connected to the bit line BL. The first bonding structure BDS1 may include a first bonding contact BDC1 connected to the bit line BL and a first bonding pad BDP1 connected to the first bonding contact BDC1. The first bonding pad BDP1 and the first bonding contact BDC1 of the first bonding structure BDS1 may include conductive material. The width of the first bonding pad BDP1 may decrease toward the stack STA and the cell plug CEP, meaning that the first bonding pad BDP1 tapers in the direction of the stack STA and the cell plug CEP to have a reduced width. For example, the width of the first bonding pad BDP1 in the first direction D1 may decrease toward the stack STA and the cell plug CEP.

[0043] The second bonding structure BDS2 may be connected to the word line pad WP of the word line contact structure WCS. The second bonding structure BDS2 may be electrically connected to the word line pad WP of the word line contact structure WCS. The second bonding structure BDS2 may include a second bonding contact BDC2 connected to the word line pad WP of the word line contact structure WCS and a second bonding pad BDP2 connected to the second bonding contact BDC2. The second bonding pad BDP2 and the second bonding contact BDC2 of the second bonding structure BDS2 may include conductive material. The width of the second bonding pad BDP2 may decrease towards the laminate STA, meaning that the second bonding pad BDP2 tapers in the direction of the laminate STA to have a reduced width. For example, the width of the second bonding pad BDP2 in the first direction D1 may decrease towards the laminate STA.

[0044] A third bonding structure BDS3 can be formed passing through the fifth insulating layer 150 and the sixth insulating layer 160. The third bonding structure BDS3 can be disposed in the cell region CER. The third bonding structure BDS3 may include a third bonding pad BDP3 and a third bonding contact BDC3. The third bonding pad BDP3 of the third bonding structure BDS3 can be connected to the first bonding pad BDP1 of the first bonding structure BDS1. The third bonding pad BDP3 of the third bonding structure BDS3 can be electrically connected to the first bonding pad BDP1 of the first bonding structure BDS1. The third bonding pad BDP3 of the third bonding structure BDS3 can be connected to the first bonding pad BDP1 of the first bonding structure BDS1. The third bonding contact BDC3 of the third bonding structure BDS3 can be connected to the third bonding pad BDP3. The third bonding contact BDC3 of the third bonding structure BDS3 may include a conductive material.

[0045] The width of the third bonding pad BDP3 can increase toward the stack-up STA and the cell plug CEP. For example, the width of the third bonding pad BDP3 in the first direction D1 can increase toward the stack-up STA and the cell plug CEP.

[0046] A fourth bonding structure BDS4 may be formed through the fifth insulating layer 150. The fourth bonding structure BDS4 may be disposed in the connection region COR. The fourth bonding structure BDS4 may include a fourth bonding pad BDP4 and a fourth bonding contact BDC4. The fourth bonding pad BDP4 of the fourth bonding structure BDS4 may be connected to the second bonding pad BDP2 of the second bonding structure BDS2. The fourth bonding pad BDP4 of the fourth bonding structure BDS4 may be electrically connected to the second bonding pad BDP2 of the second bonding structure BDS2. The fourth bonding pad BDP4 of the fourth bonding structure BDS4 may be connected to the second bonding pad BDP2 of the second bonding structure BDS2. The fourth bonding contact BDC4 may be connected to the fourth bonding pad BDP4. The fourth bonding pad BDP4 and the fourth bonding contact BDC4 of the fourth bonding structure BDS4 may include conductive material.

[0047] The width of the fourth bonding pad BDP4 can increase toward the stack STA. For example, the width of the fourth bonding pad BDP4 in the first direction D1 can increase toward the stack STA.

[0048] A seventh insulating layer 170 may be provided to cover the sixth insulating layer 160. The seventh insulating layer 170 may include an insulating material. For example, the seventh insulating layer 170 may include an oxide or a nitride.

[0049] A semiconductor layer SML may be provided, covering a portion of the seventh insulating layer 170. The semiconductor layer SML may be disposed within the cell region CER. The semiconductor layer SML may comprise a semiconductor material. For example, the semiconductor layer SML may comprise doped polysilicon. For example, the semiconductor layer SML may be doped with a P-type impurity.

[0050] A through-gate PAG may be provided, covering another portion of the seventh insulating layer 170. The through-gate PAG may be disposed within the connection region COR. The through-gate PAG may comprise the same material as the semiconductor layer SML. The through-gate PAG may comprise a semiconductor material. For example, the through-gate PAG may comprise doped polysilicon. For example, the impurity doped into the through-gate PAG may be a P-type impurity.

[0051] The gate PAG can be located at the same height as the semiconductor layer SML. For example, the gate PAG and the semiconductor layer SML can be located on the upper surface of the seventh insulating layer 170. The semiconductor layer SML may include a first surface SF1 facing the stack STA and a second surface SF2 opposite to the first surface SF1. The gate PAG may include a third surface SF3 facing the stack STA and a fourth surface SF4 opposite to the third surface SF3. The first surface SF1 of the semiconductor layer SML may be the lower surface of the semiconductor layer SML. The second surface SF2 of the semiconductor layer SML may be the upper surface of the semiconductor layer SML. The third surface SF3 of the gate PAG may be the lower surface of the gate PAG. The fourth surface SF4 of the gate PAG may be the upper surface of the gate PAG. The first surface SF1 of the semiconductor layer SML may have substantially the same height as the third surface SF3 of the gate PAG. The second surface SF2 of the semiconductor layer SML may have substantially the same height as the fourth surface SF4 of the gate PAG.

[0052] The first contact CT1 and the first metal wire ML1 may be disposed in the seventh insulating layer 170. The first contact CT1 and the first metal wire ML1 may be disposed in the cell region CER. The first contact CT1 and the first metal wire ML1 may be connected to each other. The first metal wire ML1 may be connected to the third bonding contact BDC3 of the third bonding structure BDS3. The first contact CT1 and the first metal wire ML1 may include conductive material.

[0053] The peripheral transistor TE can be disposed between the semiconductor layer SML and the seventh insulating layer 170. The peripheral transistor TE can be disposed within the cell region CER. The peripheral transistor TE can be disposed on the first surface SF1 of the semiconductor layer SML. The peripheral transistor TE can constitute the peripheral circuitry of the semiconductor device. For example, the peripheral transistor TE can constitute the page buffer of the semiconductor device.

[0054] Each peripheral transistor TE may include an impurity region IR, a gate insulating layer GI, and a gate electrode GM. The impurity region IR can be formed by doping the semiconductor layer SML with impurities, such that the conductivity type or doping concentration of the impurity region IR may be different from the conductivity type or doping concentration of the semiconductor layer SML.

[0055] The impurity region IR can be coupled to the first contact CT1. The impurity region IR can contact the first contact CT1. The gate insulating layer GI can include an insulating material. For example, the gate insulating layer GI can include an oxide. The gate electrode GM can be coupled to the first contact CT1. The gate electrode GM can contact the first contact CT1. The gate electrode GM can include a conductive material.

[0056] An isolation layer IS may be disposed within the semiconductor layer SML. The isolation layer IS electrically insulates the peripheral transistors TE from each other. The isolation layer IS may include an insulating material. For example, the isolation layer IS may include an oxide.

[0057] Each of the first contact CT1, the first metal line ML1, the third bonding structure BDS3, the first bonding structure BDS1, the bit line BL, and the bit line contact structure BCS can be defined as a first conductor CB1. The peripheral transistor TE can be connected to the cell plug CEP via the first conductor CB1. In other words, the peripheral transistor TE can be connected to the cell plug CEP via the first contact CT1, the first metal line ML1, the third bonding structure BDS3, the first bonding structure BDS1, the bit line BL, and the bit line contact structure BCS. The peripheral transistor TE can be connected to the cell plug CEP via the first conductor CB1.

[0058] A separation structure DST can be provided that passes through the sixth insulating layer 160 and the seventh insulating layer 170. The separation structure DST can be disposed in the connection region COR. The separation structure DST may include a first separator DP1 extending in a first direction D1 and a second separator DP2 extending in a second direction D2. The first separator DP1 and the second separator DP2 can be coupled to each other. The second separator DP2 can be coupled to one end of the first separator DP1. According to... Figure 1A and Figure 1C In the plan view, the split structure DST can have a T shape.

[0059] The semiconductor layer SML and the gate PAG can be separated from each other by a second separator DP2 of the separation structure DST. The semiconductor layer SML and the gate PAG can be spaced apart from each other by the second separator DP2 of the separation structure DST. The second separator DP2 of the separation structure DST can be disposed between the semiconductor layer SML and the gate PAG. The semiconductor layer SML and the gate PAG can be spaced apart from each other in the first direction D1, and the second separator DP2 of the separation structure DST is inserted between them.

[0060] The gate PAGs can be separated from each other by the first separator DP1 of the separation structure DST. The gate PAGs separated by the first separator DP1 can be defined as a first gate PAG1 and a second gate PAG2. The first gate PAG1 and the second gate PAG2 can be separated from each other by the first separator DP1 of the separation structure DST. The first separator DP1 of the separation structure DST can be disposed between the first gate PAG1 and the second gate PAG2. The first gate PAG1 and the second gate PAG2 can be separated from each other in the second direction D2, and the first separator DP1 of the separation structure DST is inserted between them.

[0061] Each of the first separator DP1 and the second separator DP2 may include a first separator layer DLa, a second separator layer DLb, and a third separator layer DLc. The first separator layer DLa, the second separator layer DLb, and the third separator layer DLc of the first separator DP1 may extend in a first direction D1. The first separator layer DLa, the second separator layer DLb, and the third separator layer DLc of the second separator DP2 may extend in a second direction D2. The first separator layer DLa of the first separator DP1 may be connected to the first separator layer DLa of the second separator DP2. The second separator layer DLb of the first separator DP1 may be connected to the second separator layer DLb of the second separator DP2. The third separator layer DLc of the first separator DP1 may be connected to the third separator layer DLc of the second separator DP2.

[0062] A second separation layer DLb may be disposed within a first separation layer DLa. The sidewalls and top surface of the second separation layer DLb may be covered by the first separation layer DLa. A third separation layer DLc may be disposed within the second separation layer DLb. The sidewalls and top surface of the third separation layer DLc may be covered by the second separation layer DLb.

[0063] The first separating layer DLa may include an insulating material. For example, the first separating layer DLa may include an oxide. The second separating layer DLb may include a semiconductor material. For example, the second separating layer DLb may include polycrystalline silicon. The third separating layer DLc may include an insulating material. For example, the third separating layer DLc may include an oxide.

[0064] A through-plug PAP can be provided, passing through the sixth insulating layer 160 and the seventh insulating layer 170. The through-plug PAP can be disposed in the connection area COR. The through-plug PAP can extend in the third direction D3. The through-plug PAP can have a columnar shape.

[0065] Each through-plug PAP may include a first through-layer PL1, a second through-layer PL2 surrounding the first through-layer PL1, and a third through-layer PL3 surrounding the second through-layer PL2. The first through-layer PL1 may be disposed within the second through-layer PL2. The second through-layer PL2 may be disposed within the third through-layer PL3. The second through-layer PL2 may cover the sidewalls and top surface of the first through-layer PL1. The third through-layer PL3 may cover the sidewalls and top surface of the second through-layer PL2.

[0066] The first through layer PL1 may include an insulating material. For example, the first through layer PL1 may include an oxide. The second through layer PL2 may include a semiconductor material. For example, the second through layer PL2 may include polysilicon. The third through layer PL3 may include an insulating material. For example, the third through layer PL3 may include an oxide.

[0067] The second through layer PL2 can be spaced apart from the through gate PAG by the third through layer PL3. The structure including the through gate PAG, the second through layer PL2 and the third through layer PL3 can be used as a through transistor in a semiconductor device.

[0068] The fourth bonding structure BDS4, the second bonding structure BDS2, and the word line contact structure WCS can each be defined as the second conductor CB2. The plug PAP can be connected to the conductive pattern CP via the second conductor CB2. In other words, the plug PAP can be connected to the conductive pattern CP via the fourth bonding structure BDS4, the second bonding structure BDS2, and the word line contact structure WCS. The plug PAP can also be electrically connected to the conductive pattern CP via the second conductor CB2.

[0069] The via plug PAP may include a first via plug PAP1 passing through a first via gate PAG1 and a second via plug PAP2 passing through a second via gate PAG2. The first via gate PAG1 may surround the first via plug PAP1. The second via gate PAG2 may surround the second via plug PAP2. The first via plug PAP1 may be arranged in a first direction D1. The second via plug PAP2 may be arranged in the first direction D1. The first via plug PAP1 may be spaced apart from the second via plug PAP2, and a first separator DP1 of the separation structure DST is inserted between them. For example, the first via plug PAP1 may be spaced apart from the second via plug PAP2, and a first separator DP1 of the separation structure DST is inserted between them.

[0070] The first through plugs PAP1, which are adjacent to each other, may be spaced apart from each other in the first direction D1. The second through plugs PAP2, which are adjacent to each other, may be spaced apart from each other in the first direction D1. The distance between the first through plugs PAP1 and the semiconductor layer SML in the first direction D1 may be different from the distance between the second through plugs PAP2 and the semiconductor layer SML in the first direction D1. For example, refer to... Figure 1C First, via plug PAP1, a first distance L1, a second distance L2, and a third distance L3 are spaced from the semiconductor layer SML in the first direction D1. Second, via plug PAP2, a fourth distance L4 and a fifth distance L5 are spaced from the semiconductor layer SML in the first direction D1. The first distance L1 may be less than the fourth distance L4. The fourth distance L4 may be less than the second distance L2. The fifth distance L5 may be less than the third distance L3.

[0071] The conductive pattern CP may include a first conductive pattern CP1, a second conductive pattern CP2 adjacent to the first conductive pattern CP1, and a third conductive pattern CP3 adjacent to the first conductive pattern CP1. The second conductive pattern CP2 and the third conductive pattern CP3 may be arranged below and above the first conductive pattern CP1, respectively. The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3 may be conductive patterns CP that are adjacent to each other.

[0072] The first via plug PAP1 and the second via plug PAP2 can be electrically connected to the conductive pattern CP. For example, when the second via plug PAP2 is electrically connected to the first conductive pattern CP1, the first via plug PAP1 can be electrically connected to the second conductive pattern CP2 adjacent to the first conductive pattern CP1, and the first via plug PAP1 can be electrically connected to the third conductive pattern CP3 adjacent to the first conductive pattern CP1.

[0073] The word line contact structure WCS connected to the first through plug PAP1 and the word line contact structure WCS connected to the second through plug PAP2 can be alternately connected to the conductive pattern CP. For example, when the word line contact structure WCS connected to the second through plug PAP2 is connected to the first conductive pattern CP1, the word line contact structure WCS connected to the first through plug PAP1 can be connected to the second conductive pattern CP2 adjacent to the first conductive pattern CP1, and the word line contact structure WCS connected to the first through plug PAP1 can be connected to the third conductive pattern CP3 adjacent to the first conductive pattern CP1.

[0074] An eighth insulating layer 180 may be provided to cover the semiconductor layer SML, through the gate PAG, the discrete structure DST, and through the plug PAP. The eighth insulating layer 180 may include an insulating material. For example, the eighth insulating layer 180 may include an oxide or a nitride.

[0075] A ninth insulating layer 190 may be provided to cover the eighth insulating layer 180. The ninth insulating layer 190 may include an insulating material. For example, the ninth insulating layer 190 may include an oxide or a nitride.

[0076] The second contact CT2 may be disposed in the eighth insulating layer 180. The second contact CT2 may be coupled to the through plug PAP. The second contact CT2 may pass through the third through layer PL3 and be coupled to the second through layer PL2. The second contact CT2 may pass through the third through layer PL3 to contact the second through layer PL2. The second contact CT2 may include a conductive material.

[0077] The second metal wire ML2 may be disposed in the ninth insulating layer 190. The second metal wire ML2 may be connected to the second contact CT2. The second metal wire ML2 may include a conductive material.

[0078] ReferenceFigure 1D Each second pass layer PL2 through the plug PAP may include a first portion PT1a that contacts the second contact CT2, a second portion PT2a that contacts the fourth engagement contact BDC4, and a third portion PT3a between the first portion PT1a and the second portion PT2a.

[0079] The first portion PT1a of the second through layer PL2 may be surrounded by the eighth insulating layer 180. The first portion PT1a of the second through layer PL2 may be arranged at the same height as the eighth insulating layer 180. The second portion PT2a of the second through layer PL2 may be surrounded by the sixth insulating layer 160 and the seventh insulating layer 170. The third portion PT3a of the second through layer PL2 may be surrounded by the through gate PAG. The third portion PT3a of the second through layer PL2 may be arranged at the same height as the through gate PAG. The third portion PT3a of the second through layer PL2 may be adjacent to the through gate PAG.

[0080] The first portion PT1a of the second pass-through layer PL2 may be located above the third portion PT3a of the second pass-through layer PL2. The second portion PT2a of the second pass-through layer PL2 may be located below the third portion PT3a of the second pass-through layer PL2. The third portion PT3a of the second pass-through layer PL2 may connect the first portion PT1a and the second portion PT2a of the second pass-through layer PL2 to each other. The second portion PT2a of the second pass-through layer PL2 may cover the lower surface of the first pass-through layer PL.

[0081] The first portion PT1a of the second through layer PL2 may include doped polysilicon. For example, the first portion PT1a of the second through layer PL2 may be doped with an N-type impurity. For example, the N-type impurity doped in the first portion PT1a of the second through layer PL2 may be phosphorus. The second portion PT2a of the second through layer PL2 may include doped polysilicon. For example, the second portion PT2a of the second through layer PL2 may be doped with an N-type impurity. For example, the N-type impurity doped in the second portion PT2a of the second through layer PL2 may be phosphorus. The third portion PT3a of the second through layer PL2 may include undoped polysilicon.

[0082] Reference Figure 1E The second separation layer DLb of each of the first separator DP1 and the second separator DP2 may include a first part PT1b, a second part PT2b and a third part PT3b.

[0083] The first portion PT1b of the second separation layer DLb may be surrounded by the eighth insulating layer 180. The first portion PT1b of the second separation layer DLb may be disposed at the same height as the eighth insulating layer 180. The second portion PT2b of the second separation layer DLb may be surrounded by the sixth insulating layer 160 and the seventh insulating layer 170. The third portion PT3b of the second through layer PL2 may be disposed at the same height as the through gate PAG and the semiconductor layer SML.

[0084] The first portion PT1b of the second separating layer DLb can be disposed above the third portion PT3b of the second separating layer DLb. The second portion PT2b of the second separating layer DLb can be disposed below the third portion PT3b of the second separating layer DLb. The third portion PT3b of the second separating layer DLb can connect the first portion PT1b and the second portion PT2b of the second separating layer DLb. The second portion PT2b of the second separating layer DLb can cover the lower surface of the third separating layer DLc.

[0085] The first portion PT1b of the second separation layer DLb may include doped polysilicon. For example, the first portion PT1b of the second separation layer DLb may be doped with an N-type impurity. For example, the N-type impurity doped in the first portion PT1b of the second separation layer DLb may be phosphorus. The second portion PT2b of the second separation layer DLb may include doped polysilicon. For example, the second portion PT2b of the second separation layer DLb may be doped with an N-type impurity. For example, the N-type impurity doped in the second portion PT2b of the second separation layer DLb may be phosphorus. The third portion PT3b of the second separation layer DLb may include undoped polysilicon.

[0086] In the semiconductor device according to the embodiment, the semiconductor layer SML on which the peripheral transistor TE is formed can be disposed at the same height as the through gate PAG through the transistor. Therefore, it may not be necessary to form a separate conductive layer as the gate of the through transistor. As a result, the size of the semiconductor device can be reduced.

[0087] In the semiconductor device according to embodiments of the present disclosure, transistors can be arranged to overlap with the stepped structure STE of the stacked body STA. Therefore, the increase in the area of ​​the semiconductor device caused by the transistors can be reduced. Furthermore, the length of the second conductor CB2, which connects the transistors and the conductive pattern CP, can be reduced.

[0088] Figure 2A , Figure 3 , Figure 4A , Figure 5A , Figure 6A , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 andFigure 12 This is a diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2B It is along Figure 2A The cross-sectional view taken by line A2-A2'. Figure 4B It is along Figure 4A The cross-sectional view taken by line A3-A3'. Figure 5B It is along Figure 5A The cross-sectional view taken by line A4-A4'. Figure 6B It is along Figure 6A The cross-sectional view taken by line A5-A5'.

[0089] For the sake of brevity, the references already mentioned above will be omitted. Figures 1A-1E Any repetitive description of the components described. The manufacturing method described below corresponds only to one embodiment of manufacturing a semiconductor device. Therefore, manufacturing such... Figures 1A-1E The method of manufacturing the semiconductor device shown is not limited to the manufacturing method described below.

[0090] Reference Figure 2A and Figure 2B A source structure SOS can be formed. A stacked body STA can be disposed on the source structure SOS. A cell plug CEP can be formed through the stacked body STA. A first insulating layer 110 can be provided to cover the stacked body STA. A first bit line contact BC1 and a first word line contact WC1 can be formed through the first insulating layer 110.

[0091] A second insulating layer 120, a third insulating layer 130, and a fourth insulating layer 140 covering the first insulating layer 110 can be formed sequentially. When forming the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140, a second bit line contact BC2, a bit line BL, and a first bonding structure BDS1 can be formed sequentially. When forming the second insulating layer 120, the third insulating layer 130, and the fourth insulating layer 140, a second word line contact WC2, a word line pad WP, ​​and a second bonding structure BDS2 can be formed sequentially.

[0092] Reference Figure 3 A second substrate 100 can be formed. The second substrate 100 may include a first region RG1 and a second region RG2. The second region RG2 may be disposed in the first region RG1. The second region RG2 may be arranged at a higher height than the first region RG1.

[0093] The first region RG1 and the second region RG2 of the second substrate 100 may include semiconductor material. The first region RG1 of the second substrate 100 may be doped with an impurity of a first doping concentration. The second region RG2 of the second substrate 100 may be doped with an impurity of a second doping concentration. For example, the first region RG1 and the second region RG2 may be doped with P-type impurities. The first doping concentration may be greater than the second doping concentration.

[0094] A peripheral transistor TE may be formed on a second region RG2 of the second substrate 100. An isolation layer IS may be formed in the second region RG2 of the second substrate 100. A seventh insulating layer 170 and a sixth insulating layer 160 covering the second substrate 100 and the peripheral transistor TE may be formed sequentially. When the sixth insulating layer 160 and the seventh insulating layer 170 are formed, the first contact CT1 and the first metal line ML1 may be formed in the seventh insulating layer 170.

[0095] Reference Figure 4A and Figure 4B The first mask layer MA1 may be formed on the sixth insulating layer 160. The first mask layer MA1 may include a first opening OP1.

[0096] The first mask layer MA1 can be used as an etching mask to etch the sixth insulating layer 160, the seventh insulating layer 170, and the second substrate 100. The first trench TR1, the second trench TR2, and the first hole HO1 can be formed by etching the sixth insulating layer 160, the seventh insulating layer 170, and the second substrate 100. The first trench TR1, the second trench TR2, and the first hole HO1 can pass through the sixth insulating layer 160 and the seventh insulating layer 170. The first trench TR1, the second trench TR2, and the first hole HO1 can pass through the second region RG2 of the second substrate 100. The lower surfaces of the first trench TR1, the second trench TR2, and the first hole HO1 can be disposed in the first region RG1 of the second substrate 100. After etching the sixth insulating layer 160, the seventh insulating layer 170, and the second substrate 100, the first mask layer MA1 can be removed.

[0097] A first groove TR1 may extend in a first direction D1. A second groove TR2 may extend in a second direction D2. The first groove TR1 and the second groove TR2 may be connected to each other. The second groove TR2 may be connected to one end of the first groove TR1. The first groove TR1 may be arranged between first holes HO1. The first groove TR1, the second groove TR2 and the first hole HO1 may be formed in the connection region COR.

[0098] Reference Figure 5A and Figure 5BA first material layer MAL1 and a second material layer MAL2 may be formed. The first material layer MAL1 may be conformally formed on the upper surface of the sixth insulating layer 160, the first trench TR1, the second trench TR2, and the first hole HO1. Conformally forming a layer on a surface means that the layer conforms to or follows the shape of the surface. A portion of the first material layer MAL1 may be formed in the first trench TR1. A portion of the first material layer MAL1 may be formed in the second trench TR2. A portion of the first material layer MAL1 may be formed in the first hole HO1. The first material layer MAL1 may include an insulating material. For example, the first material layer MAL1 may include an oxide.

[0099] A second material layer MAL2 may be conformally disposed on the first material layer MAL1. A portion of the second material layer MAL2 may be formed in the first trench TR1. A portion of the second material layer MAL2 may be formed in the second trench TR2. A portion of the second material layer MAL2 may be formed in the first via HO1. The second material layer MAL2 may include a semiconductor material. For example, the second material layer MAL2 may include polysilicon.

[0100] The second material layer MAL2 may be doped with impurity DOP. Impurity DOP can be implanted into the second material layer MAL2 in a direction opposite to the third direction D3. Impurity DOP can also be implanted into the second material layer MAL2 in a direction orthogonal to the upper surface of the second substrate 100. As impurity DOP is implanted and diffuses, the second material layer MAL2 can be doped.

[0101] In the direction in which impurity DOP is injected into the second material layer MAL2, the portion of the second material layer MAL2 surrounded by the first region RG1 may be doped with impurity DOP, the portion of the second material layer MAL2 surrounded by the second region RG2 may not be doped with impurity DOP, and the portion of the second material layer MAL2 surrounded by the sixth insulating layer 160 and the seventh insulating layer 170 may be doped with impurity DOP.

[0102] Reference Figure 6A and Figure 6BA third separation layer DLc and a first through layer PL1 can be formed on the second material layer MAL2. Forming the third separation layer DLc and the first through layer PL1 may include forming an insulating material layer on the second material layer MAL2 and separating the third separation layer DLc and the first through layer PL1 from each other by etching the insulating material layer. The third separation layer DLc can be formed in a first trench TR1 or a second trench TR2. The third separation layer DLc in the first trench TR1 and the third separation layer DLc in the second trench TR2 can be connected to each other without boundaries. In other words, the third separation layer DLc in the first trench TR1 and the third separation layer DLc in the second trench TR2 can be integrally formed with each other. The first through layer PL1 can be formed in a first hole HO1.

[0103] Reference Figure 7 A third material layer, MAL3, can be formed. Forming the third material layer, MAL3, may include depositing a semiconductor material onto the second material layer, MAL2, the third separation layer, DLc, and the first through layer, PL1. For example, the semiconductor material may be polycrystalline silicon. The semiconductor material deposited on the second material layer, MAL2, may be bonded to the second material layer, MAL2, without a boundary. In other words, the semiconductor material deposited on the second material layer, MAL2, may be integrally bonded to the second material layer, MAL2. The second material layer, MAL2, and the semiconductor material, which are integrally bonded to each other, may be defined as the third material layer, MAL3.

[0104] Reference Figure 8 The upper portion of the third material layer MAL3 and the upper portion of the first material layer MAL1 can be removed. For example, the upper portion of the third material layer MAL3 and the upper portion of the first material layer MAL1 can be removed by chemical mechanical polishing (CMP). When the upper portion of the first material layer MAL1 is removed, the first material layer MAL1 can be separated into multiple parts. The separated portions of the first material layer MAL1 can be defined as the first separation layer DLa or the third through layer PL3. When the upper portion of the third material layer MAL3 is removed, the third material layer MAL3 can be separated into multiple parts. The separated portions of the third material layer MAL3 can be defined as the second separation layer DLb or the second through layer PL2.

[0105] Since the upper portions of the third material layer MAL3 and the first material layer MAL1 are removed, a plug PAP can be formed. The plug PAP can be surrounded by the second substrate 100. The plug PAP can pass through the second region RG2 of the second substrate 100. Since the upper portions of the third material layer MAL3 and the first material layer MAL1 are removed, a separation structure DST can be formed. The separation structure DST can pass through the second region RG2 of the second substrate 100.

[0106] When the upper part of the third material layer MAL3 and the upper part of the first material layer MAL1 are removed, the upper surface of the sixth insulating layer 160 can be exposed.

[0107] Reference Figure 9 A fifth insulating layer 150 may be formed on the sixth insulating layer 160. A third bonding structure BDS3 may be formed to connect to the first metal wire ML1. A fourth bonding structure BDS4 may be formed to connect to the plug PAP.

[0108] Reference Figure 10 The second substrate 100 can be reversed. When the second substrate 100 is reversed, the components formed on the second substrate 100 can be reversed accordingly. Subsequently, the third bonding pad BP3 of the third bonding structure BDS3 can be bonded to the first bonding pad BP1 of the first bonding structure BDS1, and the fourth bonding pad BP4 of the fourth bonding structure BDS4 can be bonded to the second bonding pad BP2 of the second bonding structure BDS2.

[0109] The third bonding pad BP3 of the third bonding structure BDS3 can be bonded to the first bonding pad BP1 of the first bonding structure BDS1. The peripheral transistor TE can be electrically connected to the cell plug CEP. The fourth bonding pad BP4 of the fourth bonding structure BDS4 can be bonded to the second bonding pad BP2 of the second bonding structure BDS2, and can be electrically connected to the conductive pattern CP via the plug PAP. When electrically connected to the conductive pattern CP via the plug PAP, the peripheral transistor TE can be electrically connected to the cell plug CEP.

[0110] While the first bonding pad BP1, the second bonding pad BP2, the third bonding pad BP3 and the fourth bonding pad BP4 are bonded, the fifth insulating layer 150 can be bonded to the fourth insulating layer 140.

[0111] Reference Figure 11 The first region RG1 of the second substrate 100 can be selectively removed. For example, the first region RG1 of the second substrate 100 can be selectively removed by an leaching process.

[0112] The first region RG1 of the second substrate 100 can be removed and separated into multiple second region RG2 portions. The multiple separated portions of the second region RG2 can be defined as semiconductor layer SML or through gate PAG.

[0113] The first region RG1 of the second substrate 100 can be removed to partially expose the plug PAP and the separation structure DST. For example, the upper part of the plug PAP not embedded in the second region RG2 and the upper part of the separation structure DST can be exposed.

[0114] Reference Figure 12It can form an eighth insulating layer 180 covering the semiconductor layer SML, through the gate PAG, the discrete structure DST, and through the plug PAP.

[0115] A second mask layer MA2, including a second opening OP2, can be formed on the eighth insulating layer 180. Subsequently, the second mask layer MA2 can be used as an etching mask to perform an etching process. Through the etching process, the eighth insulating layer 180 and the third through layer PL3, passing through the plug PAP, can be etched.

[0116] The eighth insulating layer 180 and the third through layer PL3 through the plug PAP can be etched to form the second hole HO2. The second through layer PL2 through the plug PAP can be exposed through the second hole HO2. After the eighth insulating layer 180 and the third through layer PL3 through the plug PAP are etched, the second mask layer MA2 can be removed.

[0117] Subsequently, referring to Figure 1B A second contact CT2 can be formed in the second hole HO2, a ninth insulating layer 190 can be formed on the eighth insulating layer 180, and a second metal line ML2 can be formed in the ninth insulating layer 190. The second contact CT2 can be connected to a portion of the plug PAP exposed due to the removal of the first region RG1 of the second substrate 100.

[0118] A method for manufacturing a semiconductor device according to an embodiment may include forming a semiconductor layer SML and a gate PAG by separating a second substrate 100. Therefore, since it may not be necessary to form a separate conductive layer to serve as the gate for a transistor, the size of the semiconductor device can be reduced.

[0119] The method for manufacturing a semiconductor device according to the embodiment can set the width and depth of the plug PAP to target values ​​by adjusting the width and depth of the first hole HO1. The passage of transistors can be optimized based on the target values ​​of the width and depth of the plug PAP.

[0120] Figure 13 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0121] Reference Figure 13 The memory system 1100 may include a memory device 1120 and a memory controller 1110.

[0122] The memory device 1120 may include a semiconductor device according to embodiments of the present disclosure. The memory device 1120 may be a multi-chip package consisting of a plurality of flash memory chips.

[0123] The storage controller 1110 is configured to control the memory device 1120 and includes a static random access memory (SRAM) 1111, a CPU 1112, a host interface 1113, an error correction code (ECC) circuit 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs control operations on data exchange with the storage controller 1110. The host interface 1113 may include a data exchange protocol for accessing the memory system 1100. Additionally, the ECC circuit 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 performs interfacing with the memory device 1120. The storage controller 1110 may also include a read-only memory (ROM) storing code data for the host interface.

[0124] The memory system 1100 with the above configuration can be a solid-state drive (SSD) or memory card that combines a memory device 1120 and a storage controller 1110. For example, when the memory system 1100 is an SSD, the storage controller 1110 can communicate with an external device (e.g., a host) via one of the interface protocols including Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0125] Figure 14 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0126] Reference Figure 14 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. Additionally, when the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200, and may also include an application chipset, a camera image processor (CIS), mobile DRAM, etc.

[0127] According to reference Figure 13 In a similar manner as described, memory system 1210 may include memory device 1212 and memory controller 1211.

[0128] In a semiconductor device according to an embodiment of the present disclosure, the semiconductor layer on which the peripheral transistor is formed and the through gate of the transistor can be arranged at the same height, so that the size of the semiconductor device can be reduced.

[0129] Cross-references to related applications

[0130] This application claims priority to Korean Patent Application No. 10-2020-0146321, filed with the Korean Intellectual Property Office on November 4, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A laminate comprising a conductive pattern and an insulating pattern; A unit plug that passes through the stack; Semiconductor layer; A peripheral transistor, which is disposed on the semiconductor layer; A first conductor connects the peripheral transistor to the cell plug; A second conductor, which is connected to the conductive pattern; The plug is connected to the second conductor. Through the gate, the through gate surrounds the through plug; as well as The separation structure includes an insulating layer disposed between the semiconductor layer and the gate. The gate is arranged at the same height as the semiconductor layer.

2. The semiconductor device according to claim 1, wherein, The semiconductor layer and the gate comprise the same material.

3. The semiconductor device according to claim 2, wherein, The semiconductor layer and the gate comprise doped silicon.

4. The semiconductor device according to claim 1, wherein, The semiconductor layer includes a first surface on which the peripheral transistors are disposed, and The gate includes a third surface disposed at the same height as the first surface of the semiconductor layer.

5. The semiconductor device according to claim 4, wherein, The height of the second surface of the semiconductor layer opposite to the first surface of the semiconductor layer is the same as the height of the fourth surface of the gate opposite to the third surface of the gate.

6. The semiconductor device according to claim 1, wherein, The separation structure electrically isolates the semiconductor layer from the gate.

7. The semiconductor device according to claim 6, wherein, The separation structure includes a first separation layer and a second separation layer within the first separation layer, and The first separation layer comprises an insulating material.

8. The semiconductor device according to claim 7, wherein, The second separation layer comprises a semiconductor material.

9. A semiconductor device comprising: A laminate comprising a conductive pattern and an insulating pattern; A unit plug that passes through the stack; Semiconductor layer; A peripheral transistor, which is disposed on the semiconductor layer; A first conductor connects the peripheral transistor to the cell plug; A second conductor, which is connected to the conductive pattern; The plug is connected to the second conductor. Through the gate, the through gate surrounds the through plug; as well as The separation structure includes an insulating layer disposed between the gate and the semiconductor layer. The gate comprises the same material as the semiconductor layer.

10. The semiconductor device according to claim 9, wherein, The passage through the gate and the semiconductor layer comprises a semiconductor material.

11. The semiconductor device according to claim 10, wherein, The passage through the gate and the semiconductor layer comprises silicon doped with P-type impurities.

12. The semiconductor device according to claim 9, wherein, The first conductor includes a bit line.

13. The semiconductor device according to claim 9, wherein, The separation structure electrically isolates the gate from the semiconductor layer.

14. The semiconductor device according to claim 9, wherein, The through-plug includes a first through-layer and a second through-layer surrounding the first through-layer, and The first through layer is spaced apart from the through gate by the second through layer.

15. The semiconductor device according to claim 14, wherein, The first permeable layer comprises a semiconductor material, and The second pass layer includes an insulating material.

16. The semiconductor device according to claim 15, wherein, The first pass layer includes: The first part is adjacent to the gate; The second part, which is arranged above the first part; and The third part is positioned below the first part. The first portion comprises undoped polycrystalline silicon, and The second part and the third part include doped polycrystalline silicon.

17. A semiconductor device comprising: A laminate comprising alternating layers of conductive patterns and insulating patterns; A unit plug that passes through the stack; A plurality of through plugs, each of which is electrically connected to the conductive pattern, the plurality of through plugs including a plurality of first through plugs arranged in a first direction and a plurality of second through plugs arranged in the first direction; A first through gate surrounds the first through plug; A second through gate surrounds the second through plug; as well as A separation structure that separates the first through gate from the second through gate.

18. The semiconductor device according to claim 17, wherein, The first through plug is spaced apart from the second through plug, and the separation structure is inserted between the first through plug and the second through plug.

19. The semiconductor device according to claim 17, wherein, The separation structure includes: A first separation, the first separation extending in the first direction; and The second separation extends in a second direction that intersects the first direction.

20. The semiconductor device according to claim 17, wherein, The conductive pattern includes: A first conductive pattern, wherein the first conductive pattern is connected to one of the plurality of first through plugs; A second conductive pattern, adjacent to the first conductive pattern, wherein the second conductive pattern is connected to one of the plurality of second through plugs; and A third conductive pattern, which is adjacent to the first conductive pattern, is connected to a second through plug that is different from the second through plug connected to the second conductive pattern.

21. The semiconductor device according to claim 20, wherein, The first through plug connected to the first conductive pattern is arranged between the second through plug connected to the second conductive pattern and the second through plug connected to the third conductive pattern.

22. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate that includes conductive and insulating patterns; Forming unit plugs that pass through the stacked body; A substrate is formed, the substrate including a first region and a second region on the first region; Forming a separation structure extending into the second region of the substrate; Forming a through plug surrounded by the substrate; The plug is electrically connected to the conductive pattern; Remove the first region of the substrate to expose a portion of the plug; as well as Forming a contact that is connected to the portion of the plug.

23. The method according to claim 22, wherein, The step of electrically connecting the via plug to the conductive pattern includes the following steps: bonding a first bonding pad to the via plug and a second bonding pad to the conductive pattern.

24. The method of claim 22, further comprising the step of: A peripheral transistor is formed on the substrate.

25. The method of claim 24, further comprising the step of: The peripheral transistor is electrically connected to the unit plug.

26. The method of claim 25, wherein, When the peripheral transistor is electrically connected to the conductive pattern via the plug, the peripheral transistor is electrically connected to the cell plug.

27. The method according to claim 22, wherein, The separation structure passes through the second region of the substrate.

28. The method according to claim 27, wherein, The steps to form the separated structure include the following: A trench is formed through the second region of the substrate; A first material layer and a second material layer are conformally formed in the trench; and Remove the upper part of the first material layer and the upper part of the second material layer.

29. The method according to claim 22, wherein, The step of forming the plug includes the following steps: A hole is formed through the second region of the substrate; A first material layer and a second material layer are conformally formed in the hole; and Remove the upper part of the first material layer and the upper part of the second material layer.

30. The method according to claim 29, wherein, The step of forming the plug further includes the step of doping the second material layer with impurities.

31. The method according to claim 22, wherein, The through-plug includes a first through-layer and a second through-layer surrounding the first through-layer, and The steps for forming the contact point include the following: Forming a hole through the second through layer; and The contact point is formed in the hole.

Images