Interstage gain error calibration method of pipeline adc and circuit thereof, pipeline adc

Abstract

The application provides a method for calibrating inter-stage gain error of a pipeline ADC, a circuit thereof and the pipeline ADC. The method comprises the following steps: simultaneously injecting pseudo-random noise jitter in opposite directions from a sub-ADC and a sub-DAC; determining an actual gain coefficient of a pipeline stage to be calibrated based on a sampling signal interval division mode of the pipeline stage to be calibrated; and extracting the inter-stage gain error. When the pseudo-random noise jitter in opposite directions is simultaneously injected from the sub-ADC and the sub-DAC, the residual voltage is maintained at ±1 / 2*V ref Therefore, the requirement for linearity of the amplified signal of the pipeline stage to be calibrated can be greatly reduced. For a high-precision ADC, a better inter-stage gain calibration effect is achieved. Meanwhile, on the basis of completing the inter-stage gain calibration, the method for calibrating the inter-stage gain error can achieve a better spectrum scattering effect and improve the overall dynamic range of the pipeline ADC by simultaneously injecting the pseudo-random noise jitter in opposite directions from the sub-ADC and the sub-DAC.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of analog-to-digital conversion, in particular to an inter-stage gain error calibration method of a pipeline ADC, a circuit thereof and the pipeline ADC. BACKGROUND

[0002] Analog-to-digital converter (ADC) is used to convert analog signals into digital signals, which is widely used in wireless communication, high-end test equipment, image and voice processing and other fields. With the development of advanced process and design technology, and the expansion of application scenarios, the demand for high-speed and high-precision ADC is increasingly significant. Pipeline ADC can achieve a good compromise between speed and accuracy, so pipeline or pipeline-time interleaved architecture is generally used for ultra-high-speed and high-precision ADC. Figure 1 A pipeline stage ADC and a block diagram of one of the pipeline stages in the channel are given. The working principle is as follows: first, the sampling and holding circuit samples the output signal of the previous pipeline stage or the analog input signal. Next, the sub-ADC converts the sampled signal into a digital code and sends it to the sub-DAC of the pipeline stage. Then, the input signal of the pipeline stage is subtracted and amplified from the output signal of the sub-DAC, and is transmitted to the next pipeline stage to repeat the above process.

[0003] The pipeline stage ADC serially processes the input analog signal through each pipeline stage, so high-throughput fast conversion can be achieved. However, the disadvantage of this architecture is that accurate analog signal processing must be performed at each pipeline stage to ensure that the signal is not distorted in the subsequent pipeline stages. In particular, accurate gain is required between each pipeline stage. In a common switch capacitor type pipeline stage, the limited open-loop gain of the operational amplifier in each pipeline stage will seriously affect the gain of the pipeline stage. The inter-stage gain error will cause a jump in the transfer characteristic of the ADC, resulting in partial loss of the output code, thereby deteriorating the DNL (Differential Nonlinearity), i.e. the inter-stage gain error will seriously affect the linearity of the overall ADC. Moreover, the open-loop gain of the operational amplifier will be affected by temperature and voltage changes, and the foreground calibration method cannot perform accurate and effective calibration. SUMMARY

[0004] The present application provides an inter-stage gain error calibration method of a pipeline ADC, a circuit thereof and the pipeline ADC. The actual gain coefficient of the pipeline stage to be calibrated is determined, the inter-stage gain error is extracted, and the residual voltage is maintained within ±1 / 2*V ref , which can greatly alleviate the requirement for the operational amplifier of the pipeline stage to be calibrated, avoid the overflow of the residual voltage, achieve good inter-stage gain calibration effect, and at the same time achieve good spectrum scattering effect and improve the overall dynamic range of the pipeline ADC.

[0005] In a first aspect, the present invention provides an interstage gain error calibration method for a pipelined ADC, wherein the pipelined ADC includes multiple pipeline stages, and the multiple pipeline stages include a pipeline stage to be calibrated for performing n-bit digital code conversion, and a subsequent pipeline stage located one stage after the pipeline stage to be calibrated, wherein the pipeline stage to be calibrated includes a sub-ADC and a sub-DAC. The interstage gain error calibration method includes:

[0006] Input a sampling signal into the flow stage to be calibrated;

[0007] The size of the i-th pair of m pairs of pseudo-random noise injected into the sub-ADC is +1 / a i *V ref In addition to pseudo-random noise, m pairs of pseudo-random noise from the sub-DAC are also injected into the sub-DAC, with the i-th pair containing a magnitude of -1 / b. i *V ref The pseudo-random noise; or, injecting m pairs of pseudo-random noise into the sub-ADC, the i-th pair of which has a size of -1 / a i *V ref In addition to pseudo-random noise, m pairs of pseudo-random noise from the sub-DAC are also injected into the sub-DAC, with the i-th pair containing +1 / b. i *V ref The pseudo-random noise; where m is a positive integer, the i-th pair of ADC pseudo-random noise and the i-th pair of DAC pseudo-random noise correspond to the same i-th group of pseudo-random noise sequences, and a i =b i *2 n-1 ;

[0008] Based on m, n, ±1 / a i *V ref Determine the range of signals that can be used for calibration;

[0009] When the sampled signal of the pipeline stage to be calibrated is within the signal range that can be used for calibration, the actual gain coefficient of the pipeline stage to be calibrated is determined based on the ideal digital code corresponding to the weight of the i-th pseudo-random noise sequence, the subsequent digital output code of the subsequent pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated.

[0010] In the above scheme, pseudo-random noise jitter is injected simultaneously from the sub-ADC and sub-DAC in opposite directions. Based on the sampling signal interval division method of the input pipeline stage to be calibrated, the actual gain coefficient of the pipeline stage to be calibrated is determined, and the inter-stage gain error is extracted. Furthermore, when pseudo-random noise jitter is injected simultaneously from the sub-ADC and sub-DAC in opposite directions, the residual voltage is maintained within ±1 / 2*V. refWithin this range, the linearity requirements of the pipelined ADC under the amplified signal can be greatly alleviated, avoiding the phenomenon of residual voltage overflow. This interstage gain error calibration method achieves good interstage gain calibration results for high-precision ADCs. Furthermore, after completing the interstage gain calibration, this method can also achieve better spectral dispersion by simultaneously injecting pseudo-random noise jitter in opposite directions into the sub-ADC and sub-DAC, thereby improving the overall dynamic range of the pipelined ADC.

[0011] In one specific implementation, based on m, n, ±1 / a i *V ref The range of signals that can be used for calibration is determined based on m, n, and ±1 / a. i *V ref The process calculates the range of the sampled signal that is affected only by the pseudo-random noise of the i-th pair of sub-DACs and not by the pseudo-random noise of the i-th pair of sub-ADCs, and uses this range as the range that can be used for calibration. This ensures that the sampled signal input to the pipeline stage to be calibrated is only affected by the pseudo-random noise sequence injected from the sub-DACs. Calibration can be initiated when the sampled signal is within the calibrable range. That is, only the sampled signal within the calibrable range is subjected to the corresponding correlation operation, which is equivalent to the case where only the sub-DACs inject a pseudo-random noise sequence, thus enabling the extraction of inter-stage gain coefficients. During calibration, the injected pseudo-random noise sequence is equivalent to a sequence unrelated to the sampled signal, thus not interfering with the operation of the sub-ADCs and the entire pipeline ADC. Since this pseudo-random noise sequence follows the same path as the sub-DAC signal and encounters the same non-ideal conditions, the actual gain coefficient of the pipeline stage to be calibrated can be detected, and the inter-stage gain error can be extracted.

[0012] In one specific implementation, m=1; based on m, n, ±1 / a i *V ref The specific range of signals that can be used for calibration is as follows:

[0013]

[0014] in, The circuit structure for running the algorithm is simplified by injecting only a pair of pseudo-random noise into the sub-ADC and sub-DAC.

[0015] In one specific implementation, m > 1; based on m, n, ±1 / a i *V ref The specific range of signals that can be used for calibration is as follows:

[0016]

[0017] in, By injecting at least two pairs of pseudo-random noise into the sub-ADC and the sub-DAC simultaneously, the spectral spreading effect can be improved, and the overall dynamic range of the pipeline ADC can be further improved.

[0018] In one specific embodiment, the actual gain coefficient of the to-be-calibrated pipeline stage is determined by using the LMS algorithm according to the ideal digital code of the weight corresponding to the i-th group of pseudo-random noise sequences, the posterior digital output code output by the posterior pipeline stage, and the ideal gain coefficient of the to-be-calibrated pipeline stage. By using the LMS convergence iteration method, the inter-stage gain error is extracted in combination with the pseudo-random noise dithering injection technology and the correlation operation, and the accuracy of the obtained actual gain coefficient of the to-be-calibrated pipeline stage is improved.

[0019] In one specific embodiment, the determination of the actual gain coefficient of the to-be-calibrated pipeline stage by using the LMS algorithm includes: performing iterative operation according to the following formula:

[0020]

[0021] wherein, represents the iteration number starting from 0; represents the ideal inter-stage gain coefficient; represents the estimated inter-stage gain coefficient, and respectively represent the estimated inter-stage gain coefficient generated in the i-th iteration and the estimated inter-stage gain coefficient generated in the i+1-th iteration; j represents the ideal digital code of the weight corresponding to the i-th group of pseudo-random noise sequences; j represents the posterior digital output code output by the posterior pipeline stage; represents the convergence step factor. After each iteration calculation, it is determined whether the difference between and is less than a set threshold value; if not, the next iteration is continued; otherwise, is taken as the actual gain coefficient of the to-be-calibrated pipeline stage. By determining whether the difference between and is less than a set threshold value after each iteration, the iteration calculation is stopped only when it is less than the set threshold value, thereby improving the accuracy of the obtained actual gain coefficient of the to-be-calibrated pipeline stage.

[0022] ​​In one specific embodiment, the inter-stage gain error calibration method further comprises: according to the ideal digital code corresponding to the weight of the i th set of pseudo-random noise sequence, the ideal gain coefficient and the actual gain coefficient of the to-be-calibrated pipeline stage, the post-stage digital output code output by the post-stage pipeline stage after calibration, obtaining the calibrated post-stage digital output code, and improving the analog-to-digital conversion accuracy of the pipeline ADC by calibrating the post-stage digital output code output by the post-stage pipeline stage using the actual gain coefficient of the to-be-calibrated pipeline stage.

[0023] In a second aspect, the present application further provides an inter-stage gain error calibration circuit of a pipeline ADC, wherein the pipeline ADC comprises a plurality of pipeline stages, the plurality of pipeline stages comprising a to-be-calibrated pipeline stage for completing n-bit digital code conversion and a post-stage pipeline stage located at a stage after the to-be-calibrated pipeline stage, and the to-be-calibrated pipeline stage comprises a sub-ADC and a sub-DAC. The inter-stage gain error calibration circuit comprises a sample-and-hold module, a pseudo-random noise injection module, a calibration signal determination module and a gain coefficient calibration module. The sample-and-hold module is configured to obtain a sampling signal and input the sampling signal into the to-be-calibrated pipeline stage. The pseudo-random noise injection module is configured to inject, into the sub-ADC, a pseudo-random noise with a size of +1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noises while also injecting, into the sub-DAC, a pseudo-random noise with a size of -1 / b i *V ref in the i th pair of m pairs of sub-DAC pseudo-random noises; or, the pseudo-random noise injection module is configured to inject, into the sub-ADC, a pseudo-random noise with a size of -1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noises while also injecting, into the sub-DAC, a pseudo-random noise with a size of +1 / b i *V ref in the i th pair of m pairs of sub-DAC pseudo-random noises; wherein m is a positive integer, the i th pair of sub-ADC pseudo-random noises and the i th pair of sub-DAC pseudo-random noises correspond to the same i th set of pseudo-random noise sequences, and a i =b i *2 n-1 . The calibration signal determination module is configured to determine a signal range available for calibration according to m, n, ±1 / a i *V ref , and the gain coefficient calibration module is configured to determine the actual gain coefficient of the to-be-calibrated pipeline stage according to the ideal digital code corresponding to the weight of the i th set of pseudo-random noise sequence, the post-stage digital output code output by the post-stage pipeline stage and the ideal gain coefficient of the to-be-calibrated pipeline stage when the sampling signal input into the to-be-calibrated pipeline stage is located in the signal range available for calibration.

[0024] In the above scheme, by adopting the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC at the same time, and based on the sampling signal interval division mode of the input flow water stage to be calibrated, the actual gain coefficient of the flow water stage to be calibrated is determined, and the inter-stage gain error is extracted. When the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC at the same time, the residual voltage is maintained at ±1 / 2*V ref Within the range, the requirement for the linearity of the amplified signal of the flow water stage to be calibrated can be greatly relieved, and the overflow of the residual voltage can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for high-precision ADC. At the same time, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC at the same time can achieve good spectrum scattering effect, and improve the overall dynamic range of the flow water stage ADC.

[0025] In one specific embodiment, the sub-ADC includes: (n-1).5bit flow water stage ADC composed of 2 n -2 comparators, and two additional comparators with threshold values of ±(2 n -1) / 2 n *V ref The sub-DAC includes: (n-1).5bit flow water stage DAC composed of 2 n -2 capacitors, and two additional capacitors with the same size as one of the 2 n -2 capacitors. The pseudo-random noise injection module injects pseudo-random noise with sizes of ±1 / a i *V ref into the i-th pair of m pairs of sub-ADC pseudo-random noise of the sub-ADC by changing the threshold value of the comparator of the sub-ADC. The pseudo-random noise injection module also has a pseudo-random noise capacitor; the pseudo-random noise injection module injects pseudo-random noise with sizes of ±1 / b i *V ref into the i-th pair of m pairs of sub-DAC pseudo-random noise of the sub-DAC through the pseudo-random noise capacitor. It is convenient to realize the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC at the same time, and can fold the two ends of the transfer curve of the flow water stage to be calibrated, and avoid the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC.

[0026] In one specific embodiment, the calibration signal determination module determines m, n, ±1 / a i *V ref, the signal range of the sampling signal affected only by the i-th pair of pseudo-random noise of the sub-DAC and not affected by the i-th pair of pseudo-random noise of the sub-ADC is calculated, and the signal range is taken as the signal range available for calibration. The sampling signal input to the pipeline stage to be calibrated is affected only by the injection of the pseudo-random noise sequence of the sub-DAC. When the sampling signal is located in the signal range available for calibration, the calibration can be started. That is, only the sampling signal in the signal range available for calibration is subjected to the corresponding correlation operation, which is equivalent to the case where only the pseudo-random noise sequence of the sub-DAC is injected, so that the extraction of the inter-stage gain coefficient can be realized. In the calibration process, the pseudo-random noise sequence equivalent to be injected is irrelevant to the sampling signal, so as not to interfere with the operation of the sub-ADC and the entire pipeline ADC. Since the pseudo-random noise sequence passes through the same path as the sub-DAC signal, the same non-ideal condition is encountered, so that the actual gain coefficient of the pipeline stage to be calibrated can be detected, and the inter-stage gain error can be extracted.

[0027] In one specific embodiment, m = 1; the calibration signal determination module determines the signal range available for calibration according to m, n, ±1 / a i *V ref The determined signal range available for calibration is specifically:

[0028]

[0029] wherein, By injecting a pair of pseudo-random noise to the sub-ADC and the sub-DAC, the circuit structure of the operation algorithm is simplified.

[0030] In one specific embodiment, m > 1; the calibration signal determination module determines the signal range available for calibration according to m, n, ±1 / a i *V ref The determined signal range available for calibration is specifically:

[0031]

[0032] wherein, By injecting at least two pairs of pseudo-random noise to the sub-ADC and the sub-DAC at the same time, the frequency spectrum scattering effect can be improved, and the overall dynamic range of the pipeline ADC can be further improved.

[0033] In one specific embodiment, the gain coefficient calibration module determines the actual gain coefficient of the pipeline stage to be calibrated according to the ideal digital code of the weight corresponding to the i-th group of pseudo-random noise sequence, the digital output code output by the subsequent pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated, and adopts the LMS algorithm. By adopting the LMS convergence iteration mode, the inter-stage gain error extraction is performed in combination with the pseudo-random noise dithering injection technology and the correlation operation, so as to improve the accuracy of the actual gain coefficient of the pipeline stage to be calibrated obtained.

[0034] In one specific embodiment, the gain coefficient calibration module comprises an LMS algorithm iteration module and a threshold judgment module. The LMS algorithm iteration module is configured to perform iterative operation according to the following formula:

[0035]

[0036] wherein, represents the iteration number starting from 0; represents the ideal inter-stage gain coefficient; represents the estimated inter-stage gain coefficient, and respectively represent the estimated inter-stage gain coefficient generated in the i-th iteration and the estimated inter-stage gain coefficient generated in the (i+1)-th iteration; j represents the ideal digital code of the weight corresponding to the i-th set of pseudo-random noise sequence; j represents the post-stage digital output code output by the post-stage pipeline stage; represents the convergence step factor. The threshold judgment module is configured to judge whether the difference between and is less than a set threshold value after each iteration calculation; if not, the next iteration is continued by the LMS algorithm iteration module; otherwise, the threshold judgment module takes as the actual gain coefficient of the pipeline stage to be calibrated. By judging whether the difference between and is less than a set threshold value after each iteration, the iteration calculation is stopped only when it is less than the set threshold value, thereby improving the accuracy of the obtained actual gain coefficient of the pipeline stage to be calibrated. In one specific embodiment, the inter-stage gain error calibration circuit further comprises a digital output code calibration module. The digital output code calibration module is configured to calibrate the post-stage digital output code output by the post-stage pipeline stage according to the ideal digital code of the weight corresponding to the i-th set of pseudo-random noise sequence, the ideal gain coefficient and the actual gain coefficient of the pipeline stage to be calibrated, to obtain the calibrated post-stage digital output code. By calibrating the post-stage digital output code output by the post-stage pipeline stage using the actual gain coefficient of the pipeline stage to be calibrated, the analog-to-digital conversion accuracy of the pipeline ADC is improved.

[0037] In one specific embodiment, the inter-stage gain error calibration circuit further comprises a digital output code calibration module. The digital output code calibration module is configured to calibrate the post-stage digital output code output by the post-stage pipeline stage according to the ideal digital code of the weight corresponding to the i-th set of pseudo-random noise sequence, the ideal gain coefficient and the actual gain coefficient of the pipeline stage to be calibrated, to obtain the calibrated post-stage digital output code. By calibrating the post-stage digital output code output by the post-stage pipeline stage using the actual gain coefficient of the pipeline stage to be calibrated, the analog-to-digital conversion accuracy of the pipeline ADC is improved.

[0038] ​In a third aspect, the present application further provides a pipeline ADC, which comprises a plurality of pipeline stages, a to-be-calibrated pipeline stage for completing n-bit digital code conversion, and a post-stage pipeline stage located at a stage after the to-be-calibrated pipeline stage. The to-be-calibrated pipeline stage comprises a sub-ADC and a sub-DAC. The pipeline ADC further comprises the inter-stage gain error calibration circuit of any one of the above pipeline ADCs. The actual gain coefficient of the to-be-calibrated pipeline stage is determined based on the interval division mode of the sampling signal input into the to-be-calibrated pipeline stage, by simultaneously performing pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC, and the inter-stage gain error is extracted. When the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC is performed, the residual voltage is maintained at ±1 / 2*V ref In this way, the requirement for the linearity of the to-be-calibrated pipeline stage when amplifying the signal can be greatly alleviated, and the overflow of the residual voltage can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for high-precision ADCs. Meanwhile, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC and the sub-DAC can achieve good spectrum scattering effect and improve the overall dynamic range of the pipeline ADC. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A block diagram of a pipeline ADC and one of the pipeline stages in the pipeline ADC is shown in FIG. 1.

[0040] Figure 2 A flowchart of the inter-stage gain error calibration method of the pipeline ADC provided in the embodiment of the present application is shown in FIG. 2.

[0041] Figure 3 A partial module block diagram of the inter-stage gain error calibration circuit of the pipeline ADC provided in the embodiment of the present application is shown in FIG. 3.

[0042] Figure 4 A partial module block diagram of another inter-stage gain error calibration circuit of the pipeline ADC provided in the embodiment of the present application is shown in FIG. 4.

[0043] Figure 5 A circuit block diagram of the sub-ADC in the to-be-calibrated pipeline stage provided in the embodiment of the present application is shown in FIG. 5.

[0044] Figure 6 A transmission curve diagram when the pseudo-random noise is injected from the sub-DAC and the sub-ADC provided in the embodiment of the present application is shown in FIG. 6.

[0045] Figure 7 A transmission curve diagram when the pseudo-random noise is injected from the sub-DAC provided in the prior art is shown in FIG. 7.

[0046] Figure 8 a transfer curve diagram shown in the prior art only when the pseudo-random noise is injected in the sub-ADC;

[0047] Figure 9 a simulation frequency spectrum diagram of the inter-stage gain after the inter-stage gain error calibration method of the pipeline ADC provided by the embodiment of the present application is calibrated;

[0048] Figure 10 a simulation frequency spectrum diagram of the inter-stage gain when the inter-stage gain error calibration is not performed in the pipeline ADC.

[0049] Reference signs:

[0050] 10 - pipeline stage to be calibrated 11 - sub-ADC 111 - (n-1). 5bit pipeline stage ADC

[0051] 112 - threshold value for + (2 n -1) / 2 n *V ref comparator 113 - threshold value for - (2 n -1) / 2 n *V ref comparator

[0052] 12 - sub-DAC 20 - later pipeline stage 30 - pseudo-random noise injection module

[0053] 40 - gain coefficient calibration module 50 - digital output code calibration module DETAILED DESCRIPTION

[0054] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0055] In order to facilitate the understanding of the inter-stage gain error calibration method of the pipeline ADC provided by the embodiments of the present application, the application scenario of the inter-stage gain error calibration method provided by the embodiments of the present application will be described first below. The inter-stage gain error calibration method is applied in a pipeline ADC, and the pipeline ADC includes multiple pipeline stages. Referring to Figure 3, the pipeline ADC has a to-be-calibrated pipeline stage 10 for completing n-bit digital code conversion and a post-stage pipeline stage 20 located at a stage after the to-be-calibrated pipeline stage 10, wherein the to-be-calibrated pipeline stage 10 comprises a sub-ADC 11 and a sub-DAC 12, and the inter-stage gain error calibration method is used for calibrating the inter-stage gain coefficient of the to-be-calibrated pipeline stage 10. The inter-stage gain error calibration method of the pipeline ADC is described in detail below with reference to the accompanying drawings.

[0056] With reference to Figure 2 and Figure 3 , the inter-stage gain error calibration method of the pipeline ADC provided by the embodiment of the present application comprises:

[0057] Step 10: inputting a sampling signal into the to-be-calibrated pipeline stage 10;

[0058] Step 20: injecting, into the sub-ADC 11, pseudo-random noise of a size of +1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noise, and simultaneously injecting, into the sub-DAC 12, pseudo-random noise of a size of -1 / b i *V ref in the i th pair of m pairs of sub-DAC pseudo-random noise; or injecting, into the sub-ADC 11, pseudo-random noise of a size of -1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noise, and simultaneously injecting, into the sub-DAC 12, pseudo-random noise of a size of +1 / b i *V ref in the i th pair of m pairs of sub-DAC pseudo-random noise; wherein m is a positive integer, the i th pair of sub-ADC pseudo-random noise and the i th pair of sub-DAC pseudo-random noise correspond to the same i th group of pseudo-random noise sequences, and a i =b i *2 n-1 ;

[0059] Step 30: determining a signal range available for calibration according to m, n, ±1 / a i *V ref ;

[0060] Step 40: when the sampling signal input into the to-be-calibrated pipeline stage 10 is located in the signal range available for calibration, determining an actual gain coefficient of the to-be-calibrated pipeline stage 10 according to an ideal digital code corresponding to a weight of the i th group of pseudo-random noise sequences, a post-stage digital output code output by the post-stage pipeline stage 20, and an ideal gain coefficient of the to-be-calibrated pipeline stage 10.

[0061] In the above scheme, by adopting the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time, and based on the sampling signal interval division manner of the input to-be-calibrated pipeline stage 10, the actual gain coefficient of the to-be-calibrated pipeline stage 10 is determined, and the inter-stage gain error is extracted. And when the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time, the residual voltage is maintained at ±1 / 2*V ref In this way, the requirement for the linearity of the to-be-calibrated pipeline stage amplifier signal can be greatly alleviated, and the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC 12 can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for high-precision ADC. At the same time, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time can achieve good spectrum scattering effect and improve the overall dynamic range of the pipeline ADC. The above steps will be described in detail below with reference to the accompanying drawings.

[0062] First, referring to Figure 2 and Figure 3 , a sampling signal is input to the to-be-calibrated pipeline stage 10. The sampling signal can come from the output signal output by the previous stage of the to-be-calibrated pipeline stage 10, or come from the analog signal collected from a certain collection point of the analog signal. As shown in Figure 3 , V in represents the input sampling signal; as shown in Figure 3 , V res represents the output signal of the to-be-calibrated pipeline stage 10 after processing, which is output to the subsequent stage pipeline stage 20 and serves as the input signal of the subsequent stage pipeline stage 20.

[0063] Next, referring to Figure 2 and Figure 3 , the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time is performed. Specifically, m pairs of sub-ADC pseudo-random noises can be injected into the sub-ADC 11 and the sub-DAC 12, where m is a positive integer such as 1, 2, 4, 5, etc. Each pair of sub-ADC pseudo-random noises contains two pseudo-random noises of opposite values, for example, the i-th pair of sub-ADC pseudo-random noises in the m pairs of sub-ADC pseudo-random noises can contain two pseudo-random noises of +1 / a i *V ref、 and -1 / a i *V refThe two pseudo-random noises are given by the formula, where i is any positive integer less than or equal to m. Each pair of sub-DAC pseudo-random noises contains two pseudo-random noises of opposite magnitudes. For example, the i-th pair of sub-DAC pseudo-random noises in m pairs of sub-DAC pseudo-random noises may contain two pseudo-random noises of magnitude +1 / b. i *V ref、 and -1 / b i *V ref Two pseudo-random noises, where i is any positive integer less than or equal to m. The i-th pair of sub-ADC pseudo-random noise corresponds to the i-th pair of sub-DAC pseudo-random noise, which is the same i-th set of pseudo-random noise sequences. That is, the i-th set of pseudo-random noise sequences simultaneously controls the injection of the i-th pair of sub-ADC pseudo-random noise and the i-th pair of sub-DAC pseudo-random noise into sub-ADC11 and sub-DAC12, respectively. And a i With b i They also satisfy the following relationship: a i =b i *2 n-1 .

[0064] Simultaneously injecting the i-th pair of pseudo-random noise into sub-ADC11 and the i-th pair of pseudo-random noise into sub-DAC12, the positive and negative directions of the pseudo-random noise injected into sub-ADC11 and sub-DAC12 differ depending on the different binary values ​​exiting the i-th group of pseudo-random noise sequences. It should be noted that the defined main direction of injection can be defined as a positive direction if the magnitude of the pseudo-random noise injected into sub-ADC11 is positive, and a negative direction if the magnitude of the pseudo-random noise injected into sub-ADC11 is negative. The following descriptions in this patent will use this as an example. Of course, the positive and negative directions can also be defined by the magnitude of the pseudo-random noise injected into sub-DAC12. Specifically, during injection, when the binary number exiting the i-th group of pseudo-random noise sequences is the first value, the magnitude of the pseudo-random noise injected into sub-ADC11 is +1 / a. i *V ref The pseudo-random noise, and the magnitude of the i-th pair of pseudo-random noise injected into the sub-ADC11 is +1 / a i *V ref While injecting pseudo-random noise, it also injects a pseudo-random noise of magnitude -1 / b into the i-th pair of sub-DACs. i *V ref The pseudo-random noise. When the binary number that jumps out of the i-th group of pseudo-random noise sequence is the second value, the size of the i-th pair of m pairs of pseudo-random noise injected into sub-ADC11 is -1 / a. i *V ref The pseudo-random noise, and in the i-th pair of m pairs of pseudo-random noise injected into sub-ADC11, the magnitude is -1 / a. i *V refthe mth pair of the m pairs of the sub-DAC pseudo-random noise is +1 / b i *V ref . Thus, the opposite direction pseudo-random noise dithering injection is realized from the sub-ADC 11 and the sub-DAC 12 at the same time.

[0065] It needs to be additionally explained that each pair of the ADC pseudo-random noise and the sub-DAC pseudo-random noise in the m pairs of the sub-ADC pseudo-random noise and the m pairs of the sub-DAC pseudo-random noise is injected into the sub-ADC 11 and the sub-DAC 12 at the same time according to the above injection mode.

[0066] The following introduces an injection mode with n=3, m=1, 1 / a i =1 / 16, 1 / b i =1 / 4. At this time, the transmission curve when the direction of the pseudo-random noise injected into the sub-DAC 12 and the direction of the pseudo-random noise injected into the sub-ADC 11 are opposite is shown in FIG. 3, which can be seen to be able to fold the two ends of the transmission curve of the to-be-calibrated pipeline stage 10, avoiding the overflow of the residual voltage due to the pseudo-random noise injection of the sub-DAC 12. Figure 6

[0067] Figure 7 FIG. 2 is a transmission curve diagram of the prior art in which only the sub-DAC is injected with the pseudo-random noise, the injection level is 2, and the size is ±1 / 4V ref . It can be seen that the middle part of the transmission curve will move up and down due to the injection of the pseudo-random noise, so that the originally compressed transmission curve in ±1 / 2V ref is expanded to ±3 / 4V ref . At the same time, when the pseudo-random noise is negative (downward), there is a risk of exceeding -V ref at the left end of the transmission curve. Similarly, when the pseudo-random noise is positive (upward), there is a risk of exceeding V ref at the right end of the transmission curve. This will cause the residual voltage output by the current stage to exceed the quantization range of the next pipeline stage, causing nonlinearity of the conversion.

[0068] Figure 8 FIG. 1 is a transmission curve diagram of the prior art in which only the sub-ADC is injected with the pseudo-random noise, the injection level is 2, and the size is ±1 / 16V ref . It can be seen that the jump point of the transmission curve will move left and right due to the injection of the pseudo-random noise, and will also expand the originally compressed transmission curve in ±1 / 2V ref to ±3 / 4V ref , greatly increasing the requirement for the linearity of the amplified signal of the to-be-calibrated pipeline stage. ​

[0069] The injection method described above in this application is similar to... Figure 7 and Figure 8 Compared to the two injection methods shown in the prior art, the residual voltage can be maintained within ±1 / 2*V. ref Within this range, the linearity requirements for the calibrated pipelined operational amplifier signal can be greatly alleviated, avoiding the phenomenon of residual voltage overflow. Furthermore, this application injects a larger logarithm of pseudo-random noise into the sub-ADC11 and sub-DAC12 compared to... Figure 7 and Figure 8 Compared to the injection method shown, it can achieve better spectrum dispersion and improve the overall dynamic range of the pipeline ADC.

[0070] Next, refer to Figure 2 and Figure 3 Based on m, n, ±1 / a i *V ref The range of signals usable for calibration is determined. The calibration procedure is initiated only if the sampled signal received by the flow stage 10 to be calibrated falls within the range of signals usable for calibration. The calibration procedure is not initiated if the sampled signal received by the flow stage 10 to be calibrated does not fall within the range of signals usable for calibration. This is based on m, n, and ±1 / a. i *V ref When determining the range of signals that can be used for calibration, m, n, and ±1 / a can be used as a reference. i *V ref The range of the sampled signal affected only by the pseudo-random noise of the i-th pair of sub-DACs and not by the pseudo-random noise of the i-th pair of sub-ADCs is calculated, and this range is used as the range of signals that can be used for calibration. Figure 6 Taking the transmission curve shown as an example, it can be seen that the input sampled signal can be filtered accordingly, when the sampled signal size is limited to... Figure 6When the sampling signal is within the arrow range, the input sampling signal is only affected by the sub-DAC pseudo-random noise injection, and is not affected by the sub-ADC pseudo-random noise injection. When the sampling signal is within the signal range available for calibration, calibration can be performed to realize inter-stage gain calibration. In the above manner, the sampling signal of the input flow water stage 10 to be calibrated is only affected by the sub-DAC pseudo-random noise sequence injection. When the sampling signal is within the signal range available for calibration, calibration can be started. That is, only the sampling signal within the calibration available range is subjected to the corresponding correlation operation, which is equivalent to the case where only the sub-DAC 12 injects the pseudo-random noise sequence, so that the inter-stage gain coefficient can be extracted. In the calibration process, the equivalent injection is the pseudo-random noise sequence which is irrelevant to the sampling signal, so as not to interfere with the operation of the sub-ADC 11 and the entire flow pipeline ADC. Since the pseudo-random noise sequence passes through the same path as the sub-DAC 12 signal, it will encounter the same non-ideal situation, so that the actual gain coefficient of the flow water stage 10 to be calibrated can be detected, and the inter-stage gain error can be extracted.

[0071] Specifically, when m = 1, the signal range available for calibration is determined according to m, n, ±1 / a i *V ref The signal range available for calibration can be specifically:

[0072]

[0073] Wherein, By injecting a pair of pseudo-random noises to the sub-ADC 11 and the sub-DAC 12, the circuit structure of the operation algorithm is simplified.

[0074] Taking n = 3, m = 1, 1 / a i = 1 / 16, 1 / b i = 1 / 4 as an example, the input signal range affected only by the sub-DAC pseudo-random noise injection is calculated as follows:

[0075] Table 1- Signal range available for calibration statistics

[0076]

[0077] When m > 1, m can be specifically 2, 3, 4, 5, 6, 7, 8, etc. any positive integer not less than 2, at this time, the signal range available for calibration is determined according to m, n, ±1 / a i *V ref The signal range available for calibration can be specifically:

[0078]

[0079] Wherein, This means that the superposition effect of multiple pairs of pseudo-random noise from the sub-ADCs and sub-DACs is considered to derive the signal range that can be used for calibration. In addition, by simultaneously injecting at least two pairs of pseudo-random noise into the sub-ADC11 and sub-DAC12, the logarithm of the pseudo-random noise injected into the sub-ADC11 and sub-DAC12 is increased, which can improve the spectral dispersion effect and further enhance the overall dynamic range of the pipelined ADC.

[0080] Next, refer to Figure 2 , Figure 3 and Figure 4 After receiving each sampled signal, it is determined whether the sampled signal is within the signal range that can be used for calibration obtained above. If not, the calibration procedure is not started. If the sampled signal of the pipeline stage 10 to be calibrated is within the signal range that can be used for calibration, the calibration procedure is started, and the actual gain coefficient of the pipeline stage 10 to be calibrated is determined based on the ideal digital code corresponding to the weight of the i-th group of pseudo-random noise sequence, the subsequent digital output code of the subsequent pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated.

[0081] Specifically, based on the ideal digital code corresponding to the weights of the i-th group of pseudo-random noise sequence, the subsequent digital output code of the subsequent pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated, the LMS iterative algorithm can be used to determine the actual gain coefficient of the pipeline stage 10 to be calibrated. By using the LMS convergence iteration method, combined with pseudo-random noise jitter injection technology and related operations, the inter-stage gain error is extracted, thereby improving the accuracy of the obtained actual gain coefficient of the pipeline stage 10 to be calibrated.

[0082] When specifically using the LMS algorithm to determine the actual gain coefficient of the flow stage 10 to be calibrated, refer to... Figure 4 The iterative calculation can be performed according to the following formula:

[0083]

[0084] in, This indicates the number of iterations, starting from 0. Represents the ideal interstage gain coefficient; This represents the estimated interstage gain coefficient. and They represent the first j The estimated inter-stage gain coefficient generated in the iteration and the... j The estimated interstage gain coefficients are generated in +1 iterations; The ideal digital code representing the weights corresponding to the i-th group of pseudo-random noise sequences; The output digital code of the 20-stage pipeline stage; This represents the convergence step factor, which controls the accuracy and convergence time of the algorithm. For example...Figure 4 D in o B = ,like Figure 4 In This represents the actual gain coefficient of the flow stage 10 to be calibrated. Figure 4 D in PN_es = That is, first set an initial value. Substituting this into the above iterative formula, we can calculate... Then iterative calculations are performed.

[0085] Furthermore, after each iteration of the calculation, it can be determined that... and Check if the difference between them is less than a set threshold; if not, continue to the next iteration; otherwise, This serves as the actual gain coefficient for the pipeline stage 10 to be calibrated. This is determined after each iteration. and The iterative calculation stops only when the difference between the values ​​is less than a set threshold, thereby improving the accuracy of the actual gain coefficient of the pipeline stage 10 to be calibrated.

[0086] In addition, such as Figure 4 As shown, the inter-stage gain error calibration method can further include: calibrating the output digital code of the subsequent pipeline stage 20 based on the ideal digital code corresponding to the weights of the i-th group of pseudo-random noise sequences, the ideal gain coefficient of the pipeline stage 10 to be calibrated, and the actual gain coefficient, to obtain the calibrated output digital code of the subsequent stage; and calibrating the output digital code of the subsequent pipeline stage 20 by using the actual gain coefficient of the pipeline stage 10 to be calibrated, thereby improving the analog-to-digital conversion accuracy of the pipeline stage ADC. Specifically, refer to... Figure 4 The calibration can be performed using the following formula to obtain the calibrated digital output code D. o B _cal:

[0087] D o B _cal =

[0088] The following uses MATLAB to model and simulate this interstage gain error calibration method. The simulated spectra before and after interstage gain calibration are shown below. Figure 9 and Figure 10 As shown in Table 2, the performance comparison before and after calibration is shown in the figure.

[0089] Table 2 - Comparison of Simulation Performance Before and After Interstage Gain Calibration

[0090]

[0091] By adopting the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time, and based on the interval division mode of the sampling signal of the input to-be-calibrated pipeline stage 10, the actual gain coefficient of the to-be-calibrated pipeline stage 10 is determined, and the inter-stage gain error is extracted. When the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 is performed at the same time, the residual voltage is maintained at ±1 / 2*V ref In this way, the requirement for the linearity of the to-be-calibrated pipeline stage to amplify the signal can be greatly relieved, and the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC 12 can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for high-precision ADC. Meanwhile, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 can be performed, so that good spectrum scattering effect can be achieved, and the overall dynamic range of the pipeline ADC can be improved.

[0092] Further, the embodiment of the present application further provides an inter-stage gain error calibration circuit of a pipeline ADC. Referring to Figure 2 、 Figure 3 and Figure 4 , the pipeline ADC comprises a plurality of pipeline stages, the plurality of pipeline stages comprise a to-be-calibrated pipeline stage 10 for completing n-bit digital code conversion and a post-stage pipeline stage 20 located at a stage after the to-be-calibrated pipeline stage, and the to-be-calibrated pipeline stage 10 comprises a sub-ADC 11 and a sub-DAC 12. The inter-stage gain error calibration circuit comprises a sample-and-hold module, a pseudo-random noise injection module 30, a calibration signal determination module and a gain coefficient calibration module 40. The sample-and-hold module is used to acquire a sampling signal and input the sampling signal to the to-be-calibrated pipeline stage 10. The pseudo-random noise injection module 30 is used to inject pseudo-random noise with a size of +1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noise to the sub-ADC 11, and simultaneously inject pseudo-random noise with a size of -1 / b i *V ref in the i th pair of m pairs of sub-DAC pseudo-random noise to the sub-DAC 12; or the pseudo-random noise injection module 30 is used to inject pseudo-random noise with a size of -1 / a i *V ref in the i th pair of m pairs of sub-ADC pseudo-random noise to the sub-ADC 11, and simultaneously inject pseudo-random noise with a size of +1 / b i *V refwherein m is a positive integer, the ith pair of sub-ADC pseudo-random noises corresponds to the same ith group of pseudo-random noise sequences as the ith pair of sub-DAC pseudo-random noises, and a i = b i *2 n-1 The calibration signal determination module is configured to determine a signal range available for calibration according to m, n, ±1 / a i *V ref The gain coefficient calibration module 40 is configured to determine an actual gain coefficient of the flow water stage 10 to be calibrated according to an ideal digital code corresponding to a weight of the ith group of pseudo-random noise sequences, a digital output code output by the subsequent flow water stage 20, and an ideal gain coefficient of the flow water stage 10 to be calibrated, when a sampling signal input to the flow water stage 10 to be calibrated is located in the signal range available for calibration.

[0093] In the above scheme, the actual gain coefficient of the flow water stage 10 to be calibrated is determined by simultaneously injecting the sub-ADC 11 and the sub-DAC 12 with the pseudo-random noise in opposite directions, and based on the interval division manner of the sampling signal input to the flow water stage 10 to be calibrated, so as to extract the inter-stage gain error. When the sub-ADC 11 and the sub-DAC 12 simultaneously inject the pseudo-random noise in opposite directions, the residual voltage is maintained within ±1 / 2*V ref , which can greatly alleviate the requirement for the linearity of the amplified signal of the flow water stage to be calibrated, and avoid the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC 12. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for high-precision ADC. Meanwhile, on the basis of completing the inter-stage gain calibration, the sub-ADC 11 and the sub-DAC 12 can simultaneously inject the pseudo-random noise in opposite directions to achieve good spectrum scattering effect and improve the overall dynamic range of the flow water stage ADC. The above various functional modules will be described in detail below in combination with the accompanying drawings.

[0094] When the above sub-ADC 11 is set, referring to Figure 5 , the sub-ADC 11 can include an (n-1).5bit flow water stage ADC 111 composed of 2 n -2 comparators, and two comparators with threshold values of ±(2 n -1) / 2 n *V ref , i.e., a comparator 112 with a threshold value of +(2n-1) / 2n*Vref and a comparator 113 with a threshold value of -(2n-1) / 2n*Vref. The pseudo-random noise injection module 30 injects the sub-ADC 11 with the pseudo-random noise in the ith pair of m pairs of sub-ADC pseudo-random noises with sizes of ±1 / a i *Vref pseudo-random noise. Figure 5 The n=3 of the sub-ADC 11 shown in the figure, on the basis of the original 2.5 bit pipeline ADC composed of 6 comparators, respectively, increase the threshold of ±7 / 8*V ref

[0095] When setting the sub-DAC 12, the sub-DAC 12 can include (n-1).5bit pipeline DAC composed of 2 n -2 capacitors, and two capacitors with the same size as one of the 2 n -2 capacitors, that is, two capacitors with the same size as the other capacitors. There can also be a pseudo-random noise capacitor in the pseudo-random noise injection module 30, which injects the i-th pair of m pairs of sub-DAC pseudo-random noise with the size of ±1 / b i *V ref into the sub-DAC 12 through the pseudo-random noise capacitor. It is convenient to realize the pseudo-random noise dithering injection in the opposite direction from the sub-ADC 11 and the sub-DAC 12 at the same time.

[0096] When setting the calibration signal determination module, according to the reference Figure 2 , Figure 3 and Figure 4 , the calibration signal determination module can calculate the signal range of the sampling signal affected only by the i-th pair of sub-DAC pseudo-random noise and not affected by the i-th pair of sub-ADC pseudo-random noise according to m, n, ±1 / a i *V ref , and take the signal range as the signal range available for calibration. Make the sampling signal of the input calibration pipeline 10 only affected by the sub-DAC pseudo-random noise sequence injection. When the sampling signal is in the signal range available for calibration, the calibration can be started. That is, only the sampling signal in the calibration available range is subjected to the corresponding correlation operation, which is equivalent to the case where only the sub-DAC 12 injects the pseudo-random noise sequence, that is, the inter-stage gain coefficient can be extracted. In the calibration process, the equivalent injection is the pseudo-random noise sequence irrelevant to the sampling signal, so as not to interfere with the operation of the sub-ADC 11 and the entire pipeline ADC. Since the pseudo-random noise sequence passes through the same path as the sub-DAC 12 signal, it will encounter the same non-ideal situation, so that the actual gain coefficient of the calibration pipeline 10 can be detected, and the inter-stage gain error can be extracted. The working process of the calibration signal determination module can refer to the description of the foregoing method part, which will not be described here.

[0097] ​The m can be equal to 1, at this time, the calibration signal determination module determines the signal range available for calibration according to m, n, ±1 / a i *V ref The determined signal range available for calibration can be specifically:

[0098]

[0099] Wherein, By injecting a pair of pseudo-random noise into the sub-ADC 11 and the sub-DAC 12, the circuit structure of the running algorithm is simplified. For specific introduction, reference can be made to the description of the related part of the foregoing method, which will not be repeated here.

[0100] The m can be a positive integer greater than 1, at this time, the calibration signal determination module determines the signal range available for calibration according to m, n, ±1 / a i *V ref The determined signal range available for calibration can be specifically:

[0101]

[0102] Wherein, By injecting at least two pairs of pseudo-random noise into the sub-ADC 11 and the sub-DAC 12, the frequency spectrum scattering effect can be improved, and the overall dynamic range of the pipeline ADC can be further improved. For specific introduction, reference can be made to the description of the related part of the foregoing method, which will not be repeated here.

[0103] In the specific setting of the gain calibration module, reference Figure 2 , Figure 3 and Figure 4 The gain coefficient calibration module 40 can determine the actual gain coefficient of the pipeline stage 10 to be calibrated according to the ideal digital code of the weight corresponding to the i-th group of pseudo-random noise sequences, the digital output code output by the subsequent pipeline stage 20, and the ideal gain coefficient of the pipeline stage 10 to be calibrated. By using the LMS convergence iteration method, combined with the pseudo-random noise jitter injection technology and related operations, the inter-stage gain error is extracted, and the accuracy of the actual gain coefficient of the pipeline stage 10 to be calibrated is improved.

[0104] When the gain coefficient calibration module 40 specifically uses LMS convergence iteration for calibration, reference Figure 2 , Figure 3 and Figure 4 The gain coefficient calibration module 40 can include an LMS algorithm iteration module and a threshold judgment module. The LMS algorithm iteration module is used for iteration operation according to the following formula:

[0105]

[0106] Wherein, This indicates the number of iterations, starting from 0. Represents the ideal interstage gain coefficient; This represents the estimated interstage gain coefficient. and They represent the first j The estimated inter-stage gain coefficient generated in the iteration and the... j The estimated interstage gain coefficients are generated in +1 iterations; The ideal digital code representing the weights corresponding to the i-th group of pseudo-random noise sequences; The output digital code of the 20-stage pipeline stage; This represents the convergence step factor.

[0107] The threshold determination module is used to determine the threshold value after each iteration of the calculation. and The module checks if the difference between the two values ​​is less than a set threshold. If not, the LMS algorithm iteration module continues with the next iteration; otherwise, the threshold judgment module will... This serves as the actual gain coefficient for the pipeline stage 10 to be calibrated. This is determined after each iteration. and The iterative calculation stops only when the difference between the values ​​is less than a set threshold, thereby improving the accuracy of the actual gain coefficient of the pipeline stage 10 to be calibrated. The specific calculation method can be found in the description of the aforementioned method section, and will not be repeated here.

[0108] Additionally, refer to Figure 2 , Figure 3 and Figure 4 The interstage gain error calibration circuit may further include a digital output code calibration module 50. This module 50 calibrates the output digital code of the subsequent pipeline stage 20 based on the ideal digital code corresponding to the weights of the i-th group of pseudo-random noise sequences, the ideal gain coefficient of the pipeline stage 10 to be calibrated, and the actual gain coefficient. This calibrates the output digital code of the subsequent pipeline stage 20 by using the actual gain coefficient of the pipeline stage 10 to be calibrated, thereby improving the analog-to-digital conversion accuracy of the pipeline ADC. The specific implementation of the calibration process for the output digital code of the subsequent pipeline stage 20 by the digital output code calibration module 50 can be found in the aforementioned method section description, and will not be repeated here.

[0109] The actual gain coefficient of the to-be-calibrated pipeline stage 10 is determined by adopting the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time and based on the interval division mode of the sampling signal of the input to-be-calibrated pipeline stage 10, and the inter-stage gain error is extracted. When the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time is performed, the residual voltage is maintained within ±1 / 2*V ref Therefore, the requirement for the linearity of the to-be-calibrated pipeline stage under the amplified signal can be greatly relieved, and the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC 12 can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for a high-precision ADC. Meanwhile, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time can achieve good spectrum scattering effect and improve the overall dynamic range of the pipeline ADC.

[0110] In addition, the embodiment of the present application further provides a pipeline ADC, which comprises a plurality of pipeline stages, and the pipeline ADC comprises a to-be-calibrated pipeline stage 10 and a post-stage pipeline stage 20 located at a stage after the to-be-calibrated pipeline stage, wherein the to-be-calibrated pipeline stage 10 comprises a sub-ADC 11 and a sub-DAC 12. Figure 2 、 Figure 3 and Figure 4 The pipeline ADC further comprises the inter-stage gain error calibration circuit of any one of the pipeline ADCs. The actual gain coefficient of the to-be-calibrated pipeline stage 10 is determined by adopting the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time and based on the interval division mode of the sampling signal of the input to-be-calibrated pipeline stage 10, and the inter-stage gain error is extracted. When the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time is performed, the residual voltage is maintained within ±1 / 2*V ref Therefore, the requirement for the linearity of the to-be-calibrated pipeline stage under the amplified signal can be greatly relieved, and the overflow of the residual voltage caused by the pseudo-random noise injection of the sub-DAC 12 can be avoided. The inter-stage gain error calibration method can achieve good inter-stage gain calibration effect for a high-precision ADC. Meanwhile, on the basis of completing the inter-stage gain calibration, the pseudo-random noise dithering injection in opposite directions from the sub-ADC 11 and the sub-DAC 12 at the same time can achieve good spectrum scattering effect and improve the overall dynamic range of the pipeline ADC.

[0111] The above merely illustrates the specific embodiments of the present application, but the protection scope of the present application is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for calibrating inter-stage gain error of a pipeline ADC, the pipeline ADC comprising a plurality of pipeline stages, the plurality of pipeline stages having a to-be-calibrated pipeline stage for completing n-bit digital code conversion and a post-stage pipeline stage located at a stage after the to-be-calibrated pipeline stage, the to-be-calibrated pipeline stage comprising a sub-ADC and a sub-DAC; characterized in that, The inter-stage gain error calibration method comprises: inputting a sample signal into the pipeline stage to be calibrated; injecting, into the sub-ADC, a pseudo-random noise of a size of +1 / a i *V ref of the i-th pair of the m pairs of sub-DAC pseudo-random noises, while simultaneously injecting, into the sub-DAC, a pseudo-random noise of a size of -1 / b i *V ref of the i-th pair of the m pairs of sub-DAC pseudo-random noises; or, injecting, into the sub-ADC, a pseudo-random noise of a size of -1 / a i *V ref of the i-th pair of the m pairs of sub-ADC pseudo-random noises, while simultaneously injecting, into the sub-DAC, a pseudo-random noise of a size of +1 / b i *V ref of the i-th pair of the m pairs of sub-DAC pseudo-random noises; wherein m is a positive integer, V ref represents a reference voltage of the pipeline ADC, 1 / a i *V ref represents a size of the i-th pair of sub-ADC pseudo-random noises, 1 / b i *V ref represents a size of the i-th pair of sub-DAC pseudo-random noises, the i-th pair of sub-ADC pseudo-random noises and the i-th pair of sub-DAC pseudo-random noises correspond to a same i-th group of pseudo-random noise sequences, and a i =b i *2 n-1 ; determining a signal range available for calibration based on the m, n, ±1 / a i *V ref determining a signal range available for calibration based on the m, n, ±1 / a i *V ref calculating a signal range in which the sampling signal is only affected by the ith pair of sub-DAC pseudo-random noise and not affected by the ith pair of sub-ADC pseudo-random noise, and taking the signal range as the signal range available for calibration; when the sample signal input into the pipeline stage to be calibrated is within the signal range available for calibration, determining an actual gain coefficient of the pipeline stage to be calibrated according to an ideal digital code corresponding to a weight of the i-th set of pseudo-random noise sequences, a post-stage digital output code output by the post-stage pipeline stage, and an ideal gain coefficient of the pipeline stage to be calibrated.

2. The inter-stage gain error calibration method of claim 1, wherein, m=1； Based on the stated m, n, ±1 / a i *V ref The determined range of signals that can be used for calibration is specifically as follows: wherein .

3. The method of inter-stage gain error calibration of claim 1, wherein, m＞1； According to the m, n, ±1 / a i *V ref The signal range available for calibration is determined, in particular: in, .

4. The inter-stage gain error calibration method of claim 1, wherein, The actual gain coefficient of the pipeline stage to be calibrated is determined according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated by using an LMS algorithm.

5. The inter-stage gain error calibration method of claim 4, wherein, The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. wherein denotes the number of iterations starting from 0; Represents the ideal interstage gain coefficient; denote an estimated inter-stage gain coefficient, and denote an estimated inter-stage gain coefficient generated at the j first iteration and an estimated inter-stage gain coefficient generated at the j +1 iteration, respectively; a perfect number code representing the weight corresponding to the ith pseudo-random noise sequence; a late stage digital output code output by the late stage pipeline stage; represents a convergence step factor; and after each iteration calculation, it is determined whether the difference between and is less than a set threshold value; The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. Otherwise, set as the actual gain factor of the pipeline to be calibrated.

6. The inter-stage gain error calibration method of claim 1, wherein, The inter-stage gain error calibration circuit comprises: a sample holding module configured to acquire a sample signal and input the sample signal into the pipeline stage to be calibrated; 7. An inter-stage gain error calibration circuit for a pipelined ADC, the pipelined ADC comprising a plurality of pipeline stages, the plurality of pipeline stages having a to-be-calibrated pipeline stage for completing a digital code conversion of n bits, and a subsequent pipeline stage located one stage after the to-be-calibrated pipeline stage, the to-be-calibrated pipeline stage comprising a sub-ADC and a sub-DAC; characterized in that, a gain coefficient calibration module configured to, when the sample signal input into the pipeline stage to be calibrated is within the signal range available for calibration, determine an actual gain coefficient of the pipeline stage to be calibrated according to an ideal digital code corresponding to a weight of the i-th set of pseudo-random noise sequences, a post-stage digital output code output by the post-stage pipeline stage, and an ideal gain coefficient of the pipeline stage to be calibrated. The actual gain coefficient of the pipeline stage to be calibrated is determined according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated by using an LMS algorithm. a pseudo-random noise injection module configured to inject, into the sub-ADC, a pseudo-random noise of a size of +1 / a i *V ref in an i-th pair of m pairs of sub-ADC pseudo-random noises while simultaneously injecting, into the sub-DAC, a pseudo-random noise of a size of -1 / b i *V ref in the i-th pair of m pairs of sub-DAC pseudo-random noises; or the pseudo-random noise injection module is configured to inject, into the sub-ADC, a pseudo-random noise of a size of -1 / a i *V ref in the i-th pair of m pairs of sub-ADC pseudo-random noises while simultaneously injecting, into the sub-DAC, a pseudo-random noise of a size of +1 / b i *V ref in the i-th pair of m pairs of sub-DAC pseudo-random noises; wherein m is a positive integer, V ref represents a reference voltage of the pipeline ADC, 1 / a i *V ref represents the size of the i-th pair of sub-ADC pseudo-random noises, 1 / b i *V ref represents the size of the i-th pair of sub-DAC pseudo-random noises, the i-th pair of sub-ADC pseudo-random noises and the i-th pair of sub-DAC pseudo-random noises correspond to a same i-th group of pseudo-random noise sequences, and a i =b i *2 n-1 ; The calibration signal determining module is configured to determine a signal range available for calibration according to the m, n, ±1 / a i *V ref , and the signal range available for calibration includes: the calibration signal determining module calculates a signal range in which the sampling signal is only affected by the i-th pair of sub-DAC pseudo-random noise but not affected by the i-th pair of sub-ADC pseudo-random noise, and takes the signal range as the signal range available for calibration. i *V ref , and the signal range available for calibration includes: the calibration signal determining module calculates a signal range in which the sampling signal is only affected by the i-th pair of sub-DAC pseudo-random noise but not affected by the i-th pair of sub-ADC pseudo-random noise, and takes the signal range as the signal range available for calibration. The gain coefficient calibration module comprises an LMS algorithm iteration module and a threshold judgment module.

8. The inter-stage gain error calibration circuit of claim 7, wherein, The sub-ADC includes: (n-1).5bit pipelined ADC composed of 2 n -1) / 2 n -1) / 2 n *V ref comparators with threshold values of ±(2 The sub-DAC includes: (n-1).5bit pipeline DAC composed of 2 n -2 capacitors, and two capacitors with the same size as one of the 2 n -2 capacitors The pseudo-random noise injection module injects the m pairs of sub-ADC pseudo-random noises into the sub-ADCs by changing the threshold values of the comparators of the sub-ADCs, and the size of the i-th pair of the m pairs of sub-ADC pseudo-random noises is ±1 / a i *V ref ​ The pseudo-random noise injection module is further provided with a pseudo-random noise capacitor; the pseudo-random noise injection module injects, through the pseudo-random noise capacitor, the pseudo-random noise with the size of ±1 / b i *V ref in the i-th pair of m pairs of sub-DAC pseudo-random noises into the sub-DAC.

9. The inter-stage gain error calibration circuit of claim 7, wherein, m=1； The calibration signal determination module determines the signal range available for calibration according to the m, n, ±1 / a i *V ref The determined signal range available for calibration is specifically: wherein .

10. The inter-stage gain error calibration circuit of claim 7, wherein, m＞1； The calibration signal determination module determines the signal range available for calibration according to the m, n, ±1 / a i *V ref The determined signal range available for calibration is specifically: wherein .

11. The inter-stage gain error calibration circuit of claim 7, wherein, The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated.

12. The inter-stage gain error calibration circuit of claim 11, wherein, The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. The actual gain coefficient of the pipeline stage to be calibrated is determined by using an LMS algorithm according to the ideal digital code corresponding to the weight of the i-th set of pseudo-random noise sequences, the post-stage digital output code output by the post-stage pipeline stage, and the ideal gain coefficient of the pipeline stage to be calibrated. in, This indicates the number of iterations, starting from 0. represents the ideal inter-stage gain coefficient; denote an estimated inter-stage gain coefficient, and denote an estimated inter-stage gain coefficient generated at the j first iteration and an estimated inter-stage gain coefficient generated at the j +1 iteration, respectively; denotes the ideal digital code of the weight corresponding to the i-th set of pseudo-random noise sequences; a late stage digital output code output by the late stage pipeline stage; denotes the convergence step factor; The threshold determination module is used to determine the threshold after each iteration calculation. and The module checks whether the difference between the two values ​​is less than a set threshold. If it is not less, the LMS algorithm iteration module continues with the next iteration; otherwise, the threshold determination module will... This serves as the actual gain coefficient for the flow stage to be calibrated.

13. The inter-stage gain error calibration circuit of claim 7, wherein, The inter-stage gain error calibration circuit of the pipeline ADC according to any one of claims 7-13. ​ 14. A pipelined ADC, characterized by ​ ​ ​ ​

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