A moving target detection system accelerated by ZYNQ

Abstract

The present invention belongs to the technical field of ZYNQ moving target detection, and particularly relates to a moving target detection system based on ZYNQ acceleration, including an image acquisition module, an image caching module, an image processing module, and an image display module. The image acquisition module is respectively connected to the image caching module and the image processing module. The image processing module is respectively connected to the image caching module and the image display module. The image caching module is connected to the image display module. The present invention does not need to rely on a traditional computer platform, has significant advantages in terms of system volume ratio, and is convenient for deployment. Compared with an FPGA, the present invention can directly call off-chip resources such as DDR3. Compared with a traditional platform, ping-pong storage acceleration is used in the reading, writing, and storage of image data, which only requires a few clock cycles and can be processed in parallel. In contrast, traditional images must sequentially process the current frame before proceeding to the next frame, and the processing speed has a huge advantage.

Description

Technical Field

[0001] The present invention belongs to the technical field of ZYNQ moving target detection, and particularly relates to a moving target detection system accelerated by ZYNQ. Background Art

[0002] Computer vision and image processing algorithms are widely used in many industrial, medical, commercial, and research-related fields. And moving target detection is an important part of computer vision. Modern imaging systems provide high-resolution images at high frame rates and usually require complex calculations to process image data. However, in many applications, fast processing of data is required, or the delay of the analysis results needs to be minimized. In these applications, the central processing unit (CPU) cannot perform the corresponding tasks well because they cannot execute calculations at a sufficient speed. Summary of the Invention

[0003] In view of the above technical problems, the present invention provides a moving target detection system accelerated by ZYNQ, which is small in size, fast in processing speed, and wide in application range.

[0004] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0005] A moving target detection system accelerated by ZYNQ includes an image acquisition module, an image buffer module, an image processing module, and an image display module. The image acquisition module is respectively connected to the image buffer module and the image processing module. The image processing module is respectively connected to the image buffer module and the image display module. The image buffer module is connected to the image display module.

[0006] The image acquisition module includes an SCCB control module, a camera, and a first data conversion module. The SCCB control module is connected to the camera. The SCCB control module controls the camera to perform real-time acquisition of moving targets in the environment. The camera is connected to the first data conversion module. The first data conversion module is respectively connected to the image buffer module and the image processing module. The first data conversion module converts the acquired RGB565 image into an AXI4_Stream data stream.

[0007] The image cache module includes a DDR3 cache module, an AXI bus, VDMA0, and VDMA1. The DDR3 cache module is connected to VDMA0 and VDMA1 respectively through the AXI bus. VDMA0 is connected to the first data conversion module and the image processing module of the image acquisition module, and VDMA1 is connected to the image display module. VDMA0 and VDMA1 are used to convert the data stream in AXI4_Stream format into Memory Map format or convert the data in Memory Map format into AXI4_Stream data stream.

[0008] The image display module includes a second data conversion module, a display module, and an HDMI display. The second data conversion module is connected to the HDMI display through the display module, and the second data conversion module is connected to VDMA1. The second data conversion module converts the AXIS data stream into the one containing its line and field synchronization signals required for HDMI video protocol display.

[0009] The image processing module includes a format conversion module, an image filtering module, a frame difference operation module, a binarization module, and a target display module. The format conversion module is connected to the frame difference operation module through the image filtering module, and the frame difference operation module is connected to the target display module through the binarization module.

[0010] The camera uses an OV5640 camera.

[0011] A detection method for a moving target detection system based on ZYNQ acceleration. The processing method of the image processing module is as follows: including the following steps:

[0012] S1. Image format conversion: Divide the color video stream input by the camera into two parts. One is used to convert to grayscale for subsequent image processing; the other is used for display and tracking after image processing.

[0013] Convert the RGB565 data converted into the AXI4_Stream data stream into RGB888 data. Keep the high bits unchanged and supplement the low bits, that is, {R[4:0], R[2:0]}, {G[5:0], G[2:0]}, {B[4:0], B[2:0]}

[0014] Y = 0.299R + 0.587G + 0.114B

[0015] Cb = 0.568(B - Y) + 128 = -0.172R - 0.339G + 0.511B + 128

[0016] Cr = 0.713(R - Y) + 128 = 0.511R - 0.428G + 128

[0017] After the transformation matrix is multiplied by 256, it only needs to shift Y, Cb, and Cr 8 bits to the right to restore, and the following formula is obtained:

[0018] Y = ((77 * R + 150 * G + 29 * B) >> 8)

[0019] Cb = ((-43 * R - 85 * G + 128 * B) >> 8) + 128

[0020] Cr = ((128 * R - 107 * G - 21 * B) >> 8 + 128

[0021] Since the appearance of negative numbers in Verilog operations will cause errors and occupy relatively high resources, the above formula is transformed to obtain the following formula:

[0022] Y = (77 * R + 150 * G + 29 * B) >> 8

[0023] Cb = (-43 * R - 85 * G + 128 * B + 32768) >> 8

[0024] Cr = (128 * R - 107 * G - 21 * B + 32768) >> 8

[0025] The R, G, and B respectively represent the color space model with red, green, and blue as the primary colors. The Y, Cb, and Cr are a color coding method adopted by the European television system. The Y represents the brightness, that is, the gray scale value. The Cb and Cr represent the chrominance, which is used to describe the saturation and hue of the image. The conversion between the R, G, and B and the Y, Cb, and Cr is the conversion of the color space, that is, converting the primary color color space of the R, G, and B into the color space model of the brightness and chrominance represented by the Y, Cb, and Cr;

[0026] S2. Median filtering: When implementing the median filtering algorithm using Verilog, the pipelining operation method is used to perform quick sorting on the 3x3 filtering module;

[0027] In order to obtain the 3x3 filtering template, the data of the first two rows are first stored. Therefore, a RAM is introduced. When the data of the third row arrives, it is read out. At this time, a 3x1 matrix will be obtained. Next, this 3x1 matrix is continuously stored three times to obtain the required 3x3 template, and then the median filtering is implemented through Verilog;

[0028] S3, Frame Difference Method and Binarization: Consider a frame of image data input by the camera as the current frame. VDMA performs frame buffering through ping-pong operation. That is, when writing the current image data to address 0 of the DDR3 buffer module, it reads the image data buffered in the previous frame at address 1 simultaneously. The key in performing frame difference operation is to align each pixel data of the current frame with that of the previous frame. Therefore, when waiting for the current frame to be valid, VDMA reads the previous frame data from the DDR3 buffer module and caches it into the FIFO. At the same time, since both reading and writing of the FIFO require one clock cycle, it is necessary to delay the current frame data by two clock cycles to align the image data. At this time, the two frames of data can perform frame difference operation after image processing, and then perform binarization analysis on the difference result. When the absolute value of the difference result is greater than the set threshold, the result is 1 and is displayed as white, otherwise it is black. ZYNQ can process binary data with only 0 and 1 very simply and has good real-time performance. After binarization analysis is completed, count all pixel points with a value of 1, which are the detected moving targets;

[0029] S4, Target Display: After obtaining the result of binarization analysis, frame the area where the moving target is located with a rectangle and superimpose the rectangle on the original RGB color image data output by the camera to complete the detection of real-time moving targets.

[0030] The method for implementing the median filtering module in Verilog in S2 is as follows:

[0031] S2.1. First, in order to find the max, med, and min values of each row in the matrix, it is necessary to instantiate the sorting module three times;

[0032] S2.2. Second, it is necessary to obtain the min_of_max, med_of_med, and max_of_min values respectively. For this purpose, it is necessary to instantiate the sorting module three more times and input the 3 max, med, and min values of each row obtained in the first step into the sorting module;

[0033] S2.3 Finally, instantiate the sorting module one more time, take the median value with the three values output in the second step as the input.

[0034] In S4, the operation of superimposing the rectangle on the original RGB color image data output by the camera is as follows: By calculating and comparing the pixel points with a value of 1 after binarization, obtain the upper, lower, left, and right boundaries of the moving target area. Then, on the original color image data, calculate the coordinate values of each pixel point again. When the coordinate value is on the boundary, assign the R signal of the corresponding pixel point to 255 to obtain a red display border, and then output it to the HMDI display screen to complete the display and tracking of the moving target.

[0035] Compared with the prior art, the beneficial effects of the present invention are:

[0036] 1. The present invention does not rely on a traditional computer platform, has a significant advantage in terms of system volume ratio, and is convenient for deployment.

[0037] 2. Compared with an FPGA, the present invention can directly call off-chip resources such as DDR3. Compared with a traditional platform, ping-pong storage acceleration is used in the reading, writing, and storage of image data, which only requires a few clock cycles and can be processed in parallel. In contrast, traditional images must be sequentially processed for the current frame before the next frame can be processed, and the processing speed has a huge advantage.

[0038] 3. Compared with an algorithm based on a traditional platform, after transplanting the traditional algorithm, the present invention can perform parallel operations through pipeline operations, accelerating the operation speed of the algorithm.

[0039] 4. Due to the acceleration of image storage and processing operations in the present invention, images with a resolution of 1280×720 and 15fps that cannot be processed on a traditional platform can be processed on the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is the system design block diagram of the present invention;

[0041] Figure 2 is the filtering template diagram of median filtering in the present invention;

[0042] Figure 3 is the algorithm block diagram for obtaining a 3x3 filtering template in the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0043] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0044] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "connected" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0045] A moving target detection system based on ZYNQ acceleration, such as Figure 1As shown, it includes an image acquisition module, an image buffer module, an image processing module, and an image display module. The image acquisition module is respectively connected to the image buffer module and the image processing module. The image processing module is respectively connected to the image buffer module and the image display module. The image buffer module is connected to the image display module.

[0046] Furthermore, the image acquisition module includes an SCCB control module, a camera, and a first data conversion module. The SCCB control module is connected to the camera and controls the camera to perform real-time acquisition of moving targets in the environment. The camera is connected to the first data conversion module. The first data conversion module is respectively connected to the image buffer module and the image processing module, and converts the acquired RGB565 image into an AXI4_Stream data stream.

[0047] Furthermore, the image buffer module includes a DDR3 buffer module, an AXI bus, VDMA0, and VDMA1. The DDR3 buffer module is respectively connected to VDMA0 and VDMA1 through the AXI bus. VDMA0 is connected to the first data conversion module of the image acquisition module and the image processing module. VDMA1 is connected to the image display module. VDMA0 and VDMA1 are used to convert the data stream in AXI4_Stream format into Memory Map format or convert the data in Memory Map format into AXI4_Stream data stream.

[0048] Furthermore, the image display module includes a second data conversion module, a display module, and an HDMI display. The second data conversion module is connected to the HDMI display through the display module. The second data conversion module is connected to VDMA1, and converts the AXIS data stream into the HDMI video protocol display required including its line and field synchronization signals.

[0049] Furthermore, the image processing module includes a format conversion module, an image filtering module, a frame difference operation module, a binarization module, and a target display module. The format conversion module is connected to the frame difference operation module through the image filtering module. The frame difference operation module is connected to the target display module through the binarization module.

[0050] Furthermore, preferably, the camera uses an OV5640 camera. The selected OV5640 camera of the system can configure and modify the register address corresponding to the OV5640 through the SCCB control bus protocol, so as to realize the acquisition of RGB images with various resolutions and frame rates. The OV5640 can output 1080p resolution images with a maximum of 30 frames through the DVP interface, which can fully meet the design requirements. The data output by the OV5640 is 8-bit valid data controlled by the line-field synchronization signal. In this system, the image format used is RGB565. Therefore, when converting the acquired data into RGB image data, two clocks are required for each pixel acquisition. First, the 5-bit data of R and the first 3 bits of G are acquired. In the second clock, the last 3 bits of G and the 5-bit data of B are acquired, and then they are spliced into a complete 16-bit RGB565 data. In order to write the RGB565 format data into the DDR3, it must first be converted into the format data stream of AXI4_Stream (hereinafter referred to as AXIS) used by the VDMA, and the subsequent image processing module also needs to be unified into this format. This work is completed by configuring the IP core of Video in to AXI4_Stream.

[0051] Furthermore, the XC7Z020 development board of Xlinx company is used as the hardware platform. Its PS side is a dual-core ARM Cortex-A9, and the PL side is an FPGA architecture of the Xlinx Artix7 series. The development environment is Vivado 18.3.

[0052] A detection method of a moving target detection system based on ZYNQ acceleration. The processing method of the image processing module is as follows: including the following steps:

[0053] To realize the detection of a moving target, a series of processes need to be performed on the image of the moving target, such as data format conversion, filtering, binarization, morphological processing, target indication, etc. In the processing method based on the CPU, these image processing algorithms are very mature, but the CPU cannot process high-frame-rate (30 frames per second) and high-resolution images (640×480) in real time. At this time, the detection of the moving target must be completed with the help of parallel processing hardware acceleration. ZYNQ is one of the new parallel acceleration hardwares.

[0054] However, not all algorithms can be implemented on the ZYNQ platform. Appropriate algorithms need to be selected according to its characteristics, these algorithms need to be re-described in HDL, and individual algorithm function modules need to be constructed, and finally synthesized into the required algorithms. The following introduces the specific implementation method of the frame difference method for moving target detection.

[0055] S1. Image format conversion: The color image captured by the camera requires a large amount of processing. Therefore, it needs to be converted to grayscale data first for subsequent data processing. However, when it comes to image display, grayscale images cannot perform well. So, the color video stream input by the camera is divided into two parts. One is used for grayscale conversion and subsequent image processing; the other is used for display and tracking after image processing is completed.

[0056] Convert the RGB565 data converted to AXI4_Stream data stream back to RGB888 data. Keep the high bits unchanged and supplement the low bits, that is, {R[4:0], R[2:0]}, {G[5:0], G[2:0]}, {B[4:0], B[2:0]}

[0057] Y = 0.299R + 0.587G + 0.114B

[0058] Cb = 0.568(B - Y) + 128 = -0.172R - 0.339G + 0.511B + 128

[0059] Cr = 0.713(R - Y) + 128 = 0.511R - 0.428G + 128

[0060] After multiplying the conversion matrix by 256 times, only need to shift Y, Cb, and Cr to the right by 8 bits to restore, and get the following formula:

[0061] Y = ((77*R + 150*G + 29*B) >> 8)

[0062] Cb = ((-43*R - 85*G + 128*B) >> 8) + 128

[0063] Cr = ((128*R - 107*G - 21*B) >> 8 + 128

[0064] Since negative numbers in Verilog operations will cause errors and consume high resources, the above formula is transformed to get the following formula:

[0065] Y = (77*R + 150*G + 29*B) >> 8

[0066] Cb = (-43*R - 85*G + 128*B + 32768) >> 8

[0067] Cr = (128*R - 107*G - 21*B + 32768) >> 8

[0068] Wherein: R, G, and B respectively represent a color space model with red, green, and blue as the primary colors. Y, Cb, and Cr are a color encoding method adopted by the European television system. Y represents luminance, i.e., the gray-scale value, and Cb and Cr represent chrominance, which are used to describe the saturation and hue of an image. The conversion between R, G, B and Y, Cb, Cr is the conversion of color spaces, that is, converting the primary color space of R, G, B into a color space model of luminance and chrominance represented by Y, Cb, Cr.

[0069] S2. Median filtering: To improve the image quality, it is necessary to eliminate the influence of salt-and-pepper noise and impulse noise in the converted grayscale image. Therefore, median filtering is performed on the image. It produces very little blur and has a good effect on maintaining edge characteristics. Median filtering is a non-linear smoothing filter. As Figure 2 shown is the filtering template of median filtering. When implementing the median filtering algorithm using Verilog, the pipelining operation method is used to perform a quick sort on the 3x3 filtering module. In contrast, using methods such as the bubble method used by the CPU will be extremely complex and increase the operation time. As Figure 3 shown is the algorithm block diagram:

[0070] To obtain the 3x3 filtering template, the data of the first two rows are first registered. Therefore, a RAM is introduced. When the data of the third row arrives, it is read out. At this time, a 3x1 matrix will be obtained. Next, this 3x1 matrix is continuously registered three times to obtain the required 3x3 template, and then median filtering is implemented through Verilog;

[0071] S3. Frame difference method and binarization: Consider a frame of image data input by the camera as the current frame. The VDMA will perform frame buffering through ping-pong operation, that is, when writing the current image data to address 0 of the DDR3 buffer module, it will simultaneously read the image data buffered in the previous frame at address 1. The key to performing the frame difference operation is to align each pixel data of the current frame with the previous frame. Therefore, when waiting for the current frame to be valid, the VDMA reads the data of the previous frame from the DDR3 buffer module and caches it into the FIFO. At the same time, since both the read and write of the FIFO require one clock cycle, it is necessary to delay the current frame data by two clock cycles to align the image data. At this time, the two frames of data can perform the frame difference operation after image processing, and then perform binarization analysis on the difference result. When the absolute value of the difference result is greater than the set threshold, the result is 1 and is displayed as white, otherwise it is black. ZYNQ can process binary data with only 0 and 1 very simply and has good real-time performance. After the binarization analysis is completed, count all the pixel points with a value of 1, which are the detected moving targets; in this algorithm, obtaining the matrix, matrix sorting, value taking, and median finding are all parallel operations, which can significantly improve the processing speed.

[0072] S4. Target display: After obtaining the result of binary analysis, frame the area where the moving target is located with a rectangle, and overlay the rectangle on the original RGB color image data output by the camera to complete the detection of the real-time moving target.

[0073] The method for implementing the median filtering module in Verilog in S2 is as follows:

[0074] S2.1. First, in order to find the max, med, and min values of each row in the matrix, it is necessary to instantiate the sorting module three times;

[0075] S2.2. Second, it is necessary to obtain the min_of_max, med_of_med, and max_of_min values respectively. For this purpose, it is necessary to instantiate the sorting module three more times and input the 3 max, med, and min values of each row obtained in the first step into the sorting module;

[0076] S2.3. Finally, instantiate the sorting module one more time, take the middle value with the three values output in the second step as the input.

[0077] What overlays the rectangle on the original RGB color image data output by the camera in S4 is as follows: By calculating and comparing the pixel points with a binary value of 1 after binarization, the upper, lower, left, and right boundaries of the moving target area are obtained. Then, on the original color image data, calculate the coordinate values of each pixel point. When the coordinate value is on the boundary, assign the R signal of the corresponding pixel point to 255 to obtain a red display border, and then output it to the HMDI display screen to complete the display and tracking of the moving target.

[0078] The preliminary experimental results show that when the camera frame rate is set to 30 FPS, the transmission of each frame of image data takes 33.33 ms. In the case where OPENCV can only process images sequentially, the time taken for image processing cannot be ignored for each frame of image transmission, so there will be lags. At a resolution of 1280×720, OPENCV is too laggy to process. For the ZYNQ platform, the time taken for image processing can be basically ignored for 33.33 ms, so the visual effect is very smooth and has quite good real-time performance. At a resolution of 1280×720, the ZYNQ platform can still complete the task well.

[0079] Only the preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes can be made without departing from the gist of the present invention, and all such changes should be included within the protection scope of the present invention.

Claims

1. A moving target detection system based on ZYNQ acceleration, characterized in that: It includes an image acquisition module, an image buffer module, an image processing module, and an image display module. The image acquisition module is respectively connected to the image buffer module and the image processing module. The image processing module is respectively connected to the image buffer module and the image display module. The image buffer module is connected to the image display module; The processing method of the image processing module is as follows: It includes the following steps: S1. Image format conversion: Divide the color video stream input by the camera into two. One is used to convert to grayscale for subsequent image processing; the other is used for display tracking after image processing. Convert the RGB565 data converted into AXI4_Stream data stream into RGB888 data. Keep the high bits unchanged and supplement the low bits, that is, {R[4:0], R[2:0]}, {G[5:0], G[2:0]}, {B[4:0], B[2:0]} Y = 0.299R + 0.587G + 0.114B Cb = 0.568(B - Y) + 128 = -0.172R - 0.339G + 0.511B + 128 Cr = 0.713(R - Y) + 128 = 0.511R - 0.428G + 128 After multiplying the conversion matrix by 256 times, only need to shift Y, Cb, and Cr to the right by 8 bits to restore, and get the following formula: Y = ((77*R + 150*G + 29*B) >> 8) Cb = ((-43*R - 85*G + 128*B) >> 8) + 128 Cr = ((128*R - 107*G - 21*B) >> 8 + 128 Since negative numbers in Verilog operations will cause errors and occupy relatively high resources, the above formula is transformed to get the following formula: Y = (77*R + 150*G + 29*B) >> 8 Cb = (-43*R - 85*G + 128*B + 32768) >> 8 Cr = (128*R - 107*G - 21*B + 32768) >> 8 The R, G, and B respectively represent the color space model with red, green, and blue as the three primary colors. The Y, Cb, and Cr are a color coding method adopted by the European television system. The Y represents the brightness, that is, the gray scale value. The Cb and Cr represent the chrominance, which is used to describe the saturation and hue of the image. The conversion between R, G, B and Y, Cb, Cr is the conversion of the color space, that is, converting the three-primary-color color space of R, G, B into the color space model of brightness and chrominance represented by Y, Cb, Cr; S2. Median filtering: When using Verilog to implement the median filtering algorithm, use the pipelining operation method to perform quick sorting on the 3x3 filtering module; In order to obtain the 3x3 filtering template, first register the data of the first two rows. Therefore, a RAM is introduced. When the data of the third row arrives, read it out. At this time, a 3x1 matrix will be obtained. Next, continuously register this 3x1 matrix three times to obtain the required 3x3 template, and then implement median filtering through Verilog; S3. Frame difference method and binarization: Consider a frame of image data input by the camera as the current frame. The VDMA performs frame buffering through ping-pong operation. That is, when writing the current image data to address 0 of the DDR3 buffer module, it reads the image data buffered in the previous frame from address 1 simultaneously. The key to performing the frame difference operation is to align each pixel data of the current frame with that of the previous frame. Therefore, while waiting for the current frame to be valid, the VDMA reads the previous frame data from the DDR3 buffer module and caches it into the FIFO. At the same time, since both the read and write operations of the FIFO require one clock cycle, the current frame data needs to be delayed by two clock cycles to align the image data. At this time, the two frames of data can be subjected to frame difference operation after image processing, and then binarization analysis is performed on the difference result. When the absolute value of the difference result is greater than the set threshold, the result is 1 and is displayed as white; otherwise, it is black. ZYNQ can handle binary data with only 0 and 1 very simply and has good real-time performance. After the binarization analysis is completed, count all the pixel points with a value of 1, which are the detected moving targets. S4. Target display: After obtaining the result of the binarization analysis, frame the area where the moving target is located with a rectangle and superimpose the rectangle on the original RGB color image data output by the camera to complete the real-time detection of the moving target.

2. The motion target detection system based on ZYNQ acceleration according to claim 1, wherein: The image acquisition module includes an SCCB control module, a camera, and a first data conversion module. The SCCB control module is connected to the camera and controls the camera to perform real-time acquisition of moving targets in the environment. The camera is connected to the first data conversion module, and the first data conversion module is respectively connected to an image buffer module and an image processing module. The first data conversion module converts the acquired RGB565 image into an AXI4_Stream data stream.

3. The motion target detection system based on ZYNQ acceleration according to claim 2, wherein: The image buffer module includes a DDR3 buffer module, an AXI bus, VDMA0, and VDMA1. The DDR3 buffer module is connected to VDMA0 and VDMA1 respectively through the AXI bus. VDMA0 is connected to the first data conversion module and the image processing module of the image acquisition module, and VDMA1 is connected to the image display module. VDMA0 and VDMA1 are used to convert the data stream in AXI4_Stream format into Memory Map format or convert the data in Memory Map format into AXI4_Stream data stream.

4. The motion target detection system based on ZYNQ acceleration according to claim 3, characterized in that: The image display module includes a second data conversion module, a display module, and an HDMI display. The second data conversion module is connected to the HDMI display through the display module, and the second data conversion module is connected to VDMA1. The second data conversion module converts the AXIS data stream into the video protocol required for HDMI display, including its line and field synchronization signals.

5. The motion target detection system based on ZYNQ acceleration according to claim 4, wherein: The image processing module includes a format conversion module, an image filtering module, a frame difference operation module, a binarization module, and a target display module. The format conversion module is connected to the frame difference operation module through the image filtering module, and the frame difference operation module is connected to the target display module through the binarization module.

6. The motion target detection system based on ZYNQ acceleration according to claim 2, characterized in that: The camera used is an OV5640 camera.

7. A moving target detection system based on ZYNQ acceleration according to claim 1, characterized in that: The method for implementing the median filtering module in Verilog in S2 is as follows: S2.

1. First, in order to find the max, med, and min values of each row in the matrix, it is necessary to instantiate the sorting module three times. S2.

2. Secondly, it is necessary to obtain the min_of_max, med_of_med, and max_of_min values respectively. For this purpose, it is necessary to instantiate the sorting module three more times and input the three max, med, and min values of each row obtained in the first step into the sorting module. S2.

3. Finally, instantiate the sorting module one more time, take the three values output in the second step as inputs, and take the median value.

8. A moving target detection system based on ZYNQ acceleration according to claim 1, characterized in that: In S4, the method of superimposing the square box on the original RGB color image data output by the camera is as follows: By calculating and comparing the pixel points with a value of 1 after binarization, the upper, lower, left, and right boundaries of the moving target area are obtained. Then, on the original color image data, the coordinate values of each pixel point are calculated again. When the coordinate value is on the boundary, the R signal of the corresponding pixel point is assigned a value of 255, and a red display border can be obtained. Then, it is output to the HMDI display screen to complete the display and tracking of the moving target.

Images