Auxiliary device and computer program product

Abstract

The present invention provides a stacked semiconductor, a wafer stack, a method for manufacturing a stacked semiconductor, an auxiliary device, and a program that can reduce manufacturing costs. A stacked semiconductor comprising a plurality of stacked chips comprises: a logic chip; and a memory unit stacked on the logic chip, comprising at least one memory chip capable of communicating with the logic chip. The memory chip comprises: at least two memory bodies arranged in a direction intersecting the stacking direction, each memory body having a memory circuit; and a connecting portion provided between the memory bodies with a predetermined width to connect the plurality of arranged memory bodies.

Description

Technical Field

[0001] The present invention relates to a stacked semiconductor, a wafer stack, a method for manufacturing a stacked semiconductor, an auxiliary device, and a program. Background Art

[0002] Volatile memories (RAMs) such as DRAM (Dynamic Random Access Memory) have been known as storage devices. DRAMs are required to have higher capacity to accommodate the increasing performance and data volume of computing devices (hereinafter referred to as logic chips). Consequently, efforts have been underway to achieve higher capacity by miniaturizing memories (memory cell arrays, memory chips) and increasing the number of cells in a planar manner. However, this capacity increase has reached its limits due to the increased vulnerability to noise and increased die area associated with miniaturization.

[0003] Therefore, a technology has recently been developed to achieve a larger capacity by stacking multiple planar memories in three dimensions (3D). In addition, a device has been proposed in which multiple die stacks (DRAMs) are stacked on an interface die (see, for example, Patent Document 1).

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-524519. Summary of the Invention

[0007] Problems to be solved by the invention

[0008] In Patent Document 1, four die stacks are first manufactured. Then, the four die stacks are stacked on one interface die while being positioned. This increases assembly time and manufacturing costs.

[0009] An object of the present invention is to provide a stacked semiconductor, a wafer stack, a method for manufacturing a stacked semiconductor, an auxiliary device, and a program that can reduce manufacturing costs.

[0010] Solutions for solving problems

[0011] The present invention relates to a stacked semiconductor, which is composed of a plurality of stacked chips, the stacked semiconductor comprising: a logic chip; and a memory portion, which is stacked on the logic chip and has at least one memory chip capable of communicating with the logic chip, the memory chip comprising: at least two memory bodies arranged in a direction intersecting the stacking direction, the memory bodies having memory circuits; and a connecting portion, which is arranged between the memory bodies with a prescribed width to connect the plurality of arranged memory bodies respectively.

[0012] Furthermore, the stacked semiconductor may have a communication portion that is arranged to overlap in the stacking direction.

[0013] In addition, the plurality of memory chips may also stack the arranged memory bodies respectively with the memory bodies of other memory chips in the stacking direction, and the communication unit may also be configured in each of the logic chips and the plurality of memory bodies in a manner aligned in the stacking direction.

[0014] Furthermore, the memory main bodies are of the same type as the other memory main bodies arranged in an array.

[0015] Furthermore, each of the memory bodies is of a different type from the other stacked memory bodies.

[0016] In addition, the plurality of memory chips may also include: a first memory chip having a first memory body of a specified type; and a second memory chip having a second memory body of a different type from that of the first memory chip, and the communication unit may include: a first communication unit configured between the logic chip and the first memory body; and a second communication unit configured between the logic chip and the second memory body.

[0017] Furthermore, the first communication unit may be arranged at a position different from that of the second communication unit in a direction intersecting the stacking direction.

[0018] Furthermore, the logic chip and the memory chip may each have a power supply unit that is arranged to overlap.

[0019] Furthermore, the present invention relates to a wafer stack including: a logic wafer in which the logic chips are arranged in a matrix; and a memory wafer in which the memory bodies are arranged in a matrix, wherein the memory wafers are stacked on the logic wafer.

[0020] In addition, the present invention relates to a method for manufacturing a stacked semiconductor composed of a plurality of stacked chips, comprising: a stacking process of stacking a memory wafer and a logic wafer into a wafer stack, wherein the memory wafer arranges a plurality of memory bodies in a matrix, and the logic wafer arranges a plurality of logic chips arranged overlapping with each of the memory bodies in a matrix; an area determination process of determining a memory area of ​​a group including at least two of the memory bodies and one of the logic chips; and a cutting process of cutting the wafer stack according to the determined memory area.

[0021] Furthermore, the stacking step preferably stacks a plurality of memory wafers, each of which is provided with a different type of memory body.

[0022] In addition, the present invention relates to an auxiliary device that assists in cutting a wafer stack formed by stacking memory wafers and logic wafers into a plurality of stacked semiconductors according to a plurality of obtained orders, wherein the memory wafer arranges a plurality of memory bodies in a matrix, and the logic wafer arranges a plurality of logic chips arranged overlapping the memory bodies in a matrix, and the auxiliary device comprises: an order information acquisition unit that acquires a plurality of order information including the quantity of the memory bodies; a configuration information acquisition unit that acquires configuration information indicating the configuration position of the memory bodies; and an area determination unit that determines the area of ​​the memory chip composed of a plurality of the memory bodies and the logic chip based on the acquired order information and configuration information.

[0023] In addition, the present invention relates to a program that enables a computer to work as an auxiliary device, wherein the auxiliary device assists in cutting a wafer stack formed by stacking memory wafers and logic wafers into a plurality of stacked semiconductors according to a plurality of orders obtained, wherein the memory wafer configures a plurality of memory bodies in a matrix, and the logic wafer configures a plurality of logic chips respectively overlapped on the memory bodies in a matrix, and the program enables the computer to perform the following functions: an order information acquisition unit that acquires a plurality of order information including the quantity of the memory bodies; a configuration information acquisition unit that acquires configuration information showing the configuration position of the memory bodies; and an area determination unit that determines the area of ​​the memory chip and the logic chip composed of a plurality of the memory bodies based on the acquired order information and configuration information.

[0024] Effects of the Invention

[0025] According to the present invention, it is possible to provide a stacked semiconductor, a wafer stack, a method for manufacturing a stacked semiconductor, an auxiliary device, and a program that can suppress manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a perspective view showing a logic wafer and a memory wafer of a wafer stack according to the first embodiment of the present invention.

[0027] Figure 2 1 is a top view of a logic wafer according to the first embodiment.

[0028] Figure 3 FIG. 1 is a plan view showing a first memory chip of the stacked semiconductor device according to the first embodiment.

[0029] Figure 4 FIG. 1 is a plan view showing a second memory chip of the stacked semiconductor device according to the first embodiment.

[0030] Figure 5 1 is a plan view showing a third memory chip of the stacked semiconductor device according to the first embodiment.

[0031] Figure 6 It is a side view showing the stacked semiconductor according to the first embodiment.

[0032] Figure 7 It is a top view showing a logic chip of a stacked semiconductor according to the first embodiment.

[0033] Figure 8 This is a plan view showing a first communication unit in the stacked semiconductor memory body according to the first embodiment.

[0034] Figure 9 This is a plan view showing a second communication unit in the stacked semiconductor memory body according to the first embodiment.

[0035] Figure 10 This is a plan view showing a third communication unit in the stacked semiconductor memory body according to the first embodiment.

[0036] Figure 11 It is a schematic structural diagram showing an assist device according to a second embodiment of the present invention.

[0037] Figure 12 It is a block diagram showing an assist device according to the second embodiment.

[0038] Figure 13 1 is a top view of a logic wafer showing a modified example.

[0039] Figure 14 It is a plan view showing the arrangement of a stacked semiconductor according to a modification.

[0040] Figure 15 This is a table showing the relationship between the size and capacity of a stacked semiconductor according to a modified example. DETAILED DESCRIPTION

[0041] Below, refer to Figures 1 to 15 The stacked semiconductor 1 , the wafer stack 100 , the auxiliary device 200 , and the program according to each embodiment of the present invention will be described.

[0042] like Figure 1 and Figure 6 As shown, the stacked semiconductor 1 according to each embodiment is a module in which a logic chip 11 and a memory chip 21 are stacked. The stacked semiconductor 1 is obtained by cutting a wafer stack 100 in which a plurality of wafers are stacked. Figure 3 As shown, the stacked semiconductor 1 includes at least two memory bodies 211, 212, 213, and 214 having memory circuits, each disposed on a memory chip 21. By varying the number of memory bodies 211, 212, 213, and 214 in the stacked semiconductor 1 at varying cutting positions, stacked semiconductors 1 with varying capacities can be obtained.

[0043] [First embodiment]

[0044] Next, refer to Figures 1 to 10 , a stacked semiconductor 1 and a wafer stack 100 according to a first embodiment of the present invention will be described.

[0045] The wafer stack 100 is formed by stacking a plurality of wafers. Figure 1 As shown, the wafer stack 100 includes, for example, a logic wafer 10 and a memory wafer 20 .

[0046] The logic wafer 10 is, for example, a silicon substrate and is formed in a disk shape. Figure 2 As shown, the logic wafer 10 includes a plurality of logic chips 11 arranged in a matrix. The logic chips 11 will be described later.

[0047] The memory wafer 20 is, for example, a silicon substrate, and is formed into a circular plate shape with the same or approximately the same diameter as the logic wafer 10. The memory wafer 20 is stacked on the logic wafer 10. In this embodiment, a plurality of memory wafers 20 are provided and stacked on the logic wafer 10. The memory wafer 20 is stacked on the logic wafer 10, for example, by wafer bonding techniques such as surface activated bonding and hydrophilic bonding. In addition, the memory wafers 20 are also stacked on each other by wafer bonding techniques such as surface activated bonding and hydrophilic bonding. The memory wafer 20 has a plurality of memory chips 21, and the memory chip 21 includes two or more memory bodies of unit sizes described later and is arranged in a matrix. The memory chip 21 will be described later.

[0048] Next, the stacked semiconductor 1 will be described.

[0049] like Figures 3 to 6 As shown, the stacked semiconductor 1 is composed of a plurality of stacked chips. Figures 3 to 10As shown, the stacked semiconductor 1 includes a logic chip 11, a memory unit 22, a communication unit 30, and a power supply unit 40. In this embodiment, the stacked semiconductor 1 is rectangular in plan view and is the same or substantially the same size as the logic chip 11 in plan view.

[0050] The logic chip 11 is, for example, a rectangular chip in plan view. Each logic chip 11 includes, for example, a memory controller and a memory interface, a logic circuit, a power supply circuit, and an external interface. The logic chip 11 is, for example, formed in an 8×4 (mm 2 ) to 12×12(mm 2 ) size. In this embodiment, the logic chip 11 is 8×8 (mm 2 )'s size composition.

[0051] The memory unit 22 includes, for example, at least one memory chip 21. The memory unit 22 is stacked on the logic chip 11. The memory unit 22 is configured to be communicable with the logic chip 11.

[0052] The memory chip 21 is a rectangular chip in a plan view and includes at least two memory bodies 211 , 212 , 213 , and 214 and a connection portion 50 .

[0053] The memory bodies 211, 212, 213, and 214 are configured to be rectangular in plan view, for example. The memory bodies 211, 212, 213, and 214 include memory circuits. The memory bodies 211, 212, 213, and 214 are arranged in a direction intersecting the stacking direction.

[0054] Connecting portions 50 are provided with a predetermined width between the memory bodies 211, 212, 213, and 214. The connecting portions 50 connect the plurality of memory bodies 211, 212, 213, and 214 arranged in a row. The connecting portions 50 are formed, for example, in the remaining uncut area of ​​the dicable area provided on the memory wafer 20.

[0055] According to the above memory chip 21, memory main bodies 211, 212, 213, 214, and connection portion 50, a predetermined unit size (4×4 mm in this embodiment) is used. 2 ) form memory bodies 211, 212, 213, and 214. In this embodiment, the specified unit size is marked as a 1×1 size. The memory bodies 211, 212, 213, and 214 are any type of memory, such as DRAM, SRAM, flash memory, MRAM, ReRAM, FeRAM, PCRAM, etc. The memory bodies 211, 212, 213, and 214 can communicate with the logic chip 11. In this embodiment, as Figure 3As shown, the memory bodies 211, 212, 213, and 214 of 1×1 size are composed of, for example, four memory bodies (A, B, C, and D) to form a 2×2 size (8×8 mm) 2 ) size of the memory chip 21. Then, the memory chip 21 is stacked on Figure 2 8×8mm shown 2 (2×2 size) logic chip 11. The memory chip 21 is stacked on the logic chip 11 in a state having four memory bodies 211, 212, 213, 214 and a connection portion 50 extending in the in-plane direction. That is, the memory chip 21 is configured to have four unit-sized memory bodies 211, 212, 213, 214. Then, 16 memory bodies 211, 212, 213, 214 are arranged on a photomask (for example, 4×4 size). In this embodiment, as shown in FIG. Figures 3 to 6 As shown, as an example, the memory unit 22 includes: a first memory chip 21a having first memory bodies 211a, 212a, 213a, and 214a of a predetermined type; a second memory chip 21b having second memory bodies 211b, 212b, 213b, and 214b of a different type from the first memory bodies 211a, 212a, 213a, and 214a; and a third memory chip 21c having third memory bodies 211c, 212c, 213c, and 214c of a different type from the first and second memory bodies 211a, 212a, 213a, and 214a. The first, second, and third memory chips 21a, 21b, and 21c can be formed at different predetermined locations within the same memory wafer 20, or can be formed within different memory wafers 20. Figure 6 A cross-sectional view of a stacked semiconductor 1 is shown in which a first memory chip 21 a , a second memory chip 21 b , and a third memory chip 21 c are stacked in this order on a logic chip 11 .

[0056] The communication unit 30 is arranged across the logic chip 11 and the memory chip 21 in the stacking direction. Specifically, the communication unit 30 is arranged as a stacking portion of one region of the logic chip 11 and one region of the memory chip 21 in the stacking direction. Figures 7 to 10 As shown, the communication unit 30 is configured as different regions depending on the type of memory chip 21 stacked on the logic chip 11. The communication unit 30 includes a first communication unit 31, a second communication unit 32, and a third communication unit 33. Within each communication unit 30, a communication path (not shown) is provided for communication between the logic chip 11 and the memory chip 12 in the stacking direction.

[0057] The first communication unit 31 is provided between the logic chip 11 and the first memory bodies 211a, 212a, 213a, and 214a. Figure 7 and Figure 8 As shown, the first communication unit 31 is arranged on one end side of the communication unit 30 .

[0058] The second communication unit 32 is disposed between the logic chip 11 and the second memory bodies 211b, 212b, 213b, and 214b. Figure 7 and Figure 9 As shown, the second communication unit 32 is arranged at the center of the communication unit 30. That is, the second communication unit 32 is arranged at a position different from that of the first communication unit 31 in a direction intersecting the stacking direction.

[0059] The third communication unit 33 is configured in the logic chip 11 and the third memory bodies 211c, 212c, 213c, and 214c. Figure 7 and Figure 10 As shown, the third communication unit 33 is arranged on the other end side of the communication unit 30. That is, the third communication unit 33 is arranged at a different position than the first communication unit 31 and the second communication unit 32 in a direction intersecting the stacking direction. Thus, even if three types of memory chips 21, namely, the first memory chip 21a, the second memory chip 21b, and the third memory chip 21c, are stacked on the logic chip 11, each memory chip 21 can communicate with the logic chip 11 without interfering with the other memory chips 21. Alternatively, if, for example, only a plurality of first memory chips 21a are stacked on the logic chip 11, the logic chip 11 may include only the first communication unit 31.

[0060] The power supply unit 40 extends in the stacking direction and serves as a common power supply line for the first memory chip 21a (first memory main bodies 211a, 212a, 213a, 214a), the second memory chip 21b (second memory main bodies 211b, 212b, 213b, 214b), and the third memory chip 21c (third memory main bodies 211c, 212c, 213c, 214c). In this embodiment, TSVs and the like for power supply lines extending in the stacking direction are arranged in the power supply unit 40 along the communication unit 30. Alternatively, the power supply unit 40 may be arranged in a pair with the communication unit 30 sandwiched therebetween. Alternatively, the power supply unit 40 may be arranged so as to surround the communication unit 30 or at a location away from the communication unit 30 (not shown).

[0061] Next, a method for manufacturing the stacked semiconductor 1 will be described.

[0062] The method for manufacturing the stacked semiconductor 1 includes a stacking step, a cutting position determination step, and a cutting execution step.

[0063] First, in the stacking process, the memory wafer 20 equipped with the memory chips 21 (memory main bodies 211, 212, 213, and 214) is stacked on the logic wafer 10 equipped with the logic chip 11. During the stacking process, the logic wafer 10 and the memory wafer 20 are stacked with the communication unit 30 and the power supply unit 40 aligned in the stacking direction. In this embodiment, three memory wafers 20 equipped with different types of memory chips 21 (memory main bodies 211, 212, 213, and 214) are stacked on the logic chip 11.

[0064] Next, in the dicing position determination step, the dicing positions for the logic wafer 10 and the memory wafer 20 are determined. In this dicing position determination step, the dicing positions are determined, for example, based on the number of adjacent memory bodies 211, 212, 213, and 214 contained within a stacked semiconductor 1. While the dicing positions are typically determined by the size of a single logic chip 11, they can also be determined based on the size of a stacked semiconductor 1 formed by combining multiple logic chips 11.

[0065] Next, in the cutting execution step, cutting is performed at the determined cutting positions, thereby manufacturing the stacked semiconductor 1 .

[0066] According to the stacked semiconductor 1 and the wafer stacked body 100 described above, the following effects are achieved.

[0067] (1) A stacked semiconductor device 1 is constructed by stacking a plurality of chips. The stacked semiconductor device 1 includes: a logic chip 11; and a memory unit 22 stacked on the logic chip 11, including at least one memory chip 21 capable of communicating with the logic chip 11. The memory chip 21 includes: at least two memory bodies 211, 212, 213, and 214 arranged in a direction intersecting the stacking direction, the memory bodies 211, 212, 213, and 214 having memory circuits; and a connection unit 50 provided at a predetermined width between the memory bodies 211, 212, 213, and 214 to connect the plurality of arranged memory bodies 211, 212, 213, and 214. This eliminates the need to stack the required number of memory chips 21 in each device. Consequently, the manufacturing cost of the stacked semiconductor device 1 can be reduced.

[0068] (2) The stacked semiconductor device 1 further includes a communication unit 30 that is arranged across the logic chip 11 and the memory chip 21 in the stacking direction. Furthermore, the memory chips 21 have their memory bodies 211, 212, 213, and 214 arranged in a stacking direction, respectively, along with the memory bodies 211, 212, 213, and 214 of the other memory chips 21. The communication unit 30 is arranged so that the logic chip 11 and the memory bodies 211, 212, 213, and 214 are aligned in the stacking direction. Furthermore, the plurality of memory chips 21 include a first memory chip 21a having first memory bodies 211a, 212a, 213a, and 214a of a predetermined type, and a second memory chip 21b having second memory bodies 211b, 212b, 213b, and 214b of a different type from the first memory chip 21a. The communication unit 30 includes a first communication unit 31 disposed between the logic chip 11 and the first memory bodies 211a, 212a, 213a, and 214a, and a second communication unit 32 disposed between the logic chip 11 and the second memory bodies 211b, 212b, 213b, and 214b. Furthermore, the first communication unit 31 is disposed at a different position than the second communication unit 32 in a direction intersecting the stacking direction. This allows independent communication between the chips, even when different types of chips are used.

[0069] (3) The memory bodies 211, 212, 213, and 214 are of the same type as the other memory bodies 211, 212, 213, and 214 arranged in an array. Alternatively, the memory bodies 211, 212, 213, and 214 are of different types from the other memory bodies 211, 212, 213, and 214 stacked in a stack. This allows for various variations in the stacked semiconductor 1.

[0070] (4) The logic chip 11 and the memory chip 21 each have an overlapping power supply unit 40. Since the power supply unit 40 can be shared, the cost can be further reduced.

[0071] (5) A method for manufacturing a stacked semiconductor 1 composed of a plurality of stacked chips, comprising: a stacking step of stacking a memory wafer 20 and a logic wafer 10 into a wafer stack, wherein the memory wafer 20 has a plurality of memory bodies 211, 212, 213, and 214 arranged in a matrix, and the logic wafer 10 has a plurality of logic chips 11 arranged overlapping each of the memory bodies 211, 212, 213, and 214 arranged in a matrix; a region determination step of determining a memory region consisting of a group of at least two memory bodies 211, 212, 213, and 214 and one logic chip 11; and a dicing step of dicing the wafer stack according to the determined memory region. Thus, since it is not necessary to align and stack the required number of memory bodies 211, 212, 213, and 214 for each stacked semiconductor 1, manufacturing costs can be reduced.

[0072] (6) The wafer stack 100 includes a logic wafer 10 in which the aforementioned logic chips 11 are arranged in a matrix, and a memory wafer 20 in which the aforementioned memory main bodies 211, 212, 213, and 214 are arranged in a matrix, and the memory wafer 20 is stacked on the logic wafer 10. Thus, since the logic chips 11 and the memory main bodies 211, 212, 213, and 214 can be aligned before dicing, manufacturing costs can be reduced.

[0073] [Second embodiment]

[0074] Next, refer to Figure 11 and Figure 12 , the support device 200 and the program according to the second embodiment of the present invention will be described. In describing the second embodiment, the same components as those in the above-mentioned embodiment will be denoted by the same reference numerals, and their description will be omitted or simplified.

[0075] First, an overview of the support device 200 and the program according to the second embodiment will be described.

[0076] An LSI prototype service known as the "multi-project wafer method" or "pooling method" is known. In this service, multiple customers can share a single wafer to produce LSIs. This can reduce LSI prototype costs.

[0077] This method uses logic processing to prototype LSIs. Therefore, this method has the following problems: It is difficult to prototype system LSIs that use large-capacity memory or large-capacity and high-speed memory. Furthermore, there is no prototype service for three-dimensional LSIs. The support device 200 and program according to this embodiment are for supporting the device 200 when manufacturing a stacked semiconductor 1 using the shared method.

[0078] The auxiliary device 200 is, for example, a server. Figure 11As shown, the auxiliary device 200 is communicatively connected to the user terminal 300. The auxiliary device 200 assists in cutting the wafer stack 100 into a plurality of stacked semiconductors 1 according to the plurality of orders obtained. The wafer stack 100 is formed by stacking a memory wafer 20 and a logic wafer 10. In the memory wafer 20, a plurality of memory bodies 211, 212, 213, and 214 are arranged in a matrix. In the logic wafer 10, a plurality of logic chips 11 respectively arranged in a matrix and stacked on the memory bodies 211, 212, 213, and 214 are arranged in a matrix. Figure 12 As shown, the support device 200 includes an order information acquisition unit 201 , an order information storage unit 202 , a placement information storage unit 203 , a placement information acquisition unit 204 , an area determination unit 205 , and an output unit 206 .

[0079] The order information acquisition unit 201 is implemented, for example, by the operation of a CPU. The order information acquisition unit 201 acquires a plurality of order information including the quantity of the memory cells 211, 212, 213, and 214. The order information acquisition unit 201 acquires, for example, information such as the quantity (capacity) and the type of memory cells 211, 212, 213, and 214 of the manufactured stacked semiconductor 1 from the user terminal 300 as the order information.

[0080] The order information storage unit 202 is a secondary storage medium such as a hard disk, and stores the acquired order information.

[0081] The configuration information storage unit 203 is, for example, a secondary storage medium such as a hard disk, and stores configuration information indicating the locations of the memory bodies 211 , 212 , 213 , and 214 .

[0082] The configuration information acquisition unit 204 is implemented by, for example, the operation of a CPU. The configuration information acquisition unit 204 acquires configuration information indicating the locations of the memory bodies 211, 212, 213, and 214. In this embodiment, the configuration information acquisition unit 204 acquires configuration information from the configuration information storage unit 203.

[0083] The region determination unit 205 is implemented, for example, by the operation of a CPU. Based on the acquired order information and configuration information, the region determination unit 205 determines the regions of the memory chip 21 and logic chip 11, which are composed of a plurality of memory elements 211, 212, 213, and 214. For example, the region determination unit 205 determines the regions by allocating the memory elements 211, 212, 213, and 214 to the memory chips 21 arranged on the memory wafer 20 according to the order information. Alternatively, the region determination unit 205 may also determine the regions by taking into account the size of the photomask.

[0084] The output unit 206 is, for example, an output device such as a display, and outputs the determined area.

[0085] Next, the operation of the assist device will be described.

[0086] The order information acquisition unit 201 acquires order information from the user terminal 300. The order information acquisition unit 201 stores the acquired order information in the order information storage unit 202.

[0087] Next, when the area is determined, the area determination unit 205 reads the order information from the order information storage unit 202 via the order information acquisition unit 201. Furthermore, the configuration information acquisition unit 204 acquires the configuration information from the configuration information storage unit 203. The configuration information acquisition unit 204 transmits the acquired configuration information to the area determination unit 205.

[0088] The region determination unit 205 determines the region for stacking semiconductors based on the order information and the layout information. For example, the region determination unit 205 determines the region for the memory chip 21 based on the number of memory bodies 211, 212, 213, and 214 included in the order information.

[0089] The output unit 206 outputs the determined area to the outside.

[0090] Next, the program will be explained.

[0091] Each component included in the support device 200 can be implemented by hardware, software, or a combination thereof. Here, implementation by software means implementation by a computer reading and executing a program.

[0092] The program can be stored using various types of non-transitory computer readable storage media (non-transitorycomputer readable medium) and provided to the computer. Non-transitory computer readable storage media include various types of tangible storage media (tangible storage medium). Examples of non-transitory computer readable storage media include magnetic storage media (such as floppy disks, magnetic tapes, hard disk drives), magneto-optical storage media (such as magneto-optical disks), CD-ROM (Read Only Memory), CD-R, CD-R / W, semiconductor memories (such as mask ROM, PROM (Programmable ROM, Programmable Read-Only Memory), EPROM (Erasable PROM, Erasable Programmable Read-Only Memory), flash ROM, SSD (Solid State Drive), RAM (random access memory)). In addition, the program can also be provided to the computer via various types of transitory computer readable storage media (transitorycomputer readable medium). Examples of transitory computer readable storage media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable storage media can provide the program to a computer via a wired communication path such as electric wires and optical fibers, or a wireless communication path.

[0093] According to the support device 200 and the program of this embodiment, the following effects are achieved.

[0094] (7) The support device 200 includes an order information acquisition unit 201 that acquires a plurality of order information including the number of memory main bodies 211, 212, 213, and 214; a layout information acquisition unit 204 that acquires layout information indicating the layout positions of the memory main bodies 211, 212, 213, and 214; and an area determination unit 205 that determines the areas for the memory chip 21 and the logic chip 11 based on the acquired order information and layout information. This allows the order information acquired from users to be aggregated and the areas for manufacturing the stacked semiconductor 1 to be determined. Consequently, an area can be formed that optimizes the orders of multiple users, thereby reducing manufacturing costs.

[0095] While preferred embodiments of the stacked semiconductor 1 , the wafer stack 100 , the auxiliary device 200 , and the program of the present invention have been described above, the present invention is not limited to the above-described embodiments and can be modified as appropriate.

[0096] For example, in the above embodiment, regarding the types of memory wafers 20 stacked on the logic wafer, memory wafers 20 each configured with three types of memory chips 21 are stacked, but the present invention is not limited to this. For example, wafers configured with two or more memory chips 21 of the same type may also be stacked. In this case, the communication unit 30 may also be shared by wafers configured with two or more memory bodies 211, 212, 213, 214 of the same type. For example, multiple first memory bodies 211a, 212a, 213a, 214a may be provided, and the first communication unit 31 may also be configured between the logic chip 11 and the multiple first memory bodies 211a, 212a, 213a, 214a and shared by the multiple first memory bodies 211a, 212a, 213a, 214a.

[0097] Furthermore, in the above-described embodiment, the support device 200 may further include a memory type determination unit (not shown) that predetermines the type of stacked memory bodies 211, 212, 213, and 214. For example, the memory type determination unit may transmit the memory type to be stacked on the next wafer stack 100 to be manufactured to the user terminal 300 in order to receive an order from the user. Furthermore, the order information acquisition unit 201 may also acquire order information including the memory type from the user terminal 300. The region determination unit 205 may also determine a region within the wafer stack 100 that matches the order information for each user with the same memory type.

[0098] In the above embodiment, 16 memory cells 211, 212, 213, and 214 of 1×1 size (unit size) are arranged in one photomask and assigned to four logic chips 11 in groups of four. However, the present invention is not limited thereto. Figure 13 and Figure 14 As shown in FIG. 1 , two 2×2 logic chips 11 and one 2×4 logic chip 11 can also be configured in one photomask. Figure 15 The relationship between the number of memory chips 12 configured and the number of stacked layers and the memory capacity corresponding to the size and chip area (Foot Print) of the logic chip 11 is shown in FIG. Figure 15 In the figure, four values ​​are listed together in the memory capacity column. These correspond to memory devices with different unit sizes: 2Gb, 1.5Gb, 0.6Gb, and 64Gb, from left to right. These values ​​represent examples of DRAM, which prioritizes density, DRAM, which prioritizes bandwidth, DRAM, and NAND flash memory.

[0099] Furthermore, in the above-described embodiment, the logic chips 11 on the logic wafer 10 may be of different types or sizes.

[0100] Furthermore, in the above-described embodiment, cutting may be performed using laser cutting or plasma cutting.

[0101] Description of Reference Numerals

[0102] 1: Stacked semiconductors

[0103] 10: Logic wafer

[0104] 11: Logic chip

[0105] 20: Memory wafer

[0106] 21: Memory chips

[0107] 21a: First memory chip

[0108] 21b: Second memory chip

[0109] 21c: Third memory chip

[0110] 22: Memory unit

[0111] 30: Ministry of Communications

[0112] 31: First Ministry of Communications

[0113] 32: Second Department of Communications

[0114] 33: Third Department of Communications

[0115] 40: Power supply department

[0116] 50: Connection

[0117] 100: Wafer stack

[0118] 200: Auxiliary devices

[0119] 201: Order information acquisition department

[0120] 202: Order information storage department

[0121] 203: Configuration information storage unit

[0122] 204: Configuration information acquisition unit

[0123] 205: Regional Decision Department

[0124] 206: Output

[0125] 211a, 212a, 213a, 214a: first memory body

[0126] 211b, 212b, 213b, 214b: Second memory unit

[0127] 211c, 212c, 213c, 214c: third memory unit

[0128] 300: User terminal

Claims

1. An assisting device for assisting in slicing a wafer stack composed of a memory wafer and a logic wafer into a plurality of stacked semiconductors according to a plurality of received orders, wherein the memory wafer has a plurality of memory bodies arranged in a matrix, and the logic wafer has a plurality of logic chips arranged overlapping the memory bodies in a matrix. The auxiliary device comprises: an order information acquisition unit that acquires a plurality of order information including the quantity of the memory main body; a configuration information acquisition unit configured to acquire configuration information indicating a configuration position of the memory body; as well as The area determination unit determines areas of a memory chip composed of a plurality of the memory bodies and the logic chip based on the acquired order information and configuration information.

2. A computer program product that causes a computer to operate as an auxiliary device, the auxiliary device assisting in slicing a wafer stack composed of a stack of memory wafers and logic wafers into a plurality of stacked semiconductors according to a plurality of received orders, wherein the memory wafer has a plurality of memory bodies arranged in a matrix, and the logic wafer has a plurality of logic chips arranged overlapping the memory bodies in a matrix. The computer program product enables the computer to perform the following functions: an order information acquisition unit that acquires a plurality of order information including the quantity of the memory main body; a configuration information acquisition unit that acquires configuration information indicating a configuration position of the memory main body; and The area determination unit determines areas of a memory chip composed of a plurality of the memory bodies and the logic chip based on the acquired order information and configuration information.

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