Three-level power converter and control method

Abstract

A method includes detecting a voltage signal of a three-level power converter, the voltage signal indicative of capacitor voltage balancing in the three-level power converter, and dynamically adjusting an operating variable to adjust the voltage signal until the capacitor voltage balancing in the three-level power converter meets a criteria.

Description

Technical Field

[0001] This disclosure relates to a control method for achieving capacitor voltage balance in a multilevel power converter, and particularly to a control method for achieving capacitor voltage balance in a three-level power converter. Background Technology

[0002] With further technological advancements, various electronic devices, such as mobile phones, tablets, digital cameras, and MP3 players, have become popular. Each electronic device requires a relatively constant direct current (DC) power supply, allowing for regulation even if the current generated by the device varies over a wide range. When the input voltage is below a specific range, a boost DC / DC converter can be used to transform the input voltage to a regulated voltage within that range. Conversely, when the input voltage is above a specific range, a buck DC / DC converter can be used to transform the input power supply voltage to a lower voltage to meet the operating voltage specified by the electronic circuitry.

[0003] DC / DC converter topologies can vary widely. Based on topology differences, DC / DC converters can be categorized into three types: switched DC-DC converters, linear regulators, and switched-capacitor converters. Based on voltage level differences, DC / DC converters can be divided into two types: two-level power converters and three-level power converters. Switched-capacitor converters are a type of three-level power converter.

[0004] As integrated circuits become increasingly advanced while simultaneously shrinking in size, compact and efficient DC / DC conversion topologies are desired. Compared to other topologies, three-level converters such as switched-capacitor converters are less complex because they consist of multiple switches and a flying capacitor. Furthermore, switched-capacitor converters have a small footprint and can achieve efficient power conversion by switching the flying capacitor during the charging and discharging phases. Therefore, switched-capacitor converters can provide compact and efficient power supplies for integrated circuits.

[0005] In a three-level converter with flying capacitors, the voltage balance of the flying capacitors must be maintained for the three-level power converter to operate efficiently and safely as intended. Voltage imbalance on the flying capacitors can be caused by many factors, such as changes in operating conditions (e.g., startup, input or output voltage variations, load changes or transients), circuit asymmetry, component variations, tolerances, mismatched pulse width modulation (PWM) signals or gate drives, and any combination thereof.

[0006] Unbalanced capacitors not only cause asymmetrical circuit operation, which can reduce the power efficiency of three-level power converters, but also impose additional overvoltage stress on power switches and capacitors, leading to component and system failure. In applications with a wide range of input voltage variations, capacitor voltage balancing is required to reduce voltage stress on power switches and capacitors. Summary of the Invention

[0007] These and other problems are solved or circumvented by preferred embodiments of the present disclosure, and technical advantages are generally achieved. Preferred embodiments of the present disclosure provide a control mechanism for achieving capacitor voltage balance in a three-level power converter.

[0008] According to one embodiment, a method includes detecting a voltage signal of a three-level power converter, the voltage signal indicating capacitor voltage balance in the three-level power converter; and dynamically adjusting an operating variable to adjust the voltage signal until the capacitor voltage balance in the three-level power converter meets a criterion.

[0009] The three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a flying capacitor connected between the common node of the first switch and the second switch and the common node of the third switch and the fourth switch; and an output filter connected between the common node of the second switch and the third switch and ground.

[0010] The voltage signal is the voltage across the flying capacitor, and the operating variable is the duty cycle of the second switch.

[0011] The method further includes determining the duty cycle via a main control loop; determining the duty cycle change via a local control loop; and, the first switch is configured to operate with the duty cycle, and the second switch is configured to operate with the sum of the duty cycle and the duty cycle change.

[0012] The operating variable is the adjustable delay between the gate drive signal of the first switch and the gate drive signal of the second switch, and wherein the adjustable delay is obtained through a negative feedback loop.

[0013] The three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a first input capacitor and a second input capacitor connected in series between the input voltage bus and ground; a common node of the first input capacitor and the second input capacitor connected to the common node of the second switch and the third switch; and an output filter connected between the common node of the first switch and the second switch and the common node of the third switch and the fourth switch.

[0014] The output filter includes an inductor and a capacitor connected in series between the common node of the first and second switches and the common node of the third and fourth switches.

[0015] The voltage signal is the voltage at the common node of the second and third switches, and the operating variable is the duty cycle of the fourth switch.

[0016] The method further includes determining the duty cycle via a main control loop; determining the duty cycle change via a local control loop; and the first switch being configured to operate with the duty cycle, and the fourth switch being configured to operate with the sum of the duty cycle and the duty cycle change.

[0017] The operating variable is an adjustable delay placed between the gate drive signal of the first switch and the gate drive signal of the fourth switch, wherein the adjustable delay is obtained through a negative feedback loop.

[0018] According to another embodiment, an apparatus includes a multilevel power converter, comprising a plurality of switches connected in series between an input voltage bus and ground; and a controller for generating gate drive signals for the plurality of switches, wherein the gate drive signals are dynamically adjusted to achieve capacitor voltage balance in the multilevel power converter.

[0019] The multilevel power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a flying capacitor connected between the common node of the first and second switches and the common node of the third and fourth switches; a gate drive signal dynamically adjusted to maintain the voltage across the flying capacitor equal to half the voltage on the input voltage bus; and a filter connected between the common node of the second and third switches and ground.

[0020] The multilevel converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a first input capacitor and a second input capacitor connected in series between the input voltage bus and ground; a common node of the first input capacitor and the second input capacitor connected to the common node of the second switch and the third switch; a gate drive signal dynamically adjusted to maintain the voltage at the common node of the first input capacitor and the second input capacitor equal to half the voltage on the input voltage bus; and a filter connected between the common node of the first switch and the second switch and the common node of the third switch and the fourth switch.

[0021] According to yet another embodiment, a method includes determining a first duty cycle of a three-level power converter via a main control loop; and determining a second duty cycle of the three-level power converter via a local control loop based on the first duty cycle, the local control loop being configured to adjust the second duty cycle to achieve capacitor voltage balance in the three-level power converter.

[0022] The three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a flying capacitor connected between the common node of the first switch and the second switch and the common node of the third switch and the fourth switch; and a filter connected between the common node of the second switch and the third switch and ground.

[0023] The method further includes applying the first duty cycle to the first switch and applying the second duty cycle to the second switch, using the local control loop to dynamically adjust the voltage across the flying capacitor by adjusting the second duty cycle.

[0024] The method further includes dynamically adjusting the voltage across the flying capacitor by applying an adjustable delay placed between the gate drive signal of the first switch and the gate drive signal of the second switch, wherein the adjustable delay is obtained through a negative feedback loop.

[0025] The three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; a first input capacitor and a second input capacitor connected in series between the input voltage bus and ground; a common node of the first input capacitor and the second input capacitor connected to the common node of the second switch and the third switch; and a filter connected between the common node of the first switch and the second switch and the common node of the third switch and the fourth switch.

[0026] The method further includes applying the first duty cycle to the first switch and applying the second duty cycle to the fourth switch, using the local control loop to dynamically adjust the voltage at the common node of the first input capacitor and the second input capacitor by adjusting the second duty cycle.

[0027] The method further includes dynamically adjusting the voltage at the common node of the first input capacitor and the second capacitor by applying an adjustable delay between the gate drive signal of the first switch and the gate drive signal of the fourth switch, wherein the adjustable delay is obtained through a negative feedback loop.

[0028] One advantage of embodiments of this disclosure is that capacitor voltage balancing is achieved in a three-level power converter, thereby improving the efficiency, reliability, and cost of the three-level power converter.

[0029] To better understand the detailed description of this disclosure below, the features and technical advantages of this disclosure have been broadly outlined above. Additional features and advantages of this disclosure, which form the subject matter of the claims, will be described below. Those skilled in the art will understand that the disclosed concepts and specific embodiments can readily serve as the basis for modifications or the design of other structures or processes to perform the same purposes of this disclosure. Those skilled in the art will also recognize that these equivalent structures do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0030] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 A schematic diagram of a first three-level power converter according to various embodiments of the present disclosure is shown;

[0032] Figure 2 A PWM control timing diagram for a first three-level power converter in low duty cycle mode according to various embodiments of the present disclosure is shown;

[0033] Figure 3 A PWM control timing diagram for a high duty cycle mode of a first three-level power converter according to various embodiments of the present disclosure is shown;

[0034] Figure 4 A control according to various embodiments of the present disclosure is shown. Figure 1 The flowchart of the method for the first three-level power converter is shown;

[0035] Figure 5 A schematic diagram of a second three-level power converter according to various embodiments of the present disclosure is shown;

[0036] Figure 6 A timing diagram of a first PWM control applied to a second three-level power converter according to various embodiments of the present disclosure is shown;

[0037] Figure 7 A timing diagram of a second PWM control applied to a second three-level power converter according to various embodiments of the present disclosure is shown;

[0038] Figure 8 A control according to various embodiments of the present disclosure is shown. Figure 5 The flowchart of the method for the second three-level power converter is shown;

[0039] Figure 9 A feedback control loop for controlling capacitor voltage is shown according to various embodiments of the present disclosure; and

[0040] Figure 10 Various embodiments based on this disclosure are illustrated. Figure 9 The control timing diagram of the feedback control loop is shown.

[0041] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts. The accompanying drawings are provided to clearly illustrate relevant aspects of the various embodiments, and the drawings are not necessarily drawn to scale. Detailed Implementation

[0042] The following describes in detail the making and use of the presently preferred embodiments. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed below merely illustrate specific methods of making and using this disclosure and do not limit the scope of this disclosure.

[0043] This disclosure will be described in the context of a preferred embodiment, namely a control method for achieving capacitor voltage balance in a three-level power converter. However, this disclosure is also applicable to various multilevel power converters. Various embodiments will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 A schematic diagram of a first three-level power converter according to various embodiments of the present disclosure is shown. The first three-level power converter 100 includes an input capacitor Cin, a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a capacitor Cb, an output inductor Lo, and an output capacitor Co. Figure 1 As shown, the output inductor Lo and the output capacitor Co form an output filter. The common node of the output inductor Lo and the output capacitor Co is the output terminal (Vo) of the first three-level power converter 100.

[0045] The first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are connected in series between the input voltage source Vin and ground. Throughout this description, the positive terminal of the input voltage source Vin is also referred to as the input voltage bus. The common node of the first switch Q1 and the second switch Q2 is denoted as SWA, as follows: Figure 2 As shown. Similarly, the common node of the second switch Q2 and the third switch Q3 is represented as SWB. The common node of the third switch Q3 and the fourth switch Q4 is represented as SWC. For example... Figure 1 As shown, capacitor Cb is connected between SWA and SWC.

[0046] In some embodiments, capacitor Cb is used as a flying capacitor. Throughout the description, capacitor Cb is also referred to as flying capacitor Cb.

[0047] According to one embodiment, the switch (e.g., switches Q1-Q4) can be a metal oxide semiconductor field-effect transistor (MOSFET) device. Alternatively, the switching element can be any controllable switch, such as an insulated gate bipolar transistor (IGBT) device, an integrated gate commutated thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, a silicon controlled rectifier (SCR) device, a junction gate field-effect transistor (JFET) device, a MOS controlled thyristor (MCT) device, etc.

[0048] It should be noted that, although Figure 1 The diagram shows switches Q1-Q4 implemented as a single n-type transistor, but those skilled in the art will recognize that many variations, modifications, and alternatives are possible. For example, depending on the application and design requirements, switches Q1-Q4 can be implemented as p-type transistors. Furthermore, Figure 1 Each switch shown can be implemented as multiple switches connected in parallel. Furthermore, a capacitor can be connected in parallel with another switch to achieve zero-voltage switching (ZVS) / zero-current switching (ZCS).

[0049] The first three-level power converter 100 includes two different operating modes: a low duty cycle mode and a high duty cycle mode. The duty cycle of the first three-level power converter 100 is the duty cycle of the first switch Q1. The duty cycle of Q2 is equal to the duty cycle of Q1. There is a 180-degree phase shift between the leading edge of the gate drive signal of Q1 and the leading edge of the gate drive signal of Q2. The gate drive signal of Q4 is complementary to the gate drive signal Q1. The gate drive signal of Q3 is complementary to the gate drive signal Q2.

[0050] In some embodiments, when the first three-level power converter 100 operates in a low duty cycle mode, the duty cycle of the first three-level power converter 100 is between 0% and 50%. On the other hand, when the first three-level power converter 100 operates in a high duty cycle mode, the duty cycle of the first three-level power converter 100 is between 50% and 100%. These will be discussed in conjunction with... Figure 2-3 This describes the detailed operating principles of the low duty cycle mode and high duty cycle mode of the first three-level power converter 100.

[0051] Figure 1 Controller 102 is also shown. Controller 102 can be implemented as any suitable controller, such as a microprocessor. Controller 102 detects various operating parameters (e.g., input voltage Vin, output voltage Vo, voltage across the flying capacitor Cb, load current, and any combination thereof). Based on the detected operating parameters, controller 102 determines, for example... Figure 1 The gate drive signals for switches Q1-Q4 are shown.

[0052] In some embodiments, controller 102 is used to detect the input voltage Vin. More specifically, controller 102 is used to detect a voltage level of half the input voltage (Vin / 2). This voltage level (Vin / 2) can be obtained by a suitable sensor device. For example, this voltage level (Vin / 2) can be obtained by a resistor divider connected between the input voltage bus Vin and ground. Controller 102 is also used to detect the voltage across the flying capacitor Cb. Based on the detected voltage signals Vin / 2 and Vcb, controller 102 accordingly determines the gate drive signals for switches Q1, Q2, Q3, and Q4. Reference will be made below. Figures 2-4 Describe the detailed working principle of controller 102.

[0053] Figure 2 A PWM control timing diagram for a low duty cycle mode of a first three-level power converter according to various embodiments of the present disclosure is shown. Figure 2The horizontal axis represents the time interval, and there are six vertical axes. The first vertical axis Y1 represents the gate drive signal of the first switch Q1. The second vertical axis Y2 represents the gate drive signal of the second switch Q2. The third vertical axis Y3 represents the gate drive signal of the third switch Q3. The fourth vertical axis Y4 represents the gate drive signal of the fourth switch Q4. The fifth vertical axis Y5 represents the voltage at node SWB. The sixth vertical axis Y6 represents the current flowing through inductor Lo.

[0054] like Figure 2 As shown, one switching cycle of the first three-level power converter 100 can be divided into four stages. The first stage is from 0 to D·Ts, where D and Ts are the duty cycle and switching period of the first three-level power converter 100, respectively. The second stage is from D·Ts to Ts / 2. The third stage is from Ts / 2 to (Ts / 2 + D·Ts). The fourth stage is from (Ts / 2 + D·Ts) to Ts.

[0055] like Figure 2 As shown, the duty cycle of the first switch Q1 is equal to the duty cycle of the second switch Q2. The duty cycle of the first switch Q1 is in the range of 0 to 50%. In some embodiments, D is equal to the ratio of the output voltage Vo to the input voltage Vin. The gate drive signal of the fourth switch Q4 is complementary to the gate drive signal of the first switch Q1. The gate drive signal of the fourth switch Q3 is complementary to the gate drive signal of the first switch Q2. Figure 2 As shown, there is a delay between the leading edge of the gate drive signal of the first switch Q1 and the leading edge of the gate drive signal of the second switch Q2. This delay is equal to half of the switching period. Similarly, the delay between the leading edge of the gate drive signal of the fourth switch Q4 and the leading edge of the gate drive signal of the third switch Q3 is equal to half of the switching period.

[0056] During the first phase, switches Q2 and Q4 are off, and switches Q1 and Q3 are on, as follows: Figure 2 As shown. A conductive path is established between Vin and Vo due to the opening of switches Q1 and Q3. This conductive path is formed by switch Q1, the flying capacitor Cb, switch Q3, and the output inductor Lo. Current flows through this conductive path from the input power supply Vin to the output voltage Vo. The voltage at node SWB is equal to Vin / 2, as shown. Figure 2 As shown.

[0057] During the first stage, the flying capacitor Cb is charged, and energy is stored accordingly in the flying capacitor Cb. The current flowing through the inductor Lo may increase or decrease depending on the voltage applied across the inductor Lo. In some embodiments, when the input voltage Vin is greater than the sum of the voltage across the flying capacitor Cb and the output voltage Vo, the current flowing through the inductor Lo increases, and the energy stored in the inductor Lo increases accordingly. The current slope S of the inductor Lo satisfies the following equation:

[0058] S=(Vin-Vcb-Vo) / Lo (1)

[0059] Where Vcb is the voltage across the flying capacitor Cb.

[0060] During the second phase, switches Q1 and Q2 are off, and switches Q3 and Q4 are on. Due to the opening of switches Q3 and Q4, a conductive path is established between Vo and ground. This conductive path is formed by switch Q4, switch Q3, and the output inductor Lo. In some embodiments, switch Q4 provides a freewheeling path for the current flowing through the output inductor Lo. The voltage at node SWB is equal to 0, as... Figure 2 As shown.

[0061] During the second stage, the flying capacitor Cb is isolated by the switched-off switches Q1 and Q2. The current flowing through inductor Lo decreases, and the energy stored in inductor Lo decreases accordingly. The current slope S of inductor Lo satisfies the following equation:

[0062] S = -Vo / Lo (2)

[0063] During the third phase, switches Q1 and Q3 are off, and switches Q2 and Q4 are on. Due to the opening of switches Q2 and Q4, a conductive path is established between Vo and ground. This conductive path is formed by switch Q4, the flying capacitor Cb, switch Q2, and the output inductor Lo. The voltage at node SWB is equal to Vin / 2, as shown below. Figure 2 As shown.

[0064] During the third stage, the current discharges through the flying capacitor Cb, and the energy stored in the flying capacitor Cb decreases accordingly. In some embodiments, the current flowing through the inductor Lo may increase, and the energy stored in the inductor Lo increases accordingly. In the third stage, the current slope S of the inductor Lo satisfies the following equation:

[0065] S=(Vcb-Vo) / Lo (3)

[0066] During the fourth phase, switches Q1 and Q2 are off, and switches Q3 and Q4 are on. Due to the opening of switches Q3 and Q4, a conductive path is established between Vo and ground. This conductive path is formed by switch Q4, switch Q3, and the output inductor Lo. In some embodiments, switch Q4 provides a freewheeling path for the current flowing through the output inductor Lo. The voltage at node SWB is equal to 0, as... Figure 2 As shown.

[0067] During the fourth stage, the flying capacitor Cb is isolated by the switched-off switches Q1 and Q2. The current flowing through inductor Lo decreases, and the energy stored in inductor Lo decreases accordingly. In the fourth stage, the current slope S of inductor Lo satisfies the following equation:

[0068] S = -Vo / Lo (4)

[0069] Figure 3 A PWM control timing diagram for a high duty cycle mode of a first three-level power converter according to various embodiments of the present disclosure is shown; Figure 3 The horizontal axis represents the time interval, and there are six vertical axes. The first vertical axis Y1 represents the gate drive signal of the first switch Q1. The second vertical axis Y2 represents the gate drive signal of the second switch Q2. The third vertical axis Y3 represents the gate drive signal of the third switch Q3. The fourth vertical axis Y4 represents the gate drive signal of the fourth switch Q4. The fifth vertical axis Y5 represents the voltage at node SWB. The sixth vertical axis Y6 represents the current flowing through inductor Lo.

[0070] like Figure 3 As shown, one switching cycle of the first three-level power converter 100 can be divided into four stages. The first stage is from 0 to (D·Ts-Ts / 2). The second stage is from (D·Ts-Ts / 2) to Ts / 2. The third stage is from Ts / 2 to D·Ts. The fourth stage is from D·Ts to Ts.

[0071] like Figure 3 As shown, the duty cycle of the first switch Q1 is equal to the duty cycle of the second switch Q2. The duty cycle of the first switch Q1 is between 50% and 100%. In some embodiments, D is equal to the ratio of the output voltage Vo to the input voltage Vin. The gate drive signal of the fourth switch Q4 is complementary to the gate drive signal of the first switch Q1. The gate drive signal of the fourth switch Q3 is complementary to the gate drive signal of the first switch Q2. Figure 3 As shown, there is a delay between the leading edge of the gate drive signal of the first switch Q1 and the leading edge of the gate drive signal of the second switch Q2. This delay is equal to half of the switching period. Similarly, the delay between the leading edge of the gate drive signal of the third switch Q3 and the leading edge of the gate drive signal of the fourth switch Q4 is equal to half of the switching period.

[0072] During the first phase, switches Q3 and Q4 are closed, and switches Q1 and Q2 are open, as follows: Figure 3 As shown. A conductive path is established between Vin and Vo due to the opening of switches Q1 and Q2. This conductive path is formed by switches Q1 and Q2 and the output inductor Lo. Current flows through this conductive path from the input power supply Vin to the output voltage Vo. The voltage at node SWB is equal to Vin, as shown. Figure 3 As shown.

[0073] During the first stage, the current flowing through inductor Lo may increase, and the energy stored in inductor Lo will increase accordingly. The current slope S of inductor Lo satisfies the following equation:

[0074] S=(Vin-Vo) / Lo (5)

[0075] During the second phase, switches Q2 and Q4 are closed, and switches Q1 and Q3 are open, as follows: Figure 3 As shown. A conductive path is established between Vin and Vo due to the opening of switches Q1 and Q3. This conductive path is formed by switch Q1, the flying capacitor Cb, switch Q3, and the output inductor Lo. Current flows through this conductive path from the input power supply Vin to the output voltage Vo. The voltage at node SWB is equal to Vin / 2, as shown. Figure 3 As shown.

[0076] During the second stage, the flying capacitor Cb is charged, and energy is stored accordingly in the flying capacitor Cb. The current flowing through the inductor Lo may increase or decrease depending on the voltage applied across the inductor Lo. In some embodiments, when the input voltage Vin is less than the sum of the voltage across the flying capacitor Cb and the output voltage Vo, the current flowing through the inductor Lo decreases, and the energy stored in the inductor Lo decreases accordingly. The current slope S of the inductor Lo satisfies the following equation:

[0077] S=(Vin-Vcb-Vo) / Lo (6)

[0078] During the third phase, switches Q3 and Q4 are closed, and switches Q1 and Q2 are open, as follows: Figure 3 As shown. A conductive path is established between Vin and Vo due to the opening of switches Q1 and Q2. This conductive path is formed by switches Q1 and Q2 and the output inductor Lo. Current flows through this conductive path from the input power supply Vin to the output voltage Vo. The voltage at node SWB is equal to Vin, as shown. Figure 3 As shown.

[0079] During the third stage, the current flowing through inductor Lo may increase, and the energy stored in inductor Lo will increase accordingly. The current slope S of inductor Lo satisfies the following equation:

[0080] S=(Vin-Vo) / Lo (7)

[0081] During the fourth phase, switches Q1 and Q3 are off, and switches Q2 and Q4 are on. Due to the opening of switches Q2 and Q4, a conductive path is established between Vo and ground. This conductive path is formed by switch Q4, the flying capacitor Cb, switch Q2, and the output inductor Lo. The voltage at node SWB is equal to Vin / 2, as shown below. Figure 3 As shown.

[0082] During the fourth stage, the current discharges through the flying capacitor Cb, and the energy stored in the flying capacitor Cb decreases accordingly. In some embodiments, the current flowing through the inductor Lo may decrease, and the energy stored in the inductor Lo decreases accordingly. In the fourth stage, the current slope S of the inductor Lo satisfies the following equation:

[0083] S=(Vcb-Vo) / Lo (8)

[0084] In the first three-level power converter 100, it is desirable to maintain voltage balance. Specifically, Figure 1 The controller 102 shown is used to control the operation of the first three-level power converter 100 to maintain the voltage across the flying capacitor Cb equal to half of the input voltage Vin. This voltage balance helps to keep the first three-level power converter 100 operating efficiently and safely as intended.

[0085] In this circuit, controller 102 determines the duty cycle of the first three-level power converter 100 via a main feedback control loop. The duty cycle is directly applied to switch Q1. To achieve capacitor voltage balance, a duty cycle change is obtained via a local feedback control loop. The sum of the duty cycle from the main feedback control loop and the duty cycle change from the local feedback control loop is applied to switch Q2. This duty cycle adjustment helps maintain the voltage across the flying capacitor Cb equal to half the input voltage Vin. (Refer to the following...) Figure 4 Describe the detailed working principle of this capacitor voltage balance control method.

[0086] Figure 4 A control according to various embodiments of the present disclosure is shown. Figure 1 The flowchart shows the method of the first three-level power converter. Figure 4 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 4 The steps shown are as follows.

[0087] To achieve capacitor voltage balance, a trial-and-error-based control method is applied to the first three-level power converter 100, such as... Figure 1 As shown, by using a trial-and-error-based control method, the opening time of a switch (e.g., a second switch) is dynamically adjusted to balance the voltage across the flying capacitor Cb.

[0088] The first three-level power converter 100 is controlled by a main control loop (not shown). The main control loop is used to determine a suitable duty cycle to regulate the output voltage and / or current of the first three-level power converter 100. Figure 4 The trial-and-error-based control method shown is used as a local control loop. This local control loop modifies the duty cycle generated by the main control loop based on the voltage across the flying capacitor Cb. By modifying the duty cycle, the voltage across the flying capacitor can be dynamically adjusted, thereby achieving capacitor voltage balance.

[0089] In step 402, the initialization process is applied to the first three-level power converter. As the first step in adjusting the voltage of the flyover capacitor, the controller sets k to equal 1. Δton(1) equals zero. Δton(1) is the duty cycle change in the first step of adjusting the voltage of the flyover capacitor. In the first step, the opening time of the first switch Q1 is set to d(1)·Ts, where d(1) is the duty cycle generated by the main control loop and Ts is the predetermined switching period. Also in the first step, the opening time of the second switch Q2 is set to the sum of d(1)·Ts and Δton(1).

[0090] In the first step, Sgn(1) is set to 1, where Sgn is a trial-and-error direction indicator. Sgn can be set to 1 or -1, depending on whether the unbalanced capacitor voltage is reduced in this trial-and-error based control process. The detailed working principle of determining the value of Sgn will be described below with reference to steps 408-412.

[0091] In the first step, the controller is used to detect the input voltage Vin. More specifically, the controller is used to detect half of the input voltage (Vin / 2) through a suitable voltage divider circuit. Half of the input voltage sensed in the first step is defined as Vin(1) / 2, as follows: Figure 4 As shown. In addition, the controller is also used to detect the voltage across the flying capacitor. The voltage across the flying capacitor sensed in the first step is defined as Vcb(1), as... Figure 4 As shown.

[0092] In step 404, after completing the initialization process in step 402, the controller continues with step 404, wherein the controller determines the duty cycle change using the following equation:

[0093] Δton(k)=Δton(k-1)+Sgn(k-1)×tstep (9)

[0094] Where k is an integer greater than or equal to 2, and tstep is a predetermined duration. In some embodiments, tstep is set to 4 nanoseconds.

[0095] Also in step 404, the controller determines the duty cycle of the first switch Q1 and the second switch Q2 using the following equation:

[0096] ton1(k)=d(k)×Ts (10)

[0097] ton2(k)=d(k)×Ts+Δton(k) (11)

[0098] Wherein, ton1 is the opening time of the first switch Q1, and ton2 is the opening time of the second switch Q2.

[0099] In step 406, the controller is used to detect half of the input voltage (Vin(k) / 2) and the voltage across the flying capacitor (Vcb(k)) again.

[0100] In step 408, the controller determines whether the absolute value of the difference between Vin(k) / 2 and Vcb(k) is greater than or equal to the absolute value of the difference between these two values ​​obtained in the previous step. If the absolute value of the difference between Vin(k) / 2 and Vcb(k) is greater than or equal to the absolute value of the difference between these two values ​​obtained in the previous step, the method proceeds to step 410, where Sgn(k) is set to the value of -1 × Sgn(k-1). Otherwise, the method proceeds to step 412, where Sgn(k) is set to the value of Sgn(k-1). After determining the value of Sgn in step 410 or 412, the method returns to step 404 and repeats steps 404-412 again. Figure 4 The trial-and-error-based control process shown can achieve capacitor voltage balance.

[0101] It should be noted that, Figure 4 In the control method shown, k (k = 1, 2, 3, ..., N-1, N, N+1, ...) can correspond to one switching cycle or multiple switching cycles. For example, Figure 4 The control method shown allows Δton to be adjusted once per switching cycle or every other switching cycle.

[0102] It is also important to note that, Figure 4 The control method used in the flowchart only illustrates the simplest case of changing Δton using tstep. In some embodiments, tstep is set to a small constant, such as 4 nanoseconds. The selection of this constant time step tstep needs to consider both the accuracy and speed of the capacitor voltage control loop (local control loop). Alternatively, a variable time step method can be used to accelerate the adjustment of Δton, allowing the voltage across the flying capacitor to converge faster and closer to Vin / 2.

[0103] It should also be noted that the adjustment of the opening time of the second switch Q2 is merely an example. Those skilled in the art will understand that many alternatives, modifications, and variations are possible. For example, the control method can simultaneously adjust the opening times of Q1 and Q2. The opening time adjustment step (step 404) can be modified using the following equation:

[0104] ton1(k)=d(k)×Ts-Δton(k) (12)

[0105] ton2(k)=d(k)×Ts+Δton(k) (13)

[0106] In an alternative embodiment, the time adjustment step (step 404) can be modified using the following equation:

[0107] ton1(k)=d(k)×Ts+Δton(k) (14)

[0108] ton2(k)=d(k)×Ts-Δton(k) (15)

[0109] Figure 5 A schematic diagram of a second three-level power converter according to various embodiments of the present disclosure is shown. The second three-level power converter 200 includes a first switch Q1, a second switch Q2, a third switch Q3, a fourth switch Q4, a first input capacitor Cin1, a second input capacitor Cin2, an output inductor Lo, and an output capacitor Co. Figure 5 As shown, the output inductor Lo and the output capacitor Co form an output filter. The common node of the output inductor Lo and the output capacitor Co is the output terminal (Vo) of the second three-level power converter 200.

[0110] The first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are connected in series between the input voltage source Vin and ground. Throughout this description, Vin is also referred to as the input voltage bus. The common node of the first switch Q1 and the second switch Q2 is denoted as SWA, as follows: Figure 5 As shown. Similarly, the common node of the second switch Q2 and the third switch Q3 is represented as Vi_mid. The common node of the third switch Q3 and the fourth switch Q4 is represented as SWB. For example... Figure 5 As shown, the output filter is connected between SWA and SWB.

[0111] The first input capacitor Cin1 and the second input capacitor Cin2 are connected in series between the input voltage source Vin and ground. The common node of the first input capacitor Cin1 and the second input capacitor Cin2 is connected to Vi_mid, as shown below. Figure 5 As shown. The first input capacitor Cin1 and the second input capacitor Cin2 are used as voltage dividers. The voltage at node Vi_mid is equal to half of the input voltage Vin. The first input capacitor Cin1 is also called the first voltage divider capacitor. The second input capacitor Cin2 is also called the second voltage divider capacitor.

[0112] During operation, the controller 202 maintains the voltage across the first input capacitor Cin1 equal to the voltage across the second input capacitor Cin2. The common node of the first input capacitor Cin1 and the second input capacitor Cin2 is the midpoint of the second three-level power converter 200. Vi_mid is also referred to as the midpoint voltage of the second three-level power converter 200.

[0113] The second three-level power converter 200 includes three voltage levels. The first voltage level is the voltage from the input voltage Vin. The second voltage level is equal to Vi_mid, which is half the input voltage Vin. The third voltage level is zero.

[0114] According to one embodiment, the switch (e.g., switches Q1-Q4) can be a metal-oxide-semiconductor field-effect transistor (MOSFET) device. Alternatively, the switching element can be any controllable switch, such as an insulated-gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate-turn-off thyristor (GTO) device, a silicon-controlled rectifier (SCR) device, a junction-gate field-effect transistor (JFET) device, a MOS-controlled thyristor (MCT) device, etc.

[0115] It should be noted that, although Figure 5 The diagram shows switches Q1-Q4 implemented as a single n-type transistor, but those skilled in the art will recognize that many variations, modifications, and alternatives are possible. For example, depending on the application and design requirements, switches Q1-Q4 can be implemented as p-type transistors. Furthermore, Figure 5 Each switch described herein can be implemented as multiple switches connected in parallel. Furthermore, a capacitor can be connected in parallel with another switch to implement a zero-voltage switch (ZVS) / zero-current switch (ZCS).

[0116] The second three-level power converter 200 includes two different operating modes: a low duty cycle mode and a high duty cycle mode. The duty cycle of the second three-level power converter 200 is the same as the duty cycle of the first switch Q1. The duty cycle of the fourth switch Q4 is equal to the duty cycle of the first switch Q1. There is a 180-degree phase shift between the leading edges of the gate drive signals of Q1 and Q4. The gate drive signal of Q2 is complementary to the gate drive signal of Q1. The gate drive signal of Q3 is complementary to the gate drive signal of Q4.

[0117] In some embodiments, when the second three-level power converter 200 operates in a low duty cycle mode, the duty cycle of the second three-level power converter 200 is between 0% and 50%. On the other hand, when the second three-level power converter 200 operates in a high duty cycle mode, the duty cycle of the second three-level power converter 200 is between 50% and 100%. These will be discussed in conjunction with... Figure 6-7 Describes the detailed working principles of low duty cycle mode and high duty cycle mode.

[0118] Figure 5Controller 202 is also shown. Controller 202 can be implemented as any suitable controller, such as a microprocessor. Controller 202 detects various operating parameters (e.g., input voltage Vin, output voltage Vo, voltage across the flying capacitor Cb, load current, and any combination thereof). Based on the detected operating parameters, controller 202 determines, for example... Figure 5 The gate drive signals for switches Q1-Q4 are shown.

[0119] Controller 202 is used to detect the input voltage Vin. More specifically, controller 202 is used to detect a voltage level of half the input voltage (Vin / 2). This voltage level (Vin / 2) can be obtained by a sensor device. For example, this voltage level can be obtained by a resistor divider connected between Vin and ground. Controller 202 is also used to detect the midpoint voltage Vi_mid. Based on the detected voltage signal, controller 202 determines the gate drive signals for switches Q1, Q2, Q3, and Q4 accordingly. (Refer to the following...) Figure 6-8 Describe the detailed working principle of controller 202.

[0120] Figure 6 A timing diagram of a first PWM control applied to a second three-level power converter according to various embodiments of the present disclosure is shown. Figure 2 The horizontal axis represents the time interval, and there are six vertical axes. The first vertical axis Y1 represents the gate drive signal of the first switch Q1. The second vertical axis Y2 represents the gate drive signal of the fourth switch Q4. The third vertical axis Y3 represents the gate drive signal of the third switch Q3. The fourth vertical axis Y4 represents the gate drive signal of the second switch Q2. The fifth vertical axis Y5 represents the voltage difference between SWA and SWB. The sixth vertical axis Y6 represents the current flowing through the inductor Lo.

[0121] like Figure 6 As shown, one switching cycle of the second three-level power converter 200 can be divided into four stages. The first stage is from 0 to D·Ts, where D and Ts are the duty cycle and switching period of the first three-level power converter 200, respectively. The second stage is from D·Ts to Ts / 2. The third stage is from Ts / 2 to (Ts / 2 + D·Ts). The fourth stage is from (Ts / 2 + D·Ts) to Ts.

[0122] like Figure 6 As shown, the duty cycle of the first switch Q1 is equal to the duty cycle of the fourth switch Q4. The duty cycle of the first switch Q1 is between 0 and 50%. In some embodiments, D is equal to the ratio of the output voltage Vo to the input voltage Vin. The gate drive signal of the second switch Q2 is complementary to the gate drive signal of the first switch Q1. The gate drive signal of the third switch Q3 is complementary to the gate drive signal of the fourth switch Q1. Figure 6As shown, there is a delay between the leading edge of the gate drive signal of the first switch Q1 and the leading edge of the gate drive signal of the fourth switch Q4. This delay is equal to half of the switching period. Similarly, the delay between the leading edge of the gate drive signal of the second switch Q2 and the leading edge of the gate drive signal of the third switch Q3 is equal to half of the switching period.

[0123] During the first phase, switches Q2 and Q4 are off, and switches Q1 and Q3 are on, as follows: Figure 6 As shown. A conductive path is established between Vin and Vi_mid due to the opening of switches Q1 and Q3. This conductive path is formed by switch Q1, the output inductor Lo, and switch Q3. Current flows through this conductive path from the input power supply Vin to the output voltage Vo. The voltage difference between SWA and SWB is equal to Vin / 2, as shown. Figure 6 As shown.

[0124] During the first stage, the second input capacitor Cin2 is charged, and the input capacitor Cin1 is discharged. The current flowing through the inductor Lo may increase, and the energy stored in the inductor Lo increases accordingly. The current slope S of the inductor Lo satisfies the following equation:

[0125] S=(Vin-Vo-Vi_mid) / Lo (16)

[0126] During the second phase, switches Q1 and Q4 are closed, and switches Q2 and Q3 are open. The opening of switches Q2 and Q3 establishes a conductive path. This conductive path is formed by switch Q2, the output inductor Lo, the output capacitor Co, and switch Q3. In some embodiments, switches Q2 and Q3 provide a freewheeling path for the current flowing through the output inductor Lo. The voltage difference between SWA and SWB is equal to 0, as... Figure 6 As shown.

[0127] During the second stage, the current flowing through inductor Lo decreases, and the energy stored in inductor Lo decreases accordingly. The current slope S of inductor Lo satisfies the following equation:

[0128] S = -Vo / Lo (17)

[0129] During the third phase, switches Q1 and Q3 are off, and switches Q2 and Q4 are on. Due to the opening of switches Q2 and Q4, a conductive path is established between Vi_mid and ground. This conductive path is formed by switch Q2, the output inductor Lo, the output capacitor Co, and switch Q4. The voltage difference between SWA and SWB is equal to Vin / 2, as shown below. Figure 6 As shown.

[0130] During the third stage, the current discharges through the second input capacitor Cin2, and the energy stored in the second input capacitor Cin2 decreases accordingly. In some embodiments, the current flowing through the inductor Lo may increase, and the energy stored in the inductor Lo increases accordingly. In the third stage, the current slope S of the inductor Lo satisfies the following equation:

[0131] S=(Vi_mid-Vo) / Lo (18)

[0132] During the fourth stage, switches Q1 and Q4 are off, and switches Q2 and Q3 are on. The opening of switches Q2 and Q3 establishes a conductive path. This conductive path is formed by switch Q2, the output inductor Lo, the output capacitor Co, and switch Q3. In some embodiments, switches Q2 and Q3 provide a freewheeling path for the current flowing through the output inductor Lo. The voltage difference between SWA and SWB is equal to 0, as... Figure 6 As shown.

[0133] During the fourth stage, the current flowing through inductor Lo decreases, and the energy stored in inductor Lo decreases accordingly. In the fourth stage, the current slope S of inductor Lo satisfies the following equation:

[0134] S = -Vo / Lo (19)

[0135] Figure 7 A timing diagram of a second PWM control applied to a second three-level power converter according to various embodiments of the present disclosure is shown. Figure 7 The horizontal axis represents the time interval, and there are six vertical axes. The first vertical axis Y1 represents the gate drive signal of the first switch Q1. The second vertical axis Y2 represents the gate drive signal of the fourth switch Q4. The third vertical axis Y3 represents the gate drive signal of the third switch Q3. The fourth vertical axis Y4 represents the gate drive signal of the second switch Q2. The fifth vertical axis Y5 represents the voltage difference between SWA and SWB. The sixth vertical axis Y6 represents the current flowing through the inductor Lo.

[0136] like Figure 7 As shown, one switching cycle of the second three-level power converter 200 can be divided into four stages. The first stage is from 0 to (D·Ts-Ts / 2). The second stage is from (D·Ts-Ts / 2) to Ts / 2. The third stage is from Ts / 2 to D·Ts. The fourth stage is from D·Ts to Ts.

[0137] like Figure 7As shown, the duty cycle of the first switch Q1 is equal to the duty cycle of the fourth switch Q4. The duty cycle of the first switch Q1 is between 50% and 100%. In some embodiments, D is equal to the ratio of the output voltage Vo to the input voltage Vin. The gate drive signal of the second switch Q2 is complementary to the gate drive signal of the first switch Q1. The gate drive signal of the third switch Q3 is complementary to the gate drive signal of the fourth switch Q1. Figure 7 As shown, there is a delay between the leading edge of the gate drive signal of the first switch Q1 and the leading edge of the gate drive signal of the fourth switch Q4. This delay is equal to half of the switching period. Similarly, the delay between the leading edge of the gate drive signal of the third switch Q3 and the leading edge of the gate drive signal of the second switch Q2 is equal to half of the switching period.

[0138] During the first phase, switches Q2 and Q3 are off, and switches Q1 and Q4 are on, as follows: Figure 7 As shown. With switches Q1 and Q4 open, a conductive path is established between Vin and ground. This conductive path is formed by switch Q1, the output inductor Lo, the output capacitor Co, and switch Q4. Current flows through this conductive path from the input power supply Vin to ground. The voltage difference between SWA and SWB is equal to Vin, as shown. Figure 7 As shown.

[0139] During the first stage, the current flowing through inductor Lo may increase, and the energy stored in inductor Lo will increase accordingly. The current slope S of inductor Lo satisfies the following equation:

[0140] S=(Vin-Vo) / Lo (20)

[0141] During the second phase, switches Q2 and Q4 are closed, and switches Q1 and Q3 are open, as follows: Figure 7 As shown. A conductive path is established between Vin and Vi_mid due to the opening of switches Q1 and Q3. This conductive path is formed by switch Q1, the output inductor Lo, the output capacitor Co, and switch Q3. Current flows from the input power supply Vin to Vi_mid through this conductive path. The voltage difference between SWA and SWB is equal to Vin / 2, as shown. Figure 7 As shown.

[0142] During the second stage, the second input capacitor Cin2 is charged, and energy is stored accordingly in the second input capacitor Cin2. The current flowing through the inductor Lo may increase or decrease depending on the voltage applied across the inductor Lo. In some embodiments, when the input voltage Vin is less than the sum of the voltage across the second input capacitor Cin2 and the output voltage Vo, the current flowing through the inductor Lo decreases, and the energy stored in the inductor Lo decreases accordingly. The current slope S of the inductor Lo satisfies the following equation:

[0143] S=(Vin-Vo-Vi_mid) / Lo (21)

[0144] During the third phase, switches Q2 and Q3 are off, and switches Q1 and Q4 are on, as follows: Figure 7 As shown. With switches Q1 and Q4 open, a conductive path is established between Vin and ground. This conductive path is formed by switch Q1, the output inductor Lo, the output capacitor Co, and switch Q4. Current flows through this conductive path from the input power supply Vin to ground. The voltage difference between SWA and SWB is equal to Vin, as shown. Figure 7 As shown.

[0145] During the third stage, the current flowing through inductor Lo may increase, and the energy stored in inductor Lo will increase accordingly. The current slope S of inductor Lo satisfies the following equation:

[0146] S=(Vin-Vo) / Lo (22)

[0147] During the fourth phase, switches Q1 and Q3 are off, and switches Q2 and Q4 are on. Due to the opening of switches Q2 and Q4, a conductive path is established between Vi_mid and ground. This conductive path is formed by switch Q2, the output inductor Lo, the output capacitor Co, and switch Q4. The voltage difference between SWA and SWB is equal to Vin / 2, as shown below. Figure 7 As shown.

[0148] During the fourth stage, the current discharges through the second input capacitor Cin2, and the energy stored in the second input capacitor Cin2 decreases accordingly. In some embodiments, the current flowing through the inductor Lo may decrease, and the energy stored in the inductor Lo decreases accordingly. In the fourth stage, the current slope S of the inductor Lo satisfies the following equation:

[0149] S=(Vi_mid-Vo) / Lo (23)

[0150] In the second-three-level power converter 200, it is desirable to maintain voltage balance. Specifically, the controller 202 controls the operation of the second-three-level power converter 200 to maintain the voltage at node Vi_mid equal to half of the input voltage Vin. This voltage balance helps ensure that the second-three-level power converter 200 operates efficiently and safely as intended.

[0151] In operation, controller 202 determines the duty cycle of the second three-level power converter 200 through the main feedback control loop. The duty cycle is directly applied to switch Q1. To achieve capacitor voltage balance, a duty cycle change is obtained through a local feedback control loop. The sum of the duty cycle from the main feedback control loop and the duty cycle change from the local feedback control loop is applied to switch Q4. Duty cycle variation helps maintain the voltage at node Vi_mid equal to half the input voltage. (See below for reference...) Figure 8 Describe the detailed working principle of this capacitor voltage balance control method.

[0152] Figure 8 A control according to various embodiments of the present disclosure is shown. Figure 5 The flowchart shows the method for the second three-level power converter. Figure 8 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 8 The steps shown are as follows.

[0153] To achieve capacitor voltage balance, a trial-and-error-based control method is applied to a second-three-level power converter, such as... Figure 5 As shown, by using a trial-and-error-based control method, the on-time of a switch (e.g., the fourth switch Q4) is dynamically adjusted to balance the voltage across the first input capacitor Cin1 and / or across the second input capacitor Cin2. In other words, a trial-and-error-based control method is employed to maintain the midpoint voltage Vi_mid equal to half of the input voltage.

[0154] The second three-level power converter 200 is controlled by a main control loop (not shown). The main control loop is used to determine a suitable duty cycle to regulate the output voltage and / or current of the second three-level power converter 200. Figure 8 The trial-and-error-based control method shown is used as a local control loop. This local control loop modifies the duty cycle generated by the main control loop based on the voltage at node Vi_mid. By modifying the duty cycle, the voltage at node Vi_mid can be dynamically adjusted, thereby achieving capacitor voltage balance.

[0155] In step 802, the initialization process is applied to the second three-level power converter. As the first step in adjusting the voltage at node Vi_mid, the controller sets k to equal to 1. Δton(1) equals zero. Δton(1) is the duty cycle change in the first step of adjusting the voltage at node Vi_mid. In the first step, the opening time of the first switch Q1 is set to d(1)·Ts, where d(1) is the duty cycle generated by the main control loop and Ts is the predetermined switching period. Also in the first step, the opening time of the fourth switch Q4 is set to d(1)·Ts. Figure 8 The ton4(1) shown is set as the sum of d(1)·Ts and Δton(1).

[0156] In the first step, Sgn(1) is set to 1, where Sgn is a trial-and-error direction indicator. Sgn can be set to 1 or -1, depending on whether the unbalanced capacitor voltage is reduced in this trial-and-error based control process. The detailed working principle of determining the value of Sgn will be described below with reference to steps 808-812.

[0157] In the first step, the controller is used to detect the input voltage Vin. More specifically, the controller is used to detect half of the input voltage (Vin / 2) through a suitable voltage divider circuit. Half of the input voltage sensed in the first step is defined as Vin(1) / 2, as follows: Figure 8 As shown. In addition, the controller is also used to detect the voltage on node Vi_mid. The voltage on node Vi_mid sensed in the first step is defined as Vi_mid(1), as... Figure 8 As shown.

[0158] In step 804, after completing the initialization process in step 802, the controller determines the duty cycle change using the following equation:

[0159] Δton(k)=Δton(k-1)+Sgn(k-1)×tstep (24)

[0160] Where k is an integer greater than or equal to 2, and tstep is a predetermined duration. In some embodiments, tstep is set to 4 nanoseconds.

[0161] Also in step 804, the controller determines the duty cycle of the first switch Q1 and the fourth switch Q4 using the following equation:

[0162] ton1(k)=d(k)×Ts (25)

[0163] ton4(k)=d(k)×Ts+Δton(k) (26)

[0164] Where on1 is the opening time of the first switch Q1, and ton4 is the opening time of the fourth switch Q4.

[0165] In step 806, the controller is used to detect again half of the input voltage (Vin(k) / 2) and the voltage at node Vi_mid (Vi_mid(k)).

[0166] In step 808, the controller determines whether the absolute value of the difference between Vin(k) / 2 and Vi_mid(k) is greater than or equal to the absolute value of the difference between these two values ​​obtained in the previous step. If the absolute value of the difference between Vin(k) / 2 and Vi_mid(k) is greater than or equal to the absolute value of the difference between these two values ​​obtained in the previous step, the method proceeds to step 810, where Sgn(k) is set to the value of -1 × Sgn(k-1). Otherwise, the method proceeds to step 812, where Sgn(k) is set to the value of Sgn(k-1). After determining the value of Sgn in step 810 or 812, the method returns to step 804.

[0167] It should be noted that, Figure 8 In the control method shown, k (k = 1, 2, 3, ..., N-1, N, N+1, ...) can correspond to one switching cycle or multiple switching cycles. For example, Figure 8 The control method shown allows Δton to be adjusted once per switching cycle or every other switching cycle.

[0168] It is also important to note that, Figure 8 The control method used in the flowchart only illustrates the simplest case of changing Δton using tstep. In some embodiments, tstep is set to a small constant, such as 4 nanoseconds. The selection of this constant time step tstep needs to consider both the accuracy and speed of the capacitor voltage control loop (local control loop). Alternatively, a variable time step method can be used to speed up the adjustment of Δton, allowing the voltage across the input capacitor (e.g., Cin2) to converge faster and closer to Vin / 2.

[0169] Figure 8 The control methods shown are applicable to all three-level power converters that only require adjustment and / or balancing of a single voltage. Furthermore, these control methods are also suitable for applications requiring bidirectional power handling.

[0170] It should also be noted that the adjustment of the opening time of the second switch Q4 is merely an example. Those skilled in the art will understand that many alternatives, modifications, and variations are possible. For example, the control method can simultaneously adjust the opening times of Q1 and Q4. The opening time adjustment step (step 804) can be modified using the following equation:

[0171] ton1(k)=d(k)×Ts-Δton(k) (27)

[0172] ton4(k)=d(k)×Ts+Δton(k) (28)

[0173] In an alternative embodiment, the time adjustment step (step 404) can be modified using the following equation:

[0174] ton1(k)=d(k)×Ts+Δton(k) (29)

[0175] ton4(k)=d(k)×Ts-Δton(k) (30)

[0176] Figure 9 A feedback control loop for controlling capacitor voltage according to various embodiments of this disclosure is illustrated. In some embodiments, a delay time tdelay is used as a control variable to control capacitor voltage balance via a negative feedback loop. The delay time tdelay is the phase shift between two gate drive signals. As a phase shift in a three-level power converter, the effect of the delay time tdelay on capacitor voltage imbalance is always unidirectional and monotonic with respect to any operating conditions and circuit parameters. The unidirectional and monotonic behavior of tdelay is valid even when the three-level power converter operates in different load directions. For example, for a three-level power converter with a flying capacitor, if the delay time tdelay is greater than half the switching cycle (Ts / 2), and assuming all other circuit parameters are symmetrical, the voltage across the flying capacitor is always greater than Vin / 2. This relationship remains valid under bidirectional power flow.

[0177] Figure 9 The feedback control loop shown is based on Figure 1 The first three-level power converter is shown. Figure 9 The feedback control loop shown includes a comparison unit 901, a feedback compensation network transfer function 902, a summation unit 903, and a phase-shifted capacitor voltage transfer function 904. For example... Figure 9 As shown, the comparison unit 901, the feedback compensation network transfer function 902, the summation unit 903, and the phase-shifted capacitor voltage transfer function 904 are cascaded together.

[0178] The signal Vc(S), representing the voltage across the flying capacitor Cb, is compared with the flying capacitor reference voltage signal Vcref(S) at comparison unit 901. The difference between Vcref(S) and Vc(S) is fed into feedback compensation network transfer function 902. Based on a negative feedback control method, feedback compensation network transfer function 902 generates an appropriate delay Δtdelay(S) to correct the voltage across the flying capacitor Cb. Since the gate drive signal of the second switch Q2 has a phase shift (180 degrees) with the gate drive signal of the first switch Q1, an appropriate delay (Ts / 2) is added to the feedback control loop of summing unit 903. Summing unit 903 generates a phase shift tdelay(S), which is fed into phase shift to capacitor voltage transfer function 904. Phase shift to capacitor voltage transfer function 904 adjusts the voltage across the flying capacitor Cb based on the received phase shift tdelay(S).

[0179] Figure 9 The control method shown is applicable to all three-level power converters that only require adjustment and / or balancing of a single voltage. Furthermore, this control method is also suitable for applications requiring bidirectional power handling.

[0180] It should be noted that, Figure 9 The negative feedback loop shown is merely an example. Those skilled in the art will understand that many alternatives, modifications, and variations are possible. For example, Figure 9 The feedback loop shown is also applicable to Figure 5 The second three-level power converter is shown.

[0181] Figure 10 Various embodiments based on this disclosure are illustrated. Figure 9 The control timing diagram of the feedback control loop is shown. Figure 10 The horizontal axis represents the time interval, and there are six vertical axes. The first vertical axis Y1 represents the gate drive signal of the first switch Q1. The second vertical axis Y2 represents the gate drive signal of the second switch Q2. The third vertical axis Y3 represents the gate drive signal of the third switch Q3. The fourth vertical axis Y4 represents the gate drive signal of the fourth switch Q4. The fifth vertical axis Y5 represents the voltage on node SWB, such as... Figure 1 As shown. The sixth vertical axis, Y6, represents the current flowing through the inductor Lo.

[0182] like Figure 10 As shown, one switching cycle of the first three-level power converter 100 can be divided into four stages. The first stage is from 0 to (D·Ts-Ts / 2). The second stage is from (D·Ts-Ts / 2) to Ts / 2. The third stage is from Ts / 2 to D·Ts. The fourth stage is from D·Ts to Ts.

[0183] Figure 10 The control timing diagram shown is consistent with Figure 3The control timing diagram shown is similar, except that the delay Δtdelay is applied to the gate drive signal of the second switch Q2. Figure 9 The feedback control loop shown generates a delay Δtdelay. This delay Δtdelay is applied to the gate drive signal of the second switch Q2. (As shown...) Figure 10 As shown, the leading edge of the gate drive signal for the second switch Q2 begins at Ts / 2 + Δtdelay. In contrast, in Figure 3 In this circuit, the leading edge of the gate drive signal for the second switch Q2 begins at Ts / 2. The gate drive signals for Q2 and Q3 are two complementary signals. As a result of the delay Δtdelay applied to the gate drive signal for Q2, the gate drive signal for Q3 is modified accordingly. In response to the delays added to Q2 and Q3, the voltage at node SWB and the current flowing through the output inductor Lo may change, such as... Figure 10 As shown.

[0184] and Figure 3 Compared to the timing diagram shown, the charge flowing through the flying capacitor Cb remains unchanged during the first stage. However, the discharge current flowing out of the flying capacitor Cb decreases during the modified third stage (from (Ts / 2 + Δtdelay) to (D × Ts + Δtdelay)). This reduced discharge current helps increase the voltage across the flying capacitor Cb. By applying this reduced discharge current to the flying capacitor Cb, the voltage across the flying capacitor increases to a level greater than half of the input voltage.

[0185] While embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0186] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, articles, compositions of matter, apparatuses, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of this publication that processes, machines, articles, compositions of matter, apparatuses, methods, or steps that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized using existing or future developments. Therefore, the appended claims are intended to encompass such processes, machines, production processes, compositions of matter, means, methods, or steps within their scope. Accordingly, this specification and drawings should be simply regarded as illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalent substitutions falling within the scope of the invention.

Claims

1. A control method for a three-level power converter, characterized in that, include: Detect the voltage signal of the three-level power converter, the voltage signal indicating the voltage balance of the capacitors in the three-level power converter; as well as, The operating variables are dynamically adjusted to adjust the voltage signal until the capacitor voltages in the three-level power converter are balanced. The three-level power converter includes: A first switch, a second switch, a third switch, and a fourth switch are connected in series between the input voltage bus and ground; A flying capacitor connected between the common node of the first and second switches and the common node of the third and fourth switches; and, An output filter connected between the common node of the second switch and the third switch and ground; The voltage signal is the voltage across the flying capacitor, and the operating variable is the duty cycle of the second switch; The control method further includes: The duty cycle is determined by the main control loop; The duty cycle change Δton is determined by the local control loop; and... The first switch is configured to operate with the stated duty cycle, and the second switch is configured to operate with the sum of the stated duty cycle and the duty cycle variation Δton, wherein... The trial-and-error-based control method is used as the local control loop, and the trial-and-error-based control method includes: A parameter indicating the direction of trial and error, said parameter depending on the voltage Vcb across the flying capacitor; A predetermined duration; and The duty cycle change Δton is determined based on the parameter, the duty cycle change Δton before a predetermined duration and one or more switching cycles.

2. A control method for a three-level power converter, characterized in that, include: Detect the voltage signal of the three-level power converter, the voltage signal indicating the voltage balance of the capacitors in the three-level power converter; as well as The operating variables are dynamically adjusted to adjust the voltage signal until the capacitor voltages in the three-level power converter are balanced. The three-level power converter includes: A first switch, a second switch, a third switch, and a fourth switch are connected in series between the input voltage bus and ground; A first input capacitor and a second input capacitor connected in series between the input voltage bus and ground; the common node of the first input capacitor and the second input capacitor connected to the common node of the second switch and the third switch; and, An output filter connected between the common node of the first and second switches and the common node of the third and fourth switches; The voltage signal is the voltage of the common node Vi_mid of the second switch and the third switch, and the operating variable is the duty cycle of the fourth switch; The control method further includes: The duty cycle is determined by the main control loop; The duty cycle change Δton is determined by the local control loop; and... The first switch is configured to operate with the duty cycle, and the fourth switch is configured to operate with the sum of the duty cycle and the duty cycle variation Δton; The trial-and-error-based control method is used as a local control loop, and the trial-and-error-based control method includes: A parameter indicating the direction of trial and error, the parameter depending on the voltage Vi_mid; A predetermined duration; and The duty cycle change Δton is determined based on the parameter, the duty cycle change Δton before a predetermined duration and one or more switching cycles.

3. The control method according to claim 2, characterized in that, The output filter includes an inductor and a capacitor connected in series between the common node of the first and second switches and the common node of the third and fourth switches.

4. A power conversion device, characterized in that, include: A three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; A flying capacitor connected between the common node of the first and second switches and the common node of the third and fourth switches; A filter connected between the common node of the second switch and the third switch and ground; A controller for controlling the operation of the three-level power converter, the controller being used for: The voltage signal of the three-level power converter is detected, and the voltage signal is the voltage across the flying capacitor; The operating variable is dynamically adjusted to adjust the voltage signal until the capacitor voltage in the three-level power converter is balanced, and the operating variable is the duty cycle of the second switch; The controller is specifically used for: The duty cycle is determined by the main control loop; The duty cycle change Δton is determined by the local control loop; as well as, The first switch is configured to operate with the stated duty cycle, and the second switch is configured to operate with the sum of the stated duty cycle and the duty cycle variation Δton, wherein... The trial-and-error-based control method is used as a local control loop, and the trial-and-error-based control method includes: A parameter indicating the direction of trial and error, said parameter depending on the voltage Vcb across the flying capacitor; A predetermined duration; and The duty cycle change Δton is determined based on the parameter, the duty cycle change Δton before a predetermined duration and one or more switching cycles.

5. A power conversion device, characterized in that, include: A three-level power converter includes a first switch, a second switch, a third switch, and a fourth switch connected in series between the input voltage bus and ground; A first input capacitor and a second input capacitor connected in series between the input voltage bus and ground, and the common node of the first input capacitor and the second input capacitor connected to the common node of the second switch and the third switch; A filter connected between the common node of the first and second switches and the common node of the third and fourth switches; A controller for controlling the operation of the three-level power converter, the controller being used for: The voltage signal of the three-level power converter is detected, and the voltage signal is the voltage Vi_mid of the common node; The operating variable is dynamically adjusted to adjust the voltage signal until the capacitor voltage in the three-level power converter is balanced, and the operating variable is the duty cycle of the fourth switch; The controller is specifically used for: The duty cycle is determined by the main control loop; The duty cycle change Δton is determined by the local control loop; as well as, The first switch is configured to operate with the duty cycle, and the fourth switch is configured to operate with the sum of the duty cycle and the duty cycle variation Δton; The trial-and-error-based control method is used as a local control loop, and the trial-and-error-based control method includes: A parameter indicating the direction of trial and error, the parameter depending on the voltage Vi_mid; A predetermined duration; and The duty cycle change Δton is determined based on the parameter, the duty cycle change Δton before a predetermined duration and one or more switching cycles.

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