Memory control method, device, storage medium and electronic device

Abstract

The embodiments of the present application provide a memory control method, device, storage medium and electronic device. The present application obtains the number of cache misses of the cache in the processor within a unit time length, utilizes the characteristic of obtaining data from the memory when the processor cache misses, and further obtains the target bandwidth required by the memory based on the number of cache misses. The target bandwidth reflects the actual data volume required by the processor to access the memory, so that the bandwidth of the memory is adjusted to the target bandwidth to meet the processor's access requirements to the memory. Compared with the related art, the present application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth requirements for the memory, and thus adjusts the bandwidth of the memory in real time according to the actual bandwidth requirements, so as to meet the usage requirements for memory access performance. At the same time, since the bandwidth after the memory adjustment matches the actual bandwidth requirement, there is no waste of bandwidth, and the waste of power consumption can also be avoided.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a memory control method, device, storage medium, and electronic device. Background Art

[0002] Memory, also known as internal or main memory, temporarily stores processor data and data exchanged with external memory. Electronic devices such as smartphones and tablets typically have memory, and all applications deployed on these devices run in memory. Therefore, the processor frequently accesses memory. The processor's memory access performance depends on the available memory bandwidth. Higher bandwidth results in higher access performance, but also higher power consumption. Summary of the Invention

[0003] The embodiments of the present application provide a memory control method, device, storage medium and electronic device, which can not only meet the usage requirements of memory access performance but also avoid waste of power consumption.

[0004] This application discloses a memory control method, comprising:

[0005] Get the number of cache misses in the processor's cache per unit time;

[0006] Obtaining a target bandwidth required to be provided by the memory according to the number of cache misses;

[0007] The bandwidth of the memory is adjusted to the target bandwidth.

[0008] The present application also discloses a memory control device, comprising:

[0009] A quantity acquisition module is used to obtain the number of cache misses in the processor's high-speed cache within a unit time;

[0010] A bandwidth acquisition module, configured to acquire a target bandwidth required by the memory according to the number of cache misses;

[0011] The bandwidth adjustment module is configured to adjust the bandwidth of the memory to the target bandwidth.

[0012] The present application also discloses a storage medium on which a computer program is stored. When the computer program is loaded by a processor, the memory control method provided by the present application is executed.

[0013] The present application also discloses an electronic device, including a processor, a memory and a storage, wherein the memory stores a computer program, and the processor executes the memory control method provided in the present application by loading the computer program.

[0014] In an embodiment of the present application, by obtaining the number of cache misses in the high-speed cache of the processor within a unit time length, and utilizing the characteristic of obtaining data from the memory when the processor cache misses, the target bandwidth required by the memory is further obtained based on the number of cache misses. The target bandwidth reflects the actual data volume required by the processor to access the memory, so that the memory bandwidth is adjusted to the target bandwidth to meet the processor's memory access requirements. Compared with related technologies, the present application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth requirements for the memory, and thus adjusts the memory bandwidth in real time according to the actual bandwidth requirements, so as to meet the usage requirements for memory access performance. At the same time, since the adjusted bandwidth of the memory matches the actual bandwidth requirements, there is no waste of bandwidth, and it can also avoid waste of power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments.

[0016] Figure 1 A flowchart of the memory control method provided in this application.

[0017] Figure 2 This is a schematic diagram of a processor accessing memory in an embodiment of the present application.

[0018] Figure 3 This is another schematic diagram of a processor accessing a memory in an embodiment of the present application.

[0019] Figure 4 This is another flowchart of the memory control method provided by this application.

[0020] Figure 5 This is a structural diagram of the memory control device provided in this application.

[0021] Figure 6 This is a schematic diagram of the structure of the electronic device provided in this application. DETAILED DESCRIPTION

[0022] The technical solutions provided in the embodiments of the present application can be applied to various scenarios requiring data communication, and the embodiments of the present application are not limited thereto.

[0023] Please refer to Figure 1The present application provides a memory control method, a memory control device, a storage medium, and an electronic device. The memory control method may be executed by the memory control device provided in the embodiments of the present application, or by an electronic device incorporating the memory control device. The memory control device may be implemented in hardware or software. The electronic device may be a mobile electronic device such as a smartphone, tablet computer, PDA, or laptop computer, or a stationary electronic device such as a desktop computer or an advertising machine.

[0024] Please refer to Figure 1 , Figure 1 This is a flow chart of the memory control method provided in the embodiment of the present application. The specific flow of the memory control method provided in the embodiment of the present application can be as follows:

[0025] In 110 , the number of cache misses in a high-speed cache in a processor within a unit time is obtained.

[0026] It should be noted that please refer to Figure 2 Processors are typically equipped with cache memory, or high-speed cache memory, to better exploit the principle of locality (both temporal and spatial locality). This means that data in memory recently accessed by the processor will be accessed again in the near future (temporal locality), and data near the data being accessed by the processor will also be accessed again in the near future (spatial locality). Therefore, if the processor caches recently accessed data in the cache, the next time it accesses it, it can retrieve it directly from the cache, without having to retrieve it from memory. This can increase the processor's access speed by orders of magnitude.

[0027] Based on the above description, when the data to be accessed by the processor is cached in the cache, it is called a "hit", and when the data to be accessed by the processor is not cached in the cache, it is called a "miss". Based on this, in this application, the number of cache misses in the cache of the processor within a unit time length (the unit time length can be taken by ordinary technicians in this field according to actual needs, for example, the unit time length can be configured as 1 second) is first obtained, that is, the number of times the processor accesses data in the cache when the processor accesses the data within the unit time length. For example, within a unit time length of 1 second, the processor accesses the cache 10,000 times, of which the data accessed 5,000 times is cached in the cache, and the data accessed for the other 5,000 times is not cached in the cache and needs to be read from the memory. Therefore, the number of cache misses in the cache can be obtained as 5,000.

[0028] In 120 , a target bandwidth required to be provided by the memory is obtained according to the number of cache misses.

[0029] As mentioned above, it's understandable that for data missing from the cache, the processor must retrieve it from memory. Whether the processor can reliably retrieve the required data from memory depends on whether the memory can provide sufficient bandwidth. For example, if the processor needs 512Mb of data from memory per second, the memory must provide at least 512Mb / s of bandwidth for stable access.

[0030] As can be seen from the above, the number of cache misses per unit time is positively correlated with the required memory bandwidth. That is, the greater the number of cache misses, the greater the required memory bandwidth, while the smaller the number of cache misses, the smaller the required memory bandwidth. Therefore, the required memory bandwidth can be calculated based on the number of cache misses per unit time, and the bandwidth required for processor memory access is recorded as the target bandwidth.

[0031] In 130 , the bandwidth of the memory is adjusted to the target bandwidth.

[0032] Based on the above description, it can be understood that the target bandwidth provided by the memory can provide stable access to the processor. In other words, when the bandwidth provided by the memory is less than the target bandwidth, the memory cannot ensure stable access to the processor, and when the bandwidth provided by the memory is greater than the target bandwidth, the bandwidth provided by the memory will be wasted. Therefore, in the embodiment of the present application, after obtaining the target bandwidth required for the processor to access the memory based on the number of cache misses in the cache per unit time, the bandwidth of the memory can be adjusted to the aforementioned target bandwidth, thereby ensuring stable access to the memory by the processor without wasting bandwidth.

[0033] As can be seen from the above, this application obtains the number of cache misses in the high-speed cache in the processor within a unit time, and uses the characteristics of the processor obtaining data from the memory when the cache is missed, and further obtains the target bandwidth required by the memory based on the number of cache misses. The target bandwidth reflects the actual data volume required by the processor to access the memory, so that the memory bandwidth is adjusted to the target bandwidth to meet the processor's memory access requirements. Compared with related technologies, this application does not select from several fixed bandwidth widths, but analyzes the actual bandwidth requirements for the memory, and thus adjusts the memory bandwidth in real time according to the actual bandwidth requirements, so as to meet the usage requirements for memory access performance. At the same time, since the adjusted bandwidth of the memory matches the actual bandwidth requirements, there is no waste of bandwidth, and it can also avoid waste of power consumption.

[0034] Optionally, in one embodiment, when the processor includes a performance monitoring unit, obtaining the number of cache misses in a high-speed cache in the processor within a unit time includes:

[0035] The number of cache misses of a high-speed cache in a processor per unit time is obtained from a performance monitoring unit.

[0036] It should be noted that for some types of processors, a performance monitoring unit is provided. The performance monitoring unit is a hardware module for recording processor access information, such as Figure 3 For example, an ARM architecture processor is usually equipped with a performance monitoring unit to record the amount of data in the cache accessed by the processor within a unit of time, as well as the amount of data not in the cache accessed.

[0037] Therefore, in the embodiment of the present application, when the processor includes a performance monitoring unit, the number of cache misses in the processor's cache within a unit time period can be directly obtained from the performance monitoring unit.

[0038] Optionally, in one embodiment, when the processor does not include a performance monitoring unit, obtaining the number of cache misses in a high-speed cache in the processor within a unit time includes:

[0039] (1) Obtaining the access delay of the processor to the target data within a unit time, and obtaining multiple access delays;

[0040] (2) Predicting the number of cache misses per unit time in a processor's cache based on multiple access delays.

[0041] It should be noted that memory is hierarchical. The closer the memory is to the processor, the faster the access speed, the higher the cost per byte, and the smaller the capacity. Registers are closest to the CPU and have the fastest access speed, followed by cache (caches are also hierarchical, such as level 1 cache, level 2 cache, level 3 cache, etc.), and then main memory (i.e., main memory). Typically, the processor's access latency to the level 1 cache is 5-10 nanoseconds, the processor's access latency to the level 2 cache is 40-60 nanoseconds, and the processor's access latency to main memory is 100-150 nanoseconds. Therefore, the access latency required for the processor to access data can be used to roughly determine whether the processor is accessing main memory or cache, and thus predict the number of cache misses.

[0042] Among them, when the processor does not include a performance monitoring unit, it is impossible to directly obtain the number of cache misses of the cache in a unit time from the performance monitoring unit. Therefore, in an embodiment of the present application, the access delay spent by the processor when accessing the target data is recorded, wherein the target data accessed by the processor each time can be the same or different. Accordingly, when obtaining the number of cache misses of the cache in the processor in a unit time, the access delay of the processor accessing the target data recorded in the unit time can be obtained, and multiple access delays can be obtained. For example, within a unit time of 1 second, the access delay of the processor to the target data is recorded 10,000 times, and accordingly, 10,000 access delays will be obtained.

[0043] Based on the above description, the length of access latency can, to a certain extent, reflect whether the target data accessed by the processor is located in the cache or in the memory. Therefore, the embodiment of the present application presets a configuration for a latency threshold for determining whether the target data is located in the cache or in the memory, which is recorded as the preset latency threshold. It can be configured by ordinary technicians in this field based on the actual read and write performance of the cache and the memory. No specific restriction is imposed on the value of the preset latency threshold.

[0044] Accordingly, after obtaining multiple access delays recorded within a unit duration, the number of access delays greater than or equal to a preset delay threshold among the multiple access delays can be further determined, and this number can be set as the number of cache misses within the unit duration. For example, if a total of 10,000 access delays are obtained within a unit duration, and 2,000 of these access delays are greater than or equal to the preset delay threshold, the number of cache misses within the unit duration can be determined to be 2,000.

[0045] Optionally, in one embodiment, adjusting the memory bandwidth to the target bandwidth includes:

[0046] (1) According to the corresponding relationship between bandwidth and clock frequency, the target clock frequency required for the memory to provide the target bandwidth is obtained;

[0047] (2) The clock frequency of the memory is adjusted to the target clock frequency, so as to adjust the bandwidth of the memory to the target bandwidth.

[0048] It should be noted that the bandwidth that the memory can provide and its clock frequency have the following corresponding relationship:

[0049] Bandwidth = clock frequency × number of bus bits × multiplication factor / 8;

[0050] Taking DDR400 memory as an example, its operating frequency is 200MHz and the bus bit number is 64 bits. Since data is transmitted on both the rising edge and the falling edge, the multiplication factor is 2. At this time, the bandwidth is: 200×64×2 / 8=3.2GB / s.

[0051] The number of bus bits and the multiplication factor of the memory are fixed. Once the memory hardware circuit is determined, the number of bus bits and the multiplication factor are determined accordingly. In other words, by changing the clock frequency of the memory, the bandwidth provided by the memory can be changed.

[0052] Accordingly, in the embodiment of the present application, when adjusting the memory bandwidth to the target bandwidth, the clock frequency corresponding to the target bandwidth can be obtained based on the above-mentioned correspondence between bandwidth and clock frequency, and recorded as the target bandwidth required to provide the target bandwidth to the memory. Thereafter, the memory operating clock frequency is adjusted to the target clock frequency, thereby adjusting the bandwidth provided by the memory to the target bandwidth.

[0053] Optionally, in one embodiment, after adjusting the clock frequency of the memory to the target clock frequency, the method further includes:

[0054] According to the preset correspondence between the clock frequency and the operating voltage, the operating voltage of the memory is adjusted to a target operating voltage corresponding to the target clock frequency.

[0055] It should be noted that whether the memory can operate stably at a clock frequency depends on whether a corresponding operating voltage is provided to the memory, which is related to the hardware circuit of the memory itself.

[0056] Therefore, for a memory, the operating voltage required for the memory to operate stably at different clock frequencies can be pre-calibrated, thereby obtaining a corresponding relationship between the preset clock frequency and the operating voltage.

[0057] In the embodiment of the present application, to ensure that the memory can stably operate at the adjusted target bandwidth, an operating voltage corresponding to the aforementioned target clock frequency is determined based on the preset correspondence between clock frequency and operating voltage, and is recorded as the target voltage. Then, the operating voltage of the memory is adjusted to the target operating voltage corresponding to the target clock frequency.

[0058] Optionally, in one embodiment, obtaining a target bandwidth required to be provided by the memory according to the number of cache misses includes:

[0059] (1) Obtaining the data bandwidth required for the processor to access the memory per unit time based on the number of cache misses and the amount of data in the cache line of the cache;

[0060] (2) obtaining the cleaning bandwidth required by the cache to perform the cleaning operation within a unit time;

[0061] (3) Obtain the aforementioned target bandwidth based on the data bandwidth and the clearing bandwidth.

[0062] The cleaning operation refers to forcibly writing dirty (ie, overwritten) cache line data in the cache to the memory and clearing the dirty bit in the cache line to zero.

[0063] Accordingly, in the embodiment of the present application, when obtaining the target bandwidth required for memory access based on the number of cache misses, the bandwidth required for accessing the memory per unit time can be obtained based on the number of cache misses and the amount of data in the cache lines of the cache, and is recorded as the data bandwidth. It should be noted that each time the processor reads data from the memory, it obtains the data based on the amount of data in the cache lines.

[0064] For example, the amount of data in each cache line of the cache is 32 bytes. If the number of cache misses in the cache per unit time of 1 second is 5000, then the amount of data accessed by the processor to the memory per unit time of 1 second is 5000*32=160000 (bytes). Accordingly, the data bandwidth required for the processor to access the memory per unit time of 1 second is 160000 bytes / second.

[0065] As mentioned above, in addition to the bandwidth required for the processor's normal access to the memory, when performing a cleanup operation on the cache, the corresponding data in the cache needs to be written to the memory, which will write to the memory and occupy the memory bandwidth. Therefore, the cleanup bandwidth required for the cache unit to perform the cleanup operation within a unit time is also obtained.

[0066] After obtaining the above data bandwidth and cleaning bandwidth, the target bandwidth required for the memory can be obtained based on the above data bandwidth and cleaning bandwidth. For example, the bandwidth sum of the above data bandwidth and cleaning bandwidth can be directly calculated as the target bandwidth required for the memory.

[0067] Optionally, in one embodiment, obtaining the target bandwidth according to the data bandwidth, the first operation bandwidth, and the second operation bandwidth includes:

[0068] (1) Calculate the sum of data bandwidth and cleaning bandwidth and set it as candidate bandwidth;

[0069] (2) obtaining an application type of a foreground application running on the processor, and determining a target correction coefficient corresponding to the aforementioned application type based on a preset correspondence between the application type and the correction coefficient;

[0070] (3) Correct the candidate bandwidth according to the target correction coefficient, and set the corrected candidate bandwidth as the target bandwidth.

[0071] It should be noted that when a processor runs different types of applications, the degree of change in the processor's memory bandwidth requirements varies. For example, when the processor runs a Class A application, the degree of change in the processor's memory bandwidth requirements is small, while when the processor runs a Class B application, the degree of change in the processor's memory bandwidth requirements is large. Based on this, this application pre-computes statistics on the degree of change in the memory bandwidth requirements when the processor runs different types of applications and allocates correction coefficients accordingly. With the constraint that the correction coefficient is positively correlated with the degree of change, a person of ordinary skill in the art can allocate the correction coefficient according to actual needs, thereby forming a corresponding relationship between application type and correction coefficient.

[0072] Accordingly, when obtaining the target bandwidth required by the memory based on the data bandwidth and the cleanup bandwidth, the sum of the aforementioned data bandwidth and the aforementioned bandwidth can be first calculated, and the calculated sum can be recorded as the candidate bandwidth required by the memory. Then, the application type of the foreground application running on the processor is further obtained, and based on the preset application type and correction coefficient, a correction coefficient corresponding to the application type of the foreground application is determined, which is recorded as the target correction coefficient. Finally, the candidate bandwidth is corrected according to the target correction coefficient, which can be expressed as:

[0073] W'=W*r;

[0074] Wherein, W represents the candidate bandwidth, W' represents the corrected candidate bandwidth, and r represents the target correction coefficient.

[0075] As described above, after the candidate bandwidth is modified, the modified candidate bandwidth is set as the target bandwidth required to be provided by the memory.

[0076] Figure 4 Another flow chart of the memory control method provided in the embodiment of the present application. The following description is made by taking the execution subject of the memory control method as a processor in an electronic device as an example. Figure 4 As shown, the process of the memory control method provided in the embodiment of the present application can be as follows:

[0077] In 210 , the processor obtains the number of cache misses in a unit time from the performance monitoring unit.

[0078] It should be noted that please refer to Figure 3Processors are typically equipped with cache memory, or high-speed cache memory, to better exploit the principle of locality (both temporal and spatial locality). This means that data in memory recently accessed by the processor will be accessed again in the near future (temporal locality), and data near the data being accessed by the processor will also be accessed again in the near future (spatial locality). Therefore, if the processor caches recently accessed data in the cache, the next time it accesses it, it can retrieve it directly from the cache, without having to retrieve it from memory. This can increase the processor's access speed by orders of magnitude.

[0079] Based on the above description, when the data to be accessed by the processor is cached in the cache, it is called a "hit", and when the data to be accessed by the processor is not cached in the cache, it is called a "miss". Based on this, in this application, the number of cache misses in the cache of the processor within a unit time length (the unit time length can be taken by ordinary technicians in this field according to actual needs, for example, the unit time length can be configured as 1 second) is first obtained, that is, the number of times the processor accesses data in the cache when the processor accesses the data within the unit time length. For example, within a unit time length of 1 second, the processor accesses the cache 10,000 times, of which the data accessed 5,000 times is cached in the cache, and the data accessed for the other 5,000 times is not cached in the cache and needs to be read from the memory. Therefore, the number of cache misses in the cache can be obtained as 5,000.

[0080] It should be noted that for some types of processors, a performance monitoring unit is provided. The performance monitoring unit is a hardware module for recording processor access information, such as Figure 3 For example, an ARM architecture processor is usually equipped with a performance monitoring unit to record the amount of data in the cache accessed by the processor within a unit of time, as well as the amount of data not in the cache accessed.

[0081] Therefore, in the embodiment of the present application, when the processor includes a performance monitoring unit, the number of cache misses in the processor's cache within a unit time period can be directly obtained from the performance monitoring unit.

[0082] In 220 , the processor obtains the data bandwidth required for the processor to access the memory within a unit time according to the number of cache misses and the amount of data in the cache line of the cache.

[0083] As mentioned above, it's understandable that for data missing from the cache, the processor must retrieve it from memory. Whether the processor can reliably retrieve the required data from memory depends on whether the memory can provide sufficient bandwidth. For example, if the processor needs 512Mb of data from memory per second, the memory must provide at least 512Mb / s of bandwidth for stable access.

[0084] As can be seen from the above, the number of cache misses per unit time is positively correlated with the bandwidth required by the memory. That is, the greater the number of cache misses, the greater the bandwidth required by the memory. When the number of cache misses is smaller, the bandwidth required by the memory is smaller.

[0085] It should be noted that in addition to normal access operations occupying memory bandwidth, cache cleanup operations also occupy memory bandwidth. Therefore, in the embodiment of the present application, the target bandwidth required by the processor is determined based on the processor's access operations and cache cleanup operations.

[0086] Accordingly, in the embodiment of the present application, when obtaining the target bandwidth required for memory access based on the number of cache misses, the bandwidth required for accessing the memory per unit time can be obtained based on the number of cache misses and the amount of data in the cache lines of the cache, and is recorded as the data bandwidth. It should be noted that each time the processor reads data from the memory, it obtains the data based on the amount of data in the cache lines.

[0087] For example, the amount of data in each cache line of the cache is 32 bytes. If the number of cache misses in the cache per unit time of 1 second is 5000, then the amount of data accessed by the processor to the memory per unit time of 1 second is 5000*32=160000 (bytes). Accordingly, the data bandwidth required for the processor to access the memory per unit time of 1 second is 160000 bytes / second.

[0088] In 230 , the processor obtains the cleaning bandwidth required by the cache to perform a cleaning operation within a unit time.

[0089] As described above, in addition to the bandwidth required for normal processor access to the memory, the memory bandwidth is also occupied when performing a cleanup operation on the cache. Therefore, the cleanup bandwidth required for the cache unit to perform the cleanup operation within a unit time is also obtained.

[0090] In 240 , the processor calculates the sum of the data bandwidth and the cleanup bandwidth, and sets the sum as the candidate bandwidth.

[0091] It should be noted that when a processor runs different types of applications, the degree of change in the processor's memory bandwidth requirements varies. For example, when the processor runs a Class A application, the degree of change in the processor's memory bandwidth requirements is small, while when the processor runs a Class B application, the degree of change in the processor's memory bandwidth requirements is large. Based on this, this application pre-computes statistics on the degree of change in the memory bandwidth requirements when the processor runs different types of applications and allocates correction coefficients accordingly. With the constraint that the correction coefficient is positively correlated with the degree of change, a person of ordinary skill in the art can allocate the correction coefficient according to actual needs, thereby forming a corresponding relationship between application type and correction coefficient.

[0092] Accordingly, the sum of the aforementioned data bandwidth and the aforementioned bandwidth may be calculated first, and the calculated sum may be recorded as the candidate bandwidth required to be provided by the memory.

[0093] In 250 , the processor obtains the application type of the foreground application running on the processor, and determines a target correction coefficient corresponding to the application type according to a preset correspondence between the application type and the correction coefficient.

[0094] The processor further obtains the application type of the foreground application running on the processor, and determines a correction coefficient corresponding to the application type of the foreground application based on the preset application type and correction coefficient, which is recorded as a target correction coefficient.

[0095] In 260 , the processor modifies the candidate bandwidth according to the target modification coefficient and sets the modified candidate bandwidth as the target bandwidth.

[0096] The candidate bandwidth is corrected according to the target correction coefficient, which can be expressed as:

[0097] W'=W*r;

[0098] Wherein, W represents the candidate bandwidth, W' represents the corrected candidate bandwidth, and r represents the target correction coefficient.

[0099] As described above, after the candidate bandwidth is modified, the modified candidate bandwidth is set as the target bandwidth required to be provided by the memory.

[0100] In 270 , the processor obtains the target clock frequency required for the memory to provide the target bandwidth according to the correspondence between the bandwidth and the clock frequency, and adjusts the clock frequency of the memory to the target clock frequency, so as to adjust the bandwidth of the memory to the target bandwidth.

[0101] It should be noted that the bandwidth that the memory can provide and its clock frequency have the following corresponding relationship:

[0102] Bandwidth = clock frequency × number of bus bits × multiplication factor / 8;

[0103] Taking DDR400 memory as an example, its operating frequency is 200MHz and the bus bit number is 64 bits. Since data is transmitted on both the rising edge and the falling edge, the multiplication factor is 2. At this time, the bandwidth is: 200×64×2 / 8=3.2GB / s.

[0104] The number of bus bits and the multiplication factor of the memory are fixed. Once the memory hardware circuit is determined, the number of bus bits and the multiplication factor are determined accordingly. In other words, by changing the clock frequency of the memory, the bandwidth provided by the memory can be changed.

[0105] Accordingly, in the embodiment of the present application, when adjusting the memory bandwidth to the target bandwidth, the clock frequency corresponding to the target bandwidth can be obtained based on the above-mentioned correspondence between bandwidth and clock frequency, and recorded as the target bandwidth required to provide the target bandwidth to the memory. Thereafter, the memory operating clock frequency is adjusted to the target clock frequency, thereby adjusting the bandwidth provided by the memory to the target bandwidth.

[0106] In 280 , the processor adjusts the operating voltage of the memory to a target operating voltage corresponding to the target clock frequency according to a preset correspondence between the clock frequency and the operating voltage.

[0107] It should be noted that whether the memory can operate stably at a clock frequency depends on whether a corresponding operating voltage is provided to the memory, which is related to the hardware circuit of the memory itself.

[0108] Therefore, for a memory, the operating voltage required for the memory to operate stably at different clock frequencies can be pre-calibrated, thereby obtaining a corresponding relationship between the preset clock frequency and the operating voltage.

[0109] In the embodiment of the present application, to ensure that the memory can stably operate at the adjusted target bandwidth, an operating voltage corresponding to the aforementioned target clock frequency is determined based on the preset correspondence between clock frequency and operating voltage, and is recorded as the target voltage. Then, the operating voltage of the memory is adjusted to the target operating voltage corresponding to the target clock frequency.

[0110] Please refer to Figure 5 , Figure 5 This is a schematic diagram of the structure of the memory control device provided in the embodiment of the present application. The memory control device is applied to the electronic device provided in the present application. Figure 5 As shown, the memory control device may include:

[0111] A number acquisition module 310 is used to obtain the number of cache misses in the high-speed cache of the processor within a unit time length;

[0112] The bandwidth acquisition module 320 is used to obtain the target bandwidth required by the memory according to the number of cache misses;

[0113] The bandwidth adjustment module 330 is configured to adjust the memory bandwidth to a target bandwidth.

[0114] Optionally, in one embodiment, if the processor includes a performance monitoring unit, when obtaining the number of cache misses in the processor's cache within a unit time, the number obtaining module 310 is configured to:

[0115] Gets the number of cache misses from the performance monitoring unit.

[0116] Optionally, in one embodiment, if the processor does not include a performance monitoring unit, when obtaining the number of cache misses in the processor's cache within a unit time, the number obtaining module 310 is configured to:

[0117] Obtaining the access latency of the processor to the target data within a unit time, and obtaining multiple access latency;

[0118] Predict the number of cache misses based on multiple access latencies.

[0119] Optionally, in one embodiment, when adjusting the memory bandwidth to the target bandwidth, the bandwidth adjustment module 330 is configured to:

[0120] According to the correspondence between bandwidth and clock frequency, the target clock frequency required for the memory to provide the target bandwidth is obtained;

[0121] The clock frequency of the memory is adjusted to the target clock frequency, so as to adjust the bandwidth of the memory to the target bandwidth.

[0122] Optionally, in one embodiment, after adjusting the clock frequency of the memory to the target clock frequency, the bandwidth adjustment module 330 is further configured to:

[0123] According to the preset correspondence between the clock frequency and the operating voltage, the operating voltage of the memory is adjusted to a target operating voltage corresponding to the target clock frequency.

[0124] Optionally, in one embodiment, when obtaining the target bandwidth required to be provided by the memory according to the number of cache misses, the bandwidth obtaining module 320 is configured to:

[0125] Obtain the data bandwidth required for the processor to access the memory per unit time based on the number of cache misses and the amount of data in the cache line of the cache;

[0126] Get the cleaning bandwidth required by the cache to perform cleaning operations per unit time;

[0127] Obtain the target bandwidth based on the data bandwidth and cleanup bandwidth.

[0128] Optionally, in one embodiment, when acquiring the target bandwidth according to the data bandwidth and the clearing bandwidth, the bandwidth acquisition module 320 is configured to:

[0129] Calculate the sum of data bandwidth and cleanup bandwidth and set it as candidate bandwidth;

[0130] Obtaining the application type of the foreground application running on the processor, and determining a target correction coefficient corresponding to the application type based on a preset correspondence between the application type and the correction coefficient;

[0131] The candidate bandwidth is corrected according to the target correction coefficient, and the corrected candidate bandwidth is set as the target bandwidth.

[0132] It should be noted that the memory control device provided in the embodiment of the present application belongs to the same concept as the memory control method in the above embodiment. The memory control device can run any method provided in the memory control method embodiment. The specific implementation process is detailed in the above related embodiments and will not be repeated here.

[0133] The present invention also provides a storage medium having a computer program stored thereon. When the computer program is loaded by a processor of an electronic device, the steps of the memory control method provided in the present invention are executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0134] The present application also provides an electronic device. Figure 6 , the electronic device includes a processor 410 and a memory 420.

[0135] The processor in the embodiment of the present application is a general-purpose processor 410, such as an ARM architecture processor.

[0136] The memory 420 stores computer programs, which may be a high-speed random access memory or a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0137] The memory 430 may be any type of memory (also called main memory), such as DDR (Double Data Rate) memory.

[0138] In addition, the memory 420 may further include a memory controller to provide the processor 410 with access to the memory 420. The processor 410 implements the following functions by loading the computer program in the memory 420:

[0139] Get the number of cache misses in the processor's cache per unit time;

[0140] Obtaining a target bandwidth that the memory 430 needs to provide based on the number of cache misses;

[0141] The bandwidth of the memory 430 is adjusted to the target bandwidth.

[0142] Optionally, in one embodiment, if the processor includes a performance monitoring unit, when obtaining the number of cache misses in the high-speed cache in the processor within a unit time, the processor 410 is configured to execute:

[0143] Gets the number of cache misses from the performance monitoring unit.

[0144] Optionally, in one embodiment, if the processor does not include a performance monitoring unit, when obtaining the number of cache misses of a cache in the processor within a unit time, the processor 410 is configured to execute:

[0145] Obtaining the access latency of the processor to the target data within a unit time, and obtaining multiple access latency;

[0146] Predict the number of cache misses based on multiple access latencies.

[0147] Optionally, in one embodiment, when adjusting the bandwidth of the memory 430 to the target bandwidth, the processor 410 is configured to execute:

[0148] According to the correspondence between bandwidth and clock frequency, the target clock frequency required for the memory 430 to provide the target bandwidth is obtained;

[0149] The clock frequency of the memory 430 is adjusted to the target clock frequency, so as to adjust the bandwidth of the memory 430 to the target bandwidth.

[0150] Optionally, in one embodiment, after adjusting the clock frequency of the memory 430 to the target clock frequency, the processor 410 is further configured to execute:

[0151] According to the preset correspondence between the clock frequency and the operating voltage, the operating voltage of the memory 430 is adjusted to a target operating voltage corresponding to the target clock frequency.

[0152] Optionally, in one embodiment, when obtaining the target bandwidth required to be provided by the memory 430 according to the number of cache misses, the processor 410 is configured to execute:

[0153] Obtaining a data bandwidth required for the processor to access the memory 430 within a unit time according to the number of cache misses and the amount of data in the cache line of the cache;

[0154] Get the cleaning bandwidth required by the cache to perform cleaning operations per unit time;

[0155] Obtain the target bandwidth based on the data bandwidth and cleanup bandwidth.

[0156] Optionally, in one embodiment, when obtaining the target bandwidth according to the data bandwidth and the clearing bandwidth, the processor 410 is configured to execute:

[0157] Calculate the sum of data bandwidth and cleanup bandwidth and set it as candidate bandwidth;

[0158] Obtaining the application type of the foreground application running on the processor, and determining a target correction coefficient corresponding to the application type based on a preset correspondence between the application type and the correction coefficient;

[0159] The candidate bandwidth is corrected according to the target correction coefficient, and the corrected candidate bandwidth is set as the target bandwidth.

[0160] It should be noted that the electronic device provided in the embodiment of the present application and the memory control method in the above embodiment belong to the same concept. Any method provided in the memory control method embodiment can be run on the electronic device. The specific implementation process is detailed in the above embodiment and will not be repeated here.

[0161] The above is a detailed introduction to a memory control method, storage medium and electronic device provided in the embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A memory control method, characterized in that: The memory control method comprises: Get the number of cache misses in the processor's cache per unit time; Obtaining a data bandwidth required for the processor to access a memory within a unit time period according to the number of cache misses and the amount of data in the cache line of the cache; Obtaining a cleaning bandwidth required by the cache to write dirty cache line data to the memory within a unit time; Obtaining a target bandwidth required to be provided by the memory according to the data bandwidth and the cleanup bandwidth; The bandwidth of the memory is adjusted to the target bandwidth.

2. The memory control method according to claim 1, wherein: When the processor includes a performance monitoring unit, obtaining the number of cache misses in a high-speed cache in the processor within a unit time includes: The cache miss count is obtained from the performance monitoring unit.

3. The memory control method according to claim 1, wherein: When the processor does not include a performance monitoring unit, obtaining the number of cache misses of a cache in the processor within a unit time includes: Obtaining access delays of the processor accessing target data within a unit time length to obtain multiple access delays; The cache miss quantity is predicted based on the multiple access delays.

4. The memory control method according to claim 1, wherein: The adjusting the bandwidth of the memory to the target bandwidth includes: According to the corresponding relationship between bandwidth and clock frequency, obtaining the target clock frequency required for the memory to provide the target bandwidth; The clock frequency of the memory is adjusted to the target clock frequency, so as to adjust the bandwidth of the memory to the target bandwidth.

5. The memory control method according to claim 4, wherein: After adjusting the clock frequency of the memory to the target clock frequency, the method further includes: According to a preset correspondence between a clock frequency and an operating voltage, the operating voltage of the memory is adjusted to a target operating voltage corresponding to the target clock frequency.

6. The memory control method according to claim 1, wherein: The acquiring the target bandwidth according to the data bandwidth and the clearing bandwidth includes: Calculating a sum of the data bandwidth and the cleaning bandwidth, and setting the sum as a candidate bandwidth; Obtaining an application type of a foreground application running on the processor, and determining a target correction coefficient corresponding to the application type based on a preset correspondence between the application type and the correction coefficient; The candidate bandwidth is corrected according to the target correction coefficient, and the corrected candidate bandwidth is set as the target bandwidth.

7. A memory control device, characterized in that: The memory control device includes: A quantity acquisition module is used to obtain the number of cache misses in the processor's high-speed cache within a unit time; a bandwidth acquisition module, configured to acquire, based on the number of cache misses and the amount of data in the cache line of the cache, the data bandwidth required by the processor to access the memory within a unit time; acquire the cleanup bandwidth required by the cache to write dirty cache line data to the memory within a unit time; and acquire the target bandwidth required to be provided by the memory based on the data bandwidth and the cleanup bandwidth; The bandwidth adjustment module is configured to adjust the bandwidth of the memory to the target bandwidth.

8. A storage medium having a computer program stored thereon, characterized in that: When the computer program is loaded by a processor, the memory control method according to any one of claims 1 to 6 is executed.

9. An electronic device comprising a processor, a memory and a storage, wherein the memory stores a computer program, wherein: The processor executes the memory control method according to any one of claims 1 to 6 by loading the computer program.

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