Method of compensating for degradation of electroluminescent display devices and display system performing the method

Abstract

A method for compensating for degradation of an electroluminescent display device, an electroluminescent display device, and a display system are provided. The method can include grouping a plurality of pixels in a display panel into a plurality of pixel blocks arranged in a current block row and a current block column based on initial block boundaries, accumulating block stress values based on input image data, each accumulated block stress value representing a degree of degradation of pixels included in each pixel block of the plurality of pixel blocks, performing a boundary update operation on the plurality of pixel blocks, performing the boundary update operation including moving the current block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values, and correcting the input image data based on the accumulated block stress values and the updated block boundaries.

Description

[0001] Cross-applications related to technologies

[0002] This application claims priority to Korean Patent Application No. 10-2020-0145957, filed on November 4, 2020, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various example embodiments generally relate to semiconductor integrated circuits, and more specifically, to electroluminescent display devices, methods for compensating for degradation of electroluminescent display devices, and / or display systems for performing such methods. Background Technology

[0004] Compared to other types of displays, electroluminescent displays offer faster response times and lower power consumption. This improved performance is achieved, at least in part, through the use of pixels in light-emitting diodes (LEDs) or organic light-emitting diodes (OLEDs). For example, OLEDs emit light based on the recombination of electrons and holes in a light-emitting layer located between the anode and cathode. The light-emitting layer comprises materials that emit light based on a driving current flowing between the anode and cathode. The brightness of the light depends on the amount of driving current; for example, a higher driving current can produce a higher brightness of light in the displayed image.

[0005] In electroluminescent displays, pixels can become stressed and degraded due to factors such as the amount and / or level of the drive current. This degradation worsens over time as the stress caused by the drive current increases. Consequently, a decrease in brightness occurs in the electroluminescent display, which reduces its display quality. Summary of the Invention

[0006] Some example embodiments may provide a method, display device, and / or display system capable of effectively compensating for pixel degradation in an electroluminescent display device.

[0007] According to at least one example embodiment, a method for compensating for degradation of an electroluminescent display device includes: grouping a plurality of pixels in a display panel into a plurality of pixel blocks arranged in current block rows and current block columns based on initial block boundaries; accumulating block stress values ​​based on input image data, each accumulated block stress value representing the degree of degradation of a pixel in each of the plurality of pixel blocks; performing a boundary update operation on the plurality of pixel blocks, the boundary update operation including moving the current block boundaries of the plurality of pixel blocks to updated block boundaries based on the distribution of the accumulated block stress values; and correcting the input image data based on the accumulated block stress values ​​and the updated block boundaries.

[0008] According to at least one example embodiment, an electroluminescent display apparatus includes a display panel including a plurality of pixels, and at least one degradation compensation logic configured to group the plurality of pixels into a plurality of pixel blocks arranged in a current block row and a current block column based on an initial block boundary, accumulate a block stress value associated with each of the pixel blocks based on input image data, each accumulated block stress value representing a degree of degradation of pixels included in each of the pixel blocks of the plurality of pixel blocks, perform a boundary update operation on the plurality of pixel blocks, the performing of the boundary update operation including moving the current block boundary of the plurality of pixel blocks to an updated block boundary based on a distribution of the accumulated block stress values, and correct the input image data based on the accumulated block stress values and the updated block boundary.

[0009] According to at least one example embodiment, a display system includes a display panel including a plurality of pixels, a display controller, and a display driving integrated circuit. The display controller is configured to group all of the plurality of pixels into a plurality of first pixel blocks, and provide first accumulated block stress values based on input image data, each of the first accumulated block stress values representing a degree of degradation of pixels included in each of the plurality of first pixel blocks. The display driving integrated circuit is configured to group at least a portion of the plurality of pixels into a plurality of second pixel blocks, and provide second accumulated block stress values based on the input image data, each of the second accumulated block stress values representing a degree of degradation of pixels included in each of the plurality of second pixel blocks.

[0010] The method for compensating for degradation of an electroluminescent display apparatus, the electroluminescent display apparatus, and / or the display system according to one or more example embodiments can effectively compensate for degradation of pixels by reducing an amount of data of accumulated stress data through pixel grouping.

[0011] The method for compensating for degradation of an electroluminescent display apparatus, the electroluminescent display apparatus, and / or the display system according to one or more example embodiments can enhance a quality of a displayed image by updating a block boundary based on accumulated stress data to reflect and / or accurately reflect a state of degradation of pixels.

[0012] The method for compensating for degradation of an electroluminescent display apparatus, the electroluminescent display apparatus, and / or the display system according to one or more example embodiments can enhance accuracy of compensation by managing stress data by a display controller and a display driving integrated circuit, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0013] Various example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0014] FIG. 1is a flowchart illustrating a method for compensating for degradation of an electroluminescent display device, in accordance with some example embodiments.

[0015] FIG. 2 is a block diagram illustrating an electroluminescent display device, in accordance with some example embodiments.

[0016] FIG. 3 is a diagram illustrating a luminance drop that can occur as a result of accumulated stress of a pixel.

[0017] FIG. 4 is a diagram illustrating a compensation operation for compensating for pixel degradation, in accordance with some example embodiments.

[0018] FIG. 5 is a diagram illustrating an example of grouping pixels in a method for compensating for degradation of an electroluminescent display device, in accordance with some example embodiments.

[0019] FIG. 6 is a block diagram illustrating an example of degradation compensation logic included in an electroluminescent display device, in accordance with some example embodiments.

[0020] FIG. 7 is a diagram illustrating an example degradation pattern of a display panel, in accordance with some example embodiments, for describing a method for compensating for degradation of an electroluminescent display device.

[0021] FIG. 8 is a flowchart illustrating an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display device, in accordance with some example embodiments.

[0022] FIGS. 9A-11B is a diagram illustrating a boundary update operation for one block row in FIG. 8 , in accordance with some example embodiments. FIG. 7

[0023] FIGS. 12A-12E is a diagram illustrating a boundary update operation for all block rows in FIG. 7 , in accordance with some example embodiments.

[0024] FIG. 13 is a diagram illustrating updated block boundaries from a boundary update operation by FIGS. 12A-12E , in accordance with some example embodiments.

[0025] FIG. 14 and FIG. 15 is a diagram illustrating a boundary update operation for one block row in FIG. 8 , in accordance with some example embodiments. FIG. 7

[0026] FIG. 16 ​​is a diagram illustrating an update of a block boundary by a boundary update operation of FIG. 14 and FIG. 15 .

[0027] FIG. 17 is a flowchart illustrating an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display device according to some example embodiments.

[0028] FIG. 18 , FIG. 19 and FIG. 20 are diagrams for describing a boundary update operation of FIG. 17 according to some example embodiments.

[0029] FIG. 21 is a flowchart illustrating an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display device according to some example embodiments.

[0030] FIG. 22 , FIG. 23 and FIG. 24 are diagrams illustrating a boundary update operation of FIG. 21 for one block row in FIG. 7 according to some example embodiments.

[0031] FIG. 25 is a block diagram illustrating a display system according to some example embodiments.

[0032] FIG. 26 is a block diagram illustrating a display system according to some example embodiments.

[0033] FIG. 27 is a diagram illustrating a region compensation operation in a display system according to some example embodiments.

[0034] FIG. 28 is a diagram illustrating a data compensation operation in a display system according to some example embodiments.

[0035] FIG. 29 is a diagram illustrating a cumulative period compensation operation in a display system according to some example embodiments. DETAILED DESCRIPTION

[0036] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown. Like numerals refer to like elements throughout. The description of one or more example embodiments can be used to enable a person of ordinary skill in the art to practice one or more aspects of the present disclosure.

[0037] FIG. 1 is a flowchart illustrating a method of compensating for degradation of an electroluminescent display device according to some example embodiments.

[0038] Referring toFIG. 1 According to at least one example embodiment, in operation S100, a plurality of pixels in a display panel can be grouped into a plurality of pixel blocks arranged in block rows and block columns by dividing the plurality of pixels having initial block boundaries by a display driver (e.g., display driver 100, etc.) of the display panel, although example embodiments are not limited thereto. Some example embodiments of pixel grouping will be described with reference to FIGS. 2A and 2B. FIG. 2 FIG. 5 In operation S200, the display driver can accumulate (e.g., determine, calculate, etc.) block stress values based on image data to the display panel and / or provide block stress values associated with the image data to the display driver, although example embodiments are not limited thereto. Further, each accumulated block stress value can represent a degree of degradation (and / or an expected degree of degradation, a predicted degree of degradation, etc.) of pixels included in each pixel block (S200).

[0039] For example, block average values can be calculated by the display driver based on input image data for each frame, where each block average value represents an average gray scale value of pixels in each pixel block, although example embodiments are not limited thereto. Each block average value can be accumulated by the display driver for a plurality of frames to store and provide accumulated block stress values, although example embodiments are not limited thereto, e.g., block average values can be based on a single image frame, etc. Reducing the amount of data for stress values by grouping pixels can effectively compensate for degradation of pixels.

[0040] In operation S300, a boundary update operation can be performed by the display driver based on a distribution of the accumulated block stress values to move the current block boundaries of the plurality of pixel blocks to updated block boundaries.

[0041] In some example embodiments, the current block boundaries (e.g., current block boundaries, first block boundaries, etc.) can be moved by the display driver to the updated block boundaries (e.g., future block boundaries, next block boundaries, second block boundaries, etc.) such that the updated block boundaries are more concentrated in areas of the display panel where a difference in the degree of degradation of adjacent pixel blocks is greater than a desired and / or threshold degree of degradation value. In other words, the current block boundaries can be moved by the display driver to the updated block boundaries such that the updated block boundaries can be concentrated or compacted near a burn-in boundary that indicates a degradation pattern of the plurality of pixels, although example embodiments are not limited thereto. According to some example embodiments, the desired and / or threshold degree of degradation value can be a configuration setting set by a user and / or a display manufacturer, etc., and / or can be based on a comparison of an area of the display panel to other areas, etc. Some example embodiments of such a boundary update operation will be described below with reference to FIGS. 3A and 3B.

[0042] FIGS. 8-16

[0043] ​​​In some example embodiments, the current block boundary can be moved to the updated block boundary by the display driver such that the updated block boundary is more concentrated and / or changed in the area of the display panel where the degree of degradation is greater than the expected and / or threshold degree of degradation value. In other words, the current block boundary can be moved to the updated block boundary by the display driver such that the updated block boundary can be concentrated or compacted in the area of higher degree of degradation. Reference will be made to FIGS. 1-4 below to describe the operation of the display driver in moving the current block boundary to the updated block boundary. FIGS. 21-24 Some example embodiments describing such a boundary update operation.

[0044] In operation S400, the input image data can be corrected by the display driver based on the accumulated block stress value and the updated block boundary. The pixels in the display panel can be driven and / or operated by the display driver based on the corrected image data.

[0045] By grouping the pixels, the used memory capacity and / or the used data bandwidth can be reduced and / or decreased, but the values representing the pixel blocks cannot accurately reflect the degradation distribution of the pixels included in each pixel block. The block boundary between the pixel blocks can be visible and / or recognized by the user, and thus the quality and / or performance of the degradation compensation can be decreased. According to some example embodiments, by changing the block boundary such that the block boundary accurately and / or precisely reflects the true burn-in boundary and / or burn-in area, the degradation pattern can be accurately reflected and the quality of the displayed image can be enhanced.

[0046] FIG. 2 is a block diagram illustrating an electroluminescent display apparatus according to some example embodiments.

[0047] Referring to FIG. 2 , the electroluminescent display apparatus 30 can include a display panel 200 including a plurality of pixel rows 211 and / or a display driver 100 driving (e.g., operating) the display panel 200, etc., but example embodiments are not limited thereto, for example, the electroluminescent display apparatus 30 can include a greater or lesser number of constituent elements. In at least one example embodiment, the display driver 100 can include a data driver 130, a scan driver 140, a timing controller 150, a power supply (power supply unit) 160, and / or a gamma circuit 170, etc., but is not limited thereto.

[0048] The display panel 200 can be connected to the data driver 130 of the display driver 100 through a plurality of data lines, and can be connected to the scan driver 140 of the display driver 100 through a plurality of scan lines. The display panel 200 can include a pixel row 211, for example, a plurality of pixel rows, etc. That is, the display panel 200 can include a plurality of pixels PX arranged in a matrix having a plurality of rows and a plurality of columns. A row of pixels PX connected to the same scan line can be referred to as one pixel row 211. In some example embodiments, the display panel 200 can be a self-emissive display panel that emits light without using a backlight unit, but is not limited thereto. For example, the display panel 200 can be an organic light emitting diode (OLED) display panel, but is not limited thereto.

[0049] Each pixel PX in the display panel 200 can have various configurations according to a driving (e.g., operating) method of the display apparatus 30. For example, the electroluminescent display apparatus 30 can be driven and / or operated with an analog or digital driving (and / or operating) method. The analog driving method generates a gray scale using a variable voltage level corresponding to input data (e.g., image data input to the display apparatus 30), while the digital driving method generates a gray scale using a variable duration in which an LED emits light. The analog driving method is difficult to implement because it uses a driving integrated circuit (IC) that is complex to manufacture if the display is large and has a high resolution. On the other hand, the digital driving method can easily implement a high resolution through a simpler IC structure. As the size of the display panel becomes larger and / or the resolution of the display panel increases, the digital driving method can have more advantageous characteristics than the analog driving method. The method for compensating for degradation according to some example embodiments can be applied to both the analog driving method and the digital driving method.

[0050] The data driver 130 can apply a data signal to the display panel 200 through the data lines. The scan driver 140 can apply a scan signal to the display panel 200 through the scan lines.

[0051] The timing controller 150 can control the operation of the display apparatus 30. The timing controller 150 can provide a control signal to the data driver 130 and / or the scan driver 140 to control the operation of the display apparatus 30. The control signal can be desired and / or predetermined. In some example embodiments, the data driver 130, the scan driver 140, and the timing controller 150 can be implemented as one integrated circuit (IC). In other example embodiments, the data driver 130, the scan driver 140, and the timing controller 150 can be implemented as two or more integrated circuits. A driving module including at least the timing controller 150 and the data driver 130 can be referred to as a timing controller-embedded data driver (TED). According to some example embodiments, the display driver 100, the timing controller 150, and / or the driving module can be implemented as processing circuitry, or in other words, processing circuitry included in the display apparatus 30 can be capable of performing the functions of one or more of the data driver 130, the scan driver 140, and the timing controller 150, etc. The processing circuitry can include hardware such as a processor, a processor core, a logic circuit, a memory device, etc., a hardware / software combination such as at least one processor core executing software and / or executing any instruction set, or a combination thereof. For example, the processing circuitry can more specifically include, but is not limited to, a field-programmable gate array (FPGA), a programmable logic unit, an application-specific integrated circuit (ASIC), a system on chip (SoC), etc.

[0052] The timing controller 150 can receive input image data IMG and input control signals from, for example, the host apparatus 20. The input image data IMG can include red (R) image data, green (G) image data, and blue (B) image data, but example embodiments are not limited thereto. According to some example embodiments, the input image data IMG can include white image data, magenta image data, yellow image data, cyan image data, etc. The input control signals can include a main clock signal, a data enable signal, a horizontal synchronization signal, a vertical synchronization signal, etc., and are not limited thereto.

[0053] The power supply 160 can provide a high power voltage ELVDD and / or a low power voltage ELVSS, etc., to the display panel 200. In addition, the power supply 160 can supply a regulator voltage VREG to the gamma circuit 170. The gamma circuit 170 can generate a gamma reference voltage GRV based on the regulator voltage VREG.

[0054] A luminance compensation circuit (not shown) can generate a global current value indicative of a global current flowing through the display panel based on a plurality of input pixel values corresponding to a plurality of pixels, generate a global compensation value indicative of a global luminance deviation according to the global current value for each of the plurality of input pixel values, and / or generate a gamma compensation value indicative of a gamma distortion caused by compensating the input pixel values, but not limited thereto. In addition, the luminance compensation circuit can generate a compensated pixel value based on the input pixel value, the global compensation value, and / or the gamma compensation value, etc.

[0055] The timing controller 150 can include a degradation compensation logic DCB (e.g., a DCB logic circuit, a DCB processing circuit, etc.) configured to perform the method for compensating for degradation of the electroluminescent display apparatus 30 described with reference to FIG. 1 FIG. 1. Some example embodiments of the degradation compensation logic DCB will be described below with reference to FIG. 6 In some example embodiments, the degradation compensation logic DCB can be implemented as a different component from the timing controller 150, but example embodiments are not limited thereto.

[0056] FIG. 3 FIG. 1 is a graph illustrating a luminance drop that can occur as a result of a cumulative stress of a pixel, FIG. 4 FIG. 2 is a graph illustrating a compensation operation for compensating for pixel degradation according to some example embodiments.

[0057] Referring to FIG. 3 , the luminance drop can increase as the cumulative stress increases and / or the degradation of the pixel becomes more severe. In addition, the luminance drop can degrade the quality of a displayed image. To reduce and / or prevent these effects, the luminance can be compensated for based on a degree of degradation. For example, as shown in FIG. 3 , the amount of luminance compensation can be determined according to and / or based on the cumulative stress of the pixel, but not limited thereto.

[0058] The cumulative stress of the pixel can correspond to a luminance (e.g., a luminance level) of a displayed image, e.g., a gray value of input image data. The amount of luminance compensation can be predicted, calculated, and / or determined based on information corresponding to a cumulative of the gray value of each pixel. The stress data (e.g., cumulative gray value) can be stored in a non-volatile memory device, such as a flash memory. As the resolution of the display panel and / or the cumulative number of frames increases, the amount (and / or value) of stress data per pixel can significantly increase. This can result in an increase in hardware cost / complexity and / or an increase in bandwidth of data from and to the non-volatile memory device for storing the stress data. According to some example embodiments, these effects can be reduced and / or prevented by grouping the pixels in a manner to be described below with reference to FIG. 5 FIG. 2.

[0059] Referring to FIG. 4Although the pixels PX1, PX2, and PX3 are driven and / or operated based on the same data corresponding to the original luminance L0, the displayed luminances L1, L2, and L3 can also differ according to and / or based on the degree of degradation of the pixels PX1, PX2, and PX3, for example. For example, the stress value of the pixel PX2 can be greater than the stress value of the pixel PX1, and the stress value of the pixel PX3 can be greater than the stress value of the pixel PX2, but example embodiments are not limited thereto. As the driving time (e.g., operation time) and / or driving amount (e.g., operation amount) of the pixels increases, i.e., as the cumulative stress applied to the pixels increases, the OLEDs in the pixels degrade and / or deteriorate more, and the luminance of the pixels decreases.

[0060] According to at least one example embodiment, to reduce the effects of pixel degradation, the stress value of a pixel can be converted to a compensation gain based on a relationship between the cumulative stress value and the luminance drop. As shown in FIG. 4 downward compensation can be employed and / or provided such that the compensation gain is adjusted based on the pixel PX3 and / or the region corresponding to the highest degradation, or upward compensation can be employed and / or provided such that the compensation gain is adjusted based on the pixel PX1 and / or the region corresponding to the lowest degradation. In some example embodiments, based on the middle luminance between the luminance range L1 to L3, the compensation gain can increase with respect to some pixels and can decrease with respect to other pixels, but example embodiments are not limited thereto, and other luminance values can be used.

[0061] FIG. 5 is a diagram illustrating an example of grouping pixels in a method for compensating for degradation of an electroluminescent display apparatus according to some example embodiments.

[0062] Referring to FIG. 5 The pixels PX in the display panel can be grouped into a plurality of pixel groups PB11 to PBps arranged in a plurality of block rows (e.g., rows of blocks) BR1 to BRp and a plurality of block columns (e.g., columns of blocks) BC1 to BCs by dividing the pixels PX in the display panel using the initial block boundaries RBB and CBB, but example embodiments are not limited thereto. The block rows BR1 to BRp can be divided by the row block boundaries RBB, and the block columns BC1 to BCs can be divided by the column block boundaries CBB, but example embodiments are not limited thereto. Each of the plurality of pixel blocks PB11 to PBps can be divided (and / or segmented) by the row block boundaries RBB and the column block boundaries CBB. The initial pixel blocks PB11 to PBps can include the same number of pixels PX divided by the initial block boundaries RBB and CBB. For example, each of the pixel groups PB11 to PBps can be an 8x8 block including 64 pixels as shown in FIG. 5 but example embodiments are not limited thereto, and other sizes of pixel groups can be used.

[0063] As the adoption of high-speed displays (e.g., OLED displays capable of displaying at 120 Hz or higher frequencies) in electronic devices (e.g., smartphones, tablet computers, etc.) increases, the storage capacity requirement for degradation compensation increases, and the required power increases due to high-speed display driving at 120 Hz. In addition, the increase in resolution of display panels is leading to an increase in the physical size of display driving integrated circuits.

[0064] Accordingly, a display driving integrated circuit of an OLED display device includes a frame memory for storing image data and an embedded SRAM (Static Random Access Memory) as a compensation memory for storing data for enhancing image quality. Due to various data processing performed by the display driving integrated circuit, such as OLED burn-in compensation, hysteresis compensation, etc., the storage capacity of the compensation memory has increased. The increase in storage capacity leads to an increase in the size, complexity, and / or cost of the display driving integrated circuit.

[0065] By accumulating block average values, each of which is an average gray level value of pixels in each pixel block, to store and provide accumulated block stress values, the amount of stress data can be significantly reduced. When providing stress data through such compression based on the unit of a pixel block, the boundaries of stress regions can not be accurately reflected. Accordingly, when compensating for pixel degradation using accumulated block stress values, errors can occur, and block boundaries between pixel blocks can be visible and / or identifiable by a user, and the quality of a display image can decrease. According to some example embodiments, image quality can be enhanced by updating block boundaries to accurately reflect a degradation pattern of pixels.

[0066] FIG. 6 is a block diagram illustrating an example of degradation compensation logic included in an electroluminescent display device, according to some example embodiments.

[0067] Reference will now be made to FIG. 6, the degradation compensation logic 2000 (e.g., a degradation compensation logic circuit, etc.) can include a sampling unit (SAM) 210 (e.g., a sampling circuit, etc.), an accumulation unit (ACC) 220 (e.g., an accumulation circuit, etc.), a memory unit (MEM) 230 (e.g., a memory circuit, etc.), an extraction unit (EXT) 240 (e.g., an extraction circuit, etc.), a boundary update unit (BBU) 250 (e.g., a boundary circuit, etc.), a gain generation unit (GGEN) 260 (e.g., a gain generation circuit, etc.), and / or a data correction unit (DCOR) 270 (e.g., a data correction circuit, etc.), although example embodiments are not limited thereto. According to some example embodiments, the degradation compensation logic 2000 can be implemented as a processing circuit capable of performing the functions of one or more of the sampling unit (SAM) 210, the accumulation unit (ACC) 220, the memory unit (MEM) 230, the extraction unit (EXT) 240, the boundary update unit (BBU) 250, the gain generation unit (GGEN) 260, and the data correction unit (DCOR) 270, etc. The processing circuit can include hardware (such as a processor, a processor core, a logic circuit, a storage device, etc.), a hardware / software combination (such as at least one processor core executing software and / or executing any instruction set, etc.), or a combination thereof. For example, the processing circuit can more specifically include, but is not limited to, a field programmable gate array (FPGA), a programmable logic unit, an application specific integrated circuit (ASIC), a system on chip (SoC), etc.

[0068] The sampling unit 210 can calculate and provide the block average values BA based on the input image data IDATA of each frame. Each block average value BA can be an average gray scale value of the pixels in each pixel block. The accumulation unit 220 can accumulate each block average value BA for a plurality of frames to store accumulated block stress values. The memory unit 230 can include a volatile memory device and / or a non-volatile memory device, as will be described below with reference to FIG. 26

[0069] For example, each time the input image data IDATA of a new frame is provided to the degradation compensation logic 2000, the accumulation unit 220 can read out the previous accumulated block stress values BST stored in the memory unit 230, add the block average values BA of the new frame to the read values BST, and then store the added values as new accumulated block stress values BST in the memory unit 230, although example embodiments are not limited thereto.

[0070] The extraction unit 240 can extract the accumulated block stress values BST of the neighboring pixel blocks from the memory unit 230 and provide the extracted values BST to the boundary update unit 250 and / or the gain generation unit (GGEN) 260, although example embodiments are not limited thereto.

[0071] ​The boundary update unit 250 can perform a boundary update operation to move (e.g., update, recalculate, etc.) the current block boundary BB to an updated block boundary BB'. According to some example embodiments, the boundary update unit 250 can perform the boundary update operation based on the accumulated block stress value BST from the extraction unit 240 and / or based on the compensation gain CG from the gain generation unit 260, but is not limited thereto. Some example embodiments describing the boundary update operation performed by the boundary update unit 250 are described below with reference to FIGS. 7-24 FIG. 21.

[0072] The degradation compensation logic 2000 can store the updated block boundary BB' in a non-volatile memory device included in the memory unit 230. After the boundary update operation, the degradation compensation logic 2000 can provide the accumulated block stress value BST by accumulating (and / or compressing, etc.) stress values of the plurality of pixels based on the updated block boundary BB'.

[0073] The gain generation unit 260 can generate the compensation gain CG based on the accumulated block stress value corresponding to the updated pixel block defined by the updated block boundary BB'. The gain generation unit 260 can generate the compensation gain CG by a downward compensation scheme or an upward compensation scheme as described with reference to FIG. 3 and FIG. 4 , but is not limited thereto.

[0074] The data correction unit 270 can correct the input image data IDATA based on the compensation gain CG to provide corrected input image data CDATA. In some example embodiments, the data correction unit 270 can perform interpolation on the compensation gain CG corresponding to the updated pixel block to apply the interpolated gain to the input image data IDATA on a pixel-by-pixel basis, but example embodiments are not limited thereto.

[0075] FIG. 7 FIG. 22 is a diagram illustrating an example degradation pattern of a display panel according to some example embodiments, for describing a method for compensating for degradation of an electroluminescent display device.

[0076] In FIG. 7 , the thick lines indicate initial block boundaries of thirty-five pixel blocks PBij arranged in seven block rows BRi (i = 0 to 6) and five block columns BCj (j = 0 to 4), and the dashed lines indicate boundaries of pixels in the pixel blocks PBij, but example embodiments are not limited thereto and other pixel block boundaries can be used. For example, for ease of illustration and description, FIG. 7 each initial pixel block includes four pixels, but the number of pixels in the pixel blocks, the number of block rows and block columns, and the number of pixel blocks are not limited to FIG. 7 the example.

[0077] In addition, FIG. 7An example of a degradation pattern in a display panel according to at least one example embodiment is shown. The hatched rectangles indicate the degraded pixels, and it is assumed that the degradation degree is equal to all degraded pixels, but example embodiments are not limited thereto. The degradation degree can be provided not in units of pixels, but in units of blocks as described above, but is not limited thereto. For example, in the case of the third block row BR2, the degradation degree of the pixel blocks PB20 and PB24 of the first block column BC0 and the fifth block column BC4 can be 0, the degradation degree of the pixel block PB21 of the second block column BC1 can be 1, the degradation degree of the pixel block PB22 of the third block column BC2 can be 0.5, the degradation degree of the pixel block PB23 of the fourth block column BC3 can be 0.25, etc.

[0078] FIG. 7 The row coordinates 0 to 14 and the column coordinates 0 to 10 of the pixel boundaries are shown, but are not limited thereto. The block boundaries can be represented by row coordinates and column coordinates, but example embodiments are not limited thereto. For example, the pixel block PB31 of the fourth block row BR3 and the second block column BC1 can be represented by a start row coordinate 6 and a start column coordinate 2. Accordingly, updating the boundary of the pixel block can be considered as updating the start row coordinate and / or the start column coordinate of the pixel block, but example embodiments are not limited thereto.

[0079] Hereinafter, some example embodiments are described with reference to the initial grouping of pixels and the degradation pattern shown in FIG. 1, but example embodiments are not limited to the specific grouping and the specific degradation pattern. FIG. 7

[0080] FIG. 8 is a flowchart showing an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display apparatus according to some example embodiments.

[0081] Referring to FIG. 3, FIG. 8 In operation S311, FIG. 6 The boundary update unit 250 in FIG. 2 can determine, for each of the current block rows or each of the current block columns of the current pixel block, an increment value indicating a difference between the degradation degrees of the adjacent pixel blocks.

[0082] The degradation degree D(i,j) can be determined as shown in Expression 1.

[0083] Expression 1

[0084] D(i,j) = SED(BST(i,j))

[0085] ​In Expression 1, i indicates an index of a block row, j indicates an index of a block column, BST(i,j) indicates a cumulative block stress value of a corresponding pixel block PBij, D(i,j) indicates a degradation degree of the corresponding pixel block PBij. SED() indicates a function of converting the cumulative block stress value into the degradation degree. For example, the function SED() can be a linear function or a non-linear function that converts a desired and / or maximum cumulative block stress value into a value 1.

[0086] In case of updating the column block boundary CBB as shown in FIG. 5 Expression 2, the increment value ΔD(i,j) can be determined as an absolute value of a difference between the degradation degrees D(i,j) and D(i,j-1) of the adjacent pixel blocks PBij and PBij-1 in the same block row BRi.

[0087] Expression 2

[0088] ΔD(i,j) = |D(i,j) - D(i,j-1)|

[0089] In case of updating the row block boundary RBB as shown in FIG. 5 Expression 3, the increment value ΔD(i,j) can be determined as an absolute value of a difference between the degradation degrees D(i,j) and D(i-1,j) of the adjacent pixel blocks PBij and PBi-1j in the same block column BCj.

[0090] Expression 3

[0091] ΔD(i,j) = |D(i,j) - D(i-1,j)|

[0092] In operation S312, the boundary update unit 250 can determine the moving directions respectively corresponding to the current block boundaries based on the increment values, and in operation S313, can determine the updated block boundaries based on the moving directions.

[0093] In some example embodiments, the normalized increment values can be determined such that each normalized increment value corresponds to a ratio of each increment value with respect to a sum of the increment values, but the example embodiments are not limited thereto.

[0094] In case of updating the column block boundary CBB, the normalized increment values can be determined as shown in Expression 4.

[0095] Expression 4

[0096] ΔD_N(i,j) = ΔD(i,j) / ∑ΔD(i,k)

[0097] In Expression 4, ∑ indicates a sum with respect to a fixed i value (which indicates a block row BRi) and k values (which indicate respective pixel blocks PBik included in the block row BRi) of degradation degrees.

[0098] In case of updating the row block boundary RBB, the normalized delta value can be determined as shown in Expression 5.

[0099] Expression 5

[0100] ΔD_N(i,j) = ΔD(i,j) / Σ ΔD(k,j)

[0101] In Expression 5, ∑ denotes a sum with respect to a fixed j value (which denotes the block column BCj) and k values (which denote the respective pixel blocks PBkj included in the block column BCj) of the degree of degradation.

[0102] As will be described below with reference to FIGS. 9A-11B , the edge value ECNT(i,j) can be assigned to the current block boundary based on the normalized delta value ΔD_N(i,j), and the coordinate sequence SEQ can be determined by arranging the current coordinate value SX(i,j) of the current block boundary based on the edge value ECNT(i,j). The movement direction MDIR(i,j) can be determined by comparing the current coordinate value SX(i,j) and the value SEQ(i,j) of the coordinate sequence SEQ, etc.

[0103] FIGS. 9A-11B is a diagram illustrating a boundary update operation for one block row in FIG. 8 according to some example embodiments. Referring to FIG. 7 , the processing of updating the column block boundaries CBB in the third block row BR2 of the pixel blocks PB20 to PB24 is described in detail, but example embodiments are not limited thereto. FIGS. 9A-11B FIG. 7 and

[0104] FIG. 9A and FIG. 9B illustrates a first boundary update operation BUO1 for updating column block boundaries CBB10 to CBB40 of a first state ST0 to column block boundaries CBB11 to CBB41 of a second state ST1 according to at least one example embodiment. The column block boundaries CBB10 to CBB40 of the first state ST0 correspond to current column block boundaries, and the column block boundaries CBB11 to CBB41 of the second state ST1 correspond to updated column block boundaries, but example embodiments are not limited thereto. The outermost boundaries can be fixed and can not be updated, but are not limited thereto.

[0105] Referring to FIG. 9A and FIG. 9B , the coordinate sequence SEQ can be determined by arranging the current coordinate value SX(i,j) of the current block boundary based on the edge value ECNT(i,j) as described with reference to FIG. 7 ​The described initial column coordinate values SX(2, k)0 (k = 0 to 4) represent the column block boundaries CBB10 to CBB40 of the first state ST0. In other words, the initial column coordinate values SX(2, k)0 of the column block boundaries CBB10 to CBB40 of the first state ST0 corresponding to the initial block boundaries can be expressed as SX(2, 0)0 = 0, SX(2, 1)0 = 2, SX(2, 2)0 = 4, SX(2, 3)0 = 6, and SX(2, 4)0 = 8, but example embodiments are not limited thereto.

[0106] According to Expression 1, the degradation degree D(2, k) (k = 0 to 4) corresponding to the degradation pattern and / or degradation state of the third block row BR2 in FIG. 7 may be determined as D(2, 0) = 0, D(2, 1) = 1, D(2, 2) = 0.5, D(2, 3) = 0.25, and D(2, 4) = 0, but example embodiments are not limited thereto.

[0107] According to Expression 2, the delta value ΔD(2, k) representing the absolute value of the difference in the degradation degree of adjacent pixel blocks PB2k and PB2k-1 in the third block row BR2 can be determined as ΔD(2, 1) = 1, ΔD(2, 2) = 0.5, ΔD(2, 3) = 0.25, and ΔD(2, 4) = 0.25, but example embodiments are not limited thereto.

[0108] According to Expression 4, the sum of the delta values of the third block row BR2 becomes 2 (= 1 + 0.5 + 0.25 + 0.25), and the normalized delta value ΔD_N(2, k) can be determined as ΔD_N(2, 1) = 0.5, ΔD_N(2, 2) = 0.25, ΔD_N(2, 3) = 0.125, and ΔD_N(2, 4) = 0.125, but example embodiments are not limited thereto.

[0109] The edge value ECNT(2, k) can be assigned to the current block boundary based on the normalized delta value ΔD_N(2, k). For example, by multiplying the total number of edges (e.g., 4) corresponding to the total number of variable block boundaries by the normalized delta value ΔD_N(2, k), the edge value ECNT(2, k) can be determined as ECNT(2, 1) = 2, ECNT(2, 2) = 1, ECNT(2, 3) = 0.5, and ECNT(2, 4) = 0.5, but example embodiments are not limited thereto. When the edge value is not an integer, the edge number can be appropriately adjusted to an integer by rounding, rounding up, or the like. For example, ECNT(2, 3) can be adjusted from 0.5 to 1, and ECNT(2, 4) can be adjusted from 0.5 to 0, or the like.

[0110] The coordinate sequence SEQ can be determined by repeatedly arranging the current coordinate values SX(2, k)0of the column block boundaries CBB10 to CBB40 of the first state ST0 based on the edge value ECNT(2, k). In other words, the values SX(2, k) of the coordinate sequence SEQ can be determined such that SX(2, k)0= 0 corresponding to the fixed block boundary is arranged once, SX(2, 1)0= 2 corresponding to ECNT(2, 1) = 2 is arranged twice, SX(2, 2)0= 4 corresponding to ECNT(2, 2) = 1 is arranged once, and SX(2, 3)0= 6 corresponding to ECNT(2, 3) = 1 is arranged once, and so on. As a result, the values SEQ(2, k) of the coordinate sequence SEQ can be determined as SEQ(2, 0) = 0, SEQ(2, 1) = 2, SEQ(2, 2) = 2, SEQ(2, 3) = 4, and SEQ(2, 4) = 6, but example embodiments are not limited thereto.

[0111] The moving direction MDIR(2, k) of the column block boundaries CBB10 to CBB40 of the first state ST0 can be determined by comparing the coordinate values SX(2, k)0and the values SEQ(2, k) of the coordinate sequence SEQ.

[0112] For example, each of the moving directions MDIR(2, k) can be determined as the sign SIGN of each value SEQ(2, k) of the coordinate sequence SEQ minus each coordinate value SX(2, k)0of the first state ST0. As a result, the moving direction MDIR(2, k) can be determined as shown in Expression 6.

[0113] Expression 6

[0114] MDIR(2, 1) = SIGN{SEQ(2, 1) - SX(2, 1)0} = SIGN{2 - 2} = (0)

[0115] MDIR(2, 2) = SIGN{SEQ(2, 2) - SX(2, 2)0} = SIGN{2 - 4} = (-)

[0116] MDIR(2, 3) = SIGN{SEQ(2, 3) - SX(2, 3)0} = SIGN{4 - 6} = (-)

[0117] MDIR(2, 4) = SIGN{SEQ(2, 4) - SX(2, 4)0} = SIGN{6 - 8} = (-)

[0118] As shown in Expression 6, the updated block boundaries, i.e., the column block boundaries CBB11 to CBB41 of the second state ST1 can be determined based on the moving directions MDIR(2, k).

[0119] Generally, the degradation state of a pixel does not change rapidly in a short time, and thus the movement amount of each block boundary by a single boundary update operation can be limited to be less than a desired and / or maximum movement amount (e.g., a desired movement amount, etc.). For example, the movement amount of each block boundary by a single boundary update operation can be fixed to a pixel size. In other words, with a single boundary update operation, a coordinate value can change at most by one, but example embodiments are not limited thereto.

[0120] FIG. 9A and FIG. 9B An example is shown in which a coordinate value of a current block boundary is maintained when a corresponding movement direction is (0), the coordinate value of the current block boundary is decreased by 1 when the corresponding movement direction is (-), and the coordinate value of the current block boundary is increased by 1 when the corresponding movement direction is (+), but example embodiments are not limited thereto. When a block boundary cannot be moved due to an adjacent block boundary, the block boundary can be maintained without moving the block boundary.

[0121] As a result, column block boundaries CBB11 to CBB41 of the second state ST1 updated by the first boundary update operation BUO1 can be determined as SX(2,0)1=0, SX(2,1)1=2, SX(2,2)1=3, SX(2,3)1=5, and SX(2,4)1=7, etc.

[0122] Such a boundary update operation can be repeated so that the updated block boundary approaches a burn-in boundary indicating a degradation pattern of a pixel. For example, after the first boundary update operation BUO1 described with reference to FIG. 9A and FIG. 9B The second boundary update operation BUO2 of FIG. 10A and FIG. 10B and the third boundary update operation BUO3 of FIG. 11A and FIG. 11B may be sequentially performed, but example embodiments are not limited thereto. The timing and number of repeated boundary update operations can be appropriately determined based on an operating environment and operating characteristics of a display device.

[0123] FIG. 10A and FIG. 10B The second boundary update operation BUO2 of FIG. 11A and FIG. 11B The third boundary update operation BUO3 is similar to the first boundary update operation BUO1 of FIG. 9A and FIG. 9B In the following, repeated descriptions are omitted, and only the results of the second boundary update operation BUO2 and the third boundary update operation BUO3 are described.

[0124] FIG. 10A and FIG. 10BA second boundary update operation BUO2 for updating the column block boundaries CBB11 to CBB41 of the second state ST1 to the column block boundaries CBB12 to CBB42 of the third state ST2 is shown according to at least one example embodiment. The column block boundaries CBB11 to CBB41 of the second state ST1 correspond to the current column block boundaries, and the column block boundaries CBB12 to CBB42 of the third state ST2 correspond to the updated column block boundaries, although example embodiments are not limited thereto.

[0125] Referring to FIG. 10A and FIG. 10B , the coordinate values SX(2,k)1 of the column block boundaries CBB11 to CBB41 of the second state ST1 are SX(2,0)1 = 0, SX(2,1)1 = 2, SX(2,2)1 = 3, SX(2,3)1 = 5, and SX(2,4)1 = 7, and the corresponding degrees of degradation D(2,k) are D(2,0) = 0, D(2,1) = 1, D(2,2) = 0.75, D(2,3) = 0.5, and D(2,4) = 0, although example embodiments are not limited thereto. The coordinate values SX(2,k)2 of the column block boundaries CBB12 to CBB42 of the third state ST2 determined in the same manner as described with reference to FIG. 9A and FIG. 9B are SX(2,0)2 = 0, SX(2,1)2 = 2, SX(2,2)2 = 3, SX(2,3)2 = 4, and SX(2,4)2 = 7, although example embodiments are not limited thereto. The degrees of degradation D(2,k) of the pixel blocks PB20 to PB24 defined by the updated column block boundaries CBB12 to CBB42 of the third state ST2 are determined to be D(2,0) = 0, D(2,1) = 1, D(2,2) = 1, D(2,3) = 0.5, and D(2,4) = 0, although example embodiments are not limited thereto.

[0126] FIG. 11A and FIG. 11B A third boundary update operation BUO3 for updating the column block boundaries CBB12 to CBB42 of the third state ST2 to the column block boundaries CBB13 to CBB43 of the fourth state ST3 is shown according to at least one example embodiment. The column block boundaries CBB12 to CBB42 of the third state ST2 correspond to the current column block boundaries, and the column block boundaries CBB13 to CBB43 of the fourth state ST2 correspond to the updated column block boundaries.

[0127] Referring to FIG. 11A and FIG. 11B, the coordinate values SX(2, k)2 of the column block boundaries CBB12 to CBB42 of the third state ST2 are SX(2, 0)2 = 0, SX(2, 1)2 = 2, SX(2, 2)2 = 3, SX(2, 3)2 = 4, and SX(2, 4)2 = 7, and the corresponding degrees of degradation D(2, k) are D(2, 0) = 0, D(2, 1) = 1, D(2, 2) = 1, D(2, 3) = 0.5, and D(2, 4) = 0, although example embodiments are not limited thereto. The coordinate values SX(2, k)3 of the column block boundaries CBB13 to CBB43 of the fourth state ST3 determined in the same manner as described with reference to FIG. 9A and FIG. 9B The coordinate values SX(2, k)3 of the column block boundaries CBB13 to CBB43 of the fourth state ST3 determined in the same manner as described with reference to

[0128] Thus, the third boundary update operation BUO3 can not change the column block boundaries, and it should be understood that the updated block boundaries approach the burn-in boundary due to repeated boundary update operations, although example embodiments are not limited thereto.

[0129] FIGS. 12A-12E is a diagram illustrating a boundary update operation for all block rows in FIG. 7 according to at least one example embodiment. FIGS. 12A-12E The boundary update operation for each block row of FIGS. 9A-11B is substantially the same as the boundary update operation for the block rows of

[0130] FIG. 12A illustrates a process of updating the pixel blocks PB00 to PB04 included in the first block row BR0 in FIG. 7 The degree of degradation of the seventh block row BR6 is the same as the degree of degradation of the first block row BR0, and the result of the boundary update operation of the seventh block row BR6 is the same as the result of the boundary update operation of the first block row BR0, although example embodiments are not limited thereto. With reference to FIG. 12A , although the first boundary update operation BUO1 is performed, the column coordinate values SX(0, k)1 of the column block boundaries of the second state ST1 (e.g., 0, 2, 4, 6, and 8) are the same as the column coordinate values SX(0, k)0 of the column block boundaries of the first state ST0, because the first block row BR0 does not include a degraded pixel.

[0131] FIG. 12B processing of updating pixel blocks PB10 to PB14 included in the second block row BR1 in FIG. 7 FIG. 12B The column coordinate values SX(0, k)0 (e.g., 0, 2, 4, 6, and 8) of the column block boundaries of the first state ST0 are updated to the column coordinate values SX(1, k)1 (e.g., 0, 2, 3, 7, and 8) of the column block boundaries of the second state ST1 by the first boundary update operation BUO1. Thereafter, although the second boundary update operation BUO2 is performed, the column coordinate values SX(1, k)2 (e.g., 0, 2, 3, 7, and 8) of the column block boundaries of the third state ST2 are the same as the column coordinate values SX(1, k)1 (e.g., 0, 2, 3, 7, and 8) of the column block boundaries of the second state ST1.

[0132] FIG. 12C processing of updating pixel blocks PB20 to PB24 included in the third block row BR2 in FIG. 7 FIG. 12C The column coordinate values SX(2, k)0 (e.g., 0, 2, 4, 6, and 8) of the column block boundaries of the first state ST0 are updated to the column coordinate values SX(2, k)1 (e.g., 0, 2, 3, 5, and 7) of the column block boundaries of the second state ST1 by the first boundary update operation BUO1, and then updated to the column coordinate values SX(2, k)2 (e.g., 0, 2, 3, 4, and 7) of the column block boundaries of the third state ST2 by the second boundary update operation BUO2. Thereafter, although the third boundary update operation BUO3 is performed, the column coordinate values SX(2, k)3 (e.g., 0, 2, 3, 4, and 7) of the column block boundaries of the fourth state ST3 are the same as the column coordinate values SX(2, k)2 (e.g., 0, 2, 3, 4, and 7) of the column block boundaries of the third state ST2.

[0133] FIG. 12D processing of updating pixel blocks PB40 to PB44 included in the fifth block row BR4 in FIG. 7 FIG. 12D ​​​The column coordinate values ​​SX(4,k)0 (e.g., 0, 2, 4, 6, and 8) of the column block boundary in the first state ST0 are updated to the column coordinate values ​​SX(4,k)1 (e.g., 0, 2, 3, 5, and 7) of the column block boundary in the second state ST1 through the first boundary update operation BUO1, and are updated to the column coordinate values ​​SX(4,k)2 (e.g., 0, 2, 3, 4, and 6) of the column block boundary in the third state ST2 through the second boundary update operation BUO2. Subsequently, although the third boundary update operation BUO3 is performed, the column coordinate values ​​SX(4,k)3 (e.g., 0, 2, 3, 4, and 6) of the column block boundary in the fourth state ST3 are the same as the column coordinate values ​​SX(4,k)2 (e.g., 0, 2, 3, 4, and 6) of the column block boundary in the third state ST2.

[0134] FIG. 12E The diagram illustrates a pair according to at least one example embodiment. FIG. 7 The process of updating pixel blocks PB50 to PB54 in the sixth row BR5 is included. (Refer to...) FIG. 12E The column coordinate values ​​SX(5,k)0 (e.g., 0, 2, 4, 6, and 8) of the column block boundary in the first state ST0 are updated to the column coordinate values ​​SX(5,k)1 (e.g., 0, 2, 3, 5, and 7) of the column block boundary in the second state ST1 through the first boundary update operation BUO1. They are then updated to the column coordinate values ​​SX(5,k)2 (e.g., 0, 2, 3, 4, and 6) of the column block boundary in the third state ST2 through the second boundary update operation BUO2. Finally, they are updated to the column coordinate values ​​SX(5,k)3 (e.g., 0, 2, 3, 4, and 5) of the column block boundary in the fourth state ST3 through the third boundary update operation BUO3. Subsequently, although the fourth boundary update operation BUO4 is performed, the column coordinate values ​​SX(5,k)4 (e.g., 0, 2, 3, 4, and 5) of the column block boundary in the fifth state ST4 are the same as those of the column coordinate values ​​SX(5,k)3 (e.g., 0, 2, 3, 4, and 5) of the column block boundary in the fourth state ST3.

[0135] FIG. 13 This illustrates the passage based on at least one example embodiment. FIGS. 12A-12E The diagram shows the updated block boundaries of the boundary update operation.

[0136] like FIG. 13 As shown, the current block boundary can be moved to an updated block boundary, making the updated block boundary more concentrated in areas where the difference in degradation levels between adjacent pixel blocks of the display panel is greater, but the example embodiment is not limited to this. In other words, the current block boundary can be moved to an updated block boundary, making the updated block boundary more concentrated and / or more compact near burn-in boundaries, etc., indicating degradation patterns of multiple pixels, but the example embodiment is not limited to this. See also FIGS. 8-13 The described boundary update operation can be called a boundary update operation based on burn-in boundary detection.

[0137] As described with reference to FIGS. 9A-13 , for each current block row, the column block boundaries of the pixel blocks included in each current block row can be updated based on the distribution of the accumulated block stress values of the pixel blocks included in each current block row according to some example embodiments. In order to reduce the complexity of the boundary update operation, the row boundaries between the block rows can be fixed, and the boundary update operation can be performed in block row units to update the column block boundaries between the pixel blocks in the same block row, but example embodiments are not limited thereto.

[0138] Hereinafter, the boundary update operation in block column units is described with reference to FIG. 14 , FIG. 15 and FIG. 16 . In order to reduce the complexity of the boundary update operation, the column boundaries between the block columns can be fixed, and the boundary update operation can be performed in block column units to update the row block boundaries between the pixel blocks in the same block column, but example embodiments are not limited thereto.

[0139] FIG. 14 and FIG. 15 are diagrams illustrating the boundary update operation of FIG. 8 for one block row in FIG. 7 according to some example embodiments.

[0140] As an example, the process of updating the row block boundaries RBB of the plurality of pixel blocks PB01 to PB61 in the second block column BC1 in FIG. 14 and FIG. 15 is described, but example embodiments are not limited thereto. FIG. 7 and FIG. 14 illustrate the first boundary update operation BUO1 of updating the row block boundaries RBB10 to RBB60 of the first state ST0 to the row block boundaries RBB11 to RBB61 of the second state ST1, the second boundary update operation BUO2 of updating the row block boundaries RBB11 to RBB61 of the second state ST1 to the row block boundaries RBB12 to RBB62 of the third state ST2, and the third boundary update operation BUO3 of updating the row block boundaries RBB12 to RBB62 of the third state ST2 to the row block boundaries RBB13 to RBB63 of the fourth state ST3, but example embodiments are not limited thereto. FIG. 15 The boundary update operations BUO1 to BUO3 are substantially the same as the boundary update operation of

[0141] for the block row, and thus the repeated description is omitted, and only the result of the boundary update operation is described. Expression 3 and Expression 5 can be applied to the boundary update operation in block column units of FIGS. 9A-11B and FIG. 14 , and Expression 2 and Expression 4 can be applied to the boundary update operation in block row units of FIG. 15 and FIGS. 9A-11Ba boundary update operation in units of a block, but example embodiments are not limited thereto.

[0142] Referring to FIG. 14 and FIG. 15 , row coordinate values SX(k,1)0 (k=0 to 6) (e.g., 0, 2, 4, 6, 8, 10, 12) of the row block boundaries of the first state ST0 can be updated to row coordinate values SX(k,1)1 (e.g., 0, 2, 3, 5, 9, 11, 12) of the row block boundaries of the second state ST1 by the first boundary update operation BOU1, and then to row coordinate values SX(k,1)2 (e.g., 0, 2, 3, 4, 10, 11, 12) of the row block boundaries of the third state ST2, but are not limited thereto. Thereafter, although the third boundary update operation BUO3 is performed, row coordinate values SX(k,1)3 (e.g., 0, 2, 3, 4, 10, 11, 12) of the row block boundaries of the fourth state ST3 are the same as the row coordinate values SX(k,1)2 (e.g., 0, 2, 3, 4, 10, 11, 12) of the row block boundaries of the third state ST2, and so on.

[0143] As such, the third boundary update operation BUO3 can not change the column block boundaries, and it can be appreciated that, through repeated boundary update operations, the updated block boundaries approach the burn-in boundary.

[0144] FIG. 16 is a diagram illustrating updated block boundaries determined by repeatedly performing a boundary update operation with respect to each of the block columns BC0 to BC4 in the block BC of the display panel 100 according to at least one example embodiment. FIG. 14 FIG. 15

[0145] FIG. 16 illustrates all of the updated row block boundaries determined by repeatedly performing the boundary update operation described with reference to FIG. 7 and FIG. 14 and 15 .

[0146] As illustrated in FIG. 16 , the current block boundaries can be moved (e.g., changed, etc.) to the updated block boundaries such that the updated block boundaries are more concentrated in regions where the difference in the degree of degradation of the adjacent pixel blocks of the display panel is greater. In other words, the current block boundaries can be moved to the updated block boundaries such that the updated block boundaries can be concentrated and / or compacted near the burn-in boundary indicative of the degradation pattern of the plurality of pixels.

[0147] As described with reference to FIG. 14 , FIG. 15 and FIG. 16 , for each of the current block columns, the row block boundaries of the pixel blocks included in each of the current block columns can be updated based on the distribution of the accumulated block stress values of the pixel blocks included in each of the current block columns, but example embodiments are not limited thereto.​​

[0148] FIG. 17 is a flowchart showing an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display apparatus according to some example embodiments.

[0149] Referring to FIG. 17 , in operation S331, the accumulated row stress values and / or the accumulated column stress values can be determined by the degradation compensation logic 2000. Each accumulated row stress value corresponds to a sum of the accumulated block stress values of the pixel blocks included in each current block row, and each accumulated column stress value corresponds to a sum of the accumulated block stress values of the pixel blocks included in each current block column.

[0150] In operation S332, the row boundary update operation can be performed based on the distribution of the accumulated row stress values and / or the column boundary update operation can be performed based on the distribution of the accumulated column stress values by the degradation compensation logic 2000. The row boundary update operation can move the current row boundary of the current block row to the updated row boundary defining the updated block row, and the column boundary update operation can move the current column boundary of the current block column to the updated column boundary defining the updated block column.

[0151] For each updated block row or each updated block column, in operation S333, the column block boundaries of the pixel blocks included in each updated block row and / or the row block boundaries of the pixel blocks included in each updated block column can be updated by the degradation compensation logic 2000.

[0152] In some example embodiments, as will be described below with reference to FIGS. 18-20 , the row boundary update operation can be performed first, and then, for each updated block row, the column block boundaries of the pixel blocks included in each updated block row can be updated based on the distribution of the accumulated block stress values of the pixel blocks included in each updated block row, but the example embodiments are not limited thereto.

[0153] In some example embodiments, although not shown in the figures, the column boundary update operation can be performed first, and then, for each updated block column, the row block boundaries of the pixel blocks included in each updated block column can be updated based on the distribution of the accumulated block stress values of the pixel blocks included in each updated block column, etc.

[0154] FIG. 18 , FIG. 19 and FIG. 20 are diagrams for describing a boundary update operation of FIG. 17 according to at least one example embodiment. For brevity and clarity, FIG. 18 the same initial pixel grouping and the same degradation pattern as FIG. 7 are shown, but the example embodiments are not limited thereto. The description duplicated with FIG. 7 is omitted.

[0155] Referring to FIG. 18 Cumulative row stress values RSUM0 to RSUM6 can be determined by the degradation compensation logic 2000 such that each cumulative row stress value corresponds to a sum of cumulative block stress values of the pixel blocks included in each of the current block rows BR0 to BR6. In other words, the cumulative row stress values RSUM0 to RSUM6 can be determined as, for example, 1, 0.3, 0.35, 0.35, 0.3, 0.15, and 0, respectively, but are not limited thereto. A row boundary update operation can be performed based on a distribution of the cumulative row stress values RSUM0 to RSUM6 to move the current row boundaries RBB1 to RBB6 of the current block rows to the updated row boundaries RBB1' to RBB6' of the updated block rows, but is not limited thereto.

[0156] For each of the updated block rows BR0' to BR6' defined by the updated row boundaries RBB1' to RBB6', the column block boundaries of the pixel blocks PBik (i = 0 to 6, k = 0 to 4) included in each of the updated block rows BRi' can be based on a distribution of the cumulative block stress values of the pixel blocks PBik included in each of the updated block rows BRi', but is not limited thereto. FIG. 20 An updated column block boundary of the pixel blocks PBik included in each of the updated block rows BRi' obtained by the boundary update operation based on the burn-in boundary detection as described with reference to FIGS. 8-18 is shown, but example embodiments are not limited thereto.

[0157] As such, the performance of the degradation compensation can be further enhanced by first performing the row boundary update operation and then, for each of the updated block rows, updating the column block boundaries of the pixel blocks included in each of the updated block rows based on a distribution of the cumulative block stress values of the pixel blocks included in each of the updated block rows, but example embodiments are not limited thereto.

[0158] FIG. 21 is a flowchart showing an example of a boundary update operation in a method for compensating for degradation of an electroluminescent display apparatus according to some example embodiments.

[0159] Referring to FIG. 21 In operation S351, the low-pass filter functions can be determined by the degradation compensation logic 2000 based on the average values such that each of the average values corresponds to an average value of the cumulative block stress values of the adjacent pixel blocks. In operation S352, the cumulative distribution functions can be determined by the degradation compensation logic 2000 based on the values obtained by sequentially accumulating the values of the low-pass filter functions. In operation S353, the moving directions corresponding to the current block boundaries, respectively, can be determined by the degradation compensation logic 2000 based on the values of the cumulative distribution functions. In operation S354, the updated block boundaries can be determined by the degradation compensation logic 2000 based on the moving directions.

[0160] FIG. 22 、 FIG. 23 and FIG. 24 are diagrams illustrating a boundary update operation for one block row in FIG. 21 according to at least one example embodiment. FIG. 7

[0161] FIG. 22 and FIG. 23 illustrate values of a degradation degree function D, values of a low pass filter function LPF, values of a cumulative distribution function CDF, and values of a normalized cumulative distribution function CDF_N for center coordinate values (e.g., 0.5, 1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, and 9.5) of pixel blocks PB20 to PB24 in a third block row BR2 in FIG. 7 but example embodiments are not limited thereto, the values of the degradation degree function D corresponding to cumulative block stress values. FIG. 22 and FIG. 23 illustrate an example in which the low pass filter function LPF provides an average of the degradation degrees of the respective three neighboring pixels, but example embodiments are not limited thereto.

[0162] The target coordinate values TX1 to TX4 correspond to values obtained by uniformly dividing the values of the cumulative distribution function CDF and / or the normalized cumulative distribution function CDF_N. Here, the number of the target coordinate values TX1 to TX4 is, for example, four, i.e., the number of variable block boundaries. The number of the target coordinate values TX1 to TX4 corresponds to the total number of edges as described with reference to FIG. 9A and FIG. 9B .

[0163] By comparing the current coordinate values and the target coordinate values TX1 to TX4, a moving direction with respect to the current column block boundaries can be determined. FIG. 24 illustrate a process of a first boundary update operation BUO1 performed by the degradation compensation logic 2000 for updating column block boundaries CBB10 to CBB40 of a first state ST0 to column block boundaries CBB11 to CBB41 of a second state ST1, etc. The column block boundaries CBB10 to CBB40 of the first state ST0 correspond to current column block boundaries, and the column block boundaries CBB11 to CBB41 of the second state ST1 correspond to updated column block boundaries, but example embodiments are not limited thereto. The outermost boundaries can be fixed and can not be updated, but are not limited thereto.

[0164] As a result, as FIG. 24 ​As shown, the first boundary update operation BUO1 can update the column block boundaries CBB10 to CBB40 (e.g., 2, 4, 6, and 8) of the first state ST0 to the column block boundaries CBB11 to CBB41 (e.g., 2, 3, 4, and 5) of the second state ST1.

[0165] In this way, the current block boundaries can be moved (e.g., changed) to the updated block boundaries such that the updated block boundaries are more concentrated in the area of the display panel that has a greater degree of degradation. In other words, the current block boundaries can be moved (e.g., changed) to the updated block boundaries such that the updated block boundaries can be concentrated and / or compacted in the area of higher degree of degradation, although example embodiments are not limited thereto. Referring to FIGS. 21-24 The described boundary update operation can be referred to as a boundary update operation based on burn-in area detection.

[0166] FIG. 25 is a block diagram illustrating a display system according to some example embodiments.

[0167] Referring to FIG. 25 The display system 10 can include a host device 20 including at least one host processor (not shown) and / or a display device 30, etc., but can have a greater or lesser number of constituent components. The display device 30 can include a display driver integrated circuit (DDI) 100 and / or a display panel 200, etc. The host processor can be a single processor, a multi-core processor, a plurality of processors, etc., although example embodiments are not limited thereto.

[0168] The host processor can control the overall operation of the display system 10. The host processor can be an application processor (AP), a baseband processor (BBP), a micro processing unit (MPU), etc. The host device 20 can provide input image data IMG, a clock signal CLK, and / or a control signal CTRL, etc. to the display device 30. For example, the input image data IMG can include RGB pixel values and can have a resolution of w x h, where w is the number of pixels in the horizontal direction and h is the number of pixels in the vertical direction.

[0169] The control signal can include a command signal, a horizontal synchronization signal, a vertical synchronization signal, a data enable signal, etc., but is not limited thereto. For example, the input image data IMG and / or the control signal CTRL can be provided to the display driver integrated circuit 100 in the display device 30 in the form of a data packet. The command signal can include control information for controlling the display driver integrated circuit 100, image information, and / or display setting information, etc. The image information can include, for example, the resolution of the input image data IMG, etc. The display setting information can include, for example, panel information, a brightness setting value, etc. For example, the host device 20 can provide information as the display setting information according to a user input and / or according to a desired and / or predetermined setting value.

[0170] The display driving integrated circuit 100 can drive and / or operate the display panel 200 based on the input image data IMG and the control signal CTRL. The display driving integrated circuit 100 can convert the digital input image signal IMG into an analog signal, and drive and / or operate the display panel 200 based on the analog signal.

[0171] The host device 20 can include first degradation compensation logic DCB1, and the display device 30 can include second degradation compensation logic DCB2, but example embodiments are not limited thereto.

[0172] The first degradation compensation logic DCB1 can group the total plurality of pixels into a plurality of first pixel blocks, and provide first accumulated block stress values based on the input image data such that each first accumulated block stress value represents a degree of degradation of pixels included in each first pixel block, but is not limited thereto.

[0173] The second degradation compensation logic DCB2 can group at least a portion of the plurality of pixels into a plurality of second pixel blocks, and provide second accumulated block stress values based on the input image data such that each second accumulated block stress value represents a degree of degradation of pixels included in each second pixel block, but is not limited thereto.

[0174] According to some example embodiments, the first degradation compensation logic DCB1 can perform a boundary update operation based on a distribution of the first accumulated block stress values to move (e.g., change) the current block boundaries of the plurality of first pixel blocks to updated block boundaries, as described with reference to FIGS. 1-24 , but example embodiments are not limited thereto. In some example embodiments, each of the first degradation compensation logic DCB1 and the second degradation compensation logic DCB2 can perform the boundary update operation as described above.

[0175] FIG. 26 is a block diagram illustrating a display system according to some example embodiments. Descriptions duplicated with FIG. 25 may be omitted.

[0176] Referring to FIG. 26 , the display system 11 can include a host device or a display controller 21 and a display device 31, but is not limited thereto. The display device 31 can include a display driving integrated circuit 101 and a display panel (DPN) 201, etc., but is not limited thereto. According to some example embodiments, the host device can include a display controller 21, etc., but example embodiments are not limited thereto.

[0177] The display controller 21 can include first degradation compensation logic 301, and the display driving integrated circuit 101 of the display device 30 can include second degradation compensation logic 302, but example embodiments are not limited thereto. The basic operations of the first degradation compensation logic 301 and the second degradation compensation logic 302 are the same as described with reference to FIG. 6The descriptions are the same, and the repeated descriptions are omitted, but the example embodiments are not limited thereto. In FIG. 26 The reference FIG. 6 The sampling unit 210, the extraction unit 240, etc. described above are omitted.

[0178] The first degradation compensation logic 301 can include a first accumulation unit ACC1, a first gain generation unit GGEN1, a boundary update unit BBU, and / or a first memory unit MEM11, etc. A second memory unit MEM12 can be included in the first degradation compensation logic 301 and / or can be provided outside the first degradation compensation logic 301, but the example embodiments are not limited thereto.

[0179] The first accumulation unit ACC1 can store first accumulated block stress values BST1 corresponding to the plurality of first pixel blocks in the first memory unit MEM11 based on the input image data IDATA. As described above, all the pixels in the display panel can be grouped into the plurality of first pixel blocks. The first gain generation unit GGEN1 can generate first compensation gain and / or first compensation factor values CG1 corresponding to the plurality of first pixel blocks based on the first accumulated block stress values BST1 extracted from the first memory unit MEM11. As described with reference to FIGS. 1-24 The boundary update unit BBU can perform a boundary update operation to update the block boundaries of the plurality of first pixel blocks, as described with reference to

[0180] The first memory unit MEM11 can be a volatile storage device such as a static random access memory (SRAM) and / or a dynamic random access memory (DRAM), etc., and the second memory unit MEM12 can be a non-volatile storage device such as a flash memory, etc., but the example embodiments are not limited thereto. When the display controller 21 is powered off, the data such as the first accumulated block stress values BST1 stored in the first memory unit MEM11 can be moved into the second memory unit MEM12. When the display controller 21 is powered on, the data stored in the second memory unit MEM12 can be loaded into the first memory unit MEM11.

[0181] The second degradation compensation logic 302 can include a second accumulation unit ACC2, a second gain generation unit GGEN2, a data correction unit DCOR, an encoder ENC, a decoder DEC, a third memory unit MEM21, and / or a fourth memory unit MEM22, etc. A fifth memory unit MEM23 can be included in the second degradation compensation logic 302 and / or can be external to and / or outside the second degradation compensation logic 302, but the example embodiments are not limited thereto.

[0182] The second accumulation unit ACC2 can store second accumulated block stress values BST2 corresponding to the plurality of second pixel blocks in the fourth memory unit MEM22 based on the input image data IDATA. As described above, at least a portion of the pixels in the display panel can be grouped into the plurality of second pixel blocks, but example embodiments are not limited thereto. The second gain generation unit GGEN2 can generate second compensation gain and / or second compensation factor values CG2 corresponding to the plurality of second pixel blocks based on the second accumulated block stress values BST2 extracted from the fourth memory unit MEM22.

[0183] The encoder ENC can compress the first compensation factor values CG1 provided by the first degradation compensation logic 301 and store the compressed first compensation factor values in the third memory unit MEM21. The compensation factor values change slowly over time, and thus the encoder ENC can employ a high-complexity compression scheme to reduce the amount of data corresponding to the compensation factor values stored in the third memory unit MEM21. For example, the compression scheme of the encoder ENC can include a spatially compressed image encoding scheme such as a discrete cosine transform (DCT), a wavelet transform, and a fractal transform, a statistically compressed entropy encoding scheme such as a Huffman coding and an arithmetic coding, etc., but example embodiments are not limited thereto. The decoder DEC can decompress the data read from the third memory unit MEM21 to provide the first compensation factor values CG1.

[0184] The data correction unit DCOR can correct the input image data IDATA based on the first compensation factor values CG1 and the second compensation factor values CG2 to provide corrected input image data CADATA. The corrected input image data CADATA is provided to the data driver and / or the source driver SDRV, and the source driver SDRV can drive and / or operate the pixels in the display panel 201 based on the corrected input image data CADATA.

[0185] In some example embodiments, as shown in FIG. 1, the display driving integrated circuit 101 can further include a second degradation compensation logic 302 configured to generate second compensation factor values CG2 corresponding to the plurality of second pixel blocks by accumulating the input image data IDATA, but example embodiments are not limited thereto. FIG. 26 In some example embodiments, as shown in FIG. 1, the display driving integrated circuit 101 can further include a second degradation compensation logic 302 configured to generate second compensation factor values CG2 corresponding to the plurality of second pixel blocks by accumulating the input image data IDATA, but example embodiments are not limited thereto.

[0186] The third display unit MEM21 and the fourth display unit MEM22 can be volatile memory devices such as SRAM and / or DRAM, etc., and the fifth display unit MEM23 can be a non-volatile memory device such as a flash memory, etc. When the display device 31 is powered off, data such as the second accumulated block stress value BST2 stored in the fourth memory unit MEM22 can be moved to the fifth memory unit MEM23. When the display device 31 is powered on, data stored in the fifth memory unit MEM23 can be loaded into the fourth memory unit MEM22.

[0187] In some example embodiments, the first degradation compensation logic 301 can receive a panel image PIMG obtained by capturing a test image displayed in the display panel 201 using the image sensor SEN. For example, the test image can be captured by applying the same value (e.g., a desired and / or maximum grayscale value) to all pixels in the display panel 201. The first degradation compensation logic 301 can update the first compensation factor value CG1 based on the panel image PIMG, and update the first accumulated block stress value BST1 based on the updated compensation factor value, but example embodiments are not limited thereto.

[0188] The first degradation compensation logic 301 can downsample the first compensation factor value CG1, and provide the downsampled compensation factor value to the second degradation compensation logic 302. In addition, the display controller 21 can determine at least one region of interest (ROI) requiring and / or desiring higher compensation accuracy, and provide the ROI information to the second degradation compensation logic 302, etc. The second degradation compensation logic 302 can apply coarse compensation to the entire area of the display panel 201 based on the downsampled compensation factor value, and then apply fine compensation to the ROI based on the ROI information and the second compensation factor value CG2, but example embodiments are not limited thereto.

[0189] FIG. 27 is a diagram illustrating a region compensation operation in a display system according to some example embodiments.

[0190] Referring to FIG. 26 and FIG. 27 The plurality of first pixel blocks as described above can correspond to the entire area EREG of the display panel DPN, and the plurality of second pixel blocks as described above can correspond to at least one partial area REG1 of the display panel DPN, but example embodiments are not limited thereto.

[0191] The first degradation compensation logic 301 can generate the first compensation factor value CG1 for the entire area EREG of the display panel DPN based on the first accumulated block stress value BST1 accumulated by the first accumulation unit ACC1, and can provide the first compensation factor value CG1 to the second degradation compensation logic 302.

[0192] The second degradation compensation logic 302 can correct the input image data IDATA corresponding to the remaining area REG2, which does not include the partial area REG1 of the display panel DPN, based on the first compensation factor value CG1.

[0193] The second degradation compensation logic 302 can generate the second compensation factor value CG2 for the partial area REG1 of the display panel DPN based on the second accumulated block stress value BST2 accumulated by the second accumulation unit ACC2, and can correct the input image data IDATA corresponding to the partial area REG1 of the display panel DPN based on the second compensation factor value CG2.

[0194] The at least one partial area REG1 can have different structure and / or operational characteristics from the remaining area REG2, but example embodiments are not limited thereto. For example, the partial area REG1 can be an area in which an image sensor is disposed below in a lower display camera, an area in which a fingerprint input window is displayed, etc. As such, the performance of degradation compensation can be enhanced by independently managing stress data of the partial area REG1, but example embodiments are not limited thereto.

[0195] FIG. 28 is a diagram illustrating a data compensation operation in a display system according to some example embodiments.

[0196] Referring to FIG. 26 and FIG. 28 The plurality of first pixel blocks PBa as described above can correspond to the entire area of the display panel DPN, and the plurality of second pixel blocks PBb as described above can correspond to the entire area of the display panel DPN, but example embodiments are not limited thereto.

[0197] As FIG. 28 indicated, the size of each of the plurality of second pixel blocks PBb can be greater than the size of each of the plurality of first pixel blocks PBa, but example embodiments are not limited thereto. In this case, the first compensation factor value CG1 can have a relatively high resolution, the second compensation factor value CG2 can have a relatively low resolution compared to each other, but example embodiments are not limited thereto.

[0198] As described above, the second degradation compensation logic 302 can generate the second compensation factor value CG2 based on the processed image data PDATA similar to the actual displayed image. In this case, the first compensation factor value CG1 can have a relatively low precision, the second compensation factor value CG2 can have a relatively high precision.

[0199] The first degradation compensation logic 301 can generate a first compensation factor value CG1 for the entire area of the display panel DPN based on the first accumulated block stress value BST1 accumulated by the first accumulation unit ACC1, and can provide the first compensation factor value CG1 to the second degradation compensation logic 302.

[0200] The second degradation compensation logic 302 can generate a second compensation factor value CG2 for the entire area of the display panel DPN based on the second accumulated block stress value BST2 accumulated by the second accumulation unit ACC2, and can correct input image data IDATA corresponding to the entire area REG1 of the display panel DPN based on the first compensation factor value CG1 and the second compensation factor value CG2, etc.

[0201] In some example embodiments, the pixel value CCPX(x,y) of the corrected input image data CCATA can be obtained by applying a guided filter as shown in Expression 7.

[0202] Expression 7

[0203] CCPX(x,y) = Ak*CPX1(x,y) + Bk

[0204] {Ak, Bk} = MIN{∑(CCPX(x,y) - CPX2(x,y)) 2}

[0205] In Expression 7, (x,y) denotes a position of a pixel, CPX1(x,y) indicates a first compensation pixel value obtained by applying the first compensation factor value CG1 to a pixel value of the input image data IDATA, and CPX2(x,y) indicates a second compensation pixel value obtained by applying the second compensation factor value CG2 to the pixel value of the input image data IDATA. The second compensation value CPX2(x,y) can be used as an input image of a guided filter, and the first compensation value CPX1(x,y) can be used as an n-guide image of the guided filter, etc. Ak and Bk indicate coefficients corresponding to a k-th window including a pixel at (x,y) and neighboring pixels, ∑ denotes a sum for pixels in the k-th window, and MIN indicates a minimum function. As shown in Expression 7, Ak and Bk can be determined as values when ∑(CCPX(x,y) - CPX2(x,y)) according to a least mean square (LMS) is reduced and / or minimized. 2

[0206] FIG. 29 is a diagram illustrating an accumulated period compensation operation in a display system according to some example embodiments.

[0207] Referring to FIG. 26 and FIG. 29 ​The second degradation compensation logic 302 may receive a mode signal MD from the display controller 21. For example, a first logic level (e.g., logic low) of the mode signal MD may indicate normal operation OPR1 of the display controller 21, while a second logic level (e.g., logic high) of the mode signal MD may indicate low-power operation OPR2 of the display controller 21, but the example embodiment is not limited thereto. The second degradation compensation logic 302 may sample stress data in response to the mode signal MD. FIG. 29 In the diagram, t1 to t11 indicate the sampling time points of the stress data.

[0208] The first degradation compensation logic 301 can generate a first accumulated block stress value BST1 by accumulating input image data IDATA when the display controller 21 performs normal operation, and the second degradation compensation logic 302 can generate a second accumulated block stress value BST2 by accumulating input image data IDATA and / or processed image data PDATA when the display controller 21 performs low-power operation.

[0209] During low-power operation of the display controller 21 and / or independent operation of the display driver integrated circuit 101 (such as command mode, Always On Display (AOD) mode, Finger on Display (FOD) mode, low-frequency drive mode, etc.), the second degradation compensation logic 302 of the display driver integrated circuit 101, instead of the first degradation compensation logic 301 of the display controller 21, may accumulate stress data, but the example embodiment is not limited thereto. The second degradation compensation logic 302 may generate a second accumulated block stress value BST2 for at least a partial area of ​​the display panel 201 and / or a second accumulated block stress value BST2 with lower resolution compared to the first accumulated block stress value BST1 generated by the first degradation compensation logic 301.

[0210] The second degradation compensation logic 302 can convert the first compensation factor value CG1 provided by the first degradation compensation logic 301 into a first cumulative block stress value BST1, and can calculate the final compensation factor value based on the first cumulative block stress value BST1 and the second cumulative block stress value BST2.

[0211] For reference FIGS. 25-29 The accuracy and efficiency of degradation compensation can be enhanced by having the display controller and display driver integrated circuit manage stress data separately.

[0212] Various embodiments of the inventive concept can be applied to any electronic device and / or system including a display device. For example, one or more example embodiments of the inventive concept can be applied to a system such as a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an electronic book, a virtual reality (VR) device, an augmented reality (AR) device, a vehicle navigation system, a video phone, a surveillance system, an auto focus system, a tracking system, a motion detection system, etc.

[0213] The above is a description of example embodiments of the inventive concept and should not be interpreted as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily understand that many modifications can be made to the example embodiments without materially departing from the inventive concept.

Claims

1. A method for compensating for degradation of an electroluminescent display device, comprising: grouping a plurality of pixels in a display panel into a plurality of pixel blocks arranged in current block rows and current block columns based on initial block boundaries; calculating accumulated block stress values based on input image data, each accumulated block stress value representing a degree of degradation of pixels included in each pixel block of the plurality of pixel blocks; performing a boundary update operation on the plurality of pixel blocks, performing the boundary update operation including moving current block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values such that the updated block boundaries are more concentrated in areas of the display panel where a difference in degrees of degradation of adjacent pixel blocks is greater than a threshold degree of degradation value and / or are more concentrated in areas of the display panel where a degree of degradation is greater than a threshold degree of degradation value; and correcting the input image data based on the accumulated block stress values and the updated block boundaries. performing the boundary update operation includes:

2. The method of claim 1, wherein, updating the current block boundaries to the updated block boundaries based on a difference between degrees of degradation of adjacent pixel blocks in the plurality of pixel blocks. performing the boundary update operation includes:

3. The method of claim 1, wherein, updating the current block boundaries to the updated block boundaries by comparing a degree of degradation of each pixel block in the plurality of pixel blocks to a desired threshold value.

4. The method of claim 1, further comprising: repeating the boundary update operation until the updated block boundaries approach a burn-in boundary, the burn-in boundary being indicated based on a degradation pattern of the plurality of pixels. an amount of movement of each block boundary by a single boundary update operation is limited to be less than a desired amount of movement.

5. The method of claim 1, wherein, the desired amount of movement is a pixel size.

6. The method of claim 5, wherein, 7. The method of claim 1, further comprising: storing the updated block boundaries in a non-volatile memory device.

8. The method of claim 7, further comprising: updating the accumulated block stress values based on the updated block boundaries stored in the non-volatile memory device in response to the boundary update operation. performing the boundary update operation includes:

9. The method of claim 1, wherein, updating column block boundaries of pixel blocks included in each current block row based on a distribution of the accumulated block stress values of the pixel blocks included in each current block row of the current block rows. performing the boundary update operation includes:

10. The method of claim 1, wherein, updating row block boundaries of pixel blocks included in each current block column based on a distribution of the accumulated block stress values of the pixel blocks included in each current block column of the current block columns. performing the boundary update operation includes:

11. The method of claim 1, wherein, determining accumulated row stress values, determining the accumulated row stress values including summing the accumulated block stress values of pixel blocks included in each current block row of the current block rows; and performing a row boundary update operation based on a distribution of the accumulated row stress values, performing the row boundary update operation including moving current row boundaries of the current block rows to updated row boundaries defining updated block rows. performing the boundary update operation further includes:

12. The method of claim 11, wherein, ​ updating a row block boundary of the pixel blocks included in each of the updated block rows based on a distribution of the accumulated block stress values of the pixel blocks included in each of the updated block rows.

13. The method of claim 1, wherein, performing the boundary update operation includes: determining an accumulated column stress value, determining the accumulated column stress value includes summing the accumulated block stress values of the pixel blocks included in each of the current block columns; and performing a column boundary update operation based on a distribution of the accumulated column stress values, performing the column boundary update operation includes moving a current column boundary of the current block columns to an updated column boundary defining updated block columns.

14. The method of claim 13, wherein, performing the boundary update operation further includes: updating a row block boundary of the pixel blocks included in each of the updated block columns based on a distribution of the accumulated block stress values of the pixel blocks included in each of the updated block columns.

15. The method of claim 1, wherein, performing the boundary update operation includes: determining an increment value indicative of a difference between a degree of degradation of neighboring pixel blocks of each of the current block rows or each of the current block columns of the plurality of pixel blocks; determining a moving direction corresponding to the current block boundary based on the increment value; and determining the updated block boundary based on the moving direction.

16. The method of claim 15, wherein, determining the moving direction includes: determining a normalized increment value, the normalized increment value corresponding to a ratio of each increment value relative to a sum of the increment values; assigning an edge value to the current block boundary based on the normalized increment value; determining a coordinate sequence by arranging current coordinate values of the current block boundary based on the edge value; and determining the moving direction based on the current coordinate values and values of the coordinate sequence.

17. The method of claim 1, wherein, performing the boundary update operation includes: determining a low pass filter function based on an average value of the accumulated block stress values of neighboring pixel blocks; determining a cumulative distribution function based on a value obtained by sequentially accumulating values of the determined low pass filter function; determining a moving direction corresponding to the current block boundary based on a value of the cumulative distribution function; and determining the updated block boundary based on the moving direction.

18. The method of claim 17, wherein, determining the moving direction includes: determining a target coordinate value corresponding to a value obtained by uniformly dividing a value of the cumulative distribution function; and determining the moving direction based on a current coordinate value of the current block boundary and the target coordinate value.

19. An electroluminescent display device comprising: a display panel including a plurality of pixels; and at least one degradation compensation logic configured to: group the plurality of pixels into a plurality of pixel blocks arranged in current block rows and current block columns based on initial block boundaries; calculate an accumulated block stress value associated with each pixel block based on input image data, each accumulated block stress value representing a degree of degradation of pixels included in each pixel block of the plurality of pixel blocks, performing a boundary update operation on the plurality of pixel blocks, performing the boundary update operation including moving current block boundaries of the plurality of pixel blocks to updated block boundaries based on a distribution of the accumulated block stress values such that the updated block boundaries are more concentrated in regions of the display panel where a difference in degradation level of adjacent pixel blocks is greater than a threshold degradation level value, and / or are more concentrated in regions of the display panel where a degradation level is greater than a threshold degradation level value, and correcting the input image data based on the accumulated block stress values and the updated block boundaries.

20. A display system comprising: a display panel including a plurality of pixels; a display controller configured to: group all of the plurality of pixels into a plurality of first pixel blocks, provide first accumulated block stress values based on input image data, each of the first accumulated block stress values representing a degradation level of pixels included in each of the plurality of first pixel blocks, and perform a boundary update operation on the plurality of first pixel blocks, performing the boundary update operation including moving current block boundaries of the plurality of first pixel blocks to updated block boundaries based on a distribution of the first accumulated block stress values such that the updated block boundaries are more concentrated in regions of the display panel where a difference in degradation level of adjacent pixel blocks is greater than a threshold degradation level value, and / or are more concentrated in regions of the display panel where a degradation level is greater than a threshold degradation level value; and a display driver integrated circuit configured to: group at least a portion of the plurality of pixels into a plurality of second pixel blocks, and provide second accumulated block stress values based on the input image data, each of the second accumulated block stress values representing a degradation level of pixels included in each of the plurality of second pixel blocks.

Images