Packaged element and method of making the same

Abstract

The present application provides a packaging element and a manufacturing method thereof. The packaging element includes a redistribution layer, which includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test pattern, and the test pattern includes a first conductive pattern, and the first conductive pattern is formed by the conductive layer.

Description

Technical Field

[0001] This invention relates to a packaged element and a method for manufacturing the same, particularly a packaged element with a test pattern and a method for manufacturing the same. Background Technology

[0002] In packaging technology, multiple packaged components can be fabricated simultaneously by performing a redistribution layer process on a substrate. However, the stack thickness of the redistribution structure (such as a dielectric layer) may vary at different locations on the substrate, with differences potentially reaching several micrometers. Therefore, with current technology, it is difficult to ensure that effective vias can be formed in all locations of the dielectric layer if vias are to be formed in the dielectric layer at different locations. Furthermore, there is currently no way to monitor the redistribution layer process in real time, making it impossible to determine the process quality of patterned vias in real time. Summary of the Invention

[0003] According to an embodiment of the present invention, a packaged element is provided, which includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern, the test pattern including a first conductive pattern, and the first conductive pattern is formed by the conductive layer.

[0004] According to another embodiment of the present invention, a method for manufacturing a packaged element is provided, comprising providing a carrier board; and forming a redistribution layer on the carrier board. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, wherein the conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern, the test pattern including a first conductive pattern, wherein the first conductive pattern is formed by the conductive layer. Attached Figure Description

[0005] Figure 1 The diagram shown is a schematic diagram of a packaging element according to an embodiment of the present invention.

[0006] Figure 2 and Figure 3 The figures shown are schematic diagrams of different steps in the fabrication method of a packaged element according to an embodiment of the present invention.

[0007] Figure 4 The diagram shown is a schematic representation of a packaging element according to another embodiment of the present invention.

[0008] Figure 5 The diagram shown is a top view of a test pattern according to another embodiment of the present invention.

[0009] Figure 6 The diagram shown is a cross-sectional view of a packaging element according to another embodiment of the present invention.

[0010] Figure 7 The diagram shown is a top view of a test pattern according to another embodiment of the present invention.

[0011] Figure 8 The diagram shown is a cross-sectional view of a packaging element according to another embodiment of the present invention.

[0012] Figure 9 The diagram shown is a schematic representation of the position of the test pattern according to another embodiment of the present invention.

[0013] Figure 10 The diagram shown is a schematic representation of the position of the test pattern in the package element according to another embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures: 1, 1a, 2, 3, 4 - Packaged components; 12, 12a, 22, 22a, 32 - Test patterns; 121 - First conductive pattern; 1211, 1212, 1213, 1214, 1215 - Sub-sections; 121a - Notch; 122 - Dielectric pattern; 122a, 141a, 143a - Through-holes; 123 - Second conductive pattern; 123a, 18a - Openings; 14 - Redistribution layer; 141 - First dielectric layer; 143 - Second dielectric layer; 142, 144, 145 - Conductive layers; 142a - Trace; 144a - Lower pad; 145a - Upper pad; 16 - Carrier board; 16a - Component area; 16b - Peripheral area; 18 - Photoresist pattern; 20A, 20B, 20C, 20D - Dashed circles; 42 - Encapsulation structure; 44 - Pad; CE - Electronic component; D1, D2, D3, D4 - Orientation; ds1, ds2 - Distance; ML - Metal layer; MLa - Seed block; S1, S2, S3, S4, S5, S6, S7, S8 - Side; SL - Seed layer; SLa - Metal block; TD - Top view; T1, T2, T3 - Thickness. Detailed Implementation

[0015] The following provides a detailed description of the packaging elements according to embodiments of the present invention. It should be understood that many different embodiments are provided below to implement different configurations. The specific elements and arrangements below are merely for clear and simple description of some embodiments. Of course, these are only examples and not limitations. Furthermore, similar and / or corresponding reference numerals may be used in different embodiments to identify similar elements for clear description. However, these similar reference numerals are only for clear and simple description of some embodiments and do not represent any relationship between the different embodiments and / or structures discussed.

[0016] When a first layer is located on or above a second layer, this includes situations where the first layer and the second layer are in direct contact, or where there may be one or more other layers in between, in which case the first layer and the second layer may not be in direct contact.

[0017] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings. To make the content clearer and easier to understand, the accompanying drawings are simplified schematic diagrams, and the elements therein may not be drawn to scale. The number and size of the elements in the drawings are only illustrative and are not intended to limit the scope of the present invention.

[0018] Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements, and this document does not intend to distinguish between elements that have the same function but different names. In the following specification and claims, words such as "containing" and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...". It should also be understood that when an element is referred to as being "coupled" to another element (or a variation thereof), it can be directly connected to the other element or indirectly connected (e.g., electrically connected) to the other element through one or more elements.

[0019] The use of ordinal numbers, such as “first”, “second”, etc., in the specification and claims to modify elements of the claims does not imply or represent any prior ordinal number for the claimed element, nor does it represent the order of one claimed element with another or the order of manufacture. The use of these ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0020] When a component (e.g., a membrane or region) is referred to as "on another component," it can be directly on that component, or there may be other components between them. Conversely, when a component is referred to as "directly on another component," there are no components between them. Furthermore, when a component is referred to as "on another component," the two components have a vertical relationship in the planar view, and this component can be above or below the other component, depending on the orientation of the device.

[0021] In this text, the terms "approximately," "substantially," and "roughly" typically indicate within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range. The given quantity is approximate; that is, even without specific mention of "approximately," "substantially," or "roughly," their meaning is implied. Furthermore, the phrase "the range lies between the first and second values" indicates that the range includes the first value, the second value, and other values ​​in between.

[0022] It should be understood that the following embodiments can be modified by replacing, recombining, or mixing features from several different embodiments to complete other embodiments without departing from the spirit of the invention. Features from different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0023] In this invention, the thickness, length, and width can be measured using an optical microscope, and the thickness can be measured from a cross-sectional image in an electron microscope, but are not limited thereto. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an error of approximately 10% between the two values; if the first direction is perpendicular to the second direction, the angle between the first and second directions may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle between the first and second directions may be between 0 and 10 degrees.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0025] Figure 1 The diagram shown is a schematic representation of a packaging element according to an embodiment of the present invention. Figure 1 The upper part is a cross-sectional view of packaged component 1, and the lower part is a top view of the test pattern of packaged component 1. Figure 1 The right-side sectional view in the upper part is a schematic sectional view along section line A-A' of the lower part. For clarity, Figure 1 This shows a partial cross-sectional view of packaged element 1, but is not limited to this. For example... Figure 1As shown, the package element 1 may include a redistribution layer 14, which may have at least one test pattern 12. During the fabrication of the redistribution layer 14, the quality of the processes (including patterning processes) of the layers formed simultaneously with the test pattern 12 in the redistribution layer 14 can be detected in real time using the test pattern 12. In some embodiments, the package element 1 may include electronic components CE disposed on the redistribution layer 14, such as chips (e.g., semiconductor chips), passive components, or other suitable components. In some embodiments, the redistribution layer 14 may include fan-out circuit structures formed on a wafer, such as those used to achieve redistribution circuits in high-density integrated circuits (ICs), but is not limited thereto.

[0026] exist Figure 1 In this embodiment, the redistribution layer 14 may include a first dielectric layer 141, a conductive layer 142, and a second dielectric layer 143, with the conductive layer 142 disposed between the first dielectric layer 141 and the second dielectric layer 143. The test pattern 12 may include a first conductive pattern 121 and a corresponding dielectric pattern 122. The first conductive pattern 121 may be formed by the conductive layer 142, and the dielectric pattern 122 may be formed by the transparent second dielectric layer 143. For example, the conductive layer 142 may include a metallic material, such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), other metals, or any combination thereof, but is not limited thereto. The thickness T1 of the conductive layer 142 may be, for example, 4 micrometers to 5 micrometers (4 micrometers ≤ thickness T1 ≤ 5 micrometers), but is not limited thereto. The first dielectric layer 141 and the second dielectric layer 143 may include, for example, photosensitive polyimide or other suitable dielectric materials, but are not limited thereto. The thickness T2 of the first dielectric layer 141 and the thickness T3 of the second dielectric layer 143 can be, for example, from 4 micrometers to 7 micrometers (4 micrometers ≤ thickness T2 ≤ 7 micrometers; 4 micrometers ≤ thickness T3 ≤ 7 micrometers), but are not limited thereto. Here, the thickness T1 of the conductive layer 142 can refer to the maximum thickness of the portion of the conductive layer 142 that does not extend into the via (e.g., via 141a) in the top view TD. Here, the thickness T2 of the first dielectric layer 141 or the thickness T3 of the second dielectric layer 143 can refer to the maximum thickness of the dielectric layer that does not overlap with the covered conductive layer in the top view TD, such as... Figure 1 As shown, but not limited to.

[0027] exist Figure 1In some embodiments, the dielectric pattern 122 may, for example, have at least one through-hole 122a, exposing the first conductive pattern 121. In other words, in the top view TD of the package element 1, the first conductive pattern 121 may be located in the through-hole 122a, such that the first conductive pattern 121 is not completely covered by the second dielectric layer 143. In some embodiments, in the top view TD of the package element 1, the side of the first conductive pattern 121 may be approximately flush with the side of the through-hole 122a. In one embodiment, in an optical microscope image, the image color of the portion where the first conductive pattern 121 overlaps with the second dielectric layer 143 is different from the image color of the portion where the first conductive pattern 121 does not overlap with the second dielectric layer 143. The relative relationship between the first conductive pattern 121 and the dielectric pattern 122 can be checked by capturing an image of the test pattern 12 to determine whether the patterning process of each layer of the redistribution layer 14 conforms to specifications. In some embodiments, determining whether the specifications are met can be done, for example, by measuring the distance between the side of the first conductive pattern 121 and the side of the through hole 122a, checking whether the first conductive pattern 121 is completely exposed by the through hole 122a, checking whether the first conductive pattern 121 overlaps with the through hole 122a of the dielectric pattern 122 in the top view direction TD of the package element 1, or checking the area of ​​the overlapping region of the first conductive pattern 121 and the through hole 122a of the dielectric pattern 122, but is not limited thereto. In this invention, the top view direction TD can be, for example, the normal direction of the substrate 16.

[0028] like Figure 1 As shown in the lower part of the diagram, the top view shape of the first conductive pattern 121 of the test pattern 12 may substantially correspond to or be complementary to the top view shape of the through hole 122a. For example, both may be cross-shaped, star-shaped, polygonal, arc-edged, other shapes, or combinations thereof, but are not limited thereto. In some embodiments, the quality of the patterning process of the second dielectric layer 143, such as the through hole process or the photomask alignment, can be determined by measuring whether the shape of the first conductive pattern 121 is fully exposed. In some embodiments, the top view shape of the first conductive pattern 121 may be the same as or different from the top view shape of the through hole 122a.

[0029] exist Figure 1 In some embodiments, the test pattern 12 may further include a second conductive pattern 123 adjacent to the first conductive pattern 121. The second conductive pattern 123 is formed by a conductive layer 142. In other words, the first conductive pattern 121 and the second conductive pattern 123 may be formed by the same conductive layer 142. The second conductive pattern 123 may have an opening 123a, and in the top view TD, the first conductive pattern 121 and the through hole 122a are located in the opening 123a. Figure 1In some embodiments, the top view shape of the opening 123a may be the same as or different from the top view shape of the perforation 122a and / or the top view shape of the first conductive pattern 121. In some embodiments, the quality of the patterning process can be determined by measuring the distance between the side of the first conductive pattern 121 and the side of the opening 123a of its corresponding or adjacent second conductive pattern 123. For example, the quality of the patterning process can be determined by measuring the distance between the side S1 of the first conductive pattern 121 and the side S2 of the opening 123a, the distance between the side S3 of the first conductive pattern 121 and the side S4 of the opening 123a, the distance between the side S5 of the first conductive pattern 121 and the side S6 of the opening 123a, and the distance between the side S7 of the first conductive pattern 121 and the side S8 of the opening 123a, but this is not a limitation. In some embodiments, the quality of the patterning process can be determined by measuring the distance (not shown) between the side of the first conductive pattern 121 (or the side of the opening 123a) and the side of its corresponding or adjacent through-hole 122a. In some embodiments, in the top view TD of the package element 1, the side of the second conductive pattern 123 and the side of the through-hole 122a can also be approximately aligned, that is, when measured along a direction perpendicular to the top view TD, the distance between the side of the second conductive pattern 123 and the side of the through-hole 122a is less than or equal to 1 micrometer (μm), thereby improving the alignment quality.

[0030] By judging the test pattern 12, it is possible to detect whether other components formed simultaneously with the test pattern 12 conform to standards or specifications. For example, such as Figure 1 As shown, the redistribution layer 14 further includes at least one trace 142a, which is formed by the conductive layer 142. The second dielectric layer 143 may have at least one via 143a, which corresponds to the trace 142a in the top view TD of the package element 1, so that a conductive layer (e.g., conductive layer 145) formed on the second dielectric layer 143 can be electrically connected to the trace 142a through the via 143a. The trace 142a is electrically connected to the electronic component CE disposed on the redistribution layer 14, for example, through other conductive layers or conductive elements.

[0031] It should be noted that by examining the relative relationship between the first conductive pattern 121 and the via 122a, it can be determined whether the relative relationship between the via 143a formed simultaneously with the via 122a and / or the trace 142a formed simultaneously with the first conductive pattern 121 conforms to standards or specifications. Therefore, this can be detected in real time, for example, after the formation of the second dielectric layer 143. For instance, it can be detected in real time whether the via 143a at different locations of the second dielectric layer 143 penetrates the second dielectric layer 143 to expose a portion of the trace 142a. In some embodiments, the trace 142a is electrically insulated from the test pattern 12 (including the first conductive pattern 121 and / or the second conductive pattern 123).

[0032] The redistribution layer 14 may include other film layers. Figure 1 In the illustrated embodiment, the redistribution layer 14 may include a conductive layer 144 and a conductive layer 145. The conductive layer 144 is disposed below the first dielectric layer 141, and the conductive layer 145 is disposed on the second dielectric layer 143. For example, the conductive layer 144 may include at least one lower pad 144a located on the lower surface of the redistribution layer 14. The first dielectric layer 141 may have at least one through-hole 141a, allowing a trace 142a to be electrically connected to the lower pad 144a through the through-hole 141a. The conductive layer 145 may include at least one upper pad 145a located on the upper surface of the redistribution layer 14 for electrical connection to an electronic component CE or other suitable component. The upper pad 145a may be electrically connected to the trace 142a through a through-hole 143a, and the upper pad 145a may be electrically connected to the lower pad 144a through the trace 142a, but is not limited thereto. In some embodiments, the thickness of conductive layer 144 may be similar to or the same as the thickness of conductive layer 145 as that of conductive layer 142, but is not limited thereto. In some embodiments (not shown), redistribution layer 14 may include other test patterns formed of other conductive and dielectric layers to detect the patterning process quality and alignment accuracy of the corresponding conductive and dielectric layers in real time. For example, in some embodiments (not shown), at least one test pattern is formed of conductive layer 144 and first dielectric layer 141 to detect the patterning process quality of conductive layer 144 and first dielectric layer 141 in real time. In some embodiments, redistribution layer 14 may include other conductive and dielectric layers between second dielectric layer 143 and conductive layer 145 including upper pad 145a. In some embodiments, redistribution layer 14 may include other conductive and dielectric layers between first dielectric layer 141 and conductive layer 144 including lower pad 144a, but is not limited thereto. In some embodiments, test patterns formed by different conductive layers may overlap or not overlap in the top view (TD). In some embodiments, the number of test patterns 12 corresponding to a single conductive layer may not be [missing information]. Figure 1 The number shown is limited to one, but can also be multiple.

[0033] like Figure 1As shown, conductive layers 142, 144, and / or 145 can be, for example, a single-layer or multi-layer structure. For example, a multi-layer structure may include, but is not limited to, sequentially stacked seed layers SL and metal layers ML. In this case, the first conductive pattern 121, the second conductive pattern 123, the lower pad 144a, the trace 142a, and / or the upper pad 145a may respectively include seed blocks MLA and metal blocks SLa, but are not limited thereto. Conductive layers 142, 144, and 145 may include, for example, copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), nickel (Ni), other materials, or any combination thereof, but are not limited thereto.

[0034] The fabrication method of the packaged element in this embodiment will be further described below. Please refer to... Figure 2 and Figure 3 and paired Figure 1 . Figure 2 and Figure 3 The figures shown are schematic diagrams illustrating different steps in a method for fabricating a packaged element according to an embodiment of the present invention. First, as... Figure 2 As shown, a carrier substrate 16 is provided, on which a conductive layer 144 including a lower contact pad 144a is formed, and a first dielectric layer 141 is formed on the conductive layer 144 and the carrier substrate 16. For example, the carrier substrate 16 may include glass, a wafer, electronic components, electronic components surrounded by an encapsulation structure, or other substrates suitable for carrying the redistribution layer 14, wherein the encapsulation structure may include, for example, a combination of polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), resin, epoxy resin, and silicone compounds, but is not limited thereto. Subsequently, a through-hole 141a is formed in the first dielectric layer 141 to expose a portion of the lower contact pad 144a. The through-hole 141a may be formed by an exposure process and a development process, but is not limited thereto. Next, a seed layer SL is formed on the first dielectric layer 141, and the seed layer SL may extend further into the through-hole 141a. Subsequently, at least one photoresist pattern 18 is formed on the seed layer SL through an exposure and development process. Openings 18a are formed between these photoresist patterns 18, exposing a portion of the seed layer SL. Next, a metal layer ML is formed within the openings 18a, and the metal layer ML may include multiple metal blocks MLa correspondingly disposed within the openings 18a. In some embodiments, the metal layer ML can be formed using an electroplating process, a chemical electroplating process, a physical vapor deposition process, or other suitable processes. Figure 3As shown, after forming the metal layer ML, the photoresist pattern 18 is removed to expose a portion of the seed layer SL located beneath the photoresist pattern 18. Then, through an etching process, the portion of the seed layer SL not covered by the metal layer ML is removed, dividing the seed layer SL into multiple seed blocks SLa. These seed blocks SLa overlap with their corresponding metal blocks MLa to form the aforementioned trace 142a, the first conductive pattern 121, and / or the second conductive pattern 123. In other words, the trace 142a, the first conductive pattern 121, and / or the second conductive pattern 123 are formed, for example, by the conductive layer 142 (including the seed layer SL and / or the metal layer ML).

[0035] like Figure 1 As shown, after forming trace 142a, first conductive pattern 121, and / or second conductive pattern 123, a second dielectric layer 143 can be formed on trace 142a, first conductive pattern 121, and / or second conductive pattern 123 and the first dielectric layer 141. Then, vias 122a (corresponding to the first conductive pattern 121) and 143a (corresponding to trace 142a) are formed in the second dielectric layer 143. The method of forming vias 122a and 143a can be, for example, the same as or similar to the method of forming via 141a, and therefore will not be described in detail. For example, via 143a (corresponding to trace 142a) can expose a portion of trace 142a. For example, via 122a (corresponding to the first conductive pattern 121) can expose the first conductive pattern 121. A test pattern 12 is formed by the arrangement of vias 122a in the first conductive pattern 121, second conductive pattern 123, and / or second dielectric layer 143. After the test pattern 12 is formed, an inspection step can be performed to obtain a top-view image of the test pattern 12. Since the first conductive pattern 121, the second conductive pattern 123, and the trace 142a can be formed simultaneously, and the vias 122a and 143a can be formed simultaneously, the quality of the patterning process for forming the traces 142a and vias 143a can be determined by inspecting the test pattern 12. It should be noted that by inspecting the conductive layer 142 and the second dielectric layer 143 in real time, improvements can be made in real time, thereby increasing the process yield.

[0036] like Figure 1As shown, after detecting the conductive layer 142 and the second dielectric layer 143, a conductive layer 145 can be formed on the second dielectric layer 143, and then a redistribution layer 14 can be formed on the carrier 16. The conductive layer 145 is formed as an upper pad 145a, as described above regarding the formation of the trace 142a. Electronic components CE can then be selectively disposed on the upper pad 145a. Then, the carrier 16 is selectively removed to form the package element 1 of this embodiment. The package element 1 can be formed, for example, by a redistribution layer first (RDL first) process, but is not limited thereto. In some embodiments, when the carrier 16 needs to be removed from the redistribution layer 14, a release film can be provided between the carrier 16 and the redistribution layer 14, and the carrier 16 can be removed from the redistribution layer 14 by laser, heating, or other suitable methods. In some embodiments, multiple package elements 1 can be formed on the carrier 16, so a cutting process can be performed before or after removing the carrier 16 to separate the multiple package elements 1, but is not limited thereto. In some embodiments, the step of setting the electronic component CE may be performed after removing the carrier board 16 or after a dicing process. Alternatively, the step of setting the electronic component CE may be omitted. In some embodiments, conductive bumps or conductive balls may be selectively provided on the lower pad 144a of the redistribution layer 14 to facilitate electrical connection with other electronic components. The electronic components referred to in this invention may be, for example, capacitors, resistors, inductors, diodes, printed circuit boards (PCBs), combinations thereof, or other suitable electronic components, but are not limited thereto. In some embodiments, the manner in which conductive layers 144 and 145 are formed may be similar to the manner in which conductive layer 142 is formed, but are not limited thereto.

[0037] The packaged components and their fabrication methods are not limited to the above embodiments and may have different embodiments or variations. For simplicity, the same reference numerals will be used to label the same components in the different embodiments and variations below as in the first embodiment. To clearly illustrate the different embodiments and variations, the differences between the different embodiments and variations will be described below, and repeated parts will not be repeated.

[0038] Figure 4 The diagram shown is a schematic representation of a packaging element according to another embodiment of the present invention. Figure 4 The upper part is a cross-sectional view of packaged component 1a, and the lower part is a top view of test pattern 12a of packaged component 1a. Figure 4 The right-side cross-sectional view in the upper part is a schematic cross-sectional view along section line B-B' of the lower part. To clearly illustrate the package element 1a of this modified embodiment, Figure 4 This shows a partial cross-sectional view of packaged element 1a, but is not limited to this. For example... Figure 4As shown, in the packaged element 1a, the test pattern 12a may not include the second conductive pattern 123. In some embodiments, the top view shape of the first conductive pattern 121 of the test pattern 12a may be the same as or different from the top view shape of the through hole 122a. For example, the top view shape of the first conductive pattern 121 may include a circle, and the top view shape of the through hole 122a may include a rectangle, but is not limited thereto. The top view shape of the first conductive pattern 121 and the top view shape of the through hole 122a may be adjusted according to actual needs. The method of manufacturing the packaged element 1a may omit the second conductive pattern 123 in the step of forming the conductive layer 142. Other parts of the packaged element 1a and the method of manufacturing the packaged element 1a may be similar to the above embodiments, and therefore will not be repeated.

[0039] Figure 5 The diagram shown is a top view of a test pattern according to another embodiment of the present invention. Figure 6 The diagram shown is a cross-sectional view of a packaging element according to another embodiment of the present invention. Figure 6 The right-side structural portion can be along Figure 5 A cross-sectional view along section line C-C'. (See diagram.) Figure 5 and Figure 6 As shown, in the packaged element 2, the first conductive pattern 121 of the test pattern 22 includes multiple sub-sections (e.g., sub-sections 1211, 1212, 1213, 1214, 1215), which may have similar top-view shapes, but are not limited thereto. In some embodiments, the multiple sub-sections (e.g., sub-sections 1211, 1212, 1213, 1214, 1215) may be arranged along at least one direction or along multiple directions, for example, along direction D1 and / or direction D2. Direction D1 is different from direction D2; direction D1 is, for example, perpendicular to direction D2, but is not limited thereto. In some embodiments, the dimensions of the multiple sub-sections (e.g., sub-sections 1211, 1212, 1213, 1214, 1215) may increase or decrease sequentially, for example, along the at least one direction. It should be noted that the above sequential increase or decrease does not mean that the dimensions need to change proportionally. Figure 5 In the illustrated embodiment, multiple sub-parts (e.g., sub-parts 1211, 1212, 1213, 1214, 1215) may each include a notch 121a. Since the dimensions of the multiple sub-parts increase along direction D1, direction D2, and / or other directions, the width of the notch 121a also increases along direction D1, direction D2, and / or other directions, but is not limited thereto. By detecting notches 121a of different widths, the conductive layer 142 (e.g., ...) can be determined. Figure 6 The quality of the patterning process in different areas (as shown). In some embodiments, the top view shape of these sub-parts may be, for example, C-shaped, E-shaped, or other suitable shapes with notches. By detecting first conductive patterns arranged along different directions and having different notch widths 121a, the conductive layer 142 (as shown) can be determined. Figure 6 (As shown) Formation quality in different directions or regions.

[0040] It should be noted that, as Figure 6 As shown, the test pattern 22 can be formed from the first conductive pattern 121 (including multiple sub-parts) without including the second dielectric layer 143. In this case, the testing step of the conductive layer 142 can be performed before the formation of the second dielectric layer 143, but is not limited thereto. In this embodiment, the second dielectric layer 143 can be disposed on the first conductive pattern 121 without having a through hole 122a, so the step of forming the second dielectric layer 143 may not include forming the through hole 122a, but is not limited thereto. The fabrication method of other parts of the package element 2 can be similar to the above embodiment, and therefore will not be repeated.

[0041] Figure 7 The diagram shown is a top view of a test pattern according to another embodiment of the present invention. Figure 7 As shown, the first conductive pattern 121 of test pattern 22a may include multiple sub-sections (e.g., sub-sections 1211, 1212, 1213, 1214 and / or 1215). The multiple sub-sections may be arranged radially, but are not limited thereto. Figure 7 In the embodiments, the top view shape of the plurality of sub-parts of the first conductive pattern 121 is E-shaped, but it is not limited to this; the top view shape of these sub-parts can be other suitable shapes. In detail, the first conductive pattern 121 of the test pattern 22a may include a plurality of sub-parts 1211, a plurality of sub-parts 1212, a plurality of sub-parts 1213, a plurality of sub-parts 1214 and / or a plurality of sub-parts 1215, arranged sequentially from the center of the test pattern 22a to the periphery of the test pattern 22a, and having sizes that increase sequentially from small to large, but it is not limited to this. For example, sub-part 1211 may be located approximately in the center of test pattern 22a (or first conductive pattern 121). Sub-part 1211 may be arranged sequentially along direction D1 with sub-parts 1212, 1213, 1214, and 1215. Sub-part 1211 may be arranged sequentially along direction D2 with another sub-part 1212, 1213, 1214, and 1215, and so on. Sub-part 1211 may be arranged sequentially along direction D3, direction D4, or other directions with other sub-parts 1212, 1213, 1214, and 1215. Directions D1, D2, D3, and D4 may be different from or not parallel to each other. In some embodiments, the dimensions of sub-parts 1211, 1212, 1213, 1214 and 1215 may also be in descending order, but are not limited thereto.

[0042] In some embodiments, sub-parts having substantially the same size may be located on a circle centered on sub-part 1211 (e.g., Figure 7The dashed circles (20A, 20B, 20C, and 20D) shown are used. For example, sub-sections 1212 of approximately the same size can be located approximately on dashed circle 20A, and their shortest distances (e.g., distance ds1 or distance ds2) from sub-section 1211 can be designed to be approximately the same. Similarly, other sub-sections 1213, 1214, and 1215 can be located on other dashed circles (20B, 20C, and 20D) centered on sub-section 1211. It should be noted that the notches 121a of sub-sections located approximately on the same dashed circle (20A, 20B, 20C, and 20D) can face the same or different directions. With this design, the formation quality of other conductive elements (e.g., traces) on the same layer as the test pattern 22a (or the first conductive pattern 121) can be detected in different directions or areas.

[0043] Figure 8 The diagram shown is a cross-sectional view of a packaging element according to another embodiment of the present invention. Figure 8 As shown, in packaged element 4, redistribution layer 14 may be disposed on carrier 16, and carrier 16 may be included in packaged element 4. In other words, in the method of fabricating packaged element 4, redistribution layer 14 may be formed on carrier 16, and carrier 16 does not need to be removed after redistribution layer 14 is formed. Packaged element 4 may be formed, for example, by a chip-first process, but is not limited thereto. Carrier 16 may include, for example, a wafer, electronic component CE, electronic component CE surrounded by an encapsulation structure, or other components suitable for carrying redistribution layer 14 and not removed from redistribution layer 14. Electronic component CE may include, for example, a chip, but is not limited thereto. Figure 8 In some embodiments, the carrier board 16 may include an electronic component CE and an encapsulation structure 42, wherein the redistribution layer 14 may be disposed on the electronic component CE, and the encapsulation structure 42 at least surrounds the side of the electronic component CE, but is not limited thereto. In some embodiments, the encapsulation structure 42 may be disposed on the surface of the electronic component CE relative to the redistribution layer 14, or the surface of the electronic component CE relative to the redistribution layer 14 may be exposed to facilitate heat dissipation. Furthermore, the electronic component CE may have a plurality of pads 44, and the redistribution layer 14 may, for example, be electrically connected to corresponding pads 44, but is not limited thereto. Figure 8 The redistribution layer 14 of the embodiment and Figure 1 The difference in the redistribution layer 14 is that it may not include a lower pad, but rather the redistribution layer 14 is formed directly on the pad 44 of the electronic component CE, so that the traces 142a of the conductive layer 142 can be electrically connected to the pad 44, but the present invention is not limited thereto. In some embodiments, the redistribution layer 14 may also be, for example, the redistribution layer of any of the above embodiments, and the lower pad of the redistribution layer 14 is disposed on the pad 44 corresponding to the electronic component CE. Since other parts of the redistribution layer 14 can be connected to... Figure 1 , Figure 4 or Figure 6 The redistribution layer 14 shown is the same, so it will not be described in detail here. Additionally, the test pattern 12 can be set on the carrier board 16, and the test pattern 12 can be... Figure 1 and Figures 4 to 7 Any of the test patterns, so I won't go into details here.

[0044] exist Figure 8 In the fabrication method of this embodiment, the electronic component CE can be disposed on another substrate (not shown) with the chip-first fabrication process and the surface having the pad 44 facing down, and an encapsulation process is performed to form an encapsulation structure 42 on the electronic component CE. Next, the other substrate is removed, and the electronic component CE and the encapsulation structure 42 are flipped so that the surface having the pad 44 faces up. Then, a redistribution layer 14 is formed on the electronic component CE and the encapsulation structure 42. The method for forming the redistribution layer 14 can be the same as or similar to the method for forming the redistribution layer in any of the above embodiments, and therefore will not be described in detail here. After completing the redistribution layer 14 or subsequent processes, the redistribution layer 14 can be diced to form a package element 4 containing the electronic component CE. In some embodiments, conductive bumps or conductive balls can be selectively provided on the upper pad 145a of the redistribution layer 14 to facilitate electrical connection with other electronic components.

[0045] Figure 9 The diagram shown is a schematic representation of the position of the test pattern according to another embodiment of the present invention. Figure 9 As shown, the provided carrier board 16 may have multiple component areas 16a and peripheral areas 16b surrounding the multiple component areas 16a, but is not limited thereto. A packaged component 3 may be formed in the component area 16a. A redistribution layer 14 (not shown, but can be referenced) is formed on the carrier board 16. Figures 1 to 4 or Figure 8 The redistribution layer 14 includes a test pattern 32, at least one test pattern 32 being disposed on at least one of the component region 16a and the peripheral region 16b. The package element 3 may, for example, include the package element of any of the above embodiments, and the test pattern 32 may, for example, include the test pattern of any of the above embodiments. Figure 9 In some embodiments, when the test pattern 32 is formed in the peripheral area 16b of the carrier 16, the test pattern 32 may be adjacent to the corners and / or sides of the carrier 16, located in the center of the carrier 16 and / or other peripheral areas 16b, but is not limited thereto. In some embodiments, when the test pattern 32 is formed in the package element 3, the test pattern 32 may be adjacent to the corners, sides, and / or other areas of the package element 3, but is not limited thereto.

[0046] In some embodiments, after multiple packaged elements 3 are completed, for example after the corresponding redistribution layer 14 portion is completed in the element area 16a, the peripheral area 16b is removed, and the test pattern 32 formed in the peripheral area 16b of the carrier board 16 is also removed.

[0047] Figure 10 The diagram shows the location of a test pattern within a packaged element according to another embodiment of the present invention. Figure 10 As shown, the test pattern 32 can be distributed at different locations on the package element 3. For example, the test pattern 32 can be located between two adjacent upper pads 145a and / or disposed at a corner of the package element 3. In some embodiments, the size of the test pattern 32 can be, for example, smaller than the upper pad 145a, but is not limited thereto. In other embodiments, the size relationship between the test pattern 32 and the upper pad 145a can be designed as needed. The test pattern 32 can, for example, include a combination of at least one or at least two of the test patterns in the above embodiments, but is not limited thereto.

[0048] In summary, in the method for manufacturing the packaged element of the present invention, since a test pattern is formed simultaneously during the manufacturing process of the packaged element, the quality and / or alignment accuracy of the patterning process can be detected in real time by identifying the test pattern, thereby improving the process yield.

[0049] The above description is merely an embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A packaged element, characterized in that, include: A redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, wherein the conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern, which includes a first conductive pattern, a dielectric pattern, and a second conductive pattern, wherein the first conductive pattern is formed by the conductive layer. The dielectric pattern corresponds to the first conductive pattern, and the dielectric pattern is formed by the second dielectric layer. The second conductive pattern is adjacent to the first conductive pattern, the second conductive pattern is formed by the conductive layer, the second conductive pattern has an opening, and in a top view, the first conductive pattern is located in the opening.

2. The packaged element as claimed in claim 1, characterized in that, The dielectric pattern has a perforation that exposes the first conductive pattern.

3. The packaged element as claimed in claim 1, characterized in that, The redistribution layer further includes a trace formed by the conductive layer, the trace being electrically connected to an electronic component disposed on the redistribution layer, and the trace being electrically insulated from the test pattern.

4. The packaged element as claimed in claim 1, characterized in that, The conductive layer is a multilayer structure, and the multilayer structure includes a seed layer and a metal layer stacked in sequence.

5. A packaged element, characterized in that, include: A redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, wherein the conductive layer is disposed between the first dielectric layer and the second dielectric layer, and wherein the redistribution layer has a test pattern, the test pattern including a first conductive pattern, and the first conductive pattern being formed by the conductive layer. The first conductive pattern includes a plurality of sub-parts arranged along at least one direction, and the size of the plurality of sub-parts increases sequentially along the at least one direction.

6. A packaged element, characterized in that, include: A redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, wherein the conductive layer is disposed between the first dielectric layer and the second dielectric layer, and wherein the redistribution layer has a test pattern, the test pattern including a first conductive pattern, and the first conductive pattern being formed by the conductive layer. The first conductive pattern includes multiple sub-parts, and the multiple sub-parts are arranged radially.

7. A method for manufacturing a packaged component, characterized in that, include: Provide a carrier board; as well as A wiring layer is formed on the carrier board. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, with the conductive layer disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test pattern, which includes a first conductive pattern, a dielectric pattern, and a second conductive pattern, wherein the first conductive pattern is formed by the conductive layer. The dielectric pattern corresponds to the first conductive pattern, and the dielectric pattern is formed by the second dielectric layer. The second conductive pattern is adjacent to the first conductive pattern, the second conductive pattern is formed by the conductive layer, the second conductive pattern has an opening, and in a top view, the first conductive pattern is located in the opening.

8. The method for manufacturing a packaged element as described in claim 7, characterized in that, The carrier plate has multiple component areas and a peripheral area surrounding the multiple component areas, and the test pattern is disposed on at least one of the multiple component areas and the peripheral area.

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