Integrated circuit and method of manufacturing the same

Abstract

An integrated circuit (IC) having an array of active device cells and an array of dummy device cells and a method of manufacturing the same are disclosed. The IC includes a substrate, active device cells, and dummy device cells. The active device cells include an array of source / drain (S / D) regions of a first conductivity type disposed on or within the substrate and an array of gate structures having a first gate fill material disposed on the substrate. The dummy device cells include a first array of S / D regions of the first conductivity type disposed on or within the substrate, a second array of S / D regions of a second conductivity type disposed on or within the substrate, and an array of double gate structures disposed on the substrate. Each double gate structure includes a first gate fill material and a second gate fill material different from the first gate fill material.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate to integrated circuits and methods of manufacturing the same. BACKGROUND

[0002] As semiconductor technology advances, there is an ever-increasing demand for higher storage capacity, faster processing systems, higher performance, and lower cost. To meet these demands, the semiconductor industry continues to scale down the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (finFETs). This scaling increases the complexity of the semiconductor manufacturing process. SUMMARY

[0003] Embodiments of the present invention provide an integrated circuit, comprising: a substrate; an active device unit comprising: an array of source / drain (S / D) regions of a first conductivity type disposed on or within the substrate; and an array of gate structures having a first gate fill material disposed on the substrate; and a dummy device unit comprising: a first array of S / D regions of the first conductivity type disposed on or within the substrate; a second array of S / D regions of a second conductivity type disposed on or within the substrate; and an array of dual gate structures disposed on the substrate, wherein each of the dual gate structures comprises the first gate fill material and a second gate fill material different from the first gate fill material.

[0004] Another embodiment of the present invention provides an integrated circuit, comprising: a substrate; a first active source / drain (S / D) region and a second active S / D region disposed on or within the substrate; an active gate structure having a gate fill layer disposed on the substrate; a first dummy S / D region and a second dummy S / D region disposed on or within the substrate; a dummy gate structure disposed on the substrate, wherein the dummy gate structure comprises a first gate fill layer and a second gate fill layer different from the first gate fill layer, and wherein the first gate fill layer has a first top surface area and the second gate fill layer has a second top surface area equal to the first top surface area.

[0005] Yet another embodiment of the present invention provides a method of fabricating an integrated circuit, comprising: forming a first fin structure and a second fin structure on a substrate; forming a first source / drain (S / D) region and a second S / D region on the first fin structure and the second fin structure, respectively; forming a first polysilicon structure and a second polysilicon structure on the first fin structure and the second fin structure, respectively; replacing a first portion of the first polysilicon structure and the second polysilicon structure with a first metal layer; polishing the first metal layer at a first polishing rate; replacing a second portion of the second polysilicon structure with a second metal layer different from the first metal layer; and polishing the second metal layer at a second polishing rate different from the first polishing rate. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the present invention can best be understood with reference to the following detailed description when read in conjunction with the accompanying drawings.

[0007] FIGS. 1A-1J Top and cross-sectional views of active and dummy cells of an integrated circuit are shown in accordance with some embodiments.

[0008] FIGS. 1K-1O Top and cross-sectional views of active and dummy cells of an integrated circuit are shown in accordance with some embodiments.

[0009] FIGS. 2A-2J Top and cross-sectional views of active and dummy cells of an integrated circuit are shown in accordance with some embodiments.

[0010] FIGS. 2K-2M Isometric views of active and dummy cells of an integrated circuit are shown in accordance with some embodiments.

[0011] FIG. 3 is a flowchart of a method for fabricating active and dummy cells of an integrated circuit in accordance with some embodiments.

[0012] FIGS. 4A-13G Cross-sectional views of active and dummy cells of an integrated circuit at various stages of their fabrication process are shown in accordance with some embodiments.

[0013] FIG. 14 is a flowchart of another method for fabricating active and dummy cells of an integrated circuit in accordance with some embodiments.

[0014] FIGS. 15A-22C Cross-sectional views of active and dummy cells of another integrated circuit at various stages of their fabrication process are shown in accordance with some embodiments.

[0015] Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally refer to like, functionally similar, and / or structurally similar elements. The description of elements or implementation with like reference numerals being applicable to each other applies regardless of the drawing in which the reference numerals are introduced, unless otherwise noted. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are in no way limiting of the scope of the present application. For example, in the following description, forming a first part over or on a second part can include embodiments where the first part and the second part are in direct contact, and can also include embodiments where additional parts can be formed between the first part and the second part, such that the first part and the second part can not be in direct contact. As used herein, forming a first part on a second part means that the first part is formed in direct contact with the second part. Furthermore, the present application can refer to a number and / or letter of various examples. This repetition is not intended to indicate a relationship between embodiments and / or configurations discussed herein.

[0017] For purposes of the description hereinafter, spatial or directional terms, such as "below," "above," "lower," "upper," "upward," "downward," and the like, can be used where appropriate to describe the various example embodiments. These terms are used herein as descriptors of relative positions and do not necessarily imply a particular orientation of the device. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial or directional descriptors used herein interpreted accordingly.

[0018] It should be noted that a description herein referencing "one embodiment," "an embodiment," "example embodiment," "exemplary," and the like, means that a particular element, structure, or characteristic described in connection with the embodiment can be included in, or can be associated with, a corresponding element, structure, or characteristic in one or more of the embodiments, but not necessarily in every embodiment. Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0019] It should be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art in light of the teachings and / or disclosures of the present specification.

[0020] In some embodiments, the terms“about” and“substantially” can mean a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms“about” and“substantially” can refer to a percentage of a value as interpreted by one of skill in the relevant art in light of the teachings herein.

[0021] The fin structures disclosed herein can be patterned by any suitable method. For example, the fin structures can be patterned using one or more photolithography processes, including a double patterning or multiple patterning process. Double patterning or multiple patterning processes can incorporate photolithography and self-alignment processes, allowing for the creation of patterns with, for example, smaller pitches than are obtainable using a single direct photolithography process. For example, a sacrificial layer is formed over a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structures.

[0022] The present disclosure provides example integrated circuits (ICs) having active device cell arrays and dummy device cell arrays in respective active and dummy device regions, and example methods of fabricating the same. An example IC can include n-type and / or p-type active device cell arrays. An n-type active device cell array can include an array of active n-type cells (N-cells). Each active N-cell can include one or more electrically active n-type FETs (NFETs; e.g., NMOSFETs, NfinFETs, or gate-all-around (GAA) NFETs) and / or n-type structures such as n-type source / drain (S / D) regions and n-type metal gate (NMG) structures with n-type gate metal fill (e.g., n-type work function metal (nWFM)).

[0023] A p-type active device cell array can include an array of active p-type cells (P-cells). Each active P-cell can include one or more electrically active p-type FETs (PFETs; e.g., PMOSFETs, PfinFETs, or gate-all-around (GAA) PFETs) and / or p-type structures such as p-type S / D regions and p-type metal gate (PMG) structures with p-type gate metal fill (e.g., p-type WFM (nWFM)). The active N-cells and P-cells can also include contact structures disposed on one or more source / drain regions and gate structures. The contact structures can electrically couple the one or more source / drain regions and gate structures to a power source.

[0024] The term "N-cell" (also known as "N-device cell") is used herein to refer to a cell that includes NFET and / or NMG structures but excludes PFET and / or PMG structures. The term "P-cell" (also known as "P-device cell") is used herein to refer to a cell that includes PFET and / or PMG structures but excludes NFET and / or NMG structures. The term "NP-cell" (also known as "NP-device cell") is used herein to refer to a cell that includes NFET and PFET and / or NMG and PMG structures.

[0025] The dummy device cell array can be configured adjacent to or surrounding the active device cell array and can include electrically passive (“dummy”) N-cells, P-cells, and / or NP-cells. Unlike active N-cells and P-cells, dummy N-cells, P-cells, and NP-cells do not include contact structures and / or contact bonding pads or regions located on the S / D region and / or gate structure. In some embodiments, dummy N-cells and P-cells may have gate structures similar to those of the corresponding active N-cells and P-cells.

[0026] Pseudo-device cell arrays can be formed and arranged to achieve a substantially uniform surface profile on the gate structures in both types of active device cell arrays. Non-uniform surface profiles on the gate structures lead to gate height mismatch between gate structures in the active device cell array, thus degrading IC performance. To achieve a substantially uniform surface profile in both types of active device cell arrays, each pseudo-device cell array can be formed with a gate surface area ratio of approximately 1:1 between the total top surface area of ​​the pseudo-NMG structure and the total top surface area of ​​the pseudo-PMG structure in the pseudo-device cell array. This balanced gate surface area ratio between the pseudo-NMG and PMG structures during the formation of the active NMG and PMG structures in the active device cell array prevents or minimizes "dimples" caused by the chemical mechanical polishing (CMP) process. When the pseudo-device cell array has only one type of gate structure (such as a polysilicon gate structure, NMG structure, and PMG structure), the dimming effect may be due to the different polishing rates between the gate structures in the pseudo-device cell array and the active device cell array. The polishing rates can vary for different materials used in polysilicon gate structures, NMG structures, and PMG structures. Therefore, the balanced distribution of the two types of gate structures in the pseudo-device cell array provides a matching polishing rate for each type of gate structure in the active device cell array, and thus prevents or minimizes the recess effect associated with the CMP process.

[0027] In some embodiments, each pseudo-device cell array may be formed with the same number of pseudo-N cells and P cells to achieve a balanced gate surface area ratio. In some embodiments, the pseudo-N cells and P cells may be arranged in an array configuration or in an alternating configuration relative to each other. The pseudo-N cells may have the same number of pseudo-NMG structures as the pseudo-P cells. In some embodiments, the pseudo-NMG and PMG structures may have substantially equal gate dimensions (e.g., gate length, gate width, and gate height). In some embodiments, the pseudo-NMG structure may have a total top surface area substantially equal to the total top surface area of ​​the pseudo-PMG structure. In some embodiments, each pseudo-device cell array may be formed by an array of NP cells having the same number of pseudo-NFETs and PFETs and / or the same number of pseudo-NMG and PMG structures to achieve a balanced gate surface area ratio. In some embodiments, adjacent pseudo-NMG structures may be separated by an n-type S / D region, and adjacent pseudo-PMG structures may be separated by a p-type S / D region. In some embodiments, adjacent pseudo-NMG structures and adjacent pseudo-PMG structures may be separated by S / D regions of the same conductivity type (e.g., n-type or p-type).

[0028] FIGS. 1A-1C Top views of an active P-cell 102P, an active N-cell 102N, and a pseudo-NP-cell 102NP of an IC (not shown) according to some embodiments are shown respectively. FIGS. 1D-1F The following is illustrated according to some embodiments. FIGS. 1A-1C Cross-sectional views of active P-cell 102P, active N-cell 102N, and pseudo-NP-cell 102NP for lines AA, BB, and CC. FIGS. 1G-1J The following is illustrated according to some embodiments. FIGS. 1A-1C Cross-sectional views of active P-cell 102P, active N-cell 102N, and pseudo-NP-cell 102NP for lines DD, EE, FF, and GG. FIGS. 1D-1J It shows that, for simplicity, it is not shown in FIGS. 1A-1C The cross-sectional view of the additional structure is shown in the figure. Unless otherwise noted, the same annotations apply. FIGS. 1A-1J The discussion of the components in the text is applicable to each other.

[0029] refer to FIGS. 1A-1JActive P-cells 102P, active N-cells 102N, and pseudo-NP-cells 102NP can be disposed on different regions of the substrate 104 of the IC. Active P-cells 102P and active N-cells 102N can be disposed in the active device region of the IC, and pseudo-NP-cells 102NP can be disposed in the pseudo device region of the IC. In some embodiments, active P-cells 102P, active N-cells 102N, and pseudo-NP-cells 102NP can be arranged in rows or columns on the substrate 104, and pseudo-NP-cells 102NP can be disposed between active P-cells 102P and active N-cells 102N. Unlike active P-cells 102P and active N-cells 102N, pseudo-NP-cells 102NP are not electrically coupled to any power source and are electrically isolated from other structures of the IC. In some embodiments, the IC may include any number of active P-cells 102P, active N-cells 102N, and pseudo-NP-cells 102NP. In some embodiments, pseudo-NP units (such as pseudo-NP unit 102NP) may be configured to surround one or more of active P units 102P and / or active N units 102N.

[0030] The substrate 104 may be a semiconductor material, such as silicon, germanium (Ge), silicon-germanium (SiGe), silicon-on-insulator (SOI) structures, other suitable semiconductor materials, and combinations thereof. Furthermore, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, gallium, or other suitable p-type dopant) or an n-type dopant (e.g., phosphorus, arsenic, or other suitable n-type dopant).

[0031] refer to FIG. 1A , FIG. 1D and FIG. 1G In some embodiments, the active P-cell 102P may include (i) a well region 106P disposed within a substrate 104, (ii) an array of S / D regions 110P disposed within the well region 106P, (iii) an array of PMG structures 112P, (iv) a gate spacer 114 disposed along the gate sidewall of the PMG structure 112P, (v) a shallow isolation trench (STI) region 116 disposed on the substrate 104, (vi) interlayer dielectric (ILD) layers 118A-118B, (vii) an S / D contact structure 128P disposed on the S / D region 110P, and (viii) a gate contact structure 130P disposed on one of the PMG structures 112P.

[0032] In some embodiments, well region 106P may represent an n-type well region and may include n-type dopants such as phosphorus, arsenic, and other suitable n-type dopants. S / D region 110P may include p-type dopants such as boron, indium, aluminum, gallium, and other suitable p-type dopants, with a doping concentration higher than that of well region 106P. In some embodiments, S / D region 110P and PMG structure 112P inserted between S / D region 110P may form a p-type MOSFET. In some embodiments, active P-cell 102P may have any number of p-type MOSFETs.

[0033] In some embodiments, the PMG structure 112P may include (i) an interface oxide (IO) layer 120P disposed on the well region 106P, (ii) a high-k (HK) gate dielectric layer 122P disposed on the IO layer 120P, (iii) a pWFM layer 124P disposed on the HK gate dielectric layer 122P, and (iv) a gate metal filling layer 126P disposed on the pWFM layer 124P. In some embodiments, the IO layer 120P may include silicon oxide (SiO2). x ), silicon germanium oxide (SiGeO) x germanium oxide (GeO) x Or other suitable oxide materials. In some embodiments, the HK gate dielectric layer 122P may include (i) a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and (ii) having lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), or strontium (Sr) elements. High-k dielectric materials of oxides of scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu), (iii) other suitable high-k dielectric materials, and (iii) combinations thereof. As used herein, the term “high-k” refers to a high dielectric constant. In the field of semiconductor device structures and manufacturing processes, high-k refers to a dielectric constant greater than that of SiO2 (e.g., greater than 3.9).

[0034] In some embodiments, the pWFM layer 124P may comprise a substantially Al-free (e.g., Al-free) Ti-based or Ta-based nitride or alloy, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium-gold (Ti-Au) alloy, titanium-copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum-gold (Ta-Au) alloy, tantalum copper (Ta-Cu), other suitable substantially aluminum-free conductive materials, and combinations thereof. In some embodiments, the gate metal fill layer 126P may comprise a suitable conductive material, such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), other suitable conductive materials, and combinations thereof. In some embodiments, the gate metal fill layer 126P may comprise a substantially fluorine-free metal layer (e.g., fluorine-free W). The substantially fluorine-free metal layer may comprise an amount of fluorine contaminants in ionic, atomic, and / or molecular form of less than about 5 atomic percentages.

[0035] In some embodiments, the S / D contact structure 128P and the gate contact structure 130P may include conductive materials with low resistivity (e.g., resistivity of about 50 μΩ-cm, about 40 μΩ-cm, about 30 μΩ-cm, about 20 μΩ-cm-cm, or about 10 μΩ-cm), such as cobalt (Co), tungsten (W), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), other suitable conductive materials with low resistivity, and combinations thereof. In some embodiments, the gate spacer 114, the STI region 116, and the ILD layers 118A-118B may include insulating materials, such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon germanium oxide, and other suitable insulating materials.

[0036] refer to FIG. 1B , FIG. 1E and FIG. 1H In some embodiments, the active N-cell 102N may include (i) a well region 106N disposed within a substrate 104, (ii) an array of S / D regions 110N disposed within the well region 106N, (iii) an array of NMG structures 112N, (iv) a gate spacer 114 disposed along the gate sidewall of the NMG structure 112N, (v) an STI region 116 disposed on the substrate 104, (vi) ILD layers 118A-118B, (vii) an S / D contact structure 128N disposed on the S / D region 110N, and (viii) a gate contact structure 130N disposed on one of the NMG structures 112N.

[0037] In some embodiments, the well region 106N may include a p-type dopant, such as boron, indium, aluminum, gallium, and other suitable p-type dopant. The S / D region 110N may include an n-type dopant, such as phosphorus, arsenic, and other suitable n-type dopant, with a doping concentration higher than that of the well region 106N. In some embodiments, the S / D region 110N and the NMG structure 112N interposed between the S / D region 110N may form an n-type MOSFET. In some embodiments, the active N-cell 102N may have any number of n-type MOSFETs.

[0038] In some embodiments, the NMG structure 112N may include (i) an IO layer 120N disposed on the well region 106N, (ii) an HK gate dielectric layer 122N disposed on the IO layer 120N, (iii) an nWFM layer 124N disposed on the HK gate dielectric layer 122N, and (iv) a gate metal fill layer 126N disposed on the nWFM layer 124N. In some embodiments, the nWFM layer 124N may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-based conductive materials, and combinations thereof. Unless otherwise stated, the discussion of the IO layer 120P, the HK gate dielectric layer 122P, and the gate metal fill layer 126P applies to the IO layer 120N, the HK gate dielectric layer 122N, and the gate metal fill layer 126N. In some embodiments, the pWFM layer 124P and the gate metal fill layer 126P are different from the nWFM layer 124N and the gate metal fill layer 126N. As a result, according to some embodiments, the PMG structure 112P and the NMG structure 112N can be formed sequentially, rather than simultaneously.

[0039] refer to FIG. 1C , FIG. 1F and FIGS. 1I-1JIn some embodiments, the pseudo-NP cell 102NP may include (i) an array of well regions 107P-107N disposed within the substrate 104, (ii) an array of S / D regions 111P-111N disposed within the respective well regions 107P-107N, (iii) an array of dual-gate structures 115, (iv) gate spacers 114 disposed along the gate sidewalls of the dual-gate structures 115, (v) an STI region 116 disposed on the substrate 104, and (vi) ILD layers 118A-118B. Unlike the active P cell 102P and the active N cell 102N, the pseudo-NP cell 102NP does not have S / D contact structures and gate contact structures. Unless otherwise stated, the discussion of well regions 106P-106N and S / D regions 110P-110N applies to well regions 107P-107N and S / D regions 111P-111N, respectively. In some embodiments, instead of well regions 107P and 107N with different conductivity types, the pseudo-NP unit 102NP may have well regions 107P and 107N with the same conductivity type or may have well regions similar to well regions 106P or 106N. Similarly, in some embodiments, instead of S / D regions 111P and 111N with different conductivity types, the pseudo-NP unit 102NP may have S / D regions with the same conductivity type or may have an array of S / D regions similar to S / D regions 110P or 110N. In some embodiments, the pseudo-NP unit 102NP does not include well regions 107P-107N and / or S / D regions 111P-111N.

[0040] In some embodiments, each dual-gate structure 115 may include a pseudo-PMG structure 113P and a pseudo-NMG structure 113N, with the gate end face of the pseudo-NMG structure 113N adjacent to the gate end face of the pseudo-PMG structure 113P. The term "gate end face" is used herein to refer to the side surface of the gate structure along the gate length of the gate structure (e.g., along the X-axis). The term "gate sidewall" is used herein to refer to the side surface of the gate structure along the gate width of the gate structure (e.g., along the Y-axis). Unless otherwise stated, the discussion of PMG structures 112P and NMG structures 112N applies to the corresponding pseudo-PMG structures 113P and pseudo-NMG structures 113N. In some embodiments, the gate lengths GL1, GL2, GL3, and GL4 of the corresponding PMG structures 112P, NMG structures 112N, pseudo-PMG structures 113P, and pseudo-NMG structures 113N are substantially equal to each other. In some embodiments, the gate lengths GL3 and GL4 are substantially equal to each other and are different from the corresponding gate lengths GL1 and GL2. In some embodiments, gate widths GW1 and GW2 are substantially equal to each other. In some embodiments, the cell area along the XY plane of the pseudo-NP cell 102NP may be substantially equal to or different from the cell area along the XY plane of the active P cell 102P and / or the active N cell 102N.

[0041] In some embodiments, the cell area along the XY plane of the pseudo-NP cell 102NP can be from approximately 1 μm. 2 Approximately 9μm 2 Within the range of other suitable sizes. In some embodiments, the S / D region 111P and the PMG structure 113P inserted between the S / D region 111P can form a p-type MOSFET. In some embodiments, the S / D region 111N and the NMG structure 113N inserted between the S / D region 111N can form an n-type MOSFET.

[0042] In some embodiments, the gate top surface area along the XY plane of each pseudo-PMG structure 113P is substantially equal to the gate top surface area along the XY plane of each pseudo-NMG structure 113N. Therefore, the pseudo-NP cell 102NP has an approximately 1:1 gate top surface area ratio between the total gate top surface area of ​​the pseudo-PMG structures 113P and the total gate top surface area of ​​the pseudo-NMG structures 113N. This balanced gate top surface area ratio between the pseudo-PMG structures 113P and the NMG structures 113N prevents or minimizes CMP process-related recess effects in the array of PMG structures 112P and NMG structures 112N to achieve a substantially uniform gate top surface profile in the active P cells 102P and active N cells 102N. Recess effects can lead to non-uniform gate top surface profiles (e.g., FIGS. 1G-1HThe concave profiles 132P-132N shown in the diagram result in a mismatch between the gate height GH1 of the PMG structure 112P and the gate height GH2 of the NMG structure 112N, thus reducing IC performance.

[0043] If the gate top surface area ratio between the pseudo-PMG structure 113P and the NMG structure 113N is unbalanced, the CMP process-related sinking effect may not be prevented or minimized in either or both of the arrays of PMG structure 112P and NMG structure 112N. For example, if the pseudo-NP cell 102NP has a polysilicon structure or only an NMG structure instead of the dual-gate structure 115, the CMP process-related sinking effect will occur in the active P cell 102P during fabrication due to the polishing rate mismatch between the materials of the PMG structure 112P and the polysilicon or NMG structure. Furthermore, the CMP process-related sinking effect will occur in the active N cell 102N during fabrication due to the polishing rate mismatch between the materials of the NMG structure 112N and the polysilicon structure.

[0044] Similarly, if the pseudo-NP cell 102NP has a polysilicon structure or only a PMG structure instead of the dual-gate structure 115, a CMP-related dent effect will occur in the active N cell 102N due to the polishing rate mismatch between the materials of the NMG structure 112N and the polysilicon or PMG structure, and a CMP-related dent effect will occur in the active P cell 102N due to the polishing rate mismatch between the materials of the PMG structure 112P and the polysilicon structure. Therefore, a balanced distribution of the pseudo-PMG structure 113P and the pseudo-NMG structure 113N can provide a matching polishing rate for the PMG structure 112P and the NMG structure 112N to substantially uniformly polish the gate top surface during the fabrication of the active P cell 102P and the active N cell 102N. As a result, substantially equal gate heights GH1, GH2, GH3 and GH4 can be achieved for the corresponding PMG structure 112P, NMG structure 112N, pseudo-PMG structure 113P and pseudo-NMG structure 113N.

[0045] In some embodiments, in order to achieve a substantially uniform gate top surface profile in the active P-cell 102P, the total gate top surface area of ​​the pseudo-PMG structure 113P is smaller than the total gate top surface area of ​​the PMG structure 112P. Similarly, in some embodiments, in order to achieve a substantially uniform gate top surface profile in the active N-cell 102N, the total gate top surface area of ​​the pseudo-NMG structure 113N is smaller than the total gate top surface area of ​​the NMG structure 112N.

[0046] FIGS. 1A-1IThe number of well regions, S / D regions, and gate structures shown is exemplary. The active P-cell 102P, active N-cell 102N, and pseudo-NP-cell 102NP can have any number of well regions, S / D regions, and gate structures.

[0047] refer to FIGS. 1K-1L In some embodiments, the IC may include a plurality of active P cells 102P forming an active P cell array 100P and a plurality of active N cells 102N forming an active N cell array 100N in an active device region on the substrate 104, and may include pseudo NP cells 102NP forming a pseudo NP cell array 100NP in a pseudo device region on the substrate 104. FIG. 1K A top view of an active P-cell array 100P, an active N-cell array 100N, and a pseudo-NP-cell array 100NP according to some embodiments is shown. FIGS. 1L-1M The following is illustrated according to some embodiments. FIG. 1K Cross-sectional views of the active P-cell array 100P, active N-cell array 100N, and pseudo-NP-cell array 100NP of lines HH and JJ. For simplicity, some components of the active P-cell 102P, active N-cell 102N, and pseudo-NP-cell 102NP are not shown. FIGS. 1K-1M As shown in the figure. Although the array sizes of the active P-cell array 100P and the active N-cell array 100N are shown as equal to each other and different from the array size of the pseudo NP-cell array 100NP, the array sizes of the active P-cell array 100P, the active N-cell array 100N, and the pseudo NP-cell array 100NP may be equal to or different from each other. The IC may include any number of active P-cell arrays 100P, active N-cell arrays 100N, and pseudo NP-cell arrays 100NP. In some embodiments, the distance D1 between the active P-cell array 100P and the pseudo NP-cell array 100NP and the distance D2 between the active N-cell array 100N and the pseudo NP-cell array 100NP may be equal to or different from each other, and may be in the range of about 100 nm to about 1000 nm or other suitable sizes. FIGS. 1L-1M The balanced gate top surface area ratio between the PMG structure 113P and the NMG structure 113N in the pseudo-NP cell array 100NP is shown to result in a substantially uniform surface profile and substantially equal gate heights GH1 and GH2 on the PMG structure 112P and the NMG structure 112N.

[0048] In some embodiments, instead of the pseudo-NP cell array 100NP, the following can be utilized: FIG. 1N The pseudo-NP cell array 136NP shown is FIG. 1OThe illustrated pseudo-NP cell array 138NP achieves a balanced gate top surface area ratio of approximately 1:1 between the pseudo-PMG structure and the NMG structure. Each of the pseudo-NP cell arrays 136NP and 138NP may include the same number of pseudo-P cells 134P with pseudo-PMG structure 135P and pseudo-N cells 134N with pseudo-NMG structure 135N arranged in different configurations. Therefore, each pseudo-NP cell array 136NP and 138NP has a gate top surface area ratio of approximately 1:1 between the total gate top surface area of ​​the pseudo-PMG structure 135P and the total gate top surface area of ​​the pseudo-NMG structure 135N. In some embodiments, the pseudo-P cell 134P may be similar to the pseudo-NP cell 102NP, except that the pseudo-P cell 134P includes the PMG structure 135P instead of the dual-gate structure 115. In some embodiments, the pseudo-N cell 134N may be similar to the NP cell 102NP, except that the pseudo-N cell 134N includes the NMG structure 135N instead of the dual-gate structure 115. Unless otherwise stated, the discussion of PMG structure 134P and NMG structure 134N applies to PMG structure 112P and NMG structure 112N.

[0049] FIGS. 2A-2C Top views of an active P-cell 202P, an active N-cell 202N, and a pseudo-NP-cell 202NP of an IC (not shown) according to some embodiments are shown respectively. FIGS. 2D-2F The following is illustrated according to some embodiments. FIGS. 2A-2C Cross-sectional views of active P-cell 202P, active N-cell 202N, and pseudo-NP-cell 202NP for lines AA, BB, and CC. FIGS. 2G-2J The following is illustrated according to some embodiments. FIGS. 2A-2C Cross-sectional views of active P-cell 202P, active N-cell 202N, and pseudo-NP-cell 202NP of lines DD, EE, FF, and GG. FIGS. 2K-2M The corresponding embodiments are shown. FIGS. 2A-2C An isometric view of region AC. FIGS. 2D-2M It shows that, for simplicity, it is not shown in FIGS. 2A-2C The accompanying cross-sectional views and isometric views of the additional structure are shown. Unless otherwise noted, all other views are subject to the same annotations. FIGS. 1A-1M and FIGS. 2A-2M The discussion of the components in the text is applicable to each other.

[0050] refer to FIGS. 2A-2MActive P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP can be disposed on different regions of the substrate 104 of the IC. Active P-cells 202P and active N-cells 202N can be disposed in the active device region of the IC, and pseudo-NP-cells 202NP can be disposed in the pseudo device region of the IC. In some embodiments, active P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP can be arranged in rows or columns on the substrate 204, and pseudo-NP-cells 202NP can be disposed between active P-cells 202P and active N-cells 202N. Unlike active P-cells 202P and active N-cells 202N, pseudo-NP-cells 202NP are not electrically coupled to a power source and are electrically isolated from other structures of the IC. In some embodiments, the IC may include any number of active P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP. In some embodiments, pseudo-NP units (such as pseudo-NP unit 202NP) may be configured to surround one or more of active P units 202P and / or active N units 202N.

[0051] refer to FIGS. 2A-2B , FIGS. 2D-2E , FIGS. 2G-2H and FIGS. 2K-2I In some embodiments, the active P-cell 202P and active N-cell 202N may include (i) fin structures 206P and 206N disposed on the substrate 104, (ii) arrays of S / D regions 210P and 210N disposed on the respective fin structures 206P and 206N, (iii) arrays of PMG structures 212P and NMG structures 212N disposed on the portions of the fin structures 206P and 206N that do not have S / D regions 210P and 210N, and (iv) arrays along the PMG structures. Gate spacers 114 disposed on the gate sidewalls of 212P and NMG structures 212N, (v) STI regions 116 disposed on substrate 104, (vi) ILD layers 118A-118B, (vii) etch stop layer 217, (viii) S / D contact structures 228P and 228N disposed on the respective S / D regions 210P and 210N, and (ix) gate contact structures 230P and 230N disposed on the respective PMG structures 212P and NMG structures 212N.

[0052] In some embodiments, fin structures 206P-206N may comprise a material similar to substrate 104 and extend along the X-axis. In some embodiments, S / D region 210P may comprise an epitaxially grown semiconductor material, such as Si and SiGe, and may include p-type dopants, such as boron, indium, aluminum, gallium, and other suitable p-type dopants. In some embodiments, S / D region 210N may comprise an epitaxially grown semiconductor material, such as Si, and may include n-type dopants, such as phosphorus, arsenic, and other suitable n-type dopants. In some embodiments, S / D region 210P and PMG structure 212P interposed between S / D region 210P may form a p-type finFET. In some embodiments, S / D region 210N and NMG structure 212N interposed between S / D region 210N may form an n-type finFET. Unless otherwise stated, the discussion of PMG structures 112P and NMG structures 112N, S / D contact structures 128P-128N, and gate contact structures 130P-130N applies to PMG structures 212P and NMG structures 212N, S / D contact structures 228P-228N, and gate contact structures 230P-230N. In some embodiments, ESL 217 may include insulating materials such as silicon oxide, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon germanium oxide, and other suitable insulating materials.

[0053] refer to FIG. 2C , FIG. 2F , FIGS. 2I-2J and FIG. 2M In some embodiments, the pseudo-NP cell 202NP may include (i) fin structures 207P and 207N disposed on the substrate 104, (ii) an array of S / D regions 211P-211N disposed on the respective fin structures 207P-207N, (iii) an array of dual-gate structures 215, (iv) a gate spacer 114 disposed along the gate sidewall of the dual-gate structure 215, (v) an STI region 116 disposed on the substrate 104, (vi) ILD layers 118A-118B, and (vii) an etch stop layer 217. Unlike the active P cell 202P and the active N cell 202N, the pseudo-NP cell 202NP does not have an S / D contact structure or a gate contact structure. Unless otherwise stated, the discussion of fin structures 206P-206N and S / D regions 210P-210N applies to fin structures 207P-207N and S / D regions 211P-211N, respectively. In some embodiments, the pseudo-NP cell 202NP may have an S / D region of the same conductivity type. Unless otherwise stated, the discussion of the dual-gate structure 115 applies to the dual-gate structure 215.

[0054] In some embodiments, each dual-gate structure 215 may include a pseudo-PMG structure 213P and a pseudo-NMG structure 213N, with the gate end face of the pseudo-NMG structure 213N adjacent to the gate end face of the pseudo-PMG structure 213P. In some embodiments, the S / D region 211P and the PMG structure 213P inserted between the S / D region 211P may form a p-type finFET. In some embodiments, the S / D region 211N and the NMG structure 213N inserted between the S / D region 211N may form an n-type finFET. Unless otherwise stated, the discussion of the pseudo-PMG structure 113P and the pseudo-NMG structure 113N applies to the corresponding pseudo-PMG structure 213P and pseudo-NMG structure 213N. Similar to the pseudo-NP cell 102NP, the pseudo-NP cell 202NP has a gate top surface area ratio of approximately 1:1 between the total gate top surface area of ​​the pseudo-PMG structure 213P and the total gate top surface area of ​​the pseudo-NMG structure 213N. As a result, a substantially uniform gate top surface profile can be achieved in the active P-cell 202P and the active N-cell 202N, as well as substantially equal gate heights GH1 and GH2 in the corresponding PMG structure 212P and NMG structure 212N.

[0055] In some embodiments, in order to achieve a substantially uniform gate top surface profile in the active P-cell 202P, the total gate top surface area of ​​the pseudo-PMG structure 213P is smaller than the total gate top surface area of ​​the PMG structure 212P. Similarly, in some embodiments, in order to achieve a substantially uniform gate top surface profile in the active N-cell 202N, the total gate top surface area of ​​the pseudo-NMG structure 213N is smaller than the total gate top surface area of ​​the NMG structure 212N. FIGS. 2A-2M The number of fin structures, S / D regions, and gate structures shown is exemplary. Active P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP can have any number of fin structures, S / D regions, and gate structures. In some embodiments, multiple active P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP can form an array similar to the active P-cell array 100P, active N-cell array 100N, and pseudo-NP-cell array 100NP.

[0056] FIG. 3 This is a flowchart of an example method 300 for fabricating active P-cells 102P, active N-cells 102N, and pseudo-cells 102NP on a substrate 104, according to some embodiments. For illustrative purposes, reference will be made to methods for fabricating such... FIGS. 4A-13G The example manufacturing process of the active P-cell 102P, active N-cell 102N, and pseudo-NP-cell 102NP is described below. FIG. 3 The operation shown. FIGS. 4A-13G It is according to some embodiments along FIGS. 1A-1CCross-sectional views of active P-cells 102P, active N-cells 102N, and pseudo-cells 102NP for lines AA, BB, CC, DD, EE, FF, and GG. Depending on the specific application, the operations may be performed in a different order, or not at all. It should be noted that method 300 may not produce complete active P-cells 102P, active N-cells 102N, and pseudo-cells 102NP of the IC. Therefore, it should be understood that additional processes may be provided before, during, and after method 300, and only some other processes may be briefly described herein. The above describes processes with... FIGS. 1A-1J The same annotation for the components in FIGS. 4A-13G The components in.

[0057] In operation 305, well regions, S / D regions, and polysilicon structures are formed for active P-cells, active N-cells, and pseudo-NP-cells. For example, as... FIGS. 4A-4G As shown, well regions 106P, 106N, 107P, and 107N, a polysilicon structure 412, and S / D regions 110P, 110N, 111P, and 111N are formed. After the formation of the polysilicon structure 412, a gate spacer 114 can be formed, followed by the formation of the S / D regions 110P, 110N, 111P, and 111N. After the formation of the S / D regions 110P, 110N, 111P, and 111N, an ILD layer 118A can be formed.

[0058] refer to FIG. 3 In operation 310, PMG structures are selectively formed in active P-cells and pseudo-NP-cells. For example, as referenced... FIGS. 5A-8G As described, PMG structures 112P and 113P are selectively formed in the active P-cell 102P and the pseudo-NP-cell 102NP. The formation of PMG structures 112P and 113P may include the following sequential operations: (i) in FIG. 4B , FIG. 4C , FIG. 4E and FIG. 4G A patterned masking layer 540 (e.g., a photoresist layer) is formed on the structure to form FIG. 5B , FIG. 5C , FIG. 5E and FIG. 5G The structure, (ii) through from FIG. 5A and FIG. 5D The polysilicon structure 412 was etched and the structure was obtained by etching from... FIG. 5C and FIG. 5F The exposed portion of the polysilicon structure 412 is etched, and gate openings 612P and 612NP are formed essentially simultaneously. FIG. 6A , FIG. 6C , FIG. 6D and FIG. 6F(as shown), (iii) remove the patterned masking layer 540, and (iv) form an IO layer 120P on the trap regions 106P and 107P, as shown. FIG. 7A , FIG. 7C , FIG. 7D and FIG. 7F As shown, (v) in FIGS. 7A-7G (vi) deposit an HK gate dielectric layer 122P on the HK gate dielectric layer 122P, (vii) deposit a pWFM layer 124P on the HK gate dielectric layer 122P, (vii) deposit a gate metal fill layer 126P on the pWFM layer 124P, and (viii) perform a CMP process on the deposited HK gate dielectric layer 122P, pWFM layer 124P and gate metal fill layer 126P to form FIGS. 8A-8G The structure. In some embodiments, such as FIG. 5C As shown, the patterned masking layer 540 on the structure of the pseudo-NP unit 102NP partially covers about 50% of the total top surface area of ​​the polysilicon structure 412.

[0059] refer to FIG. 3 In operation 315, NMG structures are selectively formed in active N-cells and pseudo-NP-cells. For example, as referenced... FIGS. 9A-12G As described, NMG structures 112N and 113N are selectively formed in the active N-cell 102N and the pseudo-NP-cell 102NP. The formation of NMG structures 112N and 113N may include the following sequential operations: (i) in FIG. 8A , FIG. 8C , FIG. 8D and FIG. 8F A patterned masking layer 940 (e.g., a photoresist layer) is formed on the structure to form FIG. 9A , FIG. 9C , FIG. 9D and FIG. 9F The structure, (ii) through from FIG. 9B and FIG. 9E The polysilicon structure 412 was etched and the structure was obtained by etching from... FIG. 9C and FIG. 9G The structure is etched to expose the remaining portion of the polysilicon structure 412, essentially simultaneously forming gate openings 1012N and 1012NP (as shown in the image). FIG. 10B , FIG. 10C , FIG. 10E and FIG. 10G (as shown), (iii) remove the patterned masking layer 940, and (iv) form an IO layer 120N on the well regions 106N and 107N, as shown. FIG. 11B , FIG. 11C , FIG. 11E and FIG. 11G As shown, (v) in FIGS. 11A-11G(vi) deposit an HK gate dielectric layer 122N on the HK gate dielectric layer 122N, (vii) deposit an nWFM layer 124N on the HK gate dielectric layer 122N, (vii) deposit a gate metal fill layer 126N on the nWFM layer 124N, and (viii) perform a CMP process on the deposited HK gate dielectric layer 122N, nWFM layer 124N and gate metal fill layer 126N to form FIGS. 12A-12G The structure.

[0060] refer to FIG. 3 In operation 320, contact structures are selectively formed in the S / D regions of the active P-cells and active N-cells, as well as on the PMG and NMG structures. For example, as... FIGS. 13A-13B and FIGS. 13D-13E As shown, S / D contact structures 128P-128N are formed on the S / D regions 110P-110N, and gate contact structures 130P-130N are formed on the PMG structure 112P and the NMG structure 112N.

[0061] In some embodiments, the operation of method 300 can be performed to form a plurality of active P cells 102P, active N cells 102N and pseudo NP cells 102NP to form a corresponding active P cell array 100P, active N cell array 100N and pseudo NP cell array 100NP.

[0062] FIG. 14 This is a flowchart of an example method 1400 for fabricating active P-cells 202P, active N-cells 202N, and pseudo-NP-cells 202NP on a substrate 104, according to some embodiments. For illustrative purposes, reference will be made to methods for fabricating such... FIGS. 15A-22C The example manufacturing process of the active P-cell 202P, active N-cell 202N, and pseudo-NP-cell 202NP is described below. FIG. 14 The operation shown. FIGS. 15A-22C It is according to some embodiments along FIGS. 2A-2C Cross-sectional views of the active P-cell 202P, active N-cell 202N, and pseudo-NP-cell 202NP of lines AA, BB, and CC are shown. Depending on the specific application, the operations may be performed in a different order, or not at all. It should be noted that method 1400 may not produce the complete active P-cell 202P, active N-cell 202N, and pseudo-NP-cell 202NP of the IC. Therefore, it should be understood that additional processes may be provided before, during, and after method 1400, and only some other processes may be briefly described herein. The above describes processes with... FIGS. 2A-2M The same annotation for the components in FIGS. 15A-22C The components in.

[0063] In operation 1405, fin structures of active P-cells, active N-cells, and pseudo-NP-cells, as well as S / D regions and polysilicon structures, are formed. For example, as... FIGS. 15A-15C As shown, fin structures 206P, 206N, 207P, and 207N, as well as a polycrystalline silicon structure 1512, are formed. Furthermore, S / D regions 210P, 210N, 211P, and 211N are epitaxially grown on portions of the fin structures 206P, 206N, 207P, and 207N not covered by the polycrystalline silicon structure 1512. FIGS. 15A-15C (Not visible in the cross-sectional view). After the formation of the polysilicon structure 1512, the gate spacer 114 can be formed, and after the formation of the gate spacer 114, the S / D regions 210P, 210N, 211P, and 211N can be formed. After the formation of the S / D regions 210P, 210N, 211P, and 211N, the ILD layer 118A and ESL 217 can be formed (in... FIGS. 15A-15C The formation (not visible in the cross-sectional view) is due to the formation of [something].

[0064] refer to FIG. 14 In operation 1410, PMG structures are selectively formed in active P-cells and pseudo-NP-cells. For example, as referenced... FIGS. 16A-18C As described, PMG structures 212P and 213P are selectively formed in the active P-cell 202P and the pseudo-NP-cell 202NP. The formation of PMG structures 212P and 213P may include the following sequential operations: (i) by... FIG. 15A The polysilicon structure 1512 was etched and etched from the structure. FIG. 15C The exposed portion of the polysilicon structure 1512 is etched, and gate openings 1612P and 1612NP are formed essentially simultaneously. FIG. 16A and FIG. 16C (ii) An IO layer 120P is formed on fin structures 206P and 207P, as shown. FIG. 17A and FIG. 17C As shown, (iii) in FIGS. 17A-17C (vi) depositing an HK gate dielectric layer 122P on the HK gate dielectric layer 122P, (iv) depositing a pWFM layer 124P on the pWFM layer 124P, and (v) performing a CMP process on the deposited HK gate dielectric layer 122P, pWFM layer 124P, and gate metal fill layer 126P to form a FIGS. 18A-18C The structure.

[0065] refer to FIG. 14 In operation 1415, NMG structures are selectively formed in active N-cells and pseudo-NP-cells. For example, as referenced... FIGS. 19A-21CAs described, NMG structures 212N and 213N are selectively formed in the active N-cell 202N and the pseudo-NP-cell 202NP. The formation of NMG structures 212N and 213N may include the following sequential operations: (i) by... FIG. 19B The polysilicon structure 1512 was etched and etched from the structure. FIG. 19C The structure is etched to expose the remaining portion of the polysilicon structure 1512, essentially simultaneously forming gate openings 1912N and 1912NP (as shown in the image). FIG. 19B and FIG. 19C (ii) An IO layer 120N is formed on fin structures 206N and 207N, as shown. FIG. 20B and FIG. 20C As shown, (iii) in FIGS. 20A-20C (vi) deposit an HK gate dielectric layer 122N on the HK gate dielectric layer 122N, (vii) deposit an nWFM layer 124N on the HK gate dielectric layer 122N, (vii) deposit a gate metal fill layer 126N on the nWFM layer 124N, and (viii) perform a CMP process on the deposited HK gate dielectric layer 122N, nWFM layer 124N and gate metal fill layer 126N to form FIGS. 21A-21C The structure.

[0066] refer to FIG. 14 In operation 1420, contact structures are selectively formed in the S / D regions of the active P-cells and active N-cells, as well as on the PMG and NMG structures. For example, as... FIGS. 22A-22B As shown, gate contact structures 230P-230N are formed on the PMG structure 212P and the NMG structure 212N. S / D contact structures 228P-228N are formed on the S / D regions 210P-210N. FIGS. 22A-22C (Not visible in the cross-sectional view).

[0067] This invention provides example integrated circuits (ICs) and example manufacturing methods (e.g., methods 300 and 1400) of the same. The example ICs have active device cell arrays and dummy device cell arrays (e.g., active P-cell array 100P, active N-cell array 100N, and dummy NP cell arrays 100NP, 136NP, and 138NP) in corresponding active device regions and dummy device regions. The example ICs may include n-type active device cell arrays and / or p-type active device cell arrays. The n-type active device cell arrays may include an array of active N-cells (e.g., active N-cells 102N and 202N). Each active N-cell may include one or more electrically active n-type FETs (e.g., NMOSFETs, NfinFETs, or gate-all-around (GAA) NFETs) and / or n-type structures (such as N-type S / D regions (e.g., S / D regions 110N and 210N) and NMG structures (e.g., NMG structures 112N and 212N)). The p-type active device cell array may include an array of active P cells (e.g., active P cells 102P and 202P). Each active P cell may include one or more electrically active p-type FETs (e.g., PMOSFETs, PfinFETs, or gate-all-around (GAA) PFETs) and / or p-type structures (such as P-type S / D regions (e.g., S / D regions 110P and 210P) and PMG structures (e.g., PMG structures 112P and 212P)). The active N cells and active P cells may also include contact structures disposed on one or more S / D regions and gate structures (e.g., S / D contact structures 128P-128N and 228P-228N, gate contact structures 130P-130N and 230P-230N).

[0068] The dummy device cell array can be configured adjacent to or surrounding the active device cell array and can include dummy N cells and dummy P cells, and / or dummy NP cells (e.g., dummy N cell 134N, dummy P cell 134P, and dummy NP cells 102NP-202NP). Unlike active N cells and active P cells, dummy N cells, dummy P cells, and dummy NP cells do not include contact structures and / or contact bonding pads or regions located on the S / D region and / or gate structure. The dummy device cell array can be formed and arranged in a manner that achieves a substantially uniform surface profile on the gate structure in both the active P cell array and the active N cell array. Each dummy device cell array can be formed with a gate surface area ratio of approximately 1:1 between the total top surface area of ​​the dummy NMG structure and the total top surface area of ​​the dummy PMG structure to achieve a substantially uniform surface profile. This balanced gate surface area ratio between the dummy NMG structure and the dummy PMG structure can prevent or minimize the recess effects associated with the CMP process during the formation of the active NMG structure and the active PMG structure. The balanced distribution of pseudo-NMG and pseudo-PMG structures provides a matching polishing rate for active NMG and active PMG structures, and thus prevents or minimizes the pitting effect associated with the CMP process.

[0069] In some embodiments, each pseudo-device cell array (e.g., pseudo-NP cell arrays 136NP and 138NP) may be formed by the same number of pseudo-N cells (e.g., pseudo-N cells 134N) and pseudo-P cells (e.g., pseudo-P cells 134P) to achieve a balanced gate surface area ratio. In some embodiments, the pseudo-N cells and pseudo-P cells may be arranged in an array configuration or in a configuration that alternates with each other. The pseudo-N cells may have a number of pseudo-NMG structures (e.g., pseudo-NMG structures 135N) equal to the number of pseudo-PMG structures (e.g., pseudo-PMG structure 135P) of the pseudo-P cells. In some embodiments, the pseudo-NMG structures and pseudo-PMG structures may have gate dimensions (e.g., gate length, gate width, and gate height) that are substantially equal to each other. In some embodiments, the pseudo-NMG structure may have a total top surface area that is substantially equal to the total top surface area of ​​the pseudo-PMG structures. In some embodiments, each pseudo-device cell array (e.g., pseudo-NP cell array 100NP) may be formed by an array of pseudo-NP cells (e.g., pseudo-NP cells 102NP) having an equal number of pseudo-NMG structures and pseudo-PMG structures (e.g., pseudo-NMG structure 113N and pseudo-PMG structure 113P) to achieve a balanced gate surface area ratio.

[0070] In some embodiments, the integrated circuit includes a substrate, active device units, and dummy device units. The active device units include an array of source / drain (S / D) regions of a first conductivity type disposed on or within the substrate, and an array of gate structures having a first gate fill material disposed on the substrate. The dummy device units include a first array of source / drain regions of a first conductivity type disposed on or within the substrate, a second array of source / drain regions of a second conductivity type disposed on or within the substrate, and an array of dual-gate structures disposed on the substrate. Each dual-gate structure includes a first gate fill material and a second gate fill material different from the first gate fill material.

[0071] In the aforementioned integrated circuit, each of the dual-gate structures includes a first gate structure having a first end face and a second gate structure having a second end face, the second end face being adjacent to the first end face.

[0072] In the aforementioned integrated circuit, each of the dual-gate structures includes a first gate structure having a first top surface area and a second gate structure having a second top surface area, the second top surface area being equal to the first top surface area.

[0073] In the aforementioned integrated circuit, each of the dual-gate structures includes a first gate structure having a first top surface area and a second gate structure having a second top surface area; and each of the gate structures includes a top surface area greater than the first top surface area or the second top surface area.

[0074] In the aforementioned integrated circuit, the first gate filling material and the second gate filling material are work function metal layers.

[0075] In the aforementioned integrated circuit, the active device unit further includes a contact structure disposed on at least one of the gate structures; and the pseudo device unit does not include a contact structure.

[0076] In the aforementioned integrated circuit, at least one of the dual-gate structures includes a first gate structure disposed on a first well region of a first conductivity type and a second gate structure disposed on a second well region of a second conductivity type different from the first conductivity type.

[0077] In the aforementioned integrated circuit, at least one of the gate structures is disposed on a first well region of a first conductivity type; and at least one of the dual gate structures is disposed on a second well region of a second conductivity type different from the first conductivity type.

[0078] In the aforementioned integrated circuit, the active device unit includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0079] In the aforementioned integrated circuit, the active device unit includes a fin field-effect transistor (finFET).

[0080] In some embodiments, the integrated circuit includes a substrate, a first source / drain (S / D) region and a second active source / drain (S / D) region disposed on or within the substrate, an active gate structure having a gate filling layer disposed on the substrate, a first pseudo source / drain region and a second pseudo source / drain region disposed on or within the substrate, and a pseudo gate structure disposed on the substrate. The pseudo gate structure includes a first gate filling layer and a second gate filling layer different from the first gate filling layer. The first gate filling layer has a first top surface area, and the second gate filling layer has a second top surface area substantially equal to the first top surface area.

[0081] In the aforementioned integrated circuit, the active gate structure is disposed on a first fin structure on the substrate; and the dummy gate structure is disposed on a second fin structure on the substrate.

[0082] In the aforementioned integrated circuit, the dummy gate structure includes: a first gate structure surrounding a first fin structure disposed on the substrate; and a second gate structure surrounding a second fin structure disposed on the substrate.

[0083] In the aforementioned integrated circuit, the first active source / drain region and the second active source / drain region are epitaxial regions disposed on the first fin structure; and the first pseudo-source / drain region and the second pseudo-source / drain region are epitaxial regions disposed on the second fin structure.

[0084] In the aforementioned integrated circuit, the gate filling layer of the active gate structure and the first gate filling layer of the dummy gate structure comprise the same metal.

[0085] In the aforementioned integrated circuit, the top surface area of ​​the gate filling layer is greater than the top surface area of ​​the first gate filling layer or the second gate filling layer.

[0086] In some embodiments, a method includes forming a first fin structure and a second fin structure on a substrate, forming a first source / drain (S / D) region and a second source / drain (S / D) region on the first fin structure and the second fin structure respectively, forming a first polysilicon structure and a second polysilicon structure on the first fin structure and the second fin structure respectively, replacing a first portion of the first polysilicon structure and the second polysilicon structure with a first metal layer, polishing the first metal layer at a first polishing rate, replacing a second portion of the second polysilicon structure with a second metal layer different from the first metal layer, and polishing the second metal layer at a second polishing rate different from the first polishing rate.

[0087] In the above method, replacing the first portion of the first polysilicon structure and the second polysilicon structure includes forming a patterned masking layer on the top surface area of ​​the second portion, wherein the top surface area of ​​the second portion is equal to the top surface area of ​​the first portion.

[0088] In the above method, replacing the first portion of the first polysilicon structure and the second polysilicon structure includes forming a patterned masking layer on the top surface area of ​​the second portion, wherein the top surface area of ​​the second portion is smaller than the top surface area of ​​the first polysilicon structure.

[0089] In the above method, the method further includes forming a third fin structure on the substrate, wherein the second portion of the second polysilicon structure is formed on the third fin structure.

[0090] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. An integrated circuit, comprising: Substrate; Active device unit, including: An array of source / drain (S / D) regions of a first conductivity type is disposed on or within the substrate; and An array of gate structures having a first gate filling material is disposed on the substrate; and The pseudo-device unit includes: A first array of source / drain regions of the first conductivity type is disposed on or within the substrate; A second array of source / drain regions of a second conductivity type is disposed on or within the substrate; and An array of dual-gate structures is disposed on the substrate, wherein each of the dual-gate structures includes a first gate filling material and a second gate filling material different from the first gate filling material.

2. The integrated circuit according to claim 1, wherein, Each of the dual-gate structures includes a first gate structure having a first end face and a second gate structure having a second end face adjacent to the first end face.

3. The integrated circuit according to claim 1, wherein, Each of the dual-gate structures includes a first gate structure having a first top surface area and a second gate structure having a second top surface area equal to the first top surface area.

4. The integrated circuit according to claim 1, wherein, Each of the dual-gate structures includes a first gate structure having a first top surface area and a second gate structure having a second top surface area; and Each of the gate structures includes a top surface area larger than the first top surface area or the second top surface area.

5. The integrated circuit according to claim 1, wherein, The first gate filling material and the second gate filling material are work function metal layers.

6. The integrated circuit according to claim 1, wherein, The active device unit further includes a contact structure disposed on at least one of the gate structures; and The pseudo-device unit does not include a contact structure.

7. The integrated circuit according to claim 1, wherein, At least one of the dual-gate structures includes a first gate structure disposed on a first well region of a first conductivity type and a second gate structure disposed on a second well region of a second conductivity type different from the first conductivity type.

8. The integrated circuit according to claim 1, wherein, At least one of the gate structures is disposed on a first well region of a first conductivity type; and In this configuration, at least one of the dual-gate structures is disposed on a second well region of a second conductivity type different from the first conductivity type.

9. The integrated circuit according to claim 1, wherein, The active device unit includes a metal-oxide-semiconductor field-effect transistor (MOSFET).

10. The integrated circuit according to claim 1, wherein, The active device unit includes a fin field-effect transistor (finFET).

11. An integrated circuit, comprising: Substrate; A first active source / drain (S / D) region and a second active source / drain region are disposed on or within the substrate; An active gate structure having a gate filling layer is disposed on the substrate; The first pseudo-source / drain region and the second pseudo-source / drain region are disposed on or within the substrate; A dummy gate structure is disposed on the substrate, wherein the dummy gate structure includes a first gate filling layer and a second gate filling layer different from the first gate filling layer, and wherein the first gate filling layer has a first top surface area, and the second gate filling layer has a second top surface area equal to the first top surface area.

12. The integrated circuit according to claim 11, wherein, The active gate structure is disposed on the first fin structure on the substrate; and The dummy gate structure is disposed on the second fin structure on the substrate.

13. The integrated circuit according to claim 11, wherein, The pseudo-gate structure includes: A first gate structure surrounding a first fin structure disposed on the substrate; and The second gate structure surrounds the second fin structure disposed on the substrate.

14. The integrated circuit according to claim 11, wherein, The first active source / drain region and the second active source / drain region are epitaxial regions disposed on the first fin structure; and The first pseudo-source / drain region and the second pseudo-source / drain region are epitaxial regions disposed on the second fin structure.

15. The integrated circuit according to claim 11, wherein, The gate filling layer of the active gate structure and the first gate filling layer of the dummy gate structure comprise the same metal.

16. The integrated circuit according to claim 11, wherein, The top surface area of ​​the gate filling layer is greater than the top surface area of ​​the first gate filling layer or the second gate filling layer.

17. A method for manufacturing an integrated circuit, comprising: A first fin structure and a second fin structure are formed on a substrate; A first source / drain (S / D) region and a second source / drain region are formed on the first fin structure and the second fin structure, respectively; A first polycrystalline silicon structure and a second polycrystalline silicon structure are formed on the first fin structure and the second fin structure, respectively; The first portion of the first polysilicon structure and the second polysilicon structure is replaced with a first metal layer; Polish the first metal layer at a first polishing rate; The second portion of the second polysilicon structure is replaced with a second metal layer that is different from the first metal layer. as well as The second metal layer is polished at a second polishing rate that is different from the first polishing rate.

18. The method according to claim 17, wherein, The first portion replacing the first polysilicon structure and the second polysilicon structure includes forming a patterned masking layer on the top surface area of ​​the second portion, the top surface area of ​​the second portion being equal to the top surface area of ​​the first portion.

19. The method of claim 17, wherein, The first portion replacing the first polysilicon structure and the second polysilicon structure includes forming a patterned masking layer on the top surface area of ​​the second portion, wherein the top surface area of ​​the second portion is smaller than the top surface area of ​​the first polysilicon structure.

20. The method of claim 17, further comprising forming a third fin structure on the substrate, wherein, The second portion of the second polycrystalline silicon structure is formed on the third fin structure.

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