Display substrate and display device

Abstract

A display substrate and a display device are provided. The display substrate includes: a base substrate including a display area and a frame area; a plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array on the base substrate along the row direction and the column direction, and each pixel unit includes a plurality of sub-pixels; a plurality of scanning signal lines arranged on the base substrate, used to provide scanning signals to a plurality of rows of sub-pixels respectively; a gate drive circuit arranged on the base substrate and located in the frame area, used to output scanning signals; a plurality of load compensation units arranged on the base substrate and located in the frame area, the plurality of load compensation units are located between the gate drive circuit and the plurality of pixel units; and a plurality of scanning signal leads arranged on the base substrate and located in the frame area, used to transmit the scanning signals output by the gate drive circuit to the plurality of scanning signal lines respectively. At least one of the scanning signal leads crosses at least one load compensation unit along the row direction.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate and a display device. Background Art

[0002] At present, organic light-emitting diode (OLED) display panels are widely used in smart phones, TVs, virtual reality devices, wearable products and other fields due to their excellent display effects, thinness, flexibility, good shock resistance and adaptability to wearable products. With the development of display panel technology and the market's increasing requirements for display panel screen-to-body ratio and adaptability to occasions, designing display devices with narrow frame design, even frameless design and various special-shaped designs has gradually become a challenge for R&D personnel in the field of OLED display technology.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising:

[0005] A base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area;

[0006] A plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array on the substrate along a row direction and a column direction, and each pixel unit includes a plurality of sub-pixels;

[0007] A plurality of scanning signal lines are arranged on the base substrate, and the plurality of scanning signal lines are used to provide scanning signals to a plurality of rows of sub-pixels respectively;

[0008] A gate driving circuit disposed on the base substrate and located in the frame area, the gate driving circuit being used to output a scanning signal;

[0009] A plurality of load compensation units disposed on the base substrate and located in the frame region, the plurality of load compensation units being located between the gate driving circuit and the plurality of pixel units; and

[0010] A plurality of scanning signal lead lines are arranged on the base substrate and located in the frame area, and the plurality of scanning signal lead lines are used to transmit the scanning signals output by the gate driving circuit to the plurality of scanning signal lines respectively.

[0011] Wherein, at least one of the scan signal lead lines crosses at least one of the load compensation units along the row direction.

[0012] According to some exemplary embodiments, the load compensation unit includes a plurality of compensation capacitors, each compensation capacitor includes a first compensation capacitor electrode and a second compensation capacitor electrode, the first compensation capacitor electrode is located in a first conductive layer, the second compensation capacitor electrode is located in a second conductive layer, the orthographic projection of the first compensation capacitor electrode on the substrate and the orthographic projection of the second compensation capacitor electrode on the substrate at least partially overlap; and the plurality of scanning signal leads are located in a third conductive layer, the second conductive layer is located on a side of the first conductive layer away from the substrate, and the third conductive layer is located on a side of the second conductive layer away from the substrate, wherein the orthographic projection of at least one of the scanning signal leads on the substrate partially overlaps with the orthographic projection of at least one load compensation unit on the substrate.

[0013] According to some exemplary embodiments, an orthographic projection of at least one of the scan signal leads on the substrate at least partially overlaps with an orthographic projection of a first compensation capacitor electrode and a second compensation capacitor electrode of a plurality of compensation capacitors of at least one load compensation unit on the substrate.

[0014] According to some exemplary embodiments, in a load compensation unit, the first compensation capacitor electrodes of the multiple compensation capacitors are spaced apart along the row direction to form a gap between the multiple first compensation capacitor electrodes; and at least one of the scanning signal leads includes a first part, and the orthographic projection of the first part of the scanning signal lead on the substrate overlaps with the orthographic projection of the gap on the substrate.

[0015] According to some exemplary embodiments, the first portion of the scan signal lead line extends in a direction inclined with respect to both the row direction and the column direction.

[0016] According to some exemplary embodiments, the display substrate further includes: a plurality of data signal lines arranged on the base substrate, the plurality of data signal lines being used to provide data signals to a plurality of columns of sub-pixels respectively; each of the first compensation capacitor electrodes being electrically connected to one of the data signal lines through at least two first via holes, wherein the at least two first via holes are arranged at intervals along the row direction.

[0017] According to some exemplary embodiments, a positive projection of a first compensation capacitor electrode on the substrate has a first size along the column direction, a load compensation unit partially overlaps with another adjacent load compensation unit in the column direction, and a size of the overlapping portion of the two adjacent load compensation units along the column direction is less than or equal to one half of the first size.

[0018] According to some exemplary embodiments, a load compensating unit and another load compensating unit adjacent thereto are spaced apart from each other in the column direction.

[0019] According to some exemplary embodiments, the display substrate further includes: a plurality of initialization voltage lines disposed on the base substrate, the plurality of initialization voltage lines being used to respectively provide initialization voltage signals to the plurality of rows of sub-pixels; and a plurality of initialization voltage leads disposed on the base substrate and located in the frame area, the plurality of initialization voltage leads being used to transmit the initialization voltage signals to the plurality of initialization voltage lines, wherein at least one of the initialization voltage leads crosses at least one of the load compensation units along the row direction.

[0020] According to some exemplary embodiments, at least one of the initialization voltage lead wires includes a first portion, and an orthographic projection of the first portion of the initialization voltage lead wire on the base substrate partially overlaps with an orthographic projection of the gap on the base substrate.

[0021] According to some exemplary embodiments, the first portion of the initialization voltage lead line extends in a direction inclined with respect to both the row direction and the column direction.

[0022] According to some exemplary embodiments, the display substrate further includes: a plurality of driving voltage lines arranged on the base substrate, the plurality of driving voltage lines being used to respectively provide driving voltage signals to the plurality of columns of sub-pixels; each of the second compensation capacitor electrodes being electrically connected to one of the driving voltage lines through at least two second via holes, wherein the at least two second via holes are arranged at intervals along the column direction.

[0023] According to some exemplary embodiments, the display substrate further includes: a test circuit disposed on the base substrate and located in the border area, the test circuit being used to output a data signal, wherein each of the first compensation capacitor electrodes is electrically connected to the test circuit through at least two third vias.

[0024] According to some exemplary embodiments, the display substrate further includes: a driving voltage lead arranged on the base substrate and located in the frame area, the driving voltage lead being used to transmit a driving voltage signal, wherein each of the second compensation capacitor electrodes is electrically connected to the driving voltage lead through at least two fourth vias.

[0025] According to some exemplary embodiments, the load compensation unit includes at least three compensation capacitors, in one load compensation unit, first compensation capacitor electrodes of the at least three compensation capacitors are spaced apart along the row direction to respectively form a first gap and a second gap between the at least three first compensation capacitor electrodes; and at least one of the scanning signal leads includes a first part and a second part, the orthographic projection of the first part of the scanning signal lead on the substrate overlaps with the orthographic projection of the first gap on the substrate, and the orthographic projection of the second part on the substrate overlaps with the orthographic projection of the second gap on the substrate.

[0026] According to some exemplary embodiments, at least one of the first portion and the second portion of the scan signal lead line extends in a direction inclined with respect to both the row direction and the column direction.

[0027] According to some exemplary embodiments, at least one of the initialization voltage leads includes a first portion and a second portion, the orthographic projection of the first portion of the initialization voltage lead on the base substrate partially overlaps with the orthographic projection of the first gap on the base substrate, and the orthographic projection of the second portion of the initialization voltage lead on the base substrate partially overlaps with the orthographic projection of the second gap on the base substrate.

[0028] According to some exemplary embodiments, at least one of the first portion and the second portion of the initialization voltage lead line extends in a direction inclined with respect to both the row direction and the column direction.

[0029] According to some exemplary embodiments, in a load compensation unit, second compensation capacitor electrodes of the plurality of compensation capacitors are connected to each other.

[0030] According to some exemplary embodiments, in a load compensation unit, an orthographic projection of a first compensation capacitor electrode of the plurality of compensation capacitors on the substrate falls within an orthographic projection of a plurality of second compensation capacitor electrodes connected to each other on the substrate.

[0031] According to some exemplary embodiments, an orthographic projection of a plurality of second compensation capacitor electrodes connected to each other on the base substrate covers an orthographic projection of each of the first gap and the second gap on the base substrate.

[0032] According to some exemplary embodiments, the orthographic projections of a plurality of second compensation capacitor electrodes connected to each other on the base substrate cover the orthographic projections of each of the first and second parts of the scan signal lead on the base substrate; and the orthographic projections of a plurality of second compensation capacitor electrodes connected to each other on the base substrate cover the orthographic projections of each of the first and second parts of the initialization voltage lead on the base substrate.

[0033] According to some exemplary embodiments, a size of each of the first gap and the second gap along the row direction is between 1 and 6 micrometers.

[0034] According to some exemplary embodiments, the plurality of scan signal lines are located in the first conductive layer; and / or the plurality of initialization voltage lines are located in the second conductive layer.

[0035] According to some exemplary embodiments, an orthographic projection of the display area on the base substrate is in the shape of a rounded rectangle.

[0036] According to some exemplary embodiments, the plurality of load compensating units are arranged along contour lines of rounded corners of the rounded rectangle.

[0037] According to some exemplary embodiments, multiple load compensation units correspond one-to-one to multiple columns of pixel units, respectively, and the overlapping area of ​​the first compensation capacitor electrode and the second compensation capacitor electrode in each load compensation unit is proportional to the number of missing pixel units in a column of pixel units corresponding to the load compensation unit.

[0038] In another aspect, a display device is provided, comprising the display substrate as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0040] Figure 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure;

[0041] Figure 2 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, wherein a pixel unit and a load compensation unit included in a display substrate are schematically shown;

[0042] Figure 3 yes Figure 2 A partial enlarged view of part I in FIG.

[0043] Figure 4 yes Figure 3 A partial enlarged view of part II in FIG.

[0044] Figure 5 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0045] Figure 6 is a plan view showing an exemplary implementation of a sub-pixel in a display area of ​​a display substrate according to some exemplary embodiments of the present disclosure;

[0046] Figures 7 to 10 It is shown Figure 6 A plan view of some film layers of an exemplary embodiment of a sub-pixel in FIG. 1 , wherein: Figures 7 to 10 The semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer are schematically shown respectively;

[0047] Fig.11 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Figure 6 A schematic diagram of a cross-sectional structure taken along line AA';

[0048] Figure 12 to Figure 14 They are Figure 4 A layered diagram of Fig.12 Schematically shows a partial plan view of the first conductive layer, Fig.13 Schematically shows a partial plan view of the second conductive layer, Fig.14 schematically shows a partial plan view of a third conductive layer; and

[0049] Fig.15 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Figure 4 Schematic diagram of the cross-sectional structure taken along line BB' in FIG. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0052] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0053] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0054] For ease of description, spatial relational terms, such as "upper", "lower", "left", "right", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as "below" or "beneath" other elements or features will be oriented "above" or "above" the other elements or features.

[0055] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] It should be noted that, in this article, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. Usually, multiple elements, components, structures and / or parts located in the "same layer" have approximately the same thickness.

[0057] The embodiments of the present disclosure at least provide a display substrate and a display device. The display substrate comprises: a substrate, the substrate comprising a display area and a frame area located at least on one side of the display area; a plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array on the substrate along the row direction and the column direction, and each pixel unit comprises a plurality of sub-pixels; a plurality of scanning signal lines arranged on the substrate, the plurality of scanning signal lines are used to provide scanning signals to a plurality of rows of sub-pixels respectively; a gate driving circuit arranged on the substrate and located in the frame area, the gate driving circuit is used to output scanning signals; a plurality of load compensation units arranged on the substrate and located in the frame area, the plurality of load compensation units are located between the gate driving circuit and the plurality of pixel units; and a plurality of scanning signal leads arranged on the substrate and located in the frame area, the plurality of scanning signal leads are used to transmit the scanning signals output by the gate driving circuit to the plurality of scanning signal lines respectively, wherein at least one of the scanning signal leads crosses over at least one of the load compensation units along the row direction. In the display substrate and display device provided by the embodiments of the present disclosure, the scanning signal lead for supplying the scanning signal is placed above the load compensation unit, so that there is an overlap between the scanning signal lead and the load compensation unit, which can compensate the scanning signal lead and improve the stability of the scanning signal.

[0058] Figure 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure. Figure 2 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, in which a pixel unit and a load compensation unit included in a display substrate are schematically shown.

[0059] Combined with reference Figure 1 and Figure 2 The display device 1000 may include a display substrate. The display substrate may include a base substrate 100, and the base substrate 100 may include a display area AA and a frame area NA located at at least one side of the display area. Figure 1 In the illustrated embodiment, the border area NA surrounds the display area AA, but the embodiments of the present disclosure are not limited thereto. In other embodiments, the border area NA may be located on at least one side of the display area AA but does not surround the display area AA.

[0060] The display substrate may include a plurality of pixel units P located in the display area AA. It should be noted that the pixel unit P is the smallest unit for displaying an image. For example, the pixel unit P may include a light emitting device that emits white light and / or colored light.

[0061] The pixel unit P may be provided in plurality to be arranged in a matrix form along rows extending in a first direction (e.g., row direction) X and columns extending in a second direction (e.g., column direction) Y. However, the embodiments of the present disclosure do not specifically limit the arrangement form of the pixel unit P, and the pixel unit P may be arranged in various forms. For example, the pixel unit P may be arranged such that a direction inclined with respect to the first direction X and the second direction Y becomes a column direction, and such that a direction intersecting the column direction becomes a row direction.

[0062] A pixel unit P may include a plurality of sub-pixels. For example, a pixel unit P may include three sub-pixels, namely, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For another example, a pixel unit P may include four sub-pixels, namely, a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. For example, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, the third sub-pixel SP3 may be a blue sub-pixel, and the fourth sub-pixel may be a white sub-pixel.

[0063] Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. For example, the first sub-pixel SP1 may include a first light-emitting element and a first pixel driving circuit for driving the first light-emitting element, and the first light-emitting element may emit red light; the second sub-pixel SP2 may include a second light-emitting element and a second pixel driving circuit for driving the second light-emitting element, and the second light-emitting element may emit green light; the third sub-pixel SP3 may include a third light-emitting element and a third pixel driving circuit for driving the third light-emitting element, and the third light-emitting element may emit blue light.

[0064] For example, in an OLED display panel, the light-emitting element of a sub-pixel may include a stacked anode, a light-emitting material layer, and a cathode. Thus, the light-emitting region of the sub-pixel may be the region corresponding to the portion of the light-emitting material layer sandwiched between the anode and the cathode.

[0065] Reference Figure 1 The display substrate may include components such as a load compensation unit 1, a test circuit 200, a gate driving circuit 300, and a multiplexer 400 located in the peripheral area NA.

[0066] The display area AA may include a first boundary AA1 , a second boundary AA2 , a third boundary AA3 , and a fourth boundary AA4 (eg, an upper boundary, a lower boundary, a left boundary, and a right boundary) connected in sequence.

[0067] In some embodiments of the present disclosure, the orthographic projection of the display area AA on the base substrate 100 may be in the shape of a rounded rectangle. For the convenience of description, the four rounded corners of the rounded rectangle may be respectively referred to as a first rounded corner portion 101, a second rounded corner portion 102, a third rounded corner portion 103, and a fourth rounded corner portion 104. For example, the first rounded corner portion 101 may be located at Figure 1 The second rounded corner 102 may be located at the upper left corner of Figure 1 The third rounded corner 103 may be located at the upper right corner of Figure 1 The fourth rounded corner 104 may be located at the lower left corner of Figure 1 In the lower right corner.

[0068] The test circuit 200 may be located at a side of the peripheral area NA adjacent to the first boundary AA1 , and the test circuit 200 is disposed opposite to the first boundary AA1 , the first rounded corner portion 101 , and the second rounded corner portion 102 .

[0069] For example, the test circuit 200 may include a plurality of test pins (described below), which may be used to provide test signals, for example, the test signals may include data signals for a plurality of pixel units P in the display area AA.

[0070] The multiplexer 400 may be located at a side of the peripheral area NA adjacent to the second boundary AA2 , and the multiplexer 400 is disposed opposite to the second boundary AA2 , the third rounded corner portion 103 , and the fourth rounded corner portion 104 .

[0071] For example, the multiplexer 400 can perform time division multiplexing on the signal lines in the wiring area. Figure 1 As shown, the display substrate includes an integrated circuit IC disposed in the peripheral area NA and a wiring area 500 located between the integrated circuit IC and the multiplexer 400. Each signal output by the integrated circuit IC is transmitted to the multiplexer 400 through the signal line in the wiring area 500. Then, under the control of the signal control terminal of the multiplexer 400, each signal is output to each pixel unit P in the display area AA. By providing the multiplexer 400, the number of signal lines arranged in the wiring area can be reduced, thereby reducing the wiring pressure in the wiring area.

[0072] The gate driving circuit 300 may be located on one side of the peripheral area NA adjacent to the third boundary AA3 and on one side of the peripheral area NA adjacent to the fourth boundary AA4. Figure 1 It is shown that the driving circuit is located at the left and right sides of the display area AA, but the embodiments of the present disclosure are not limited thereto, and the driving circuit can be located at any suitable position in the peripheral area NA.

[0073] For example, the gate driver circuit 300 can adopt GOA technology, i.e., Gate Driver on Array. In GOA technology, the gate driver circuit is directly arranged on the array substrate to replace the external driver chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a gate line. The turn-on voltage is output in turn through each level of shift register to realize the row-by-row scanning of the pixel. In some embodiments, each level of shift register can also be connected to multiple gate lines. In this way, it can adapt to the development trend of high resolution and narrow frame of display substrate.

[0074] The display substrate may include a plurality of load compensation units 1. Figure 1 and Figure 2 As shown, some of the multiple load compensation units 1 are located in the peripheral area NA adjacent to the first rounded corner 101, and other load compensation units 1 are located in the peripheral area NA adjacent to the second rounded corner 102. The multiple load compensation units 1 are all located between the test circuit 200 and the display area AA.

[0075] Figure 3 yes Figure 2 A partial enlarged view of part I in FIG. Figure 2 and Figure 3, a plurality of sub-pixels are arranged in an array on the base substrate 100, that is, a plurality of rows of sub-pixels and a plurality of columns of sub-pixels are formed on the base substrate 100. For the plurality of columns of sub-pixels, since the display area AA is in a rounded rectangular shape, the number of sub-pixels included in each column of sub-pixels is inconsistent.

[0076] Reference Figure 2 , the rounded rectangle has a center 105. The first straight line L1 extends along the column direction Y and passes through the center 105. The second straight line L2 extends along the column direction Y and passes through the rounded corner of the rounded rectangle, for example, through the first rounded corner portion 101. In the area where the first straight line L1 is located, the number of sub-pixels included in a column of sub-pixels is N. In the area where the second straight line L2 is located, the number of sub-pixels included in a column of sub-pixels is M. Due to the existence of the rounded corners, the number M is less than the number N. Combined with reference Figure 2 As the second straight line L2 gradually approaches the third boundary AA3, the number M may gradually decrease.

[0077] In the embodiments of the present disclosure, for the convenience of description, a column of sub-pixels in the area where the first straight line L1 is located is referred to as a reference pixel column, and sub-pixel columns corresponding to each rounded corner are referred to as edge pixel columns.

[0078] The display substrate further includes a plurality of data signal lines disposed on the base substrate 100, and the plurality of data signal lines are used to provide data signals to the plurality of columns of sub-pixels respectively. Since the number of sub-pixels in the edge pixel column is less than the number of sub-pixels in the reference pixel column, the load on the data signal line providing the data signal to the edge pixel column is inconsistent with the load on the data signal line providing the data signal to the reference pixel column. Therefore, it is necessary to perform load compensation on the edge pixel column so that the load on each data signal line is consistent, thereby avoiding display differences and ensuring display quality.

[0079] For example, the fewer the number of sub-pixels in the edge pixel column, the smaller the load on the data signal line that provides the data signal, and the greater the load that needs to be compensated. Therefore, optionally, in the display substrate provided by the embodiment of the present disclosure, the more sub-pixels are connected to the data signal line corresponding to the load compensation unit, the smaller the compensation load value of the load compensation unit. Load compensation units with different compensation load values ​​are used to compensate data signal lines with different numbers of sub-pixels, so that the loads on different data signal lines are uniform, display differences are avoided, and display quality is guaranteed.

[0080] For example, the number of sub-pixels included in the reference pixel column is N, and the number of sub-pixels included in the edge pixel column is M. When compensating the load on the data signal line, the value of the load to be compensated can be determined according to the difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column.

[0081] Figure 4 yes Figure 3 A partial enlarged view of part II in FIG. Figures 1 to 4 , the multiple load compensation units 1 are arranged along the contour lines of the rounded corners of the rounded rectangle.

[0082] Reference Figure 3 and Figure 4 , multiple load compensation units 1 correspond to multiple columns of pixel units P respectively. One pixel unit P may include multiple sub-pixels, for example, 3 sub-pixels (for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3). One load compensation unit 1 may include multiple compensation capacitors, for example, 3 compensation capacitors. The multiple compensation capacitors may include a first compensation capacitor 11, a second compensation capacitor 12, and a third compensation capacitor 13. In a group of corresponding load compensation units 1 and a column of pixel units P, the first compensation capacitor 11 may be used to compensate a column of first sub-pixels SP1, the second compensation capacitor 12 may be used to compensate a column of second sub-pixels SP2, and the third compensation capacitor 13 may be used to compensate a column of third sub-pixels SP3.

[0083] In an embodiment of the present disclosure, each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element. Figure 4 In the figure, the rectangular area surrounded by dotted lines represents the area of ​​each sub-pixel. Below, taking the 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit of each sub-pixel located in the display area AA is described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. In the absence of conflict, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.

[0084] Figure 5 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 6 is a plan view showing an exemplary implementation of a sub-pixel in a display area of ​​a display substrate according to some exemplary embodiments of the present disclosure. Figures 7 to 10 It is shown Figure 6 A plan view of some layers of an exemplary embodiment of a sub-pixel in FIG. Figures 7 to 10 The semiconductor layer, the first conductive layer, the second conductive layer and the third conductive layer are schematically shown respectively.

[0085] Combined with reference Figures 5 to 10, the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (ie, OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0086] The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (i.e., a scanning signal of a previous row), a light control line 63 for transmitting a light control signal En, a data signal line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power line 67 for transmitting a VSS voltage.

[0087] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be arranged along the Figure 7 The active layer may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0088] The active layer may include, for example, polysilicon, and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped or the doping type may be different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0089] The first transistor T1 includes a first active layer 20a and a first gate G1. The first active layer 20a includes a first channel region 201a, a first source region 203a, and a first drain region 205a. The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. And the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. Figure 4As shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also called an initialization transistor.

[0090] The second transistor T2 includes a second active layer 20b and a second gate G2. The second active layer 20b includes a second channel region 201b, a second source region 203b, and a second drain region 205b. The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3.

[0091] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in two opposite directions relative to the third channel region 201c. The third source region 203c of the third transistor T3 is connected to the fourth drain region 205d and the fifth drain region 205e. The third drain region 205c is connected to the second source region 203b and the sixth source region 203f. The gate G3 of the third transistor T3 is electrically connected to the node N1 through the vias VAH1 and VAH2 and the first connection line 68. The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. That is, the third transistor T3 is also called the driving transistor.

[0092] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4. The fourth active layer 20d includes a fourth channel region 201d, a fourth source region 203d and a fourth drain region 205d. The fourth transistor T4 is used as a switching device for selecting a light-emitting target sub-pixel. The fourth gate G4 is connected to the scan signal line 61, the fourth source region 203d is connected to the data signal line 64 through the via VAH4, and the fourth drain region 205d is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.

[0093] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth channel region 201e, a fifth source region 203e and a fifth drain region 205e. The fifth source region 203e can be connected to the driving voltage line 65 through a via VAH6. The gate G5 of the fifth transistor T5 is electrically connected to the light emitting control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65. And the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0094] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6, and the sixth active layer 20f includes a sixth channel region 201f, a sixth source region 203f and a sixth drain region 205f. The sixth drain region 205f can be connected to the anode of the OLED through a via VAH7. The gate G6 of the sixth transistor T6 is electrically connected to the light emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emitting control signal En transmitted through the light emitting control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED.

[0095] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g and a seventh channel region 201g. The seventh drain region 205g is connected to the first source region 203a of the first transistor T1. The seventh drain region 205g can be electrically connected to the initialization voltage line 66 through the via VAH8, the second connection line 69 and the via VAH5. The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66.

[0096] One end (hereinafter referred to as a first capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second capacitor electrode) Cst2 is electrically connected to the driving voltage line 65 .

[0097] The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power line 67 to receive the common voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0098] It should be noted that in Figure 4 In the figure, each thin film transistor T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0099] In operation, in the initialization stage, a reset control signal RESET having a low level is supplied through the reset signal line 62. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the third transistor T3 through the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.

[0100] In the data programming stage, a scan signal Sn having a low level is supplied through the scan signal line 61. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode connection state through the turned-on second transistor T2 and is biased in a forward direction.

[0101] Subsequently, a compensation voltage Dm+Vth (for example, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via the data signal line 64 is applied to the gate G3 of the third transistor T3. Subsequently, the driving voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0102] In the light emitting phase, the light emitting control signal En from the light emitting control line 63 changes from a high level to a low level. Subsequently, in the light emitting phase, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emitting control signal En.

[0103] Then, a driving current is generated based on a difference between a voltage of a gate G3 of the third transistor T3 and the driving voltage VDD. A driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.

[0104] In the light emitting stage, based on the current-voltage relationship of the third transistor T3, the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst. The driving current Id is proportional to (Dm-VDD) 2. Therefore, the driving current Id may not be affected by the variation of the threshold voltage Vth of the third transistor T3.

[0105] Fig.11 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Figure 6 Schematic diagram of the cross-sectional structure taken along line AA' in FIG.

[0106] Combined with reference Figures 6 to 11 , the display substrate includes a base substrate 100 and a plurality of film layers disposed on the base substrate 100. In some embodiments, the plurality of film layers include at least a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23. The semiconductor layer 20, the first conductive layer 21, the second conductive layer 22, and the third conductive layer 23 are sequentially disposed away from the base substrate 100. The plurality of film layers also include at least a plurality of insulating film layers, for example, the plurality of insulating film layers may include a first gate insulating layer 24, a second gate insulating layer 25, and an interlayer insulating layer 26. The first gate insulating layer 24 may be disposed between the semiconductor layer 20 and the first conductive layer 21, the second gate insulating layer 25 may be disposed between the first conductive layer 21 and the second conductive layer 22, and the interlayer insulating layer 26 may be disposed between the second conductive layer 22 and the third conductive layer 23.

[0107] For example, the semiconductor layer 20 may be formed of a semiconductor material such as low temperature polysilicon, and the film thickness thereof may be in the range of 400 to 800 angstroms, for example, 500 angstroms. The first conductive layer 21 and the second conductive layer 22 may be formed of a conductive material forming a gate electrode of a thin film transistor, for example, the conductive material may be Mo, and the film thickness thereof may be in the range of 2000 to 4000 angstroms, for example, 3000 angstroms. The third conductive layer 23 may be formed of a conductive material forming a source electrode and a drain electrode of a thin film transistor, for example, the conductive material may include Ti, Al, etc. The third conductive layer 23 may have a stacked structure formed of Ti / Al / Ti, and the film thickness thereof may be in the range of 6000 to 9000 angstroms. For example, in the case where the third conductive layer 23 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 6000 angstroms, and 500 angstroms, respectively. For example, the first gate insulating layer 24 and the second gate insulating layer 25 may be formed of silicon oxide, silicon nitride or silicon oxynitride, and each layer may have a thickness of about 1000 to 2000 angstroms. For example, the interlayer insulating layer 26 may be formed of silicon oxide, silicon nitride or silicon oxynitride, and have a thickness of about 3000 to 6000 angstroms.

[0108] The display substrate includes a scan signal line 61, a reset signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged along a row direction to respectively apply a scan signal Sn, a reset control signal RESET, a light emission control signal En, and an initialization voltage Vint to the sub-pixels 11, 12, and 13. The display substrate may further include a data signal line 64 and a drive voltage line 65 crossing the scan signal line 61, the reset signal line 62, the light emission control line 63, and the initialization voltage line 66 to respectively apply a data signal Dm and a drive voltage VDD to the sub-pixels 10.

[0109] like Figure 8 As shown, the scanning signal line 61, the reset signal line 62 and the light emitting control line 63 are all located in the first conductive layer 21. The gates G1 to G7 of the above-mentioned transistors are also located in the first conductive layer 21. For example, the portion where the reset signal line 62 overlaps with the semiconductor layer 20 forms the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, respectively; the portion where the scanning signal line 61 overlaps with the semiconductor layer 20 forms the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4, respectively; the portion where the light emitting control line 63 overlaps with the semiconductor layer 20 forms the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5, respectively.

[0110] Continue to refer to Figure 8 , the display substrate may further include a plurality of first gate structures CG1. The plurality of first gate structures CG1 are also located in the first conductive layer 21. The portion of the first gate structure CG1 overlapping the semiconductor layer 20 forms a third gate G3 of the third transistor T3. The first gate structure CG1 also forms a terminal of the storage capacitor Cst, for example, a first capacitor electrode Cst1. That is, the first gate structure CG1 is used as both a gate of the third transistor T3 and an electrode of the storage capacitor Cst.

[0111] like Fig. 9As shown, the initialization voltage line 66 is located in the second conductive layer 22. The display substrate may further include a plurality of second gate structures CG2. The plurality of second gate structures CG2 are also located in the second conductive layer 22. The second gate structure CG2 forms another terminal of the storage capacitor Cst, such as a second capacitor electrode Cst2. That is, the first gate structure CG1 and the second gate structure CG2 are arranged relative to each other, and their orthographic projections on the base substrate 100 at least partially overlap with each other, and a second gate insulating layer 25 is arranged between them. For example, the first gate structure CG1 can be electrically connected to the node N1 through vias VAH1 and VAH2 and the first connecting line 68, and the second gate structure CG2 can be electrically connected to the driving voltage line 65 through the via VAH9, that is, the two are connected to different voltage signals. In this way, the portion where the first gate structure CG1 and the second gate structure CG2 overlap each other can form the storage capacitor Cst.

[0112] like Fig.10 As shown, the data signal line 64 and the driving voltage line 65 are located in the third conductive layer 23. In addition, the first connecting line 68 and the second connecting line 69 are also located in the third conductive layer 23.

[0113] Figure 12 to Figure 14 They are Figure 4 A layered diagram of Fig.12 Schematically shows a partial plan view of the first conductive layer, Fig.13 Schematically shows a partial plan view of the second conductive layer, Fig.14 Schematically shows a partial plan view of the third conductive layer. It should be noted that in order to clearly show the structure of the embodiment of the present disclosure, Figure 12 to Figure 14 In the above description, the planar structure of each sub-pixel in the display area AA is omitted. The specific planar structure of each sub-pixel can be found in the above description of Figures 5 to 10 Description.

[0114] Combined with reference Figure 4 , Figure 12 to Figure 14 Each compensation capacitor may include a first compensation capacitor electrode 110 and a second compensation capacitor electrode 120 . The first compensation capacitor electrode 110 is located in the first conductive layer 21 , and the second compensation capacitor electrode 120 is located in the second conductive layer 22 .

[0115] The first compensation capacitor electrode 110 and the second compensation capacitor electrode 120 are arranged opposite to each other, and their orthographic projections on the base substrate 100 at least partially overlap each other, and a second gate insulating layer 25 is arranged between them. For example, the first compensation capacitor electrode 110 can be electrically connected to a data signal, and the second compensation capacitor electrode 120 can be electrically connected to a driving voltage, that is, the two are connected to different voltage signals. In this way, the overlapping portion of the first compensation capacitor electrode 110 and the second compensation capacitor electrode 120 can form the compensation capacitor.

[0116] In some exemplary embodiments of the present disclosure, in a load compensation unit, the first compensation capacitor electrodes 110 of a plurality of compensation capacitors are spaced apart from each other, that is, a gap is provided between any two adjacent first compensation capacitor electrodes 110 .

[0117] For example, in the illustrated embodiment, a load compensation unit 1 may include three compensation capacitors, namely a first compensation capacitor 11, a second compensation capacitor 12, and a third compensation capacitor 13. The first compensation capacitor electrodes 110 of the first compensation capacitor 11, the second compensation capacitor 12, and the third compensation capacitor 13 are arranged at intervals from each other. That is, a first gap 14 is arranged between the first compensation capacitor electrode 110 of the first compensation capacitor 11 and the first compensation capacitor electrode 110 of the second compensation capacitor 12; a second gap 15 is arranged between the first compensation capacitor electrode 110 of the second compensation capacitor 12 and the first compensation capacitor electrode 110 of the third compensation capacitor 13.

[0118] For example, in the illustrated embodiment, each first compensation capacitor electrode 110 can extend along the column direction Y, multiple first compensation capacitor electrodes 110 in a load compensation unit 1 can be spaced apart along the row direction X, and the first gap 14 and the second gap 15 both extend along the column direction Y.

[0119] In some exemplary embodiments of the present disclosure, in one load compensation unit, the second compensation capacitor electrodes 120 of the plurality of compensation capacitors are connected to each other. In other words, the plurality of second compensation capacitor electrodes 120 of one load compensation unit are formed into a continuously extending integral structure.

[0120] For example, in a load compensation unit 1, the orthographic projection of the first compensation capacitor electrodes 110 of the plurality of compensation capacitors on the base substrate 100 falls within the orthographic projection of the plurality of second compensation capacitor electrodes 120 connected to each other on the base substrate 100. In this way, it is helpful to increase the overlapping area between the first compensation capacitor electrodes and the second compensation capacitor electrodes, thereby facilitating the increase of the capacitance value of the compensation capacitor.

[0121] It should be noted that, in the embodiment of the present disclosure, the second compensation capacitor electrodes 120 of a plurality of adjacent load compensation units may be connected to each other. In other words, the plurality of second compensation capacitor electrodes 120 of a plurality of load compensation units may be formed into a continuously extending integral structure.

[0122] Reference Fig.12 The first compensation capacitor electrode 110 may include a first electrode body 111, a first electrode connecting portion 112, and a second electrode connecting portion 113. The orthographic projection of the first electrode body 111 on the substrate is substantially rectangular. The first electrode connecting portion 112 is connected to the end of the first electrode body 111 close to the display area AA, and the second electrode connecting portion 113 is connected to the end of the first electrode body 111 away from the display area AA.

[0123] Reference Fig.13 The second compensation capacitor electrode 120 may include a second electrode body 121, a third electrode connection portion 122 and a fourth electrode connection portion 123. The orthographic projection of the second electrode body 121 on the substrate is substantially rectangular. The third electrode connection portion 122 is connected to the end of the second electrode body 121 close to the display area AA, and the fourth electrode connection portion 123 is connected to the end of the second electrode body 121 away from the display area AA.

[0124] Reference Figure 4 The display substrate further includes a plurality of first via holes VH1, for example, at least two first via holes VH1. The plurality of first via holes VH1 expose a portion of the first electrode connecting portion 112. A data signal line 64 is electrically connected to a first compensation capacitor electrode 110 through the plurality of first via holes VH1.

[0125] like Figure 4 As shown, a plurality of first via holes VH1 are arranged at intervals along the row direction X. That is, a plurality of first via holes VH1 connected to the same data signal line 64 are arranged along the row direction X. In this way, it is beneficial to fully utilize space to arrange the connection structure between the compensation capacitor and the data signal line.

[0126] The display substrate further includes a plurality of second via holes VH2, for example, at least two second via holes VH2. The plurality of second via holes VH2 expose a portion of the third electrode connecting portion 122. A driving voltage line 65 is electrically connected to a second compensation capacitor electrode 120 through the plurality of second via holes VH2.

[0127] The plurality of second via holes VH2 are arranged at intervals along the column direction Y. That is, the plurality of second via holes VH2 connected to the same driving voltage line 65 are arranged along the column direction Y. In this way, it is beneficial to fully utilize the space to arrange the connection structure between the compensation capacitor and the driving voltage line.

[0128] Combination Figure 1 and Figure 4 The test circuit 200 may include a plurality of test pins 201, and the plurality of test pins 201 may be used to provide a test signal. For example, the test signal may include a data signal for a plurality of pixel units P in the display area AA.

[0129] The display substrate further includes a plurality of third via holes VH3, for example, at least two third via holes VH3. The plurality of third via holes VH3 expose a portion of the second electrode connecting portion 113. A test pin 201 is electrically connected to a first compensation capacitor electrode 110 through the plurality of third via holes VH3.

[0130] The plurality of third via holes VH3 are arranged at intervals along the column direction Y. That is, the plurality of third via holes VH3 connected to the same test pin 201 are arranged along the column direction Y.

[0131] That is, one end of the first compensation capacitor electrode 110 is electrically connected to the test pin 201 of the test circuit 200, and the other end is electrically connected to the data signal line 64. In this way, the compensation capacitor is electrically connected to the data signal line 64 to compensate for the load on the data signal line 64 of a column of sub-pixels.

[0132] The display substrate further includes a plurality of fourth via holes VH4, for example, at least two fourth via holes VH4. The plurality of fourth via holes VH4 expose a portion of the fourth electrode connection portion 123. The display substrate may further include a driving voltage lead 650 for providing a driving voltage VDD. The driving voltage lead 650 is electrically connected to a second compensation capacitor electrode 120 through the plurality of fourth via holes VH4. The plurality of fourth via holes VH4 are arranged at intervals along the column direction Y.

[0133] That is, one end of the second compensation capacitor electrode 120 is electrically connected to the driving voltage lead 650 , and the other end is electrically connected to the driving voltage line 65 .

[0134] The display substrate may further include a plurality of scan signal leads 610 disposed on the base substrate 100 and located in the frame area NA. The plurality of scan signal leads 610 are used to transmit the scan signals output by the gate drive circuit 300 to the plurality of scan signal lines 61 and the plurality of reset signal lines 62. For example, the plurality of scan signal leads 610 may be located in the third conductive layer 23.

[0135] Reference Figure 3 and Figure 4 At least one of the plurality of scan signal lead lines 610 crosses over at least one load compensation unit 1 along the row direction X.

[0136] For each row of sub-pixels, a scan signal line 61 and a reset signal line 62 extending along the row direction X provide scan signals and reset signals to each sub-pixel in the row, respectively. Correspondingly, one end of a scan signal lead 610 is electrically connected to the gate drive circuit 300, and the other end is electrically connected to the scan signal line 61 and the reset signal line 62 through a signal transfer structure, so as to transmit the scan signal output by the gate drive circuit 300 to the plurality of scan signal lines 61 and the plurality of reset signal lines 62.

[0137] At the first rounded corner 101 and the second rounded corner 102, since a load compensation unit 1 is provided between the gate driving circuit 300 and each row of sub-pixels, a plurality of scanning signal leads 610 at the first rounded corner 101 and the second rounded corner 102 cross at least one load compensation unit 1 along the row direction X.

[0138] For example, the scan signal lead 610 may cross one load compensation unit 1 along the row direction X. Alternatively, the scan signal lead 610 may cross two adjacent load compensation units 1 along the row direction X.

[0139] For example, the orthographic projection of at least one of the plurality of scan signal leads 610 on the base substrate 100 at least partially overlaps with the orthographic projections of the first compensation capacitor electrode 110 and the second compensation capacitor electrode 120 of the plurality of compensation capacitors of at least one load compensation unit 1 on the base substrate 100 .

[0140] In an embodiment of the present disclosure, a scan signal lead for supplying a scan signal is placed above a load compensation unit so that there is an overlap between the scan signal lead and the load compensation unit, which can compensate the scan signal lead and improve the stability of the scan signal.

[0141] Fig.15 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Figure 4 Schematic diagram of the cross-sectional structure taken along line BB' in FIG. Figure 4 and Fig.15 In a load compensation unit 1, the first compensation capacitor electrodes 110 of the plurality of compensation capacitors are arranged at intervals along the row direction X to form gaps between the plurality of first compensation capacitor electrodes 110, for example, the first gaps 14 and the second gaps 15 described above.

[0142] At least one of the plurality of scanning signal leads 610 includes a first portion 611, and an orthographic projection of the first portion 611 on the base substrate 100 partially overlaps with an orthographic projection of the gap on the base substrate 100. For example, the first portion 611 of the scanning signal lead 610 extends in a direction inclined relative to both the row direction X and the column direction Y.

[0143] For example, at least one of the multiple scanning signal leads 610 includes a first part 611 and a second part 612, wherein the orthographic projection of the first part 611 on the base substrate 100 partially overlaps with the orthographic projection of the first gap 14 on the base substrate 100, and the orthographic projection of the second part 612 on the base substrate 100 partially overlaps with the orthographic projection of the second gap 15 on the base substrate 100.

[0144] For example, at least one of the first portion 611 and the second portion 612 of the scan signal lead 610 extends in a direction that is inclined relative to both the row direction X and the column direction Y. Optionally, both the first portion 611 and the second portion 612 of the scan signal lead 610 extend in a direction that is inclined relative to both the row direction X and the column direction Y. Optionally, one of the first portion 611 and the second portion 612 of the scan signal lead 610 extends in a direction that is inclined relative to both the row direction X and the column direction Y, and the other extends in the row direction X.

[0145] Continue to refer to Figure 4 The display substrate may further include a plurality of initialization voltage leads 660 disposed on the base substrate 100 and located in the frame area NA. The plurality of initialization voltage leads 660 are used to transmit the initialization voltage signal to the initialization voltage line 66. For example, the plurality of initialization voltage leads 660 may be located in the third conductive layer 23.

[0146] Reference Figure 3 and Figure 4 At least one of the plurality of initialization voltage leads 660 crosses over at least one load compensation unit 1 along the row direction X.

[0147] For example, at the first rounded corner portion 101 and the second rounded corner portion 102 , a plurality of initialization voltage lead lines 660 at the first rounded corner portion 101 and the second rounded corner portion 102 cross over at least one load compensation unit 1 along the row direction X.

[0148] For example, the initialization voltage lead 660 may cross over one load compensation unit 1 along the row direction X. Alternatively, the initialization voltage lead 660 may cross over two adjacent load compensation units 1 along the row direction X.

[0149] For example, the orthographic projection of at least one of the multiple initialization voltage leads 660 on the base substrate 100 at least partially overlaps with the orthographic projections of the first compensation capacitor electrode 110 and the second compensation capacitor electrode 120 of the multiple compensation capacitors of at least one load compensation unit 1 on the base substrate 100 .

[0150] In an embodiment of the present disclosure, an initialization voltage lead for supplying an initialization voltage signal is placed above a load compensation unit so that there is an overlap between the initialization voltage lead and the load compensation unit, which can compensate the initialization voltage lead and improve the stability of the initialization voltage signal.

[0151] At least one of the plurality of initialization voltage leads 660 includes a first portion 661, and an orthographic projection of the first portion 661 on the base substrate 100 partially overlaps with an orthographic projection of the gap on the base substrate 100. For example, the first portion 661 of the initialization voltage lead 660 extends in a direction inclined relative to both the row direction X and the column direction Y.

[0152] For example, at least one of the multiple initialization voltage leads 660 includes a first part 661 and a second part 662, wherein the orthographic projection of the first part 661 on the base substrate 100 partially overlaps with the orthographic projection of the first gap 14 on the base substrate 100, and the orthographic projection of the second part 662 on the base substrate 100 partially overlaps with the orthographic projection of the second gap 15 on the base substrate 100.

[0153] For example, at least one of the first portion 661 and the second portion 662 of the initialization voltage lead 660 extends in a direction that is inclined relative to both the row direction X and the column direction Y. Optionally, both the first portion 661 and the second portion 662 of the initialization voltage lead 660 extend in a direction that is inclined relative to both the row direction X and the column direction Y. Optionally, one of the first portion 661 and the second portion 662 of the initialization voltage lead 660 extends in a direction that is inclined relative to both the row direction X and the column direction Y, and the other extends in the row direction X.

[0154] Continue to refer to Figure 3 , Figure 4 and Figure 12 to Figure 14 , an orthographic projection of a first compensation capacitor electrode 110 on the substrate 100 has a first size along the column direction Y. The first size of the orthographic projection of a first compensation capacitor electrode 110 on the substrate 100 along the column direction Y can be represented by the size of the orthographic projection of the first electrode body 111 on the substrate 100 along the column direction Y, that is, Figure 3 The H1 in it indicates.

[0155] For example, a load compensation unit 1 partially overlaps with another load compensation unit 1 adjacent to it in the column direction Y, and the size of the overlapping portion of the two adjacent load compensation units along the column direction Y may be less than or equal to one half of the first size H1. For example, the size of the overlapping portion of the two adjacent load compensation units along the column direction Y may be less than or equal to one half of the first size H1.

[0156] For example, one load compensation unit 1 and another load compensation unit 1 adjacent thereto may not overlap in the column direction Y, that is, one load compensation unit 1 and another load compensation unit 1 adjacent thereto are arranged at intervals in the column direction Y.

[0157] In the embodiment of the present disclosure, as described above, the number of sub-pixels included in the reference pixel column is N, and the number of sub-pixels included in the edge pixel column is M. When compensating the load on the data signal line, the value of the load to be compensated can be determined according to the difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column. Figure 1 In the rounded rectangular display substrate shown, since the difference between the number of sub-pixels included in the edge pixel column to be compensated and the number of sub-pixels included in the reference pixel column is small, the capacitance value of the compensation capacitor can be set to be small. In other words, the overlapping area of ​​the first compensation capacitor electrode 110 and the second compensation capacitor electrode 120 in each load compensation unit 1 is proportional to the number of missing pixel units in a column of pixel units corresponding to the load compensation unit 1 (i.e., the value of NM).

[0158] In some exemplary embodiments, the capacitance value of each compensation capacitor may be less than a capacitance threshold. For example, the capacitance threshold may be approximately 5 fF.

[0159] Since the capacitance value of the compensation capacitor is small, the mutual influence between adjacent compensation capacitors is also small, and accordingly, the gap between adjacent compensation capacitors can be set to be small. For example, in the embodiment of the present disclosure, the size of each of the first gap 14 and the second gap 15 along the row direction X is between 1 and 6 microns.

[0160] In addition, in the embodiment of the present disclosure, since the mutual influence between adjacent compensation capacitors is small, a partition member, such as one located in the semiconductor layer 20, may not be provided in the first gap 14 and the second gap 15 to isolate adjacent compensation capacitors. In other words, the orthographic projection of each of the first gap 14 and the second gap 15 on the base substrate 100 does not overlap with the orthographic projection of the semiconductor layer 20 on the base substrate 100.

[0161] Through the above arrangement, the occupied area of ​​the load compensation unit can be reduced, which is conducive to achieving a narrow frame.

[0162] At least some embodiments of the present disclosure also provide a display panel, which includes the display substrate as described above. For example, the display panel may be an OLED display panel.

[0163] Reference Figure 1 At least some embodiments of the present disclosure further provide a display device. The display device may include the display substrate described above. The display device includes a display area AA and a frame area NA, and the frame area NA has a small width, thereby realizing a display device with a narrow frame.

[0164] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0165] It should be understood that the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description, which will not be repeated here.

[0166] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will appreciate that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, characterized in that: The display substrate comprises: A base substrate, the base substrate comprising a display area and a frame area located on at least one side of the display area; A plurality of pixel units located in the display area, the plurality of pixel units are arranged in an array on the substrate along a row direction and a column direction, and each pixel unit includes a plurality of sub-pixels; A plurality of scanning signal lines disposed on the base substrate, the plurality of scanning signal lines being used to provide scanning signals to a plurality of rows of sub-pixels respectively; A gate driving circuit disposed on the base substrate and located in the frame area, the gate driving circuit being used to output a scanning signal; A plurality of load compensation units are disposed on the base substrate and located in the frame area, and the plurality of load compensation units are located between the gate driving circuit and the plurality of pixel units; and A plurality of scanning signal lead lines are arranged on the base substrate and located in the frame area, and the plurality of scanning signal lead lines are used to transmit the scanning signals output by the gate driving circuit to the plurality of scanning signal lines respectively. Wherein, at least one of the scan signal leads crosses over at least one of the load compensation units along the row direction; The load compensation unit comprises at least three compensation capacitors, and in one load compensation unit, first compensation capacitor electrodes of the at least three compensation capacitors are arranged at intervals along the row direction to form a first gap and a second gap respectively between the at least three first compensation capacitor electrodes; At least one of the scanning signal leads comprises a first portion and a second portion, the orthographic projection of the first portion of the scanning signal lead on the base substrate partially overlaps with the orthographic projection of the first gap on the base substrate, and the orthographic projection of the second portion on the base substrate partially overlaps with the orthographic projection of the second gap on the base substrate; One of the first and second parts of the scan signal lead line extends in a direction inclined relative to both the row direction and the column direction, and the other of the first and second parts of the scan signal lead line extends in the row direction; Each compensation capacitor comprises a first compensation capacitor electrode and a second compensation capacitor electrode, wherein the first compensation capacitor electrode is located in a first conductive layer, and the second compensation capacitor electrode is located in a second conductive layer, and an orthographic projection of the first compensation capacitor electrode on the substrate and an orthographic projection of the second compensation capacitor electrode on the substrate at least partially overlap; The plurality of scanning signal leads are located in the third conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the third conductive layer is located on a side of the second conductive layer away from the base substrate; and The display substrate further comprises: a plurality of data signal lines arranged on the base substrate, the plurality of data signal lines are used to provide data signals to a plurality of columns of sub-pixels respectively, and each of the compensation capacitors is electrically connected to one of the data signal lines.

2. The display substrate according to claim 1, characterized in that: An orthographic projection of at least one of the scan signal leads on the substrate partially overlaps with an orthographic projection of at least one load compensation unit on the substrate.

3. The display substrate according to claim 2, characterized in that: The orthographic projection of at least one of the scanning signal leads on the substrate at least partially overlaps with the orthographic projections of the first compensation capacitor electrodes and the second compensation capacitor electrodes of the plurality of compensation capacitors of at least one load compensation unit on the substrate.

4. The display substrate according to claim 2 or 3, characterized in that: In a load compensation unit, the first compensation capacitor electrodes of the plurality of compensation capacitors are arranged at intervals along the row direction to form gaps between the plurality of first compensation capacitor electrodes; as well as At least one of the scan signal leads comprises a first portion, and an orthographic projection of the first portion of the scan signal lead on the base substrate partially overlaps with an orthographic projection of the gap on the base substrate.

5. The display substrate according to claim 4, characterized in that: The first portion of the scan signal lead line extends in a direction inclined with respect to both the row direction and the column direction.

6. The display substrate according to claim 2 or 3, characterized in that: Each of the first compensation capacitor electrodes is electrically connected to one of the data signal lines through at least two first via holes. Wherein, the at least two first via holes are arranged at intervals along the row direction.

7. The display substrate according to claim 2 or 3, characterized in that: The orthographic projection of one of the first compensation capacitor electrodes on the substrate has a first size along the column direction, a load compensation unit partially overlaps with another adjacent load compensation unit in the column direction, and the size of the overlapping part of the two adjacent load compensation units along the column direction is less than or equal to half of the first size.

8. The display substrate according to claim 2 or 3, characterized in that: A load compensation unit is arranged with an interval from another load compensation unit adjacent to it in the column direction.

9. The display substrate according to claim 4, characterized in that: The display substrate further comprises: A plurality of initialization voltage lines disposed on the base substrate, the plurality of initialization voltage lines being used to provide initialization voltage signals to the plurality of rows of sub-pixels respectively; and A plurality of initialization voltage leads are disposed on the base substrate and located in the frame area, and the plurality of initialization voltage leads are used to transmit an initialization voltage signal to the plurality of initialization voltage lines. Wherein, at least one of the initialization voltage leads crosses over at least one of the load compensation units along the row direction.

10. The display substrate according to claim 9, characterized in that: At least one of the initialization voltage lead wires includes a first portion, and an orthographic projection of the first portion of the initialization voltage lead wire on the base substrate partially overlaps with an orthographic projection of the gap on the base substrate.

11. The display substrate according to claim 10, characterized in that: A first portion of the initialization voltage lead line extends in a direction inclined with respect to both the row direction and the column direction.

12. The display substrate according to claim 6, characterized in that: The display substrate further comprises: a plurality of driving voltage lines disposed on the base substrate, the plurality of driving voltage lines being used to provide driving voltage signals to the plurality of columns of sub-pixels respectively; Each of the second compensation capacitor electrodes is electrically connected to one of the driving voltage lines through at least two second via holes. Wherein, the at least two second via holes are arranged at intervals along the column direction.

13. The display substrate according to claim 6, characterized in that: The display substrate further comprises: a test circuit disposed on the base substrate and located in the frame area, the test circuit being used to output a data signal. Wherein, each of the first compensation capacitor electrodes is electrically connected to the test circuit through at least two third vias.

14. The display substrate according to claim 12, characterized in that: The display substrate further comprises: a driving voltage lead wire disposed on the base substrate and located in the frame region, the driving voltage lead wire being used to transmit a driving voltage signal, Wherein, each of the second compensation capacitor electrodes is electrically connected to the driving voltage lead through at least two fourth via holes.

15. The display substrate according to claim 9, characterized in that: At least one of the initialization voltage leads includes a first part and a second part, wherein the orthographic projection of the first part of the initialization voltage lead on the base substrate partially overlaps with the orthographic projection of the first gap on the base substrate, and the orthographic projection of the second part of the initialization voltage lead on the base substrate partially overlaps with the orthographic projection of the second gap on the base substrate.

16. The display substrate according to claim 15, characterized in that: At least one of the first portion and the second portion of the initialization voltage lead line extends in a direction inclined with respect to both the row direction and the column direction.

17. The display substrate according to claim 16, characterized in that: In a load compensation unit, the second compensation capacitor electrodes of the plurality of compensation capacitors are connected to each other.

18. The display substrate according to claim 17, characterized in that: In a load compensation unit, the orthographic projections of first compensation capacitor electrodes of the plurality of compensation capacitors on the substrate fall within the orthographic projections of a plurality of second compensation capacitor electrodes connected to each other on the substrate.

19. The display substrate according to claim 18, characterized in that: The orthographic projections of the plurality of second compensation capacitor electrodes connected to each other on the base substrate cover the orthographic projections of each of the first gap and the second gap on the base substrate.

20. The display substrate according to claim 19, characterized in that: The orthographic projections of the plurality of second compensation capacitor electrodes connected to each other on the base substrate cover the orthographic projections of each of the first part and the second part of the scan signal lead on the base substrate; as well as The orthographic projections of the plurality of second compensation capacitor electrodes connected to each other on the base substrate cover the orthographic projections of each of the first portion and the second portion of the initialization voltage lead on the base substrate.

21. The display substrate according to claim 1, characterized in that: A size of each of the first gap and the second gap along the row direction is between 1 and 6 micrometers.

22. The display substrate according to claim 9, characterized in that: The plurality of scanning signal lines are located in the first conductive layer; and / or, The plurality of initialization voltage lines are located in the second conductive layer.

23. The display substrate according to claim 1, characterized in that: The orthographic projection of the display area on the base substrate is in the shape of a rounded rectangle.

24. The display substrate according to claim 23, characterized in that: The plurality of load compensating units are arranged along contour lines of rounded corners of the rounded rectangle.

25. The display substrate according to claim 3, characterized in that: The multiple load compensation units correspond to multiple columns of pixel units respectively, and the overlapping area of ​​the first compensation capacitor electrode and the second compensation capacitor electrode in each load compensation unit is proportional to the number of missing pixel units in a column of pixel units corresponding to the load compensation unit.

26. A display device comprising the display substrate according to any one of claims 1-25.

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