Method and system for compressing and decompressing compensation data for compensating uneven display brightness

Abstract

A display system (400) includes a display (102) having a plurality of pixels, a processor (114), and control logic (104). The processor (114) includes: a graphics pipeline (404) configured to generate a plurality of pixel data slices for the plurality of pixels; and a preprocessing module (405) configured to generate a plurality of compensation data slices for the pixel data and compress the compensation data. The method of compressing the compensation data is to determine a plurality of quantized downsampled compensation data slices according to the compensation data, convert the quantized downsampled compensation data into M index data units, and convert the M index data units into M bitstreams. The control logic (104) is operatively coupled to the display (102) and the processor (114) and includes a postprocessing module (408) configured to decompress the compressed compensation data based on the M bitstreams to provide control signals.

Description

Technical Field

[0001] The present disclosure generally relates to display technologies, and more particularly, to display data processing. Background Art

[0002] In display technologies, "mura" refers to uneven brightness of a display screen, resulting in a decline in display quality. "Demura" refers to the process of compensating for uneven brightness. According to the physical characteristics of the display screen, compensation data is generated to compensate for pixel data displayed on the display screen. The compensation data is usually arranged in the form of a look-up table, and the look-up table is stored in a memory, such as a flash memory. The compensation data is usually compressed first and then decompressed during the display process to reduce the storage space in the memory. Summary of the Invention

[0003] The present disclosure generally relates to display technologies, and more specifically, to compression and decompression of compensation data for compensating for uneven brightness.

[0004] In one example, a display system includes a display having a plurality of pixels, a processor, and control logic operatively coupled to the display and the processor. The processor includes a graphics pipeline configured to generate a plurality of pixel data slices of the pixel data and a preprocessing module configured to generate a plurality of compensation data slices of the pixel data and compress the compensation data. Compression of the compensation data includes the following operations. First, based on the compensation data, a plurality of quantized downsampled compensation data is determined. The size of the quantized downsampled compensation data is smaller than the size of the compensation data. The quantized downsampled compensation data is converted into M index data units. M is a positive integer greater than 1 and less than the size of the quantized downsampled compensation data. The M units of the index data are converted into M bitstreams. The control logic includes a postprocessing module configured to decompress the compensation data based on the M bitstreams to provide a control signal for driving the display.

[0005] In another example, a method for compressing and decompressing display compensation data is provided. The method includes the following operations. First, a plurality of compensation data slices for pixel data for display are generated. The compensation data can be compressed by the following operations. Based on the compensation data, a plurality of quantized downsampled compensation data is determined, and the size of the quantized downsampled compensation data is smaller than the size of the compensation data. The quantized downsampled compensation data is converted into M index data units, where M is a positive integer greater than 1 and less than the size of the quantized downsampled compensation data. The M units of the index data are converted into M bitstreams. The compensation data is decompressed according to the M bitstreams to provide a control signal for driving the display.

[0006] In another example, a non-transitory computer-readable medium stores a set of instructions that, when executed by at least one processor, cause the at least one processor to determine a method for compressing and decompressing compensation data for display. The method includes the following operations. First, a plurality of compensation data slices for pixel data for display are generated. The compensation data can be compressed by the following operations. A plurality of quantized downsampled compensation data are determined based on the compensation data, and the size of the quantized downsampled compensation data is smaller than the size of the compensation data. The quantized downsampled compensation data are converted into M index data units, where M is a positive integer greater than 1 and less than the size of the quantized downsampled compensation data. The M units of the index data are converted into M code streams. The compensation data is decompressed according to the M code streams to provide a control signal for driving the display. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments will be understood more readily from the following description when taken in conjunction with the accompanying drawings, in which like reference numerals designate like elements, and in which:

[0008] Figure 1 A block diagram showing a device that includes display and control logic according to an embodiment of the present invention.

[0009] Figures 2A - 2C Shows Figure 1 A side view schematic diagram of various embodiments of the shown display.

[0010] Figure 3 Shows according to Figure 1 A plan view of an embodiment of the shown display including a plurality of driver displays;

[0011] Figure 4A A system block diagram showing a display, control logic, and a processor according to an embodiment;

[0012] Figure 4B Shows according to an embodiment Figure 4A A detailed block diagram of an example of a preprocessing module in the shown processor;

[0013] Figure 4C Shows according to an embodiment Figure 4A A detailed block diagram of an example of a post-processing module in the shown processor.

[0014] Figure 5A Is a schematic diagram of a downsampling operation of a display screen according to an embodiment.

[0015] Figure 5B Shows a plurality of exemplary downsampled compensation data in an exemplary order according to an embodiment;

[0016] Figure 5C Shows a plurality of exemplary quantization values according to an embodiment of the present invention.

[0017] Figure 5D Shows an exemplary specific range quantization method according to one embodiment.

[0018] Figure 5E Shows exemplary multiple quantized downsampling compensation data slices according to one embodiment.

[0019] Figure 5F Shows multiple downsampling compensation data slices of exemplary sequential quantization according to one embodiment.

[0020] Figure 5G Shows an index for forming basic lookup table (IBL) data exemplarily according to one embodiment.

[0021] Figure 5H Shows an example of M units divided to form IBL data according to one embodiment.

[0022] Figure 5I Shows multiple IBL values of exemplary order according to the present invention.

[0023] Figure 5J Shows an example of forming an initial bitstream according to one embodiment.

[0024] Figure 5K Shows an exemplary compression compensation data structure according to one embodiment.

[0025] Figure 6A Shows an example of forming IBL data according to one embodiment.

[0026] Figure 6B Illustrates an example of forming quantized downsampling compensation data according to one embodiment.

[0027] Figure 6C Schematically illustrates an upsampling operation on a display screen according to one embodiment of the present invention.

[0028] Figure 7A and 7B Shows an upsampling operation on a display screen according to an embodiment of the present invention; Figure 7A and 7B Illustrates a flowchart of a method for compressed compensation data in a display screen according to one embodiment; and

[0029] Figure 8 Shows a flowchart of a method for decompressing compensation data in a display screen according to one embodiment of the present invention. Detailed Description

[0030] In the following detailed description, numerous specific details are set forth by way of example in order to provide a thorough understanding of the relevant disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be practiced without such details. In other instances, well-known methods, procedures, systems, components, and / or circuits have been described in relatively great detail in order to avoid unnecessarily obscuring aspects of the present disclosure.

[0031] Throughout the specification and claims, the meanings of terms may be implicit as well as explicit in the context in which they are used. Similarly, the phrase "in one embodiment / instance" used herein does not necessarily refer to the same embodiment, and the phrase "in another embodiment / example" used herein does not necessarily refer to another embodiment. For example, the claimed subject matter may include combinations of example embodiments, in whole or in part.

[0032] In general, terms can be understood, at least in part, from their use in context. For example, terms such as "and," "or," or "and / or" used herein may include a variety of meanings that may, at least in part, depend on the context in which they are used. Generally, "or" if used to relate a list, such as a, b, or c, is inclusive of a, b, and c if used in an inclusive sense, and exclusive of a, b, or c if used in an exclusive sense. Additionally, the term "one or more" used herein can, at least in part, depend on context and can be used to denote any feature, structure, or characteristic in the singular, or can also be used to describe combinations of multiple features, structures, or characteristics. Similarly, terms such as "a," "an," or "the" can, at least in part, depend on context and can be understood to convey a singular or plural meaning. Additionally, the term "based on" can be understood to not necessarily convey an exclusive set of factors, and may allow for the presence of other factors not necessarily expressly stated, again, at least in part, depending on context.

[0033] As will be disclosed in detail below, among other novel features, the display systems, devices, and methods of the present disclosure can effectively reduce the size of compensation data for compensating display non-uniformity (e.g., "mura" caused by, for example, manufacturing non-uniformity) of a display screen. The compensation data can be compressed, thereby improving efficiency and accuracy. Less storage space is required for storing the compressed compensation data in a memory (e.g., flash memory). Compared with conventional methods, the bandwidth for transmitting the compressed compensation data can be reduced using the data compression method of the present disclosure.

[0034] According to embodiments of the present disclosure, the compensation data undergoes multiple compression operations, significantly reducing the size of the compensation data. At the beginning of the process, the compensation data is downsampled, for example, downsampled with a coefficient greater than 1, reducing the size of the compensation data. Then the downsampled compensation data is quantized so that the quantization values of at least two blocks of the downsampled compensation data are the same, further reducing the size of the compensation data. The quantized downsampled compensation data is further converted into index data, which only includes non-negative integers and has a smaller range than the quantized downsampled compensation data. Since the quantized downsampled compensation data often includes negative and positive values and has a relatively arbitrary distribution, converting the quantized downsampled compensation data into index data can further reduce the size of the compensation data. Then, the index data is divided into M units and converted into M binary bitstreams (e.g., bits), further reducing the quantized downsampled compensation data. In some embodiments, the downsampling and quantization operations are lossy data compression. In some embodiments, the conversion from the quantized downsampled compensation data to the index data and the conversion from the index data to the bitstream include lossless data compression. The compressed compensation data, including the bitstream and other data for decompressing the compensation data, can be stored in a flash memory. In some embodiments, the compression of the compensation data, i.e., downsampling, quantization, and conversion, is performed by a processor (or an application processor (AP)).

[0035] Accessing and decompressing the stored compressed compensation data forms decompressed compensation data. First, the M bitstreams are converted into the corresponding index data. Then the index data is converted into the corresponding quantized downsampled compensation data. Since the conversions employed in the data compression are lossless data compression, the quantized downsampled compensation data formed in the decompression operation is exactly the same as the quantized downsampled compensation data before conversion in the compression operation. In some embodiments, the conversion operations in the decompression operation are the respective reverse operations of the conversion operations in the compression operation. The quantized downsampled compensation data is further upsampled by the same coefficient as the downsampling to form the decompressed compensation data, which has the same size as the compensation data (or the original compensation data before compression and decompression operations). In some embodiments, the decompression of the compressed compensation data, i.e., conversion and upsampling, is performed by control logic (or a display driver integrated circuit (DDIC)).

[0036] Other novel features will be partly described in the following description, partly obvious to those of ordinary skill in the art, and understood by reading the following content and the drawings or by producing or operating embodiments of the invention. The novel features of the present disclosure can be realized and achieved by practicing or using aspects of the methods, tools, and combinations described in the detailed embodiments discussed below.

[0037] For ease of description, as used herein, "a piece of data" or similar such description refers to a set of data (e.g., compensation data or display data), which may include one or more values. For example, in the present disclosure, a "compensation data slice" refers to any number of values used to compensate a pixel. The compensation data slice may include at least one value for compensating a sub-pixel. When a data slice includes one value, "data slice" and "value" may be interchangeable. For example, when the compensation data slice includes only one value, the compensation data slice may also be referred to as a compensation value, or similar to a compensation value. The number of specific numerical values included in the compensation data slice should not be limited.

[0038] Figure 1 An apparatus 100 is shown, including a display device 102 and control logic 104. The apparatus 100 may be any suitable device, e.g., a VR / AR device (e.g., a VR headset, etc.), a handheld device (e.g., a feature phone or a smartphone, a tablet computer, etc.), a wearable device (e.g., glasses, a wristwatch, etc.), an automotive console, a gaming console, a television, a laptop computer, a desktop computer, a netbook computer, a media center, a set-top box, a global positioning system (GPS), an electronic billboard, an electronic sign, a printer, or any other suitable device. In the present embodiment, the display 102 is operatively coupled to the control logic 104 and is part of the apparatus 100, such as but not limited to a head-mounted display, a computer display, a television screen, a dashboard, an electronic billboard, or an electronic sign. The display 102 may be an OLED display, a liquid crystal display (LCD), an E-ink display, an electroluminescent display (ELD), an electronic billboard display with LEDs or incandescent lamps, or any other suitable type of display.

[0039] The control logic 104 can be any suitable hardware, software, firmware, or combination thereof, configured to receive display data 106 (e.g., pixel data and compensation data) and generate control signals 108 to drive sub-pixels on the display 102. The control signals 108 are used to control the writing of display data to the sub-pixels and to direct the operation of the display 102. For example, sub-pixel rendering algorithms for various sub-pixel arrangements can be part of or implemented by the control logic 104. The control logic 104 can include any other suitable components, such as encoders, decoders, one or more processors, controllers, and storage devices. The control logic 104 can be implemented as a stand-alone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The device 100 can also include any other suitable components, such as but not limited to a tracking device 110 (e.g., an inertial sensor, a camera, an eye tracker, a GPS, or any other suitable device for tracking the movement of eye movements, facial expressions, head movements, body movements, and gestures) and an input device 112 (e.g., a mouse, a keyboard, a remote control, a handwriting device, a microphone, a scanner, etc.).

[0040] In this embodiment, the device 100 can be a handheld device or a VR / AR device, such as a smart phone, a tablet, or a VR headset. The device 100 can also include a processor 114 and a memory 116. The processor 114 can be, for example, a graphics processor (e.g., a graphics processing unit (GPU)), an application processor (AP), a general-purpose processor (e.g., an APU, an accelerator processing unit; a GPGPU, general-purpose computing on a GPU), or any other suitable processor. The memory 116 can be, for example, a discrete frame buffer or a unified memory. The processor 114 is configured to generate display data 106 in a display frame and can temporarily store it in the memory 116 before sending the display data 106 to the control logic 104. The processor 114 can also generate other data, such as but not limited to control instructions 118 or test signals, and provide them to the control logic 104 directly or through the memory 116. Then, the control logic 104 receives the display data 106 from the memory 116 or directly from the processor 114. In some embodiments, no control instructions 118 are directly transmitted from the processor 114 to the control logic 104. In some embodiments, the compensation data transmitted from the processor 114 to the memory 116 and / or from the memory 116 to the control logic 104 can be compressed.

[0041] In some embodiments, control logic 104 is part of device 100, processor 114 is part of an external device of device 100, and memory 116 is an external storage device for storing data calculated by processor 114. Data stored in processor 114 can be input into control logic 104 for further processing. In some embodiments, control instructions 118 are not transmitted from processor 114 to control logic 104. For example, device 100 can be a smartphone or a tablet computer, and control logic 104 can be part of device 100. Processor 114 can be part of an external computer different from device 100 / control logic 104. Display data 106 can include any suitable data calculated by processor 114 and transmitted from processor 114 to control logic 104. For example, the display data can include compressed compensation data. In some embodiments, display data 106 does not include pixel data. Memory 116 can include a flash drive for storing compressed compensation data processed by processor 114. Memory 116 can be coupled to control logic 104 to input the compressed compensation data into device 100, such that control logic 104 can decompress the compressed compensation data and generate corresponding control signals 108 for display 102.

[0042] Figure 2A A side view showing an embodiment of display 102 includes sub-pixels 202, 204, 206, and 208. Display 102 can be any suitable type of display, for example, an OLED display, such as an active matrix OLED (AMOLED) display, or any other suitable display. Display 102 can include a display screen 210, which is operatively coupled to control logic 104. Figure 2A The example shown illustrates a side-by-side (also known as side emitter) OLED color patterning architecture, where a light-emitting material of one color is deposited through a metal mask, while other color regions are masked.

[0043] In this embodiment, display screen 210 includes a light-emitting layer 214 and a driving circuit layer 216. As Figure 2A shown, light-emitting layer 214 includes a plurality of light-emitting elements (e.g., OLEDs) 218, 220, 222, and 224, corresponding to a plurality of sub-pixels 202, 204, 206, and 208, respectively. Figure 2A A, B, C, and D in Figure 2AAs shown, the light-emitting layer 214 further includes a black matrix 226 disposed between the OLEDs 218, 220, 222, and 224. The black matrix 226 serves as the boundary of the sub-pixels 202, 204, 206, and 208 and is used to block light emitted from components outside the OLEDs 218, 220, 222, and 224. Each of the OLEDs 218, 220, 222, and 224 in the light-emitting layer 214 can emit light of a predetermined color and brightness.

[0044] In this embodiment, the driving circuit layer 216 includes a plurality of pixel circuits 228, 230, 232, and 234, where each pixel circuit 228, 230, 232, and 234 includes one or more thin-film transistors (TFTs), corresponding to the OLEDs 218, 220, 222, and 224 of the sub-pixels 202, 204, 206, and 208 of the OLEDs, respectively. The pixel circuits 228, 230, 232, and 234 can be addressed by control signals 108 from the control logic 104, and configured to drive the corresponding sub-pixels 202, 204, 206, and 208 by controlling the light emitted from their respective OLEDs 218, 220, 222, and 224 according to the control signals 108. The driving circuit layer 216 may further include one or more drivers (not shown), which are formed on the same substrate as the pixel circuits 228, 230, 232, and 234. The drivers on the panel may include circuits for controlling light emission, gate scanning, and data writing, as described in detail below. Scan lines and data lines are also formed in the driving circuit layer 216 for transmitting scan signals and data signals from the driving circuits 228, 230, 232, and 234 to the respective pixel circuits 228, 230, 232, and 234. The display screen 210 may include any other suitable components, such as one or more glass substrates, polarization layers, or touch panels (not shown). In this embodiment, the pixel circuits 228, 230, 232, and 234 and other elements in the driving circuit layer 216 in this embodiment are formed on a low-temperature polycrystalline silicon (LTPS) layer deposited on a glass substrate, and the TFTs in each pixel circuit 228, 230, 232, and 234 are p-type transistors (e.g., PMOS LTPS-TFTs). In some embodiments, the elements in the driving circuit layer 216 may be formed on an amorphous silicon (a-Si) layer, and the TFTs in each pixel circuit may be n-type transistors (e.g., NMOS TFTs). In some embodiments, the TFTs in each pixel circuit may be organic TFTs (OTFTs) or indium gallium zinc oxide TFTs (IGZO).

[0045] As Figure 2AAs shown, each of the sub-pixels 202, 204, 206, and 208 is formed by at least one OLED 218, 220, 222, and 224 driven by corresponding pixel circuits 228, 230, 232, and 234. The OLED can be formed by a sandwich structure of an anode, an organic light-emitting layer, and a cathode. Depending on the characteristics of the organic light-emitting layer of each OLED (e.g., material, structure, etc.), the sub-pixels can exhibit different colors and brightness. In this embodiment, each of the OLEDs 218, 220, 222, and 224 is a top-emitting OLED. In some embodiments, the OLED can be in a different configuration, such as a bottom-emitting OLED. In one example, a pixel can be composed of three adjacent sub-pixels, such as sub-pixels with three primary colors (red, green, and blue) to present full color. In another example, a pixel can include four adjacent sub-pixels, such as sub-pixels with three primary colors (red, green, and blue) and white. In yet another example, a pixel can include two adjacent sub-pixels. For example, sub-pixels A 202 and B 204 can form one pixel, and sub-pixels C 206 and D 208 can form another pixel. Here, since the display data 106 is typically programmed at the pixel level, two sub-pixels of each pixel or multiple sub-pixels of several adjacent pixels can be co-addressed through sub-pixel rendering to present the appropriate brightness and color of each pixel, such as the display data 106 (e.g., pixel data). However, it should be understood that in some embodiments, the display data 106 can be programmed at the sub-pixel level such that the display data 106 can directly address individual sub-pixels without sub-pixel rendering. Since three primary colors (red, green, and blue) are generally required to present full color, a specially designed sub-pixel arrangement can be provided for the display 102 in combination with a sub-pixel rendering algorithm to achieve an appropriate apparent color resolution. In some embodiments, the resolution of each of red, green, and blue is equal to each other. In other embodiments, the resolutions of red, green, and blue may not be exactly the same.

[0046] Figure 2A The example shown illustrates a side-by-side patterned architecture where a light-emitting material of one color is deposited through a metal mask while other color regions are masked. In another embodiment, a patterned architecture of a white OLED with a color filter layer (WOLED+CF) can be applied to the display screen 210. In the WOLED+CF architecture, a stack of light-emitting materials forms a light-emitting layer for white light. The color of each individual sub-pixel is defined by another layer of color filter layers of different colors. Since the organic light-emitting material does not need to be patterned through a metal mask, the resolution and display size can be improved through the WOLED+CF patterned architecture. Figure 2BAn embodiment of a WOLED+CF patterning architecture applied to a display screen 210 is shown. In this embodiment, the display screen 210 includes a driving circuit layer 216, a light-emitting layer 236, a color filter layer 238, and a packaging layer 239. In this embodiment, the light-emitting layer 236 includes a stack of light-emitting sub-layers and emits white light. The color filter layer 238 may include a color filter layer array having a plurality of color filter layers 240, 242, 244, and 246 corresponding to sub-pixels 202, 204, 206, and 208 respectively. Figure 2B A, B, C, and D in Figure 2B represent four different color filter layers, such as, for example but not limited to, red, green, blue, yellow, cyan, magenta, or white. The color filter layers 240, 242, 244, and 246 may be formed of a resin film containing dyes or pigments having the desired colors. Depending on the characteristics (e.g., color, thickness, etc.) of their respective color filter layers, the sub-pixels may exhibit distinct colors and brightnesses. The packaging layer 239 may include a packaging glass substrate or a substrate manufactured by thin-film encapsulation (TFE) technology. The driving circuit layer 216 may include a pixel circuit array including LTPS, IGZO, or OTFT transistors. The display screen 210 may include any other suitable elements, such as a polarization layer, or a touch panel (not shown).

[0047] In another embodiment, a patterning architecture of a blue OLED with a transferred color filter layer (BOLED+transferred color filter layer (BOLED+transferred CF)) may also be applied to the display screen 210. In the BOLED+transferred color filter layer (BOLED+transferred color filter layer (BOLED+transferred color filter layer CF)) architecture, a light-emitting material for blue light is deposited without a metal mask, and the color of each individual sub-pixel is defined by another layer of transferred color filter layers as different colors of transferred color filter layers. Figure 2C An embodiment of a BOLED+transfer CF patterning architecture applied to a display screen 210 is shown. The display screen 210 in this embodiment includes a driving circuit layer 216, a light-emitting layer 248, a transferred color layer 250, and a packaging layer 251. The light-emitting layer 248 emits blue light in this embodiment and may be deposited without using a metal mask. It should be understood that in some embodiments, the light-emitting layer 248 may emit light of other colors. The color transfer layer 250 may include a transferred color filter layer array 250 having a plurality of transferred color filter layers 252, 254, 256, and 258 corresponding to sub-pixels 202, 204, 206, and 208 respectively. Figure 2CA, B, C, and D in [description] represent four different color transfer color filter layers, for example but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each type of transfer color filter layer can be formed of a color-changing material. Depending on the characteristics (e.g., color, thickness, etc.) of their respective transfer color filter layers, the sub-pixels can exhibit distinct colors and brightness. The encapsulation layer 251 can include an encapsulation glass substrate or a substrate manufactured by TFE technology. The driving circuit layer 216 can include a pixel circuit array of LTPS, IGZO, or OTFT transistors. The display screen 210 can include any other suitable components, such as a polarization layer or a touch panel (not shown).

[0048] The compression and decompression methods of the present disclosure are applicable to any known OLED patterning architecture, including but not limited to the side-by-side, WOLED+CF, and BOLED+CCM patterning architectures described above. Although Figures 2A - 2C shown in the manner of an OLED display, it should be understood that they are for illustrative purposes only and are not restrictive. The methods disclosed herein can be applied to any suitable display, as described above.

[0049] Figure 3 is Figure 1 a plan view of the display 102 shown, which includes a plurality of drivers. According to one embodiment of the present invention, Figure 3 is Figure 1 a plan view of the display 102 shown. In this embodiment, the display screen 210 includes a sub-pixel array 300 (e.g., OLED), a plurality of pixel circuits (not shown), and a plurality of on-panel drivers, including a light-emitting driver 302, a gate scan driver 304, and a source write driver 306. The pixel circuit is operatively coupled to the sub-pixel array 300 and the on-panel drivers 302, 304, and 306. In this embodiment, the light-emitting driver 302 is configured to cause the sub-pixel array 300 to emit light in each frame. It should be understood that although Figure 3 only one light-emitting driver 302 is shown, in some embodiments, a plurality of light-emitting drivers can cooperate with each other.

[0050] In the present embodiment, the gate scan driver 304 applies a plurality of scan signals S0 - Sn, which are generated based on the control signal 108 from the control logic 104, to the scan lines (also referred to as gate lines) of each row of sub - pixels 300 in the array of sub - pixels 300. During the scan / charge period, the scan signals S0 - Sn are applied to the gate electrodes of the switching transistors of each pixel circuit to turn on the switching transistors, so that the data signals of the corresponding sub - pixels are written by the source write driver 306. As will be described in detail below, in different embodiments, the order of applying the scan signals to each row of the sub - pixel array 300 (i.e., the gate scan order) can be different. In some embodiments, not all rows of sub - pixels are scanned in each frame. It should be understood that although Figure 3 a single gate scan driver 304 is shown, in some embodiments, multiple gate scan drivers can cooperate with each other to scan the array of sub - pixels 300.

[0051] In the present embodiment, the source write driver 306 is configured to write the display data received from the control logic 104 into the sub - pixel array 300 in each frame. For example, the source write driver 306 can simultaneously apply the data signals D0 - Dm to the data lines (also referred to as source lines) of each column of sub - pixels 300. That is, the source write driver 306 can include one or more shift registers, digital - to - analog converters (DACs), multiplexers (MUXs), and arithmetic circuits for controlling a timing of applying a voltage to the source electrodes of the switching transistors of each pixel circuit (i.e., during the scan / charge period in each frame) and an amplitude of applying the voltage according to the gradient of the display data 106. It should be understood that although Figure 3 a single source write driver 306 is shown, in some embodiments, multiple source write drivers can cooperate with each other to apply data signals to the data lines of each column of sub - pixels.

[0052] Figure 4A is a block diagram showing a display system 400, which shows that the display system 400 according to one embodiment includes a display 102, a control logic 104, and a processor 114.

[0053] As described above, the processor 114 can be any processor capable of generating display data 106, such as pixel data and / or compensation data, in each frame and providing the display data 106 to the control logic 104. The processor 114 can be, for example, a GPU, an AP, an APU, or a GPGPGPU. The processor 114 can also generate other data, such as but not limited to, control instructions 118 ( Figure 1 optional in Figure 4A(not shown in the figure), and provide it to the control logic 104. The display data stream 106 transmitted from the processor 114 to the control logic 104 may include the original display data and / or compensation data of the pixels on the display screen 210.

[0054] In this embodiment, the processor 114 includes a graphics pipeline 404, a preprocessing module 405, and a data transmitter 406. Each graphics pipeline 404 can be a two-dimensional (2D) rendering pipeline or a three-dimensional (3D) rendering pipeline for converting a two-dimensional or three-dimensional image with geometric primitives in vertex form into a display data block, where each display data block corresponds to a pixel on the display screen 210. The graphics pipeline 404 can be implemented as software (e.g., a computing program), hardware (e.g., a processing unit), or a combination thereof. The graphics pipeline 404 may include multiple stages, such as a vertex shader for processing vertex data, a rasterizer for converting vertices into fragments with interpolated data, a pixel shader for calculating the lighting, color, depth, and texture of each display data block, and a render output unit (ROP) for performing final processing (e.g., blending) on each display data block and writing it to an appropriate position in a frame buffer (not shown). Each graphics pipeline 404 can independently process a set of vertex data simultaneously and generate corresponding display data sets in parallel.

[0055] In this embodiment, the graphics pipeline 404 is configured to generate multiple display data for the pixels on the display screen 210 in each frame, including pixel data and / or compensation data. Each display data slice can correspond to a pixel in the pixel array on the display screen 210. For example, for a display screen with a resolution of 2400×2160, in each frame, the display data generated by the graphics pipeline 404 includes 2400×2160 blocks, where each block represents a set of values of the electrical signals to be applied to the respective pixels (e.g., including several sub-pixels). The display data can be generated by the graphics pipeline 404 at an appropriate frame rate (e.g., frequency), at which continuous display frames are provided to the display screen 210, such as 30 frames per second, 60 frames per second, 72 frames per second, 120 frames per second, or 240 frames per second. In some embodiments, the graphics pipeline 404 only generates pixel data, and the compensation data is generated by a separate unit in the preprocessing module 405, such as a compensation data generation unit. The specific manner of generating the compensation data should not be limited by the embodiments of the present disclosure.

[0056] The preprocessing module 405 is operatively coupled to the graphics pipeline 404 and is configured to process the display data of the display screen 210 provided by the graphics pipeline 404 to, for example, generate compensation data and compress the compensation data. Figure 4B is shown in accordance with Figure 4ADetailed block diagram of the preprocessing module 405 in the processor 114 of one embodiment. In this embodiment, the preprocessing module 405 includes a downsampling unit 412, a quantization unit 413, a basic look-up table determination unit 414, a sub-look-up table determination unit 415, and a bitstream determination unit 416. The graphics pipeline 404 can generate a plurality of compensation data slices in each frame. Each compensation data slice can be used to compensate a pixel on the display screen 210. For example, for a display screen with a resolution of 2400×2160, the compensation data generated in each frame includes 2400×2160 slices, where each compensation data slice represents a set of electrical signal values to be applied to each pixel (e.g., including a number of sub-pixels). In some embodiments, each compensation data slice corresponds to (or is used to compensate) a respective sub-pixel. In some embodiments, the resolution refers to the physical / native resolution of the display screen 210. In some different embodiments, each compensation data (e.g., each set of electrical signal values) can be a single value or multiple values.

[0057] In some embodiments, in each frame, the preprocessing module 405 performs a downsampling operation on the compensation data. A plurality of downsampled compensation data slices can be generated. The downsampling operation can be performed by the downsampling unit 412. The downsampling unit 412 can determine a plurality of downsampled compensation data slices. Each downsampled compensation data slice can represent the downsampled value of more than one compensation data. Therefore, the size (e.g., the number of slices) of the downsampled compensation data can be smaller than the size of the compensation data (e.g., before the downsampling process). In some embodiments, the downsampling unit 412 determines a downsampling coefficient (e.g., greater than 1) representing the ratio of the reduced size of the compensation data. Figure 5A An exemplary downsampling process performed by the downsampling unit 412 is shown.

[0058] As Figure 5A shown, the downsampling unit 412 can receive a plurality of compensation data slices generated by the graphics pipeline 404. The compensation data can be arranged in an array 501 composed of a plurality of rows and a plurality of columns. Each row can include a plurality of compensation data slices arranged in the row direction (e.g., the horizontal direction), and each column can include a plurality of compensation data slices arranged in the column direction (e.g., the vertical direction). In some embodiments, the downsampling unit 412 determines a downsampling coefficient of m×n, which corresponds to the compensation data slices in m rows and n columns. In some embodiments, m and n are each positive integers, where m is less than the number of rows and n is less than the number of columns. In some embodiments, m×n is also referred to as the block size. In some embodiments, the downsampling unit 412 divides the array 501 into a plurality of blocks and obtains the downsampled value of each block. In some embodiments, each block has the same block size, e.g., m×n. In some embodiments, each block is downsampled to be represented by a single downsampled compensation value.

[0059] In some embodiments, the size of the compensation data (i.e., the number of rows and columns) is the same as the size of the pixel data. That is, the number of rows in the array 501 is equal to the number of rows of the pixel data in the display screen 210, and the number of columns in the array 501 is equal to the number of columns of the pixel data in the display screen 210. That is, the size (or dimension) of the array 501 corresponds to the arrangement of the pixels in the display screen 210, and each element of the array 501 (i.e., each block of the compensation data) represents the compensation data of the corresponding pixel in the display screen 210. Accordingly, each block corresponds to an m×n pixel array / block in the display screen 210. In some embodiments, the downsampling unit 412 divides the compensation data array (e.g., having a size of (mJ)×(nK)) into J×K blocks 502, and each block 502 includes m×n compensation data. J may be equal to the number of rows divided by m, and K may be equal to the number of columns divided by n. For example, each block 502 includes a plurality of compensation data, such as a plurality of compensation data slices such as CDa, CDb, CDc, CDd,........... etc.

[0060] The downsampling unit 412 may determine a plurality of downsampled compensation data slices according to the division of the compensation data. In some embodiments, as an exemplary data structure, the downsampled compensation data is arranged in a J×K array 503, where each element 504 (e.g., DSCD11, DSCD12,...) is a downsampled compensation data slice. In some embodiments, each element 504 is a downsampled compensation value. In some embodiments, the size of the array 503, e.g., J×K, is smaller than the size of the array 501. As Figure 5AAs shown, the downsampling unit 412 may downsample the compensation data (e.g., CDa,...) in the upper left block 502 and determine the downsampled compensation data slice (e.g., DSCD11) of the upper left block 502. In some embodiments, the downsampling unit 412 stores the DSCD11 array 503. In some embodiments, the downsampling unit 412 also downsamples the compensation data (e.g., CDb, CDc, CDd,...) from the upper right block 502, the lower left block 502, and the lower right block 502, and determines and stores the respective downsampled data blocks of the compensation data (e.g., DSCD12, DSCD21, DSCD22,...) on the lower right block, the lower left block, and the lower right block 502 of the DSCD11 in the array 503. In some embodiments, the arrangement of the downsampled data in the array 503 may correspond to the arrangement of the J×K blocks of the compensation data. In some embodiments, the downsampling unit 412 determines the downsampled compensation data row by row or column by column in sequence. In some embodiments, the J×K array 503 includes J×K downsampled compensation values. That is, DSCD11, DSCD12, DSCD13,..., DSCD21, DSCD22, DSCD23,..., DSCD31, DSCD32, DSCD33,... may be the downsampled compensation values of the respective blocks in the array 501. In some embodiments, the downsampling operation is a lossy data compression process.

[0061] The downsampling unit 412 may downsample the block 502 using any suitable method, such as an average downsampling method, a median downsampling method, a maximum downsampling method, a minimum downsampling method, a position-specified downsampling method, and / or a gradient downsampling method. For example, for each block 502, the respective downsampled compensation data (or downsampled compensation value) may be the average value of the compensation data in the block 502 (e.g., using the average downsampling method), the median value of the compensation data in the block 502 (e.g., using the median downsampling method), the maximum value of the compensation data in the block 502 (e.g., using the maximum downsampling method), the maximum value of the compensation data in the block 502 (e.g., using the maximum downsampling method), the minimum value of the compensation data in the block 502 (e.g., using the minimum downsampling method), the position-specified value of the compensation data in the block 502 (e.g., using the position-specified downsampling method), and / or the gradient value of the block 502 (e.g., using the gradient downsampling method). In some embodiments, the position-specified value of the position-specified block 502 refers to the value of the compensation data slice at a specific position / element of the block 502. For example, the downsampling unit 412 may determine the downsampled compensation data / value of the block 502 as the value of the compensation data slice of the first upper left element in the block 502. In some embodiments, the gradient value refers to the highest gradient value of the block 502. The gradient value of each pixel corresponding to the block 502 may be calculated as:

[0062]

[0063] Among them, abs(f) represents the absolute value of the function, (x, y) represents the coordinates of the pixel, and f(x, y) represents the compensation value of the pixel.

[0064] In various embodiments, the block size of one block 502 may be different from the block size of another block 502. That is, for different blocks 502, the values of M and N may be different. In some embodiments, the block size of one block 502 in one row / column is different from the block size of another block 502 in another row / column. The size of the array 503, that is, J×K, may change correspondingly with the change of the value of m and / or n. In some embodiments, more than one downsampling method is used to downsample the J×K blocks. For example, the downsampling method for downsampling one block 502 in one row / column is different from the downsampling method for downsampling another block 502 in another row / column.

[0065] The preprocessing module 405 may determine a plurality of quantized downsampling compensation data slices 502 from the downsampling compensation data. This operation may be performed by the quantization unit 413. The quantization unit 413 may quantize the downsampling compensation data to form quantized downsampling compensation data. The quantization unit 413 may determine a plurality of different (i.e., non-repeating) downsampling compensation data slices, arrange the non-repeating downsampling compensation data in order, and quantize one or more adjacent non-repeating downsampling compensation data to form quantized downsampling compensation data. Therefore, the number of blocks of the quantized downsampling compensation data is less than the number of blocks of the downsampling compensation data. In some embodiments, the arrangement order of the non-repeating downsampling compensation data is ascending order. In some embodiments, each block of downsampling compensation data is a downsampling compensation value, and the arrangement order of the plurality of non-repeating downsampling compensation values is ascending order. In some embodiments, the quantization unit 413 also determines the number of occurrences of each block of downsampling compensation data in the plurality of downsampling compensation data slices (for example, in the array 503). The number of occurrences is represented by the number of occurrences (num0, num1, num2,...) determined by the quantization unit 413.

[0066] Figure 5BShows a plurality of non-repeating downsampling compensation data slices arranged in ascending order (e.g., in a queue). In some embodiments, the quantization unit 413 stores the non-repeating downsampling compensation data in the table 506 in order. DSCD0, DSCD1, DSCD2, ..., ..., DSCD6, ... represent all the different (e.g., non-repeating) downsampling compensation data that appear in the array 503. In some embodiments, DSCD0, DSCD1, DSCD2, ..., ..., DSCD6, ... each represent a different value. In some embodiments, the quantization unit 413 determines an occurrence count, num0, num1, num2, ..., ..., num6, ..., where each represents the occurrence count of the respective slice of the non-repeating downsampling compensation data (DSCD) in the array 503. In some embodiments, all the non-repeating downsampling compensation data are stored in one column of the table 506, the occurrence counts are stored in another column of the table 506, and each occurrence count is mapped to the occurrence count of the respective downsampling compensation data slice. In some embodiments, the number of non-repeating downsampling compensation data slices is X (e.g., X rows in the table 506), and the table 506 can have a size of X×2. For example, DSCD0 can be the smallest non-repeating downsampling compensation value and is sorted as the first in the queue. DSCD0 can have an occurrence count num0, e.g., 50, and can appear as DSCD11, DSCD13, DSCD21, ..... That is, DSCD0 can appear repeatedly (e.g., 50 times) in the downsampling compensation data of the array 503. In ascending order, DSCD1 can be the second smallest downsampling compensation value and is sorted as the second in the queue, and DSCD2 can be the third smallest downsampling compensation value and is sorted as the third in the queue.

[0067] The preprocessing module 405 can determine a plurality of quantization data slices according to the order of the downsampling compensation data (e.g., in ascending order). Each quantization data slice can be different from each other and can represent the order of a plurality of adjacent non-repeating quantization slices in adjacent non-repeating downsampling compensation data. The quantization unit 413 can perform this operation. The quantization unit 413 can determine the quantization data using the downsampling compensation data in the table 506. In some embodiments, the quantization unit 413 can use the downsampling compensation data and the respective occurrence counts in the table 506 to determine the quantization data. In some embodiments, the plurality of quantization data includes a plurality of quantization values, and each quantization value represents the quantization value of a plurality of adjacent downsampling compensation data in adjacent non-repeating downsampling compensation data in the table 506. The number of adjacent downsampling compensation data slices can be referred to as j, where the number is any suitable positive integer step including the total number (i.e., X) of non-repeating compensation slices less than the downsampling compensation data.

[0068] Figure 5C Shows a plurality of schematic quantization data slices QDSCD0, QDSCD1, QDSCD2, ... determined by quantization of the non-repetitive downsampling compensation data in Table 506. Each of QDSCD0, QDSCD1, QDSCD1, QDSCD2, ... can be different from each other (non-repetitive) and represents the quantization of one or more downsampling compensation data in Table 506. In some embodiments, each of QDSCD0, QDSCD1, QDSCD2, ..... is a quantization value. In some embodiments, QDSCD0, QDSCD1, QDSCD2, ... are arranged in ascending order in a queue. In some embodiments, the quantization unit 413 stores the queue in Table 510. The value of j can be greater than 1, and in various embodiments, the value of j can be 2, 3, 4, ... or 16. For example, j can be equal to 3, and the quantization unit 413 can determine that the quantization unit 413 determines the quantization value QDSCD0 of DSCD0, DSCD1, and DSCD2 as the quantization value QDSCD0, and determines the quantization value QDSCD1 of DSCD3, DSCD4, and DSCD5 as the quantization value QDSCD1. In some embodiments, j is a constant value for all quantization values. In some embodiments, j varies for different quantization values. In some different embodiments, the value of j for each quantization value is determined according to the method used to determine the quantization value. In some embodiments, the size of the queue in Table 510 (e.g., the number of rows or the number of quantization values) is equal to Y, and Y is less than or equal to X.

[0069] The quantization unit 413 can use any suitable method to determine the quantization data. In some embodiments, the method includes an average quantization method, a maximum quantization method, a minimum quantization method, a median quantization method, a median quantization method, and / or a quantization method for a specific range. For example, the quantization unit 413 can determine that the quantization value is equal to the average of j adjacent downsampling compensation data of the downsampling compensation data (e.g., using the average quantization method), the maximum of j adjacent downsampling compensation data of the downsampling compensation data (e.g., using the maximum quantization method), the minimum of j adjacent downsampling compensation data of the downsampling compensation data (e.g., using the minimum quantization method), the median value of j adjacent downsampling compensation data (e.g., using the median quantization method), and / or a specific range value of j adjacent downsampling compensation data (e.g., using the quantization method for a specific range). In various embodiments, the same quantization method or different quantization methods can be used to determine the quantization data.

[0070] Figure 5DAn exemplary specific range quantization method is shown. The X-axis represents the value of the downsampling compensation data ("DSCD value"), and the Y-axis represents the value of the quantized downsampling compensation data ("QDSCD value"). In some embodiments, the quantization unit 413 determines a plurality of ranges along the x-axis according to the value of the downsampling compensation data. Each range can be defined by a pair of thresholds. In some embodiments, for each range, the quantization unit 413 determines a quantization value as the quantized downsampling compensation data for any downsampling compensation data within the respective range. The quantization values for each range can be different quantization values. For ease of illustration, Figure 5D 8 ranges are shown, which are respectively 8 specific ranges defined by 8 pairs of thresholds (DSCDb3, DSCDb2), (DSCDb2, DSCDb1), (DSCDb1, DSCDb0), (DSCDb0, 0), (0, DSCDa0), (DSCDa0, DSCDa1), (DSCDa1), (DSCDa2), (DSCDa2, DSCDa3). In turn, these eight ranges can correspond to the quantization values Qb3, Qb2, Qb1, Qb0, Qa0, Qa0, Qa1, Qa2, and Qa3. That is, any piece of downsampling compensation data (or a non-repeating piece of downsampling compensation data) falling within the corresponding range is quantized to the corresponding quantization value within that range. For example, DSCD0, DSCD1, and DSCD2 can be within the range of (DSCDb2, DSCDb1), and the quantization unit 413 can determine that the quantization values of DSCD0, DSCD1, and DSCD2 are equal to Qb2. That is, the quantization values corresponding to DSCD0, DSCD1, and DSCD2 are Qb2. In some embodiments, the thresholds are determined according to the distribution of the downsampling compensation data. For example, a pair of thresholds can be determined to include the maximum number of adjacent non-repeating downsampling compensation data, which can reduce the number of quantization values, improve the compression efficiency, and reduce the storage space of the compensated data after compression.

[0071] In some embodiments, such as Figure 5DAs shown, the ranges are continuous, for example, one range immediately follows another range. In some embodiments, the ranges are discontinuous, for example, one range is separated from another range. The number of non-repeating downsampling compensation data (i.e., j) in each range may be the same or different. In some embodiments, the downsampling compensation data is nominally uniformly distributed. In some embodiments, the values of j adjacent non-repeating downsampling compensation data in the downsampling compensation data have small and / or linear variations along the y-axis. In this case, in some embodiments, the quantization values are nominally uniformly distributed along the y-axis, and j is the same number for all quantization values. In one embodiment, DSCDa0 is equal to 3, Qa0 is equal to 2, and DSCD0, DSCD1, and DSCD2 are equal to 1, 2, and 3 respectively. Then, the quantization unit 413 makes the quantization values of DSCD0, DSCD1, and DSCD2 (or the corresponding quantization values) equal to 2 respectively, and then referring to Figure 5C , after determining the quantization values of every j adjacent downsampling compensation data (for example, Qb3, Qb2, Qb1, Qb0, Qa0, Qa1, Qa2, Qa3), the quantization unit 413 arranges the quantization values in ascending order in a queue. For the sake of illustration, the quantized data arranged in the queue is represented as multiple quantization values. qdscd0, qdscd1, qdscd2, qdscd2, qdscd3,.....

[0072] Figure 5E Shows a plurality of quantized downsampling compensation data slices in the array 512. In some embodiments, the size of the array 512 is J×K. Each element of the array 512 may have the same value as the quantization value of the corresponding downsampling compensation data slice in the array 503. In some embodiments, the array 512 includes J×K quantized downsampling compensation values. In some embodiments, the quantization unit 413 generates the array 512 according to the table 510 and the array 503, for example, by replacing each block of downsampling compensation data in the array 503 with the quantization values in the table 510 and generating the corresponding quantized downsampling compensation data (for example, equal to the quantization value). In some embodiments, the quantization unit 413 maps each block of downsampling compensation data in the array 503 (for example, sequentially or in parallel) to the non-repeating downsampling compensation data with the same value in the table 506, and maps the non-repeating downsampling compensation data to the quantization values in the table 510. For example, QDSCD11 represents the quantization value of DSCD11, QDSCD12 represents the quantization value of DSCD12, QDSCD21 represents the quantization value of DSCD21, etc. Since the elements in the array 512 are determined according to the table 510, each element (QDSCD11, QDSCD12,......) in the array 512 is equal to an element (QDSCD0, QDSCD1,......) in the table 510.

[0073] The quantization unit 413 may sort the quantization data (e.g., Y quantization values) in Table 510 by the number of occurrences and generate a plurality of first indexes, each index mapping to a quantization value. The values of the first indexes may be non-repeating and may include any suitable non-negative integers. In some embodiments, the number of occurrences of each quantization value (i.e., QDSCD0, QDSCD1, QDSCD2, QDSCD3, ...) is determined, representing the number of occurrences of each quantization value in the array 512. In some embodiments, the quantized data is sorted in descending order of the number of occurrences. In some embodiments, the sorted quantized data is arranged in a queue. Each quantization value may correspond to a number of occurrences and a first index. In some embodiments, the quantization unit 413 stores the sorted quantization data, the number of occurrences, and the first index in columns in a table respectively. In some embodiments, each quantization value is mapped to the corresponding number of occurrences and first index.

[0074] Figure 5F An exemplary Table 514 is shown, in which the quantized data (i.e., non-repeating) is arranged in a column in descending order of the corresponding number of occurrences. In some embodiments, num0≥num1≥num2≥num3, ..... A plurality of first indexes (I0, I1, I2, ...), each mapping to a respective quantization value (or respective quantization value or respective number of occurrences) are stored in another column of Table 514. In some embodiments, I0, I1, I2, ... are equal to 0, 1, 2, .... respectively. In some embodiments, the quantization unit 413 determines whether the number of first indexes (i.e., the number of non-repeating quantization values) exceeds a predetermined size limit, which may be any suitable positive integer, such as 16, 32, 64 or the like. If the quantization unit 413 determines that the number of first indexes is greater than the predetermined size limit, the quantization unit 413 may increase the value of j (the number of adjacent downsampling compensation data or the number of steps in Table 506) and perform quantization of the downsampling compensation data again. The quantization unit 413 may continue to adjust the value of j until the number of first indexes (or Y) is equal to or less than the predetermined size limit. In some embodiments, the size of Table 514 is Y×3, and Y is less than or equal to the predetermined size limit.

[0075] The range of the first indexes may be smaller than the range of the non-repeating quantization values. For example, the non-repeating quantization values of non-repeating quantization may include negative values, zero, and / or positive values, while the first indexes may include only non-negative values. It should be noted that in various embodiments, the first indexes may include any set of values having a range smaller than the non-repeating quantization values. For example, the range of the non-repeating quantization values of non-repeating quantization may be from -20 to 20, and the range of the first indexes may be from 0 to 30, -15 to 15, etc. The specific values and the number of the first indexes should not be limited by the embodiments of the present disclosure.

[0076] The preprocessing module 405 can determine a basic lookup table (base lut or first lookup table) according to Table 514 to form IBL data (or index data). The basic lookup table determination unit 414 can perform this operation. In some embodiments, the basic lookup table determination unit 414 can form a basic lookup table including all the first indexes in Table 514 (i.e., Y first indexes I0, I1, I2,...) and corresponding non-repetitive quantization values (i.e., Y quantization values QDSCD0, QDSCD1, QDSCD2,...). Figure 5G An exemplary basic lookup table 520 is shown. In some embodiments, the first column of the basic lookup table 520 includes Y first indexes, and their arrangement order is the same as that in Table 514. For illustrative purposes, in the basic lookup table 520, the first indexes are represented by IBL0, IBL1, IBL2,... (i.e., I0 = IBL0, I1 = IBL1, I2 = IBL2,...). The second column of the basic lookup table 520 can include Y quantization values arranged in the same order as in Table 514.

[0077] The basic lookup table determination unit 414 can determine a plurality of IBL data blocks according to the basic lookup table 520 and the quantized downsampling compensation data in the array 512. In some embodiments, the IBL data is stored in a J×K array, and each element of this array is an IBL value corresponding to a quantized downsampling compensation data slice in the array 512 (or the corresponding downsampling compensation data in the array 503). Each IBL value is mapped to a first index value that has the same value as the non-repetitive quantization value (in the basic lookup table 520 or Table 514) of the quantized downsampling compensation data slice in the array 512.

[0078] Figure 5G An example of forming IBL data is shown. In some embodiments, the IBL data is formed by converting the quantized downsampling compensation data into a plurality of non-negative values using the basic lookup table 520. As Figure 5GAs shown, the basic look-up table determination unit 414 may form an array of IBL data row by row or column by column. As an example, the basic look-up table determination unit 414 may select a row 516 (or a column, not shown) of the quantized downsampling compensation data from the array 512, and determine a first index for each element in the row 516 (or column) according to the basic look-up table 520. An IBL value in a row 518 (or a column, not shown) may be formed, where each element in the row 518 (or column) is an IBL value mapped to the corresponding quantized downsampling compensation data slice. In some embodiments, the basic look-up table determination unit 414 selects rows from the array 512, for example, sequentially from top to bottom, and forms an IBL data array row by row. In some embodiments, the basic look-up table determination unit 414 sequentially selects columns from the array 512, for example, from left to right, and forms an IBL data array column by column. In some embodiments, the space for storing the IBL data array is smaller than the space for storing the quantized downsampling compensation data array 512.

[0079] In some embodiments, the basic look-up table determination unit 414 selects a row 516 (e.g., the first row) of the array 512, which includes K quantized downsampling compensation data (e.g., QDSCD11, QDSCD12, QDSCD13, ...). The basic look-up table determination unit 414 can map each piece of quantized downsampling compensation data (e.g., QDSCD11, QDSCD12, QDSCD13, ...) in the row 516 to one of the sorted quantized values of the same value in the basic look-up table 520 (e.g., QDSCD0, QDSCD0, QDSCD13, ...) for each piece of quantized downsampling compensation data (e.g., QDSCD11, QDSCD12, QDSCD13, ...). QDSCD0, QDSCD1, QDSCD1, QDSCD2), and determine the first index (IBL0, IBL1, IBL2, ...) mapped to the quantized value, which first index is mapped to the quantized value of the corresponding quantized downsampling compensation data slice. Then, the basic look-up table determination unit 414 can generate a row of K IBL values, each IBL value having the same value as the respective first index (IBL0, IBL1, IBL2, ...) in the basic look-up table 520. For example, the basic look-up table determination unit 414 can map QDSCD11 (i.e., the first element 516 in the array 512 and the first element (1, 1) in the array 512) to QDSCD0 (e.g., having the same value as QDSCD11), determine the first index IBL0 (i.e., mapped to QDSCD0), and determine that IBL11 (i.e., the element (1, 1) in the IBL data array) has the value of IBL0. The basic look-up table determination unit 414 can process each element in the row 516 sequentially or in parallel. IBL data for the row 518 can be formed, i.e., an array including multiple IBL values such as IBL11, IBL12, IBL13, ..... The basic look-up table determination unit 414 can form a J×K array of IBL data, each element of which corresponds to the value of the first index mapped to the array 512 (or the corresponding downsampling compensation data in the array 503) through the quantized data. In some embodiments, the space for storing each row (e.g., row 518) of the IBL data is smaller than the space for storing each row (e.g., row 516) of the array 512.

[0080] The preprocessing module 405 may further divide the array IBL data array into M units, where M is a positive number less than J or K, and the basic lookup table determination unit 414 can perform this operation. In some embodiments, the IBL data array is divided by rows, and each unit includes one or more rows of the IBL data array, and M is a positive number less than J. In some embodiments, each unit includes one row, and M is equal to J; in some embodiments, each unit includes one column, and M is equal to K; in some embodiments, every two adjacent rows form a unit, and M is equal to J / 2. In some embodiments, every two adjacent columns form a unit, and M is equal to K / 2. Figure 5H Exemplary partitions 522 and 524 are shown. In partition 522, M units 522a, 522b, 522b, 522c,... are formed, and each unit 522a, 522b, 522c,... includes two adjacent rows of IBL data. In partition 524, M units 524a, 524b, 524b, 524c,... are formed, and each unit includes two adjacent columns of IBL data.

[0081] The preprocessing module 405 may sort the first index according to the number of occurrences in each of the M units. The sub-lookup table determination unit 415 can perform this operation. In some embodiments, the sub-lookup table determination unit 415 determines the number of occurrences of each non-repeating first index in the unit and sorts the non-repeating first indexes according to the number of occurrences. In some embodiments, the number of occurrences is arranged in descending order. Figure 5I An exemplary order is shown, in which the non-repeating first indexes (IBL0, IBL1, IBL2,...) in each unit are arranged in descending order of the number of occurrences in the queue. In some embodiments, the sub-lookup table determination unit 415 generates a table 526, where the sorted non-repeating first indexes are stored in one column, and the number of occurrences of the first indexes (num0, num1, num2,...) are arranged in another column. As shown in Table 526, each number of occurrences is mapped to the corresponding first index. In some embodiments, M tables are generated, and each table corresponds to a respective IBL value / data unit. In some embodiments, the sub-lookup table determination unit 415 selects the column of the sorted non-repeating first indexes and uses this column as the initial sub-lookup table. M initial sub-lookup tables can be formed. In some embodiments, the preprocessing module 405 converts the IBL data (e.g., formed and arranged in the J×K array by the transformation shown in Figure 5G the transformation shown) into M code streams according to N of the M initial sub-lookup tables. The detailed description is as follows.

[0082] In some embodiments, for each unit, the sub - lookup - table determination unit 415 also determines a plurality of second indexes (i.e., IIBL0, IIBL1, IIBL2,...), where each second index maps to a respective first index. The values of the second indexes can be non - repeating and can include any suitable integer greater than or equal to 0. In some embodiments, IIBL0, IIBL1, IIBL2,... are equal to 0, 1, 2,... respectively. In some embodiments, the second indexes are stored and stored in another column of table 526, as Figure 5I shown, where each second index is mapped to a corresponding first index and the number of occurrences. In some embodiments, the sub - lookup - table determination unit 415 selects the columns of the first index and the second index and uses these two columns as the initial sub - lookup table. In one embodiment, in table 526, IBL0 is equal to 0, num0 is equal to 100, and IIBL0 is equal to 0; IBL1 is equal to 1, num1 is equal to 50, and IIBL0 is equal to 1; IBL2 is equal to 2, num2 is equal to 30, and IIBL2 is equal to 2; and IBL3 is equal to 3, num3 is equal to 20, and IIBL2 is equal to 3.

[0083] As described above, for each unit, the sub - lookup - table determination unit 415 can determine the initial sub - lookup table according to table 526. In some embodiments, the initial sub - lookup table includes a column that includes non - repeating first indexes sorted. In some embodiments, the initial sub - lookup table includes two columns, where one column includes the first indexes arranged in order and the other column includes the second indexes each mapping to a respective first index. M initial sub - lookup tables can be formed. The M initial sub - lookup tables can include or not include duplicate initial sub - lookup tables. In some embodiments, the sub - lookup - table determination unit 415 sorts the M initial sub - lookup tables according to their number of occurrences. In some embodiments, determining the number of occurrences of each initial sub - lookup table, the sub - lookup - table determination unit 415 sorts the M initial sub - lookup tables in descending order of the number of occurrences. In some embodiments, the sub - lookup - table determination unit 415 then selects the N initial sub - lookup tables with the highest number of occurrences (e.g., the top N initial sub - lookup tables). In some embodiments, N is a suitable positive integer, less than or equal to M, such as 16 or 32. In some embodiments, the sub - lookup - table determination unit 415 determines an index for each of the N initial sub - lookup tables.

[0084] For each of the M cells of the IBL data, the preprocessing module 405 can form N initial bitstreams based on the respective cell and N initial sub-lookup tables. The bitstream size (e.g., size) of each initial bitstream can be determined, and the initial bitstream with the shortest bitstream size can be determined as the bitstream for the corresponding cell. The preprocessing module 405 can also determine the initial sub-lookup table used to generate the bitstream as the sub-lookup table (e.g., the second lookup table) for the respective cell. The index of the sub-lookup table can be determined as the index of the corresponding initial sub-lookup table. The bitstream determination unit 416 can perform these operations. In some embodiments, for the M cells, M bitstreams are determined, each bitstream corresponding to a respective cell. The bitstream determination unit 416 can accordingly determine the bitstream size of each bitstream, the sub-lookup table for each cell, and the index of the respective sub-lookup table. In various embodiments, the bitstream determination unit 416 determines the bitstream, bitstream size, and the index of each sub-lookup table for each of the M cells sequentially or in parallel.

[0085] Figure 5J An example of forming the initial bitstream is shown. In some embodiments, the initial bitstream is formed by converting the IBL data of a cell into multiple binary code sets using one of the N initial sub-lookup tables and a variable-length coding table. The space for storing the binary codes can be smaller than the space for storing the respective IBL data, improving the compression efficiency of the compensation data. In some embodiments, the initial sub-lookup table includes a first index column, and each first index in the initial sub-lookup table maps to a respective binary code set in the variable-length coding table. In some embodiments, the coding stream determination unit 416 maps each IBL value in the respective cell to a first index with the same value, maps the first index to the respective binary code set, and determines / forms the respective elements in the initial coding stream to be the same as the binary code set. In some embodiments, the initial sub-lookup table includes a second index column that each maps to a respective first index, and the first index is mapped to the binary code through the second index. For example, each first index maps to a respective second index, and the second index is further mapped to the respective binary code set.

[0086] As described above, the cell 519 can include at least one row / column of IBL values. For ease of illustration, Figure 5J The formation of the initial bitstream formed by a column of IBL values, e.g., K IBL values (IBL11, IBL12, IBL13,...) is described in detail. For ease of illustration, the cell 519 is depicted as a cell 519 having a column of IBL values and can be represented by row 518. As Figure 5JAs shown, the initial sub-lookup table 532 may include a first index column (IBL0, IBL1, IBL2, ...) arranged in the same order as in table 526. In some embodiments, the initial sub-lookup table 532 further includes a second index (IIBL0, IIBL1, IIBL2, ...) column arranged in the same order as in table 526. Each second index is mapped to a corresponding first index (e.g., the first index of the same row in table 526). The variable length coding table 530 may include a set of multiple binary codings (0, 10, 1110, 1110, ...), each binary coding including one or more bits and mapped to respective first indices. In some embodiments, when the initial sub-lookup table 532 does not include a second index column, each first index is directly mapped to its respective set of binary codes. In some embodiments, when the initial sub-lookup table 532 includes a second index column, each first index is mapped to its respective set of binary codes through its respective second index. As Figure 5J shown, the first index IBL0 may be mapped to the binary code "0" through the second IIBL0 (or directly, not shown), the first index IBL1 may be mapped to the binary code "10" through the second IIBL1 (or directly), the first index IBL2 may be mapped to the binary code "110" through the second IIBL2 (or directly), ...... In some embodiments, the coding stream determination unit 416 locates in the initial sub-lookup table 532 a first index (IBL0, IBL1, IBL2, ...) having the same value as the binary coding values (IBL11, IBL12, IBL13, ...) in the unit 519, maps the first index value to the first index, and maps the first index value to the corresponding set of binary coding values in the variable length coding table 530. The code stream determination unit 416 may further determine that the respective elements in the initial code stream 528 are the mapped sets of binary code values. Each element of the initial code stream 528 may include one or more bits. The IBL values in the unit 519 may be processed sequentially or in parallel, and the set of binary codes corresponding to each IBL value in the unit 519 may be determined. In some embodiments, the unit 519 includes K IBL values, and the initial code stream 528 includes K sets of binary codes. The arrangement of the K sets of binary codes may correspond to the arrangement of the K IBL values. For example, in the initial code stream 528, the binary code "0" (i.e., corresponding to IBL11) is arranged as the first element, the binary code "10" (i.e., corresponding to IBL12) is arranged as the second element, the binary code "110" (i.e., corresponding to IBL13) is arranged as the third element, ......, and so on.

[0087] The bitstream determination unit 416 may determine the bitstream size (e.g., length) of the initial bitstream 528. In some embodiments, the bitstream size of the initial bitstream 528 is calculated as the total number of bits in the initial bitstream 528, i.e., the total number of bits of "0" and "1". For example, as Figure 5J shown, the bitstream size of the initial bitstream 528 is calculated as (1 + 2 + 3 + 4 + 5 + 6 + 7 +...). In some embodiments, the bitstream size of the initial bitstream 528 is calculated according to the unit 519, the variable length coding table 530, and the table 526. That is, the bitstream size of the unit IBL value can be determined without generating the initial coding stream of the unit. For example, from the table 526, the coding stream determination unit 416 can determine the occurrence times of the first index mapped to (i.e., corresponding to) all different (non-repeating) IBL values in the unit 519 in the table 526, and determine the set of binary codings mapped to the first index in the variable length coding table 530. The size of the initial coding stream can be the sum of the number of bits of each multiplied by their respective occurrence times, where the number of bits is the number of bits in all the mapped binary coding sets. For example, referring to Figure 5J , assuming that the non-repeating binary bitstream values in the unit 518 are IBL11, IBL12,..., IBL17, which are respectively mapped to IBL0, IBL1,..., IBL6, then the bitstream size of the initial bitstream 528 is (1×num0 + 2×num1 + 3×num2 + 4×num3 + 5×num4 + 6×num5 + 7×num6). In various embodiments, the variable length coding table 530 may include any suitable coding table that can be used to map source values / symbols to variable bit numbers and should not be limited by the embodiments of the present disclosure.

[0088] In some embodiments, the unit 519 includes IBL values in two rows / columns. The bitstream determination unit 416 may process these two rows / columns sequentially or in parallel to generate the initial bitstreams of the two rows / columns. For example, for a unit with 2×K IBL values, an initial bitstream of 1×2K elements can be generated. In some embodiments, the bits corresponding to the second row / column of each unit are arranged after the bits corresponding to the first row / column.

[0089] The bitstream determination unit 416 may store the bitstream, the size of the bitstream, and the index of the sub-lookup table for each of the M units, and the N initial sub-lookup tables and the base lookup table in a memory as compression compensation data, such as the memory 116, such as a flash memory, etc. Figure 5K Depicts an exemplary data structure of the compression compensation data. As Figure 5KAs shown, the bitstream determination unit can store a base lookup table, N initial sub-lookup tables, and the bitstream data of each unit in the memory. In some embodiments, the bitstream data of each unit (UNIT 0, UNIT 1, UNIT 2, ...) respectively includes an index (INDEX 0, INDEX1, INDEX 2, ...), a bitstream size (SIZE 0, SIZE 1, SIZE 2, ...), and a bitstream (CODE STREAM 0, CODESTREAM 1, CODE STREAM 2, ...). In some embodiments, the index represents the index of the sub-lookup table corresponding to the unit, the bitstream size represents the bitstream size of the bitstream of the unit, and the bitstream represents the bitstream of the unit. In some embodiments, the total size of the M bitstreams, for example, the total size of the bitstreams stored in the memory is less than the total size of the IBL data of the M units.

[0090] The decompression of the compressed compensation data can be performed by the post-processing module 408 in the control logic 104, and the post-processing module 408 can be operatively coupled to the pre-processing module 405 in the processor 114. Figure 4C is a diagram showing Figure 4A a detailed block diagram of the post-processing module 408 in the control logic 104 according to an embodiment of. In this embodiment, the post-processing module 408 includes a data reading unit 421, a QDSCD determination unit 422, and an upsampling unit 423.

[0091] The post-processing module 408 can obtain the compressed compensation data from the memory. The data reading unit 421 can perform this operation. In some embodiments, the data reading unit 421 obtains the base lookup table, N initial sub-lookup tables, and the bitstream information of the M units in sequence, for example, in the order in which the data is stored in the memory.

[0092] The post-processing module 408 may determine the IBL value corresponding to each of the M units. The QDSCD determination unit 422 may perform this operation. The QDSCD determination unit 422 may sequentially read out the bitstream data of each of the M units and decompress the respective bitstream data. In some embodiments, for each unit, the QDSCD determination unit 422 reads out the index (INDEX 0, INDEX 1, INDEX 2, INDEX 2,...) and the bitstream size (SIZE 0, SIZE 1, SIZE 2,...) mapped to the index. According to the bitstream size, the QDSCD determination unit 422 determines the bitstream (CODE STREAM0, CODE STREAM 1, CODE STREAM 2,...) mapped to the bitstream size. In some embodiments, the QDSCD determination unit 422 determines a sub-lookup table according to the index and determines the variable length coding table for the compression process. For each coding stream, the QDSCD determination unit 422 may determine the unit of the IBL data according to the variable length coding table and the sub-lookup table.

[0093] Figure 6A An example of forming the IBL data from the coding stream is shown. As Figure 6A shown, the QDSCD determination unit 422 is a unit that converts the coding stream 602 into the IBL data 608 through the variable length coding table 530 and the sub-lookup table 604. In some embodiments, for each unit, the sub-lookup table 604 (for decompression) represents the initial sub-lookup table (e.g., 532), which is retrieved by its index number and is used to generate the coding stream of the unit. In some embodiments, the conversion shown in FIG. 6a is the reverse operation of the conversion shown in FIG. 5j. In some embodiments, the QDSCD determination unit 422 locates the set of binary codes identical to each element of the bitstream 602 in the variable length coding table 606 and maps each element of the bitstream 602 to the corresponding set of binary codes. The QDSCD determination unit 422 may be based on the same mapping relationship described during the compression process ( Figure 5J) The binary code set is mapped to respective first indices (IBL0, IBL1, IBL2,...) in the sub - lookup table 604. Then, the QDSCD determination unit 422 can determine that each IBL value (e.g., IBL11, IBL12,...) in the unit 608 has the same value as the respective first index. In some embodiments, the arrangement of the IBL values in the unit 608 matches the arrangement of the corresponding elements in the bitstream 602. For example, in the unit 608, IBL11 (i.e., corresponding to the binary code "0") is arranged as the first element, IBL12 (i.e., corresponding to the binary code "10") is arranged as the second element, IBL13 (i.e., corresponding to the binary code "110") is arranged as the third element,......, and so on. In some embodiments, the bitstream 602 includes K elements, and each element includes a set of binary codes. Accordingly, the unit 608 may include 1×K binary code values. In some embodiments, the bitstream 602 includes 2K elements, and accordingly, the unit 608 may include 2×K IBL values.

[0094] The sub - lookup table 604 may or may not include a column of second indices (IIBL0, IIBL1, IIBL2,...), where, as described above, the second indices (IIBL0, IIBL1, IIBL2,...) are indices of the first indices (IIBL0, IIBL1,...). When the sub - lookup table 604 does not include the second index, the binary code set in the variable - length coding table 606 can be directly mapped to the corresponding first index. When the sub - lookup table 604 includes the second index, the binary code set in the variable - length coding table 606 can be mapped to the corresponding first index through the second index.

[0095] The post - processing module 408 can determine the quantization down - sampling compensation data corresponding to the IBL value of each unit. The QDSCD determination unit 422 can perform this operation. In some embodiments, for each unit, the QDSCD determination unit 422 determines one or more sets of quantized down - sampling compensation data, where each set of quantized down - sampling compensation data is a quantized down - sampling compensation value corresponding to each IBL value in the unit. The QDSCD determination unit 422 can obtain a base lookup table from the memory for this operation.

[0096] Figure 6B An example of forming a column of quantized down - sampling compensation data from the IBL value of one unit is shown. As Figure 6B shown, the QDSCD determination unit 422 converts each unit 608 of the IBL data into a row 612 of quantized down - sampling compensation values through the base lookup table 520. In some embodiments, Figure 6B the conversion shown is Figure 5GThe reverse operation of the conversion shown. In some embodiments, the QDSCD determination unit 422 locates the first index (IBL0, IBL1, IBL2,...) in the basic lookup table 520 that has the same value as each IBL value (IBL11, IBL12,...) in the basic lookup table 520 in unit 608 and maps each IBL value to the corresponding first index. The QDSCD determination unit 422 can determine the quantization values (QDSCD0, QDSCD1, QDSCD2,...) in the sub-lookup table 604 that are mapped to each first index according to the same mapping relationship as described ([ Figure 5G in). Then, the QDSCD determination unit 422 can determine that each quantized downsampling compensation value (QDSCD11, QDSCD12, QDSCD13,...) in row 612 has the same permutation relationship as the corresponding IBL value, such that it has the same value as its respective quantization value. For example, in row 612, QDSCD11 (i.e., corresponding to IBL11) is arranged as the first element and has the same value as QDSCD0, QDSCD12 (i.e., corresponding to IBL12) is arranged as the second element and has the same value as QDSCD1, QDSCD13 (i.e., corresponding to iBl13) is arranged as the third element and has the same value as QDSCD2,...... In some embodiments, unit 608 includes 1×K IBL values. Correspondingly, row 612 may include 1×K quantized downsampling compensation values. In some embodiments, unit 608 includes 2×K IBL values. Correspondingly, row 612 may include 2×K IBL quantized downsampling compensation values. In some embodiments, M units of IBL values are converted into an array of J×K quantized downsampling compensation values.

[0097] The post-processing module 408 can upsample each quantized downsampling compensation value to form decompression compensation data. The upsampling unit 423 can perform this operation. Figure 6C An exemplary upsampling operation is shown. As Figure 6C shown, the upsampling unit 423 can upsample each quantized downsampling compensation value J×K quantized compensation value 632 (e.g., QDSCD11, QDSCD12, QDSCD21, QDSCD22,...) in the J×K quantized downsampling compensation value array 631 by its respective block size. An upsampled data array 633 including (mJ)×(nK) compensation values can be formed. In some embodiments, the array 633 can be used to compensate the pixel data of the display screen 210. In some embodiments, for each quantized downsampling compensation value 632, the block size can be the same and can be m×n, which is in Figure 5ADetermined previously during the downsampling process shown. That is, for each quantized downsampling compensation value 632, a block 634 of m×n upsampling compensation values is formed. The upsampling unit 423 can determine the m×n upsampling compensation values 632 according to the corresponding quantized downsampling compensation values 632. The m×n upsampling compensation values can be determined using any suitable upsampling method, such as an even upsampling method and / or an interpolation upsampling method. In some embodiments, by using the even value upsampling method, each upsampling compensation value in block 634 can be the same as the corresponding quantized downsampling compensation value. For example, USCDa = QDSCD11, USCDb = QDSCD12, USCDc = QDSCD21, USCDd = QDSCD22, ..., and so on. In some embodiments, by using the interpolation upsampling method, each upsampling compensation value in block 634 can be determined to be linearly proportional to the distances between each upsampling compensation value in adjacent blocks 634 and each downsampling compensation value in adjacent blocks 634.

[0098] In some embodiments, the post - processing module 408 includes a control signal generation unit (not shown) for generating control signals for the display 102. In some embodiments, the control signal generation unit includes a timing controller (TCON) and a clock signal generator. The TCON can provide various enable signals to the driver 409 of the display 102. The clock signal generator can provide various clock signals to the driver 409 of the display 102. As described above, the control signal 108, including the enable signal and the clock signal, can control the gate scan driver 304 to scan the corresponding pixel rows in the gate scan order and control the source write driver 306 to write each set of display data in the order of the display data blocks in the display dataset. In other words, the control signal 108 can cause the pixels in the display screen 210 to be refreshed in a certain order at a certain speed. As described in detail below, the refresh order and rate of the pixels in the first part and the second part of the display screen 210 can be determined by the control signal generation unit according to the frame rate of the corresponding display dataset received by the control logic 104.

[0099] As Figure 4A, the data transmitter 406 in this embodiment is operatively coupled to the preprocessing module 405 and is configured to send the display data stream 106 in each frame to the control logic 104 through the memory 116. The display data stream 106 may include the original display data and compensation data (e.g., compressed compensation data) of the image to be applied to the corresponding pixels in each frame. For example, in each frame, the original display data (e.g., sub-image for displaying a sub-image) and one or more compensation values may be transmitted as the display data stream 106. In one embodiment, in one frame, the display data 106 may also include compensation data that is compressed and stored in the memory 116 before being transmitted to the control logic 104. The memory 116 may include any suitable storage device for caching, buffering, and / or storing the display data 106 between the processor 114 and the control logic 104. In some embodiments, the memory 116 is not coupled between the processor 114 and the control logic 104. That is, the display data 106, such as pixel data and compressed compensation data, may be transmitted from the processor 114 to the control logic 104 without any buffering or storage.

[0100] The data transmitter 406 may be any suitable display interface between the processor 114 and the control logic 104, such as but not limited to, a Display Serial Interface (DSI), a Display Pixel Interface (DPI), a Display Bus Interface (DBI) of the Mobile Industry Processor Interface (MIPI) Alliance, a Unified Display Interface (UDI), a Digital Visual Interface (DVI), a High-Definition Multimedia Interface (HDMI), and a DisplayPort (DP). Based on the specific interface standard adopted by the data transmitter 406, the display data stream 106 may be serially transmitted with any suitable timing signals, such as Vertical Sync (V-Sync), Horizontal Sync (H-Sync), Vertical Back Porch (VBP), Horizontal Back Porch (HBP), Vertical Front Porch (VFP), and Horizontal Front Porch (HVP), in a corresponding data format. These signals are used to organize and synchronize the pixel array on the display screen 210 and to synchronize the display data stream 106 in each frame with the pixel array on the display screen 210. In some embodiments, the data receiver 407 may receive any original display data and compensation data (e.g., compressed compensation data) from the data transmitter 406 or the memory 116 and output the received data to the post-processing module 408, such as for data decompression.

[0101] In some embodiments, control logic 104 and display 102 are part of a device, such as a smart phone or a tablet computer, and processor 114 is part of a computer external to the device (i.e., external to control logic 104). For example, processor 114 can be part of a computer for generating and compressing compensation data for the device. In some embodiments, data transfer between processor 114 and control logic 104 is through memory 116, which is a storage device such as a flash memory for storing compressed compensation data by processor 114. In some embodiments, processor 114 generates and compresses compensation data and stores the compressed compensation data in memory 116 (e.g., flash memory). Memory 116 can be coupled to control logic 104 such that the compressed compensation data is input into control logic 104 for decompression. In this case, no pixel data is stored in the flash memory. Control logic 104 further decompresses the compressed compensation data and generates control signal 108 based on the compensation data.

[0102] Figure 7A and 7B FIG. shows a flowchart of a method 700 for compressing compensation data according to one embodiment. Figure 7B is Figure 7A a continuation of. The description will be made with reference to the above figures such as Figures 1 to 3 5A - 5K. However, any suitable circuitry, logic, unit or module can be employed. The method can be performed by any suitable circuitry, logic, unit or module that can include hardware (e.g., circuits, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device), firmware, or a combination thereof. It should be understood that not all steps may be required to perform the disclosure provided herein. Further, as will be understood by those of ordinary skill in the art, some steps may be performed simultaneously or in a different order than Figure 8 shown. In some embodiments, each operation of method 700 can be performed by pre - processing module 405.

[0103] Starting from 702, multiple compensation data can be downsampled to form multiple downsampled compensation data (DSCD). At 704, multiple quantization values can be determined based on the downsampled compensation data, and the downsampled compensation data can be quantized based on the quantization values to form multiple quantized downsampled compensation data (QDSCD). Multiple quantization values can be generated based on the downsampled compensation data, and the multiple quantization values can be used to form the quantized downsampled compensation data. At 706, a basic look-up table can be determined based on the quantized downsampled compensation data and the quantization values. In some embodiments, the basic look-up table includes quantization values sorted and arranged in descending order of the occurrence count of the quantization values. At 708, it can be determined whether the size of the basic look-up table is greater than a predetermined size limit (Size_BL). If so, the method proceeds to 704, where the quantization step size is increased to reduce the size of the basic look-up table. If not, the method advances to 710, where the quantized downsampled compensation data can be converted into an array of IBL data based on the basic look-up table. At 712, the IBL data can be divided into M IBL value units. In some embodiments, each unit includes one or more rows / columns of IBL values. At 714, M initial sub-look-up tables can be determined and sorted based on the occurrence count of the M initial sub-look-up tables, and N of them with the highest occurrence count can be selected. At 716, each unit of the IBL values can be converted into a code stream based on the variable length coding table and the N initial sub-look-up tables. The sub-look-up table, the index of the sub-look-up table, and the code stream size of the code stream can be determined. The code stream can correspond to the initial code stream with the shortest code stream size among the N initial code streams generated based on the IBL values and the units of the N initial sub-look-up tables. The sub-look-up table can be the initial sub-look-up table for generating the code stream. The index can be the index of the initial sub-look-up table for generating the code stream. At 718, the basic look-up table, the N initial sub-look-up tables, and the code stream information of each unit can be stored. The code stream information of each unit can include the code stream, the sub-look-up table, the index of the sub-look-up table, and the code stream size of the code stream.

[0104] Figure 8 is a flowchart method 800 for decompressing compressed compensation data according to one embodiment. It will be described with reference to the above figures such as Figures 1 to 3 6A - 6C. However, any suitable circuit, logic, unit, or module can be employed. The method can be executed by any suitable circuit, logic, unit, or module that can include hardware (e.g., circuits, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device), firmware. , or a combination thereof. It should be understood that not all steps may be required to perform the disclosure provided herein. Additionally, as will be understood by those of ordinary skill in the art, some steps can be performed simultaneously, or in an order different from Figure 8executed in different orders shown. In some embodiments, each operation of method 800 may be performed by post-processing module 408.

[0105] Starting from 802, a basic lookup table, N initial sub-lookup tables, and bitstream information for each unit may be read out. The bitstream information for each unit may include a bitstream, a sub-lookup table, an index of the sub-lookup table, and the bitstream size of the bitstream. At 804, based on the bitstream, the sub-lookup table, and the variable length coding table (e.g., 716) used during the compression process, the bitstream for each unit may be converted into a corresponding IBL value. At 806, based on the IBL value and the basic lookup table, the IBL value for each unit may be converted into at least one row of quantized downsampled compensation values. At 808, the quantized downsampled compensation values may be upsampled to form decompressed compensation data.

[0106] The foregoing detailed description of the invention and the examples described therein are for illustrative and descriptive purposes only and do not impose any limitation on the present disclosure. Accordingly, it is contemplated that the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display system, comprising: a display having a plurality of pixels; a processor comprising: a graphics pipeline configured to generate a plurality of pixel data slices corresponding to the plurality of pixels; a preprocessing module configured to generate a plurality of compensation data slices corresponding to the plurality of pixel data slices and compress the compensation data by: determining a plurality of quantized downsampled compensation data slices based on the compensation data, the size of the quantized downsampled compensation data being smaller than the size of the compensation data, wherein the quantization value is specifically determined according to the number of non-repeating downsampled compensation data slices, and each quantization value corresponds to a plurality of adjacent non-repeating downsampled compensation data slices arranged in sequence; converting the quantized downsampled compensation data into M index data units, where M is a positive integer greater than 1 and less than the size of the quantized downsampled compensation data; converting the M index data units into M bitstreams, and control logic operatively coupled to the display and the processor, comprising: a postprocessing module configured to decompress the compressed compensation data according to the M bitstreams to provide control signals for driving the display.

2. The system according to claim 1, wherein the range of the index data is smaller than the range of the quantized downsampled compensation data, and the total size of the M index data units is smaller than the size of the quantized downsampled compensation data.

3. The system according to claim 1, wherein the total size of the M bitstreams is smaller than the size of the M index data units.

4. The system according to claim 1, wherein to determine a plurality of quantized downsampled compensation data slices, the preprocessing module is configured to: downsample the compensation data to determine a plurality of quantized downsampled compensation data slices; and quantize the downsampled compensation data to determine a plurality of quantized downsampled compensation data slices.

5. The system according to claim 4, wherein to downsample the compensation data, the preprocessing module is configured to: divide the compensation data array into a plurality of blocks, each block including more than one compensation data slice; determine one downsampled compensation data slice for each block.

6. The system according to claim 5, wherein to determine the downsampled compensation data slice for each block, the preprocessing module is configured to perform at least one of average downsampling, median downsampling, maximum downsampling, minimum downsampling, position-specified downsampling, or gradient downsampling.

7. The system according to claim 5, wherein each of the plurality of blocks has a block size of m×n compensation data, where m is a positive integer greater than 1 and less than the number of rows in the compensation data array, and n is a positive integer greater than 1 and less than the number of columns in the compensation data array; and the plurality of downsampled compensation data slices are arranged in a J×K array, where J is equal to the number of rows divided by m, and K is equal to the number of columns divided by n.

8. The system according to claim 7, wherein to quantize the downsampled compensation data, the preprocessing module is configured to: determine a plurality of non-repeating downsampled compensation data slices; and sort the plurality of non-repeating downsampled compensation data slices in sequence.

9. The system according to claim 8, wherein The order includes an ascending order arrangement of the multiple non-repeating downsampling compensation data slices.

10. The system according to claim 8, wherein, the preprocessing module is further configured to determine the occurrence times of each of the multiple non-repeating downsampling compensation data slices.

11. The system according to claim 10, wherein, in order to quantify the compensated data of the downsampling, the preprocessing module is further configured to determine a plurality of quantization values, each quantization value corresponding to a plurality of adjacent non-repeating downsampling compensation data slices arranged in order.

12. The system according to claim 11, wherein, the preprocessing module determines each of the quantization values based on at least one of a maximum value, a minimum value, a median value, or a specific range value of the plurality of adjacent non-repeating downsampling compensation data slices, and each range value is defined by a pair of thresholds.

13. The system according to claim 12, characterized in that, the preprocessing module determines the specific range value of the plurality of adjacent non-repeating downsampling compensation data slices through the following steps: determine a plurality of ranges, each range including a plurality of adjacent non-repeating downsampling compensation data slices; and for each range, determine a corresponding quantization value for the plurality of adjacent non-repeating downsampling compensation data slices.

14. The system according to claim 13, wherein, the plurality of ranges are determined in order based on the distribution of the plurality of non-repeating downsampling compensation data slices.

15. The system according to claim 11, wherein, the preprocessing module is further configured to: form a J×K array of the quantized downsampling compensated data by replacing each of the plurality of downsampling compensated data slices with its respective quantization value.

16. The system according to claim 15, wherein, in order to convert the quantized downsampling compensated data into M index data units, the preprocessing module is further configured to: sort the plurality of quantization values in descending order of the occurrence times of each of the plurality of quantization values in the J×K array of the quantized downsampling compensated data; determine a plurality of first indices, each first index mapping to a corresponding one of the plurality of sorted quantization values; and determine a first lookup table including the first indices and the sorted quantization values.

17. The system according to claim 16, wherein, in the first lookup table, the sorted quantization values are arranged in one column, and the first indices are arranged in another column.

18. The system according to claim 16, wherein, the preprocessing module is further configured to determine a size limit of the first lookup table such that the number of the sorted quantization values is less than or equal to the size limit.

19. In the case where the number of the sorted quantization values is greater than the size limit in the system according to claim 18, the preprocessing module is configured to increase the number of adjacent downsampling compensation data slices to reduce the number of quantization values.

20. The system according to claim 16, wherein, in order to form the M index data units, the preprocessing module is further configured to: map the plurality of quantized downsampling compensated data to the sorted quantization values in the first lookup table; Converting multiple quantized downsampled compensation data into first index values that are the same as the first indices mapped to the quantized values of the associated order using a first lookup table to form a J×K array of index data; and Dividing the J×K array of index data into M index data units, each of the M units including at least one row or at least one column of first index values.

21. The system according to claim 20, wherein, Each of the M units includes two rows or two columns of first index values.

22. The system according to claim 20, wherein, For the M units, the preprocessing module is configured to: Sort the non-repeating first index values in each unit in a third order to form multiple sorted non-repeating first indices, the third order being in descending order of the number of occurrences of the first index values in each unit; and Determine an initial second lookup table based on the sorted non-repeating first indices in each unit to form M initial second lookup tables.

23. The system according to claim 22, wherein, For the M units, the preprocessing module is further configured to determine multiple second indices, each second index being mapped to a corresponding one of the sorted non-repeating first indices.

24. The system according to claim 22, wherein, The preprocessing module is further configured to: Determine the number of occurrences of the M initial second lookup tables; Sort the M initial second lookup tables in descending order of each number of occurrences; and Determine N initial second lookup tables having N highest numbers of occurrences, where N is a positive integer less than M.

25. The system according to claim 24, wherein, For each of the M units of index data, in order to determine the M bitstreams and the second lookup table, the preprocessing module is configured to: Determine a variable length coding table; Determine N initial bitstreams in the M units based on the respective units of the index data, the N initial second lookup tables, and the variable length coding table; Determine the bitstream size of each of the N initial bitstreams for each of the M units; and For each of the M units, determine one of the N initial bitstreams corresponding to the shortest bitstream size as the bitstream of the unit and determine the initial second lookup table corresponding to the bitstream as the second lookup table of the unit.

26. The system according to claim 25, wherein, The preprocessing module is further configured to determine the indices of the second lookup tables in the N initial second lookup tables.

27. The system according to claim 26, wherein, In order to form each initial bitstream of the N initial bitstreams, the preprocessing module is configured to: Map each first index value in each unit to the sorted non-repeating first indices in the respective initial second lookup tables; Map the sorted non-repeating first indices to multiple sets of binary codes in the variable length coding table; and Form a corresponding initial bitstream including multiple elements, each element being a set of binary codes mapped to a corresponding one of the sorted non-repeating first indices.

28. The system according to claim 27, wherein, The multiple sets of binary codes include multiple bits, and the size of each initial code stream is equal to the total number of bits.

29. The system according to claim 23, wherein, the preprocessing module is further configured to store the first lookup table in memory, and (i) the second lookup table, (ii) the code stream, (iii) the code stream size, and (iv) the index value of the second lookup table in each of the M index data units.

30. The system according to claim 29, wherein, to decompress the compressed compensation data, the control logic is configured to, for each of the M index data units, determine the code stream according to the data stream size; determine the second lookup table according to the index value of the second lookup table; and determine the first index value in each unit based on the second lookup table and the code stream.

31. The system according to claim 30, wherein, for each of the M index data units, the control logic is configured to, map multiple elements in the code stream of each unit to multiple sets of binary codes in a variable length coding table; map the multiple sets of binary codes to sorted non-repeating first indices in the second lookup table; determine that each first index value is the same as one of the sorted non-repeating first index values mapped to the set of binary codes.

32. The system according to claim 30, wherein, the control logic is further configured to determine the quantized downsampled compensation data corresponding to each of the M index data units based on the first lookup table and the corresponding unit of the first index value.

33. The system according to claim 32, wherein, the control logic is configured to, for each of the M index data units, map the first index value in each unit to the first index in the first lookup table; and respectively form multiple quantized downsampled compensation data slices, each quantized downsampled compensation data slice being the same as one of the sorted quantized values mapped to the first index.

34. The system according to claim 32, wherein, the control logic is further configured to upsample each of the quantized downsampled compensation data with the same block size to compress the compensation data.

35. The system according to claim 34, wherein, to upsample each quantized downsampled compensation data, the control logic is configured to perform at least one of even upsampling or interpolation upsampling.

36. A method for compressing and decompressing compensation data of a display, comprising: generating multiple compensation data slices corresponding to multiple pixel data slices of a display; compressing the compensation data by: determining multiple quantized downsampled compensation data slices based on the compensation data, the size of the quantized downsampled compensation data slices being smaller than the size of the compensation data, wherein the quantization value is specifically determined according to the number of non-repeating downsampled compensation data slices, and each quantization value corresponds to multiple adjacent non-repeating downsampled compensation data slices arranged in sequence; converting the quantized and downsampled compensation data into M index data units, where M is a positive integer greater than 1 and less than the size of the quantized and downsampled compensation data; and Convert the M index data units into M bitstreams; and Decompress the compressed compensation data based on the M bitstreams to provide a control signal for driving a display.

37. The method according to claim 36, wherein determining the plurality of quantized downsampled compensation data comprises: Downsample the compensation data to determine a plurality of downsampled compensation data; and Quantize the downsampled compensation data to determine a plurality of quantized downsampled compensation data.

38. The method according to claim 37, wherein, Downsampling the compensation data comprises: Dividing an array of compensation data into a plurality of blocks, each block including more than one compensation data slice; and Determining a downsampled compensation data slice for each block.

39. The method according to claim 38, wherein determining a downsampled compensation data slice for each block comprises: Performing at least one of average downsampling, median downsampling, maximum downsampling, minimum downsampling, downsampling at a specified position, or gradient downsampling.

40. The method according to claim 38, wherein dividing the array of compensation data comprises: Determining that each block of the plurality of blocks has a block size of m×n compensation data slices, where m is a positive integer greater than 1 and less than the number of rows of the compensation data array, and n is a positive integer greater than 1 and less than the number of columns of the compensation data array; and Arranging the plurality of downsampled compensation data slices in a J×K array, where J is the number of rows divided by m, and K is the number of columns divided by n.

41. The method according to claim 40, wherein quantizing the downsampled compensation data comprises: Determining a plurality of non-repeating downsampled compensation data slices; and Sorting the plurality of non-repeating downsampled compensation data slices in order.

42. The method according to claim 41, further comprising determining the number of occurrences of each of the plurality of non-repeating downsampled compensation data slices.

43. The method according to claim 42, wherein quantizing the downsampled compensation data further comprises determining a plurality of quantization values, each quantization value corresponding to a plurality of adjacent ones of the non-repeating downsampled compensation data slices in the order.

44. The method according to claim 43, wherein, Determining the plurality of quantization values comprises determining each quantization value based on at least one of the maximum value, minimum value, median value, or specific range value in a plurality of adjacent slices of non-repeating downsampled compensation data, each range value being defined by a pair of thresholds.

45. The method according to claim 44, characterized in that, Determining the specific range value of the plurality of adjacent non-repeating downsampled compensation data slices comprises: Determining a plurality of ranges, each range including a corresponding plurality of adjacent non-repeating downsampled compensation data slices; and For each range, determining the corresponding quantization value of the corresponding plurality of adjacent non-repeating downsampled compensation data slices.

46. The method according to claim 45, comprises: Determining the plurality of ranges in order based on the distribution of the plurality of non-repeating downsampled compensation data slices.

47. The method according to claim 43, further comprises: Forming a J×K array of quantized downsampled compensation data by replacing each of the plurality of downsampled compensation data slices with its respective quantization value.

48. The method according to claim 47, wherein converting the quantized downsampling compensation data into the M index data units comprises: sorting a plurality of quantization values in descending order of the number of occurrences of the plurality of quantization values in the J×K array of the quantized downsampling compensation data; determining a plurality of first indexes, each first index mapping to a corresponding one of the plurality of sorted quantization values; and determining a first lookup table including the first indexes and the sorted quantization values.

49. The method according to claim 48, further comprises: in the first lookup table, arranging the sorted quantization values in one column and arranging the first indexes in another column.

50. The method according to claim 48, further comprises determining a size limit of the first lookup table such that the number of the sorted quantization values is less than or equal to the size limit.

51. The method according to claim 50, comprises: in response to the number of the sorted quantization values being greater than the size limit, increasing the number of adjacent downsampling compensation data slices to reduce the number of quantization values.

52. The method according to claim 48, further comprises: mapping a plurality of quantized downsampling compensation data to the sorted quantization values in the first lookup table; forming a J×K array of index data by converting a plurality of quantized downsampling compensation data slices into the same first index values as the corresponding first indexes mapped to the corresponding sorted quantization values by using the first lookup table; and dividing the J×K array of index data into M index data units, each of the M units including at least one row of first index values or at least one column of first index values.

53. The method according to claim 52, further comprises: sorting the non-repeating first index values in each unit in a third order to form a plurality of sorted non-repeating first indexes, the third order being in descending order of the corresponding number of occurrences of the first index values in each unit; and determining an initial second lookup table according to the sorted non-repeating first indexes in each unit to form M initial second lookup tables.

54. The method according to claim 53, further comprises, for each of the M units, determining a plurality of second indexes, each second index being mapped to a corresponding one of the sorted non-repeating first indexes.

55. The method according to claim 53, further comprises: determining the number of occurrences of the M initial second lookup tables; sorting the M initial second lookup tables in descending order of each number of occurrences; and determining N initial second lookup tables having N highest numbers of occurrences, N being a positive integer less than M.

56. The method according to claim 55, wherein, for each of the M index data units, determining the M bitstreams and the second lookup table comprises: determining a variable length coding table; determining N initial bitstreams in the M units according to each unit of the index data, the N initial second lookup tables and the variable length coding table; determining the bitstream size of each of the N initial bitstreams for each of the M units; and For each of the M units, determine one of the N initial code streams corresponding to the shortest code stream size as the code stream for the corresponding unit, and use the initial second lookup table corresponding to this code stream as the second lookup table for each unit.

57. The method according to claim 56, further comprising determining an index of the second lookup table among the N initial second lookup tables.

58. The method according to claim 57, wherein forming each of the N initial code streams comprises: mapping each first index value in each unit to a sorted non-repeating first index in each initial second lookup table; mapping the sorted non-repeating first indices to multiple sets of binary codes in a variable length coding table; and forming a corresponding initial code stream including multiple elements, each element being a set of binary codes mapped to a corresponding one of the sorted non-repeating first indices.

59. The method according to claim 53, further comprises: storing in memory, for each of the M units of the first lookup table and the index data, (i) the second lookup table, (ii) the code stream, (iii) the code stream size, and (iv) the index value of the second lookup table.

60. The method according to claim 59, wherein, decompressing the compressed compensated data comprises: determining a code stream according to the data stream size; determining a second lookup table according to the index value of the second lookup table; and determining the first index value in each unit based on the second lookup table and the code stream.

61. The method according to claim 60, comprises: for each of the M index data units: mapping multiple elements in the code stream of each unit to multiple sets of binary codes in a variable length coding table; mapping the multiple sets of binary codes to sorted non-repeating first indices in the second lookup table; determining that each first index value is the same as the sorted non-repeating first index value mapped to the set of binary codes.

62. The method according to claim 60, further comprises: determining the quantized downsampled compensated data corresponding to each of the M index data units based on the first lookup table and the corresponding unit of the first index value.

63. The method according to claim 62, comprises: for each of the M index data units: mapping the first index value in each unit to a first index in the first lookup table; and respectively forming multiple quantized downsampled compensated data slices, each compensated data slice being the same as one of the sorted quantized values mapped to the first index.

64. The method according to claim 61, further comprises: upsampling each of the quantized downsampled compensated data with the same block size to compress the compensated data.

65. The method according to claim 64, wherein, upsampling each quantized downsampled compensated data comprises performing at least one of even upsampling or interpolation upsampling.

66. The method according to claim 36, wherein, compressing the compensated data is performed by a processor, and decompressing the compressed compensated data is performed by control logic external to the processor.

67. A non-transitory computer-readable medium stores a set of instructions that, when executed by at least one processor, cause the at least one processor to determine a method for compressing and decompressing compensation data for a display. The method includes: generating a plurality of compensation data slices corresponding to a plurality of pixel data slices of the display; compressing the compensation data by: determining a plurality of quantized downsampled compensation data based on the compensation data, the size of the quantized downsampled compensation data being smaller than the size of the compensation data, wherein the quantization value is specifically determined according to the number of non-repeating downsampled compensation data slices, and each quantization value corresponds to a plurality of adjacent non-repeating downsampled compensation data slices arranged in sequence; converting the quantized and downsampled compensation data into M index data units, where M is a positive integer greater than 1 and less than the size of the quantized and downsampled compensation data; and converting the M index data units into M bitstreams; and decompressing the compressed compensation data based on the M bitstreams to provide a control signal for driving the display.

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